SCU

Data Structures
struct	XMC_SCU_CLOCK_CONFIG_t
struct	XMC_SCU_CLOCK_SYSPLL_CONFIG_t

Macros
#define	XMC_SCU_INTERRUPT_EVENT_DLR_OVERRUN   SCU_INTERRUPT_SRSTAT_DLROVR_Msk
#define	XMC_SCU_INTERRUPT_EVENT_HDCLR_UPDATED   SCU_INTERRUPT_SRSTAT_HDCLR_Msk
#define	XMC_SCU_INTERRUPT_EVENT_HDCR_UPDATED   SCU_INTERRUPT_SRSTAT_HDCR_Msk
#define	XMC_SCU_INTERRUPT_EVENT_HDSET_UPDATED   SCU_INTERRUPT_SRSTAT_HDSET_Msk
#define	XMC_SCU_INTERRUPT_EVENT_OSCSICTRL_UPDATED   SCU_INTERRUPT_SRSTAT_OSCSICTRL_Msk
#define	XMC_SCU_INTERRUPT_EVENT_OSCULCTRL_UPDATED   SCU_INTERRUPT_SRSTAT_OSCULCTRL_Msk
#define	XMC_SCU_INTERRUPT_EVENT_RMX_UPDATED   SCU_INTERRUPT_SRSTAT_RMX_Msk
#define	XMC_SCU_INTERRUPT_EVENT_RTC_ALARM   SCU_INTERRUPT_SRSTAT_AI_Msk
#define	XMC_SCU_INTERRUPT_EVENT_RTC_PERIODIC   SCU_INTERRUPT_SRSTAT_PI_Msk
#define	XMC_SCU_INTERRUPT_EVENT_RTCATIM0_UPDATED   SCU_INTERRUPT_SRSTAT_RTC_ATIM0_Msk
#define	XMC_SCU_INTERRUPT_EVENT_RTCATIM1_UPDATED   SCU_INTERRUPT_SRSTAT_RTC_ATIM1_Msk
#define	XMC_SCU_INTERRUPT_EVENT_RTCCTR_UPDATED   SCU_INTERRUPT_SRSTAT_RTC_CTR_Msk
#define	XMC_SCU_INTERRUPT_EVENT_RTCTIM0_UPDATED   SCU_INTERRUPT_SRSTAT_RTC_TIM0_Msk
#define	XMC_SCU_INTERRUPT_EVENT_RTCTIM1_UPDATED   SCU_INTERRUPT_SRSTAT_RTC_TIM1_Msk
#define	XMC_SCU_INTERRUPT_EVENT_WDT_WARN   SCU_INTERRUPT_SRSTAT_PRWARN_Msk

Typedefs
typedef void(*	XMC_SCU_INTERRUPT_EVENT_HANDLER_t) (void)
typedef uint32_t	XMC_SCU_INTERRUPT_EVENT_t

Enumerations

Functions
void	XMC_SCU_CalibrateTemperatureSensor (uint32_t offset, uint32_t gain)
void	XMC_SCU_CLOCK_DisableClock (const XMC_SCU_CLOCK_t clock)
void	XMC_SCU_CLOCK_DisableHighPerformanceOscillator (void)
void	XMC_SCU_CLOCK_DisableHighPerformanceOscillatorGeneralPurposeInput (void)
void	XMC_SCU_CLOCK_DisableLowPowerOscillator (void)
void	XMC_SCU_CLOCK_DisableLowPowerOscillatorGeneralPurposeInput (void)
void	XMC_SCU_CLOCK_DisableSystemPll (void)
void	XMC_SCU_CLOCK_DisableUsbPll (void)
void	XMC_SCU_CLOCK_EnableClock (const XMC_SCU_CLOCK_t clock)
void	XMC_SCU_CLOCK_EnableHighPerformanceOscillator (void)
void	XMC_SCU_CLOCK_EnableHighPerformanceOscillatorGeneralPurposeInput (void)
void	XMC_SCU_CLOCK_EnableLowPowerOscillator (void)
void	XMC_SCU_CLOCK_EnableLowPowerOscillatorGeneralPurposeInput (void)
void	XMC_SCU_CLOCK_EnableSystemPll (void)
void	XMC_SCU_CLOCK_EnableUsbPll (void)
void	XMC_SCU_CLOCK_GatePeripheralClock (const XMC_SCU_PERIPHERAL_CLOCK_t peripheral)
uint32_t	XMC_SCU_CLOCK_GetCcuClockDivider (void)
uint32_t	XMC_SCU_CLOCK_GetCcuClockFrequency (void)
uint32_t	XMC_SCU_CLOCK_GetCpuClockDivider (void)
uint32_t	XMC_SCU_CLOCK_GetCpuClockFrequency (void)
uint32_t	XMC_SCU_CLOCK_GetEbuClockDivider (void)
uint32_t	XMC_SCU_CLOCK_GetEbuClockFrequency (void)
uint32_t	XMC_SCU_CLOCK_GetECATClockDivider (void)
XMC_SCU_CLOCK_ECATCLKSRC_t	XMC_SCU_CLOCK_GetECATClockSource (void)
uint32_t	XMC_SCU_CLOCK_GetEthernetClockFrequency (void)
uint32_t	XMC_SCU_CLOCK_GetExternalOutputClockDivider (void)
uint32_t	XMC_SCU_CLOCK_GetExternalOutputClockFrequency (void)
XMC_SCU_CLOCK_EXTOUTCLKSRC_t	XMC_SCU_CLOCK_GetExternalOutputClockSource (void)
uint32_t	XMC_SCU_CLOCK_GetHighPerformanceOscillatorGeneralPurposeInputStatus (void)
uint32_t	XMC_SCU_CLOCK_GetLowPowerOscillatorGeneralPurposeInputStatus (void)
uint32_t	XMC_SCU_CLOCK_GetPeripheralClockDivider (void)
uint32_t	XMC_SCU_CLOCK_GetPeripheralClockFrequency (void)
uint32_t	XMC_SCU_CLOCK_GetSystemClockDivider (void)
uint32_t	XMC_SCU_CLOCK_GetSystemClockFrequency (void)
XMC_SCU_CLOCK_SYSCLKSRC_t	XMC_SCU_CLOCK_GetSystemClockSource (void)
uint32_t	XMC_SCU_CLOCK_GetSystemPllClockFrequency (void)
XMC_SCU_CLOCK_SYSPLLCLKSRC_t	XMC_SCU_CLOCK_GetSystemPllClockSource (void)
uint32_t	XMC_SCU_CLOCK_GetSystemPllClockSourceFrequency (void)
uint32_t	XMC_SCU_CLOCK_GetUsbClockDivider (void)
uint32_t	XMC_SCU_CLOCK_GetUsbClockFrequency (void)
XMC_SCU_CLOCK_USBCLKSRC_t	XMC_SCU_CLOCK_GetUsbClockSource (void)
uint32_t	XMC_SCU_CLOCK_GetUsbPllClockFrequency (void)
uint32_t	XMC_SCU_CLOCK_GetWdtClockDivider (void)
uint32_t	XMC_SCU_CLOCK_GetWdtClockFrequency (void)
XMC_SCU_CLOCK_WDTCLKSRC_t	XMC_SCU_CLOCK_GetWdtClockSource (void)
void	XMC_SCU_CLOCK_Init (const XMC_SCU_CLOCK_CONFIG_t *const config)
bool	XMC_SCU_CLOCK_IsClockEnabled (const XMC_SCU_CLOCK_t clock)
bool	XMC_SCU_CLOCK_IsHighPerformanceOscillatorStable (void)
bool	XMC_SCU_CLOCK_IsLowPowerOscillatorStable (void)
bool	XMC_SCU_CLOCK_IsPeripheralClockGated (const XMC_SCU_PERIPHERAL_CLOCK_t peripheral)
bool	XMC_SCU_CLOCK_IsSystemPllLocked (void)
bool	XMC_SCU_CLOCK_IsUsbPllLocked (void)
void	XMC_SCU_CLOCK_SetBackupClockCalibrationMode (XMC_SCU_CLOCK_FOFI_CALIBRATION_MODE_t mode)
void	XMC_SCU_CLOCK_SetCcuClockDivider (const uint32_t ratio)
void	XMC_SCU_CLOCK_SetCpuClockDivider (const uint32_t ratio)
void	XMC_SCU_CLOCK_SetDeepSleepConfig (int32_t config)
void	XMC_SCU_CLOCK_SetEbuClockDivider (const uint32_t ratio)
void	XMC_SCU_CLOCK_SetECATClockDivider (const uint32_t divider)
void	XMC_SCU_CLOCK_SetECATClockSource (const XMC_SCU_CLOCK_ECATCLKSRC_t source)
void	XMC_SCU_CLOCK_SetExternalOutputClockDivider (const uint32_t ratio)
void	XMC_SCU_CLOCK_SetExternalOutputClockSource (const XMC_SCU_CLOCK_EXTOUTCLKSRC_t clock)
void	XMC_SCU_CLOCK_SetPeripheralClockDivider (const uint32_t ratio)
void	XMC_SCU_CLOCK_SetSleepConfig (int32_t config)
void	XMC_SCU_CLOCK_SetSystemClockDivider (const uint32_t divider)
void	XMC_SCU_CLOCK_SetSystemClockSource (const XMC_SCU_CLOCK_SYSCLKSRC_t source)
void	XMC_SCU_CLOCK_SetSystemPllClockSource (const XMC_SCU_CLOCK_SYSPLLCLKSRC_t source)
void	XMC_SCU_CLOCK_SetUsbClockDivider (const uint32_t ratio)
void	XMC_SCU_CLOCK_SetUsbClockSource (const XMC_SCU_CLOCK_USBCLKSRC_t source)
void	XMC_SCU_CLOCK_SetWdtClockDivider (const uint32_t ratio)
void	XMC_SCU_CLOCK_SetWdtClockSource (const XMC_SCU_CLOCK_WDTCLKSRC_t source)
void	XMC_SCU_CLOCK_StartSystemPll (XMC_SCU_CLOCK_SYSPLLCLKSRC_t source, XMC_SCU_CLOCK_SYSPLL_MODE_t mode, uint32_t pdiv, uint32_t ndiv, uint32_t kdiv)
void	XMC_SCU_CLOCK_StartUsbPll (uint32_t pdiv, uint32_t ndiv)
void	XMC_SCU_CLOCK_StepSystemPllFrequency (uint32_t kdiv)
void	XMC_SCU_CLOCK_StopSystemPll (void)
void	XMC_SCU_CLOCK_StopUsbPll (void)
void	XMC_SCU_CLOCK_UngatePeripheralClock (const XMC_SCU_PERIPHERAL_CLOCK_t peripheral)
void	XMC_SCU_DisableOutOfRangeComparator (const uint32_t group, const uint32_t channel)
void	XMC_SCU_DisableTemperatureSensor (void)
void	XMC_SCU_EnableOutOfRangeComparator (const uint32_t group, const uint32_t channel)
void	XMC_SCU_EnableTemperatureSensor (void)
uint32_t	XMC_SCU_GetBootMode (void)
uint32_t	XMC_SCU_GetMirrorStatus (void)
uint32_t	XMC_SCU_GetTemperatureMeasurement (void)
void	XMC_SCU_HIB_ClearEventStatus (int32_t event)
void	XMC_SCU_HIB_ClearWakeupEventDetectionStatus (void)
void	XMC_SCU_HIB_DisableEvent (int32_t event)
void	XMC_SCU_HIB_DisableHibernateDomain (void)
void	XMC_SCU_HIB_DisableInternalSlowClock (void)
void	XMC_SCU_HIB_EnableEvent (int32_t event)
void	XMC_SCU_HIB_EnableHibernateDomain (void)
void	XMC_SCU_HIB_EnableInternalSlowClock (void)
void	XMC_SCU_HIB_EnterHibernateState (void)
void	XMC_SCU_HIB_EnterHibernateStateEx (XMC_SCU_HIB_HIBERNATE_MODE_t mode)
int32_t	XMC_SCU_HIB_GetEventStatus (void)
int32_t	XMC_SCU_HIB_GetHibernateControlStatus (void)
XMC_SCU_HIB_RTCCLKSRC_t	XMC_SCU_HIB_GetRtcClockSource (void)
XMC_SCU_HIB_RTCCLKSRC_t	XMC_SCU_HIB_GetStdbyClockSource (void)
bool	XMC_SCU_HIB_IsHibernateDomainEnabled (void)
bool	XMC_SCU_HIB_IsWakeupEventDetected (void)
void	XMC_SCU_HIB_LPAC_ClearStatus (int32_t status)
int32_t	XMC_SCU_HIB_LPAC_GetStatus (void)
void	XMC_SCU_HIB_LPAC_SetHIBIO0Thresholds (uint8_t lower, uint8_t upper)
void	XMC_SCU_HIB_LPAC_SetHIBIO1Thresholds (uint8_t lower, uint8_t upper)
void	XMC_SCU_HIB_LPAC_SetInput (XMC_SCU_HIB_LPAC_INPUT_t input)
void	XMC_SCU_HIB_LPAC_SetTiming (bool enable_delay, uint16_t interval_count, uint8_t settle_count)
void	XMC_SCU_HIB_LPAC_SetTrigger (XMC_SCU_HIB_LPAC_TRIGGER_t trigger)
void	XMC_SCU_HIB_LPAC_SetVBATThresholds (uint8_t lower, uint8_t upper)
void	XMC_SCU_HIB_LPAC_TriggerCompare (XMC_SCU_HIB_LPAC_INPUT_t input)
void	XMC_SCU_HIB_SetInput0 (XMC_SCU_HIB_IO_t pin)
void	XMC_SCU_HIB_SetPinMode (XMC_SCU_HIB_IO_t pin, XMC_SCU_HIB_PIN_MODE_t mode)
void	XMC_SCU_HIB_SetPinOutputLevel (XMC_SCU_HIB_IO_t pin, XMC_SCU_HIB_IO_OUTPUT_LEVEL_t level)
void	XMC_SCU_HIB_SetRtcClockSource (const XMC_SCU_HIB_RTCCLKSRC_t source)
void	XMC_SCU_HIB_SetSR0Input (XMC_SCU_HIB_SR0_INPUT_t input)
void	XMC_SCU_HIB_SetStandbyClockSource (const XMC_SCU_HIB_STDBYCLKSRC_t source)
void	XMC_SCU_HIB_SetWakeupTriggerInput (XMC_SCU_HIB_IO_t pin)
void	XMC_SCU_HIB_TriggerEvent (int32_t event)
bool	XMC_SCU_HighTemperature (void)
void	XMC_SCU_INTERRUPT_ClearEventStatus (const XMC_SCU_INTERRUPT_EVENT_t event)
void	XMC_SCU_INTERRUPT_DisableEvent (const XMC_SCU_INTERRUPT_EVENT_t event)
void	XMC_SCU_INTERRUPT_DisableNmiRequest (const uint32_t request)
void	XMC_SCU_INTERRUPT_EnableEvent (const XMC_SCU_INTERRUPT_EVENT_t event)
void	XMC_SCU_INTERRUPT_EnableNmiRequest (const uint32_t request)
XMC_SCU_STATUS_t	XMC_SCU_INTERRUPT_SetEventHandler (const XMC_SCU_INTERRUPT_EVENT_t event, const XMC_SCU_INTERRUPT_EVENT_HANDLER_t handler)
void	XMC_SCU_INTERRUPT_TriggerEvent (const XMC_SCU_INTERRUPT_EVENT_t event)
XMC_SCU_INTERRUPT_EVENT_t	XMC_SCU_INTERUPT_GetEventStatus (void)
void	XMC_SCU_IRQHandler (uint32_t sr_num)
bool	XMC_SCU_IsTemperatureSensorBusy (void)
bool	XMC_SCU_IsTemperatureSensorEnabled (void)
bool	XMC_SCU_IsTemperatureSensorReady (void)
bool	XMC_SCU_LowTemperature (void)
void	XMC_SCU_PARITY_ClearStatus (const uint32_t memory)
void	XMC_SCU_PARITY_Disable (const uint32_t memory)
void	XMC_SCU_PARITY_DisableTrapGeneration (const uint32_t memory)
void	XMC_SCU_PARITY_Enable (const uint32_t memory)
void	XMC_SCU_PARITY_EnableTrapGeneration (const uint32_t memory)
uint32_t	XMC_SCU_PARITY_GetStatus (void)
void	XMC_SCU_POWER_DisableMonitor (void)
void	XMC_SCU_POWER_DisableUsb (void)
void	XMC_SCU_POWER_EnableMonitor (uint8_t threshold, uint8_t interval)
void	XMC_SCU_POWER_EnableUsb (void)
float	XMC_SCU_POWER_GetEVR13Voltage (void)
float	XMC_SCU_POWER_GetEVR33Voltage (void)
int32_t	XMC_SCU_POWER_GetEVRStatus (void)
void	XMC_SCU_POWER_WaitForEvent (XMC_SCU_POWER_MODE_t mode)
void	XMC_SCU_POWER_WaitForInterrupt (XMC_SCU_POWER_MODE_t mode, bool sleep_on_exit)
uint32_t	XMC_SCU_ReadFromRetentionMemory (uint32_t address)
uint32_t	XMC_SCU_ReadGPR (const uint32_t index)
void	XMC_SCU_RESET_AssertPeripheralReset (const XMC_SCU_PERIPHERAL_RESET_t peripheral)
void	XMC_SCU_RESET_ClearDeviceResetReason (void)
void	XMC_SCU_RESET_DeassertPeripheralReset (const XMC_SCU_PERIPHERAL_RESET_t peripheral)
uint32_t	XMC_SCU_RESET_GetDeviceResetReason (void)
bool	XMC_SCU_RESET_IsPeripheralResetAsserted (const XMC_SCU_PERIPHERAL_RESET_t peripheral)
void	XMC_SCU_SetBootMode (const XMC_SCU_BOOTMODE_t mode)
void	XMC_SCU_SetCcuTriggerHigh (const uint32_t trigger)
void	XMC_SCU_SetCcuTriggerLow (const uint32_t trigger)
void	XMC_SCU_SetRawTempLimits (const uint32_t lower_temp, const uint32_t upper_temp)
XMC_SCU_STATUS_t	XMC_SCU_StartTemperatureMeasurement (void)
void	XMC_SCU_TRAP_ClearStatus (const uint32_t trap)
void	XMC_SCU_TRAP_Disable (const uint32_t trap)
void	XMC_SCU_TRAP_Enable (const uint32_t trap)
uint32_t	XMC_SCU_TRAP_GetStatus (void)
void	XMC_SCU_TRAP_Trigger (const uint32_t trap)
void	XMC_SCU_WriteGPR (const uint32_t index, const uint32_t data)
void	XMC_SCU_WriteToRetentionMemory (uint32_t address, uint32_t data)

Detailed Description

System control unit is the SoC power, reset and a clock manager with additional responsibility of providing system stability protection and other auxiliary functions.
SCU provides the following features,

1. Power control
2. Hibernate control
3. Reset control
4. Clock control
5. Miscellaneous control(boot mode, system interrupts etc.)
   
   

The SCU driver is divided in to clock control logic, reset control logic, system interrupt control logic , hibernate control logic, trap control logic, parity control logic and miscellaneous control logic.

Clock driver features:

1. Allows clock configuration using the structure XMC_SCU_CLOCK_CONFIG_t and API XMC_SCU_CLOCK_Init()
2. Provides structure XMC_SCU_CLOCK_SYSPLL_CONFIG_t for configuring the system PLL
3. Allows selection of clock source for system PLL, XMC_SCU_CLOCK_GetSystemPllClockSource()
4. Provides APIs for configuring different module clock frequencies XMC_SCU_CLOCK_SetWdtClockDivider(), XMC_SCU_CLOCK_SetUsbClockDivider()
5. Allows selection of clock source for external output, XMC_SCU_CLOCK_SetExternalOutputClockSource()
6. Provides APIs for enabling external high power oscillator and ultra low power oscillator, XMC_SCU_CLOCK_EnableHighPerformanceOscillator(), XMC_SCU_CLOCK_EnableLowPowerOscillator()
7. Provides APIs for getting various clock frequencies XMC_SCU_CLOCK_GetPeripheralClockFrequency(), XMC_SCU_CLOCK_GetCpuClockFrequency(), XMC_SCU_CLOCK_GetSystemClockFrequency()
   

Reset driver features:

1. Allows to handle peripheral reset XMC_SCU_RESET_AssertPeripheralReset(), XMC_SCU_RESET_DeassertPeripheralReset()
2. Allows configuration of NMI generation for selected events, XMC_SCU_INTERRUPT_EnableNmiRequest()
   

Interrupt driver features:

1. Provides APIs for enabling/ disabling interrupt event generation XMC_SCU_INTERRUPT_EnableEvent(), XMC_SCU_INTERRUPT_DisableEvent()
2. Provides API for registering callback function for events XMC_SCU_INTERRUPT_SetEventHandler()
   

Hibernate driver features:

1. Allows configuration of hibernate domain XMC_SCU_HIB_EnableHibernateDomain(), XMC_SCU_HIB_DisableHibernateDomain()
2. Allows selection of standby clock source, XMC_SCU_HIB_SetStandbyClockSource()
3. Allows selection of RTC clock source, XMC_SCU_HIB_SetRtcClockSource()
4. Provides API for enabling slow internal clock used for backup clock, XMC_SCU_HIB_EnableInternalSlowClock()
   

Trap driver features:

1. Allows handling of trap XMC_SCU_TRAP_Enable(), XMC_SCU_TRAP_GetStatus(), XMC_SCU_TRAP_Trigger()
   

Parity driver features:

1. Parity error generated by on-chip RAM can be monitored, XMC_SCU_PARITY_Enable(), XMC_SCU_PARITY_GetStatus()
2. Allows configuration of trap generation on detection of parity error, XMC_SCU_PARITY_EnableTrapGeneration()

Power driver features:

1. Allows to power the USB module XMC_SCU_POWER_EnableUsb(), XMC_SCU_POWER_DisableUsb()

Miscellaneous features:

1. Allows to trigger multiple capture compare unit(CCU) channels to be started together XMC_SCU_SetCcuTriggerHigh()
2. Enables configuration of out of range comparator (ORC) XMC_SCU_EnableOutOfRangeComparator()
3. Enables configuration of die temperature sensor XMC_SCU_EnableTemperatureSensor(), XMC_SCU_CalibrateTemperatureSensor()
4. Enables configuration of device boot mode XMC_SCU_SetBootMode()
   

Macro Definition Documentation

#define XMC_SCU_INTERRUPT_EVENT_DLR_OVERRUN   SCU_INTERRUPT_SRSTAT_DLROVR_Msk

DLR overrun event.

#define XMC_SCU_INTERRUPT_EVENT_HDCLR_UPDATED   SCU_INTERRUPT_SRSTAT_HDCLR_Msk

HIB HDCLR register update event.

#define XMC_SCU_INTERRUPT_EVENT_HDCR_UPDATED   SCU_INTERRUPT_SRSTAT_HDCR_Msk

HIB HDCR register update event.

#define XMC_SCU_INTERRUPT_EVENT_HDSET_UPDATED   SCU_INTERRUPT_SRSTAT_HDSET_Msk

HIB HDSET register update event.

#define XMC_SCU_INTERRUPT_EVENT_OSCSICTRL_UPDATED   SCU_INTERRUPT_SRSTAT_OSCSICTRL_Msk

HIB OSCSICTRL register update event.

#define XMC_SCU_INTERRUPT_EVENT_OSCULCTRL_UPDATED   SCU_INTERRUPT_SRSTAT_OSCULCTRL_Msk

HIB OSCULCTRL register update event.

#define XMC_SCU_INTERRUPT_EVENT_RMX_UPDATED   SCU_INTERRUPT_SRSTAT_RMX_Msk

HIB RMX register update event.

#define XMC_SCU_INTERRUPT_EVENT_RTC_ALARM   SCU_INTERRUPT_SRSTAT_AI_Msk

RTC alarm event.

#define XMC_SCU_INTERRUPT_EVENT_RTC_PERIODIC   SCU_INTERRUPT_SRSTAT_PI_Msk

RTC periodic interrupt.

#define XMC_SCU_INTERRUPT_EVENT_RTCATIM0_UPDATED   SCU_INTERRUPT_SRSTAT_RTC_ATIM0_Msk

HIB RTCATIM0 register update event.

#define XMC_SCU_INTERRUPT_EVENT_RTCATIM1_UPDATED   SCU_INTERRUPT_SRSTAT_RTC_ATIM1_Msk

HIB RTCATIM1 register update event.

#define XMC_SCU_INTERRUPT_EVENT_RTCCTR_UPDATED   SCU_INTERRUPT_SRSTAT_RTC_CTR_Msk

HIB RTCCTR register update event.

#define XMC_SCU_INTERRUPT_EVENT_RTCTIM0_UPDATED   SCU_INTERRUPT_SRSTAT_RTC_TIM0_Msk

HIB TIM0 register update event.

#define XMC_SCU_INTERRUPT_EVENT_RTCTIM1_UPDATED   SCU_INTERRUPT_SRSTAT_RTC_TIM1_Msk

HIB TIM1 register update event.

#define XMC_SCU_INTERRUPT_EVENT_WDT_WARN   SCU_INTERRUPT_SRSTAT_PRWARN_Msk

Watchdog prewarning event.

Typedef Documentation

typedef void(* XMC_SCU_INTERRUPT_EVENT_HANDLER_t) (void)

Function pointer type used for registering callback functions on SCU event occurrence.

typedef uint32_t XMC_SCU_INTERRUPT_EVENT_t

Defines enumerations for events which can lead to interrupt. These enumeration values represent the status of one of the bits in SRSTAT register. Use type XMC_SCU_INTERRUPT_EVENT_t for accessing these enum parameters.

Enumeration Type Documentation

enum XMC_SCU_BOOTMODE_t

Defines options for selecting device boot mode. These enums are used to configure SWCON bits of STCON register. User can choose among various boot modes by configuring SWCON bits. Use type XMC_SCU_BOOTMODE_t for accessing these enum parameters.

Enumerator
XMC_SCU_BOOTMODE_NORMAL	Boot from start of flash.
XMC_SCU_BOOTMODE_ASC_BSL	UART bootstrap.
XMC_SCU_BOOTMODE_BMI	Boot Mode Index - Customized boot sequence.
XMC_SCU_BOOTMODE_CAN_BSL	CAN bootstrap.
XMC_SCU_BOOTMODE_PSRAM_BOOT	Boot from PSRAM.
XMC_SCU_BOOTMODE_ABM0	Boot from flash - fixed alternative address 0.
XMC_SCU_BOOTMODE_ABM1	Boot from flash - fixed alternative address 1.
XMC_SCU_BOOTMODE_FABM	fallback Alternate Boot Mode (ABM) - Try ABM-0 then try ABM-1.

enum XMC_SCU_CCU_TRIGGER_t

Defines Capture/Compare unit timer slice trigger, that enables synchronous start function available on the SCU, CCUCON register. Use type XMC_SCU_CCU_TRIGGER_t for accessing these enum parameters.

Enumerator
XMC_SCU_CCU_TRIGGER_CCU40	Trigger mask used for Global Start Control of CCU40 peripheral.
XMC_SCU_CCU_TRIGGER_CCU80	Trigger mask used for Global Start Control of CCU80 peripheral.

enum XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_t

Defines the source of the system clock and peripherals clock gating in DEEPSLEEP state. In addition the state of FLASH, PLL and PLLVCO during DEEPSLEEP state. Use this enum as parameter of XMC_SCU_CLOCK_SetDeepSleepConfig before going to DEEPSLEEP state.

The DEEPSLEEP state of the system corresponds to the DEEPSLEEP state of the CPU. The state is entered via WFI or WFE instruction of the CPU. In this state the clock to the CPU is stopped.

In Deep Sleep state the OSC_HP and the PLL may be switched off. The wake-up logic in the NVIC is still clocked by a free-running clock. Peripherals are only clocked when configured to stay enabled. Configuration of peripherals and any SRAM content is preserved. The Flash module can be put into low-power mode to achieve a further power reduction. On wake-up Flash module will be restarted again before instructions or data access is possible. Any interrupt will bring the system back to operation via the NVIC.The clock setup before entering Deep Sleep state is restored upon wake-up.

Enumerator
XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_SYSCLK_FOFI	fOFI used as system clock source in DEEPSLEEP state
XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_SYSCLK_FPLL	fPLL used as system clock source in DEEPSLEEP state
XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_FLASH_POWERDOWN	Flash power down in DEEPSLEEP state
XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_PLL_POWERDOWN	Switch off main PLL in DEEPSLEEP state
XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_VCO_POWERDOWN	Switch off VCO of main PLL in DEEPSLEEP state
XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_DISABLE_USB	USB clock disabled in DEEPSLEEP state
XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_ENABLE_USB	USB clock enabled in DEEPSLEEP state
XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_DISABLE_SDMMC	SDMMC clock disabled in DEEPSLEEP state
XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_ENABLE_SDMMC	SDMMC clock enabled in DEEPSLEEP state
XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_DISABLE_ETH	ETH clock disabled in DEEPSLEEP state
XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_ENABLE_ETH	ETH clock enabled in DEEPSLEEP state
XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_DISABLE_EBU	EBU clock disabled in DEEPSLEEP state
XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_ENABLE_EBU	EBU clock enabled in DEEPSLEEP state
XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_DISABLE_CCU	CCU clock disabled in DEEPSLEEP state
XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_ENABLE_CCU	CCU clock enabled in DEEPSLEEP state
XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_DISABLE_WDT	WDT clock disabled in DEEPSLEEP state
XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_ENABLE_WDT	WDT clock enabled in DEEPSLEEP state

enum XMC_SCU_CLOCK_ECATCLKSRC_t

Defines options for selecting the ECAT clock source.

Enumerator
XMC_SCU_CLOCK_ECATCLKSRC_USBPLL	USB PLL (fUSBPLL) as a source for ECAT clock.
XMC_SCU_CLOCK_ECATCLKSRC_SYSPLL	Main PLL output (fPLL) as a source for ECAT clock.

enum XMC_SCU_CLOCK_EXTOUTCLKSRC_t

Defines options for selecting the source of external clock out (fEXT). These enums are used to configure ECKSEL bits of EXTCLKCR register. User can choose either fSYS or fPLL or fUSBPLL clock as a source for external clock out (fEXT). Use type XMC_SCU_CLOCK_EXTOUTCLKSRC_t for accessing these enum parameters.

Enumerator
XMC_SCU_CLOCK_EXTOUTCLKSRC_SYS	System clock (fSYS) as the source for external clock out (fEXT).
XMC_SCU_CLOCK_EXTOUTCLKSRC_USB	USB PLL output(fUSB PLL) as the source for external clock out (fEXT).
XMC_SCU_CLOCK_EXTOUTCLKSRC_PLL	Main PLL output(fPLL) as the source for external clock out (fEXT).

enum XMC_SCU_CLOCK_FOFI_CALIBRATION_MODE_t

Defines options for backup clock trimming. These enums are used to configure AOTREN FOTR bits of PLLCON0 register. Use type XMC_SCU_CLOCK_BACKUP_TRIM_t for accessing these enum parameters.

Enumerator
XMC_SCU_CLOCK_FOFI_CALIBRATION_MODE_FACTORY	Factory Oscillator Calibration: Force adjustment of the internal oscillator with the firmware defined values.
XMC_SCU_CLOCK_FOFI_CALIBRATION_MODE_AUTOMATIC	Automatic Oscillator Calibration adjustment of the fOFI clock with fSTDBY clock.

enum XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_t

Defines the source of the system clock and peripherals clock gating in SLEEP state. Use this enum as parameter of XMC_SCU_CLOCK_SetSleepConfig before going to SLEEP state.

The SLEEP state of the system corresponds to the SLEEP state of the CPU. The state is entered via WFI or WFE instruction of the CPU. In this state the clock to the CPU is stopped. Peripherals are only clocked when configured to stay enabled.

Peripherals can continue to operate unaffected and eventually generate an event to wake-up the CPU. Any interrupt to the NVIC will bring the CPU back to operation. The clock tree upon exit from SLEEP state is restored to what it was before entry into SLEEP state.

Enumerator
XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_SYSCLK_FOFI	fOFI used as system clock source in SLEEP state
XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_SYSCLK_FPLL	fPLL used as system clock source in SLEEP state
XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_DISABLE_USB	USB clock disabled in SLEEP state
XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_ENABLE_USB	USB clock enabled in SLEEP state
XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_DISABLE_SDMMC	SDMMC clock disabled in SLEEP state
XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_ENABLE_SDMMC	SDMMC clock enabled in SLEEP state
XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_DISABLE_ETH	ETH clock disabled in SLEEP state
XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_ENABLE_ETH	ETH clock enabled in SLEEP state
XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_DISABLE_EBU	EBU clock disabled in SLEEP state
XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_ENABLE_EBU	EBU clock enabled in SLEEP state
XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_DISABLED_CCU	CCU clock disabled in SLEEP state
XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_ENABLE_CCU	CCU clock enabled in SLEEP state
XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_DISABLED_WDT	WDT clock disabled in SLEEP state
XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_ENABLE_WDT	WDT clock enabled in SLEEP state

enum XMC_SCU_CLOCK_SYSCLKSRC_t

Defines options for system clock (fSYS) source. These enums are used to configure SYSSEL bits of SYSCLKCR Clock Control Register. Use type XMC_SCU_CLOCK_SYSCLKSRC_t for accessing these enum parameters.

Enumerator
XMC_SCU_CLOCK_SYSCLKSRC_OFI	Internal Fast Clock (fOFI) as a source for system clock (fSYS).
XMC_SCU_CLOCK_SYSCLKSRC_PLL	PLL output (fPLL) as a source for system clock (fSYS).

enum XMC_SCU_CLOCK_SYSPLL_MODE_t

Defines various PLL modes of operation. These enums are used to configure VCOBYP bit of PLLCON0 register. User can choose either normal or prescalar mode by configuring VCOBYP bit. Use type XMC_SCU_PLL_MODE_t for accessing these enum parameters.

Enumerator
XMC_SCU_CLOCK_SYSPLL_MODE_DISABLED	fPLL derived from fOSC and PLL operating in prescalar mode(i.e.VCO bypassed).
XMC_SCU_CLOCK_SYSPLL_MODE_NORMAL	fPLL derived from fVCO and PLL operating in normal mode.
XMC_SCU_CLOCK_SYSPLL_MODE_PRESCALAR	fPLL derived from fOSC and PLL operating in prescalar mode(i.e.VCO bypassed).

enum XMC_SCU_CLOCK_SYSPLLCLKSRC_t

Defines options for selecting the P-Divider input frequency. These enums are used to configure PINSEL bits of PLLCON2 register. Use type XMC_SCU_CLOCK_OSCCLKSRC_t for accessing these enum parameters.

Enumerator
XMC_SCU_CLOCK_SYSPLLCLKSRC_OSCHP	External crystal oscillator (fOHP) as the source for P-Divider.
XMC_SCU_CLOCK_SYSPLLCLKSRC_OFI	Backup clock(fOFI) as the source for P-Divider.

enum XMC_SCU_CLOCK_t

Defines enumerations for disabling the clocks sources of peripherals. Disabling of the peripheral clock is configured via the CLKCLR registers. Use type XMC_SCU_PERIPHERAL_CLOCK_t for accessing these enum parameters.

Enumerator
XMC_SCU_CLOCK_USB	USB module clock.
XMC_SCU_CLOCK_MMC	MMC module clock.
XMC_SCU_CLOCK_ETH	Ethernet module clock.
XMC_SCU_CLOCK_EBU	EBU module clock.
XMC_SCU_CLOCK_CCU	CCU module clock.
XMC_SCU_CLOCK_WDT	WDT module clock.

enum XMC_SCU_CLOCK_USBCLKSRC_t

Defines options for selecting the USB clock source(fUSB/fSDMMC). These enums are used to configure USBSEL bits of USBCLKCR register. User can choose either fPLL or fUSBPLL clock as a source for USB clock. Use type XMC_SCU_CLOCK_USBCLKSRC_t for accessing these enum parameters.

Enumerator
XMC_SCU_CLOCK_USBCLKSRC_USBPLL	USB PLL(fUSB PLL) as a source for USB clock (fUSB/fSDMMC).
XMC_SCU_CLOCK_USBCLKSRC_SYSPLL	Main PLL output (fPLL) as a source for USB clock (fUSB/fSDMMC).

enum XMC_SCU_CLOCK_WDTCLKSRC_t

Defines options for selecting the source of WDT clock(fWDT). These enums are used to configure WDTSEL bits of WDTCLKCR register. User can choose either fOFI or fPLL or fSTDBY clock as a source for WDT clock. Use type XMC_SCU_CLOCK_USBCLKSRC_t for accessing these enum parameters.

Enumerator
XMC_SCU_CLOCK_WDTCLKSRC_OFI	Internal Fast Clock (fOFI) as the source for WDT clock (fWDT).
XMC_SCU_CLOCK_WDTCLKSRC_STDBY	Standby clock (fSTDBY) as the source for WDT clock (fWDT).
XMC_SCU_CLOCK_WDTCLKSRC_PLL	PLL output (fPLL) as the source for WDT clock (fWDT).

enum XMC_SCU_HIB_CTRL_STATUS_t

Define status of external hibernate control

Enumerator
XMC_SCU_HIB_CTRL_STATUS_NO_ACTIVE	Hibernate not driven active to pads
XMC_SCU_HIB_CTRL_STATUS_ACTIVE	Hibernate driven active to pads

enum XMC_SCU_HIB_EVENT_t

Hibernate domain event status

Enumerator
XMC_SCU_HIB_EVENT_WAKEUP_ON_POS_EDGE	Wake-up on positive edge pin event
XMC_SCU_HIB_EVENT_WAKEUP_ON_NEG_EDGE	Wake-up on negative edge pin event
XMC_SCU_HIB_EVENT_WAKEUP_ON_RTC	Wake-up on RTC event
XMC_SCU_HIB_EVENT_ULPWDG	ULP watchdog alarm status
XMC_SCU_HIB_EVENT_LPAC_VBAT_POSEDGE	Wake-up on LPAC positive edge of VBAT threshold crossing. Note Only available in XMC44, XMC42 and XMC41 series
XMC_SCU_HIB_EVENT_LPAC_VBAT_NEGEDGE	Wake-up on LPAC negative edge of VBAT threshold crossing. Note Only available in XMC44, XMC42 and XMC41 series
XMC_SCU_HIB_EVENT_LPAC_HIB_IO_0_POSEDGE	Wake-up on LPAC positive edge of HIB_IO_0 threshold crossing. Note Only available in XMC44, XMC42 and XMC41 series
XMC_SCU_HIB_EVENT_LPAC_HIB_IO_0_NEGEDGE	Wake-up on LPAC negative edge of HIB_IO_0 threshold crossing. Note Only available in XMC44, XMC42 and XMC41 series
XMC_SCU_HIB_EVENT_LPAC_HIB_IO_1_POSEDGE	Wake-up on LPAC positive edge of HIB_IO_1 threshold crossing. Note Only available in XMC44 series and LQFP100.
XMC_SCU_HIB_EVENT_LPAC_HIB_IO_1_NEGEDGE	Wake-up on LPAC negative edge of HIB_IO_1 threshold crossing. Note Only available in XMC44 series and LQFP100.

enum XMC_SCU_HIB_HIBERNATE_MODE_t

Selects hibernate mode

Enumerator
XMC_SCU_HIB_HIBERNATE_MODE_EXTERNAL	Request external hibernate mode
XMC_SCU_HIB_HIBERNATE_MODE_INTERNAL	Request internal hibernate mode. Note Only available in XMC44, XMC42 and XMC41 series

enum XMC_SCU_HIB_IO_OUTPUT_LEVEL_t

Selects the output polarity of the HIB_IOx

Enumerator
XMC_SCU_HIB_IO_OUTPUT_LEVEL_LOW	Direct value
XMC_SCU_HIB_IO_OUTPUT_LEVEL_HIGH	Inverted value

enum XMC_SCU_HIB_IO_t

Hibernate domain dedicated pins

Enumerator
XMC_SCU_HIB_IO_0	HIB_IO_0 pin. At the first power-up and with every reset of the hibernate domain this pin is configured as opendrain output and drives "0". As output the medium driver mode is active.
XMC_SCU_HIB_IO_1	HIB_IO_1 pin. At the first power-up and with every reset of the hibernate domain this pin is configured as input with no pull device active. As output the medium driver mode is active. Note : Only available in certain packages

enum XMC_SCU_HIB_LPAC_INPUT_t

HIB LPAC input selection

Enumerator
XMC_SCU_HIB_LPAC_INPUT_DISABLED	Comparator permanently in power down
XMC_SCU_HIB_LPAC_INPUT_VBAT	Comparator activated for VBAT input
XMC_SCU_HIB_LPAC_INPUT_HIB_IO_0	Comparator activated for HIB_IO_0 input
XMC_SCU_HIB_LPAC_INPUT_HIB_IO_1	Comparator activated for HIB_IO_1 input. Note Only available in XMC44 series and LQFP100 package.

enum XMC_SCU_HIB_LPAC_STATUS_t

HIB LPAC status

Enumerator
XMC_SCU_HIB_LPAC_STATUS_VBAT_COMPARE_DONE	VBAT compare operation completed
XMC_SCU_HIB_LPAC_STATUS_HIB_IO_0_COMPARE_DONE	HBI_IO_0 compare operation completed
XMC_SCU_HIB_LPAC_STATUS_HIB_IO_1_COMPARE_DONE	HBI_IO_1 compare operation completed. Note Only available in XMC44 series and LQFP100 package.
XMC_SCU_HIB_LPAC_STATUS_VBAT_ABOVE_THRESHOLD	VBAT comparison result above programmed threshold
XMC_SCU_HIB_LPAC_STATUS_HIB_IO_0_ABOVE_THRESHOLD	HBI_IO_0 comparison result above programmed threshold
XMC_SCU_HIB_LPAC_STATUS_HIB_IO_1_ABOVE_THRESHOLD	HBI_IO_1 comparison result above programmed threshold. Note Only available in XMC44 series and LQFP100 package.

enum XMC_SCU_HIB_LPAC_TRIGGER_t

HIB LPAC start trigger selection for selected inputs

Enumerator
XMC_SCU_HIB_LPAC_TRIGGER_SUBSECOND_INTERVAL_COUNTER	Sub-second interval counter
XMC_SCU_HIB_LPAC_TRIGGER_RTC_ALARM_EVENT	RTC alarm event
XMC_SCU_HIB_LPAC_TRIGGER_RTC_PERIODIC_EVENT	RTC periodic event
XMC_SCU_HIB_LPAC_TRIGGER_ON_WAKEUP_POSITIVE_EDGE_EVENT	On digital wakeup input positive edge event
XMC_SCU_HIB_LPAC_TRIGGER_ON_WAKEUP_NEGATIVE_EDGE_EVENT	On digital wakeup input negative edge event
XMC_SCU_HIB_LPAC_TRIGGER_CONTINOUS	Continuous measurement
XMC_SCU_HIB_LPAC_TRIGGER_SINGLE_SHOT	Single shot on software request

enum XMC_SCU_HIB_PIN_MODE_t

HIB_IOx pin I/O control

Enumerator
XMC_SCU_HIB_PIN_MODE_INPUT_PULL_NONE	Direct input, no input pull device connected
XMC_SCU_HIB_PIN_MODE_INPUT_PULL_DOWN	Direct input, input pull down device connected
XMC_SCU_HIB_PIN_MODE_INPUT_PULL_UP	Direct input, input pull up device connected
XMC_SCU_HIB_PIN_MODE_OUTPUT_PUSH_PULL_HIBCTRL	Push-pull HIB control output
XMC_SCU_HIB_PIN_MODE_OUTPUT_PUSH_PULL_WDTSRV	Push-pull WDT service output
XMC_SCU_HIB_PIN_MODE_OUTPUT_PUSH_PULL_GPIO	Push-pull GPIO output
XMC_SCU_HIB_PIN_MODE_OUTPUT_OPEN_DRAIN_HIBCTRL	Open drain HIB control output
XMC_SCU_HIB_PIN_MODE_OUTPUT_OPEN_DRAIN_WDTSRV	Open drain WDT service output
XMC_SCU_HIB_PIN_MODE_OUTPUT_OPEN_DRAIN_GPIO	Open drain GPIO output

enum XMC_SCU_HIB_RTCCLKSRC_t

Defines options for selecting the source of RTC Clock (fRTC). These enums are used to configure RCS bit of HDCR register. User can choose either fOSI or fULP clock as a source for RTC Clock (fRTC). Use type XMC_SCU_HIB_RTCCLKSRC_t for accessing these enum parameters.

Enumerator
XMC_SCU_HIB_RTCCLKSRC_OSI	Internal Slow Clock (fOSI) as the source for RTC Clock (fRTC).
XMC_SCU_HIB_RTCCLKSRC_ULP	Ultra Low Power Clock (fULP) as the source for RTC Clock (fRTC).

enum XMC_SCU_HIB_SR0_INPUT_t

Selects input signal HIB_SR0 of ERU0

Enumerator
XMC_SCU_HIB_SR0_INPUT_HIB_IO_0	Set HIB_SR0 to HIB_IO_0 digital input
XMC_SCU_HIB_SR0_INPUT_HIB_IO_1	Set HIB_SR0 to HIB_IO_1 digital input. Note Only available in certain packages.
XMC_SCU_HIB_SR0_INPUT_ACMP0	Set HIB_SR0 to LPAC CMP0. Note Only available in XMC44, XMC42 and XMC41 series.

enum XMC_SCU_HIB_STDBYCLKSRC_t

Defines options for selecting the source of Standby Clock (fSTDBY). These enums are used to configure STDBYSEL bit of HDCR register. User can choose either fOSI or fULP clock as a source for Standby Clock (fSTDBY). Use type XMC_SCU_HIB_STDBYCLKSRC_t for accessing these enum parameters.

Enumerator
XMC_SCU_HIB_STDBYCLKSRC_OSI	Internal Slow Clock (fOSI) as the source for Standby Clock (fSTDBY).
XMC_SCU_HIB_STDBYCLKSRC_OSCULP	Ultra Low Power Clock (fULP) as the source for Standby Clock (fSTDBY).

enum XMC_SCU_NMIREQ_t

Defines enumeration for the events that can generate non maskable interrupt(NMI). The NMI generation can be enabled with NMIREQEN register. The event will be reflected in SRSTAT or will be mirrored in the TRAPSTAT register. These enums can be used to configure NMI request generation bits of NMIREQEN register. Once configured, these events can generate non maskable interrupt. All the enum items are tabulated as per bits present in NMIREQEN register. Use type XMC_SCU_NMIREQ_t for accessing these enum parameters.

Enumerator
XMC_SCU_NMIREQ_WDT_WARN	Watchdog timer Pre-Warning event
XMC_SCU_NMIREQ_RTC_PI	RTC Periodic event
XMC_SCU_NMIREQ_RTC_AI	RTC Alarm event
XMC_SCU_NMIREQ_ERU0_0	Channel 0 event of ERU0
XMC_SCU_NMIREQ_ERU0_1	Channel 1 event of ERU0
XMC_SCU_NMIREQ_ERU0_2	Channel 2 event of ERU0
XMC_SCU_NMIREQ_ERU0_3	Channel 3 event of ERU0

enum XMC_SCU_PARITY_t

Defines enumerations for different parity event generating modules that in turn generate a trap. Parity can be enabled with PETE register in order to get the trap flag reflected in TRAPRAW register. These enums are used to configure parity error trap generation mechanism bits of PETE register. All the enum items are tabulated as per bits present in PETE register. Use type XMC_SCU_PARITY_t for accessing these enum parameters.

Enumerator
XMC_SCU_PARITY_PSRAM_MEM	Program SRAM parity error trap.
XMC_SCU_PARITY_DSRAM1_MEM	Data SRAM-1 parity error trap.
XMC_SCU_PARITY_USIC0_MEM	USIC0 memory parity error trap.
XMC_SCU_PARITY_MCAN_MEM	CAN memory parity error trap.
XMC_SCU_PARITY_PMU_MEM	PMU Prefetch memory parity error trap.
XMC_SCU_PARITY_USB_MEM	USB memory parity error trap.

enum XMC_SCU_PERIPHERAL_CLOCK_t

Defines enumeration for peripherals that support clock gating. The enumerations can be used for gating or ungating the peripheral clocks. All the enum items are tabulated as per bits present in CGATSTAT0 register. Use type XMC_SCU_PERIPHERAL_CLOCK_t for accessing these enum parameters.

Enumerator
XMC_SCU_PERIPHERAL_CLOCK_VADC	VADC peripheral gating.
XMC_SCU_PERIPHERAL_CLOCK_DSD	DSD peripheral gating.
XMC_SCU_PERIPHERAL_CLOCK_CCU40	CCU40 peripheral gating.
XMC_SCU_PERIPHERAL_CLOCK_CCU80	CCU80 peripheral gating.
XMC_SCU_PERIPHERAL_CLOCK_POSIF0	POSIF0 peripheral gating.
XMC_SCU_PERIPHERAL_CLOCK_USIC0	USIC0 peripheral gating.
XMC_SCU_PERIPHERAL_CLOCK_ERU1	ERU1 peripheral gating.
XMC_SCU_PERIPHERAL_CLOCK_HRPWM0	HRPWM0 peripheral gating.
XMC_SCU_PERIPHERAL_CLOCK_LEDTS0	LEDTS0 peripheral gating.
XMC_SCU_PERIPHERAL_CLOCK_MCAN	MCAN peripheral gating.
XMC_SCU_PERIPHERAL_CLOCK_DAC	DAC peripheral gating.
XMC_SCU_PERIPHERAL_CLOCK_SDMMC	SDMMC peripheral gating.
XMC_SCU_PERIPHERAL_CLOCK_USIC1	USIC1 peripheral gating.
XMC_SCU_PERIPHERAL_CLOCK_USIC2	USIC2 peripheral gating.
XMC_SCU_PERIPHERAL_CLOCK_PORTS	PORTS peripheral gating.
XMC_SCU_PERIPHERAL_CLOCK_WDT	WDT peripheral gating.
XMC_SCU_PERIPHERAL_CLOCK_ETH0	ETH0 peripheral gating.
XMC_SCU_PERIPHERAL_CLOCK_GPDMA0	DMA0 peripheral gating.
XMC_SCU_PERIPHERAL_CLOCK_GPDMA1	DMA1 peripheral gating.
XMC_SCU_PERIPHERAL_CLOCK_FCE	FCE peripheral gating.
XMC_SCU_PERIPHERAL_CLOCK_USB0	USB0 peripheral gating.
XMC_SCU_PERIPHERAL_CLOCK_ECAT0	ECAT0 peripheral gating.
XMC_SCU_PERIPHERAL_CLOCK_EBU	EBU peripheral gating.

enum XMC_SCU_PERIPHERAL_RESET_t

Defines enumeration representing different peripheral reset bits in the PRSTAT registers. All the enum items are tabulated as per bits present in PRSTAT0, PRSTAT1, PRSTAT2, PRSTAT3 registers. Use type XMC_SCU_PERIPHERAL_RESET_t for accessing these enum parameters. Note: Release of reset should be prevented when the peripheral clock is gated in cases where kernel clock and bus interface clocks are shared, in order to avoid system hang-up.

Enumerator
XMC_SCU_PERIPHERAL_RESET_VADC	VADC reset.
XMC_SCU_PERIPHERAL_RESET_DSD	DSD reset.
XMC_SCU_PERIPHERAL_RESET_CCU40	CCU40 reset.
XMC_SCU_PERIPHERAL_RESET_CCU80	CCU80 reset.
XMC_SCU_PERIPHERAL_RESET_POSIF0	POSIF0 reset.
XMC_SCU_PERIPHERAL_RESET_USIC0	USIC0 reset.
XMC_SCU_PERIPHERAL_RESET_ERU1	ERU1 reset.
XMC_SCU_PERIPHERAL_RESET_HRPWM0	HRPWM0 reset.
XMC_SCU_PERIPHERAL_RESET_LEDTS0	LEDTS0 reset.
XMC_SCU_PERIPHERAL_RESET_MCAN	MCAN reset.
XMC_SCU_PERIPHERAL_RESET_DAC	DAC reset.
XMC_SCU_PERIPHERAL_RESET_SDMMC	SDMMC reset.
XMC_SCU_PERIPHERAL_RESET_USIC1	USIC1 reset.
XMC_SCU_PERIPHERAL_RESET_USIC2	USIC2 reset.
XMC_SCU_PERIPHERAL_RESET_PORTS	PORTS reset.
XMC_SCU_PERIPHERAL_RESET_WDT	WDT reset.
XMC_SCU_PERIPHERAL_RESET_ETH0	ETH0 reset.
XMC_SCU_PERIPHERAL_RESET_GPDMA0	DMA0 reset.
XMC_SCU_PERIPHERAL_RESET_GPDMA1	DMA1 reset.
XMC_SCU_PERIPHERAL_RESET_FCE	FCE reset.
XMC_SCU_PERIPHERAL_RESET_USB0	USB0 reset.
XMC_SCU_PERIPHERAL_RESET_ECAT0	ECAT0 reset.
XMC_SCU_PERIPHERAL_RESET_EBU	EBU reset.

enum XMC_SCU_POWER_EVR_STATUS_t

Defines status of EVR13 regulator

Enumerator
XMC_SCU_POWER_EVR_STATUS_OK	EVR13 regulator No overvoltage condition
XMC_SCU_POWER_EVR_STATUS_EVR13_OVERVOLTAGE	EVR13 regulator is in overvoltage

enum XMC_SCU_POWER_MODE_t

Low power modes

Enumerator
XMC_SCU_POWER_MODE_SLEEP	sleep mode stops the processor clock
XMC_SCU_POWER_MODE_DEEPSLEEP	deep sleep mode stops the system clock and switches off the PLL and flash memory.

enum XMC_SCU_RESET_REASON_t

Defines the different causes for last reset. The cause of the last reset gets automatically stored in the SCU_RSTSTAT register and can be checked by user software to determine the state of the system and for debuggging purpose. All the enum items are tabulated as per bits present in SCU_RSTSTAT register. Use type XMC_SCU_RESET_REASON_t for accessing these enum parameters.

Enumerator
XMC_SCU_RESET_REASON_PORST	Reset due to Power on reset.
XMC_SCU_RESET_REASON_SWD	Reset due to Supply Watchdog reset.
XMC_SCU_RESET_REASON_PV	Reset due to Power Validation reset.
XMC_SCU_RESET_REASON_SW	Reset due to Software reset.
XMC_SCU_RESET_REASON_LOCKUP	Reset due to reset due to CPU lockup.
XMC_SCU_RESET_REASON_WATCHDOG	Reset due to Watchdog timer initiated reset.
XMC_SCU_RESET_REASON_PARITY_ERROR	Reset due to reset due to memory parity error.

enum XMC_SCU_STATUS_t

Defines the status of SCU API execution, used to verify the SCU related API calls.

Enumerator
XMC_SCU_STATUS_OK	SCU related operation successfully completed.
XMC_SCU_STATUS_ERROR	SCU related operation failed. When API cannot fulfill request, this value is returned.
XMC_SCU_STATUS_BUSY	Cannot execute the SCU related operation request because another operation is in progress. XMC_SCU_STATUS_BUSY is returned when API is busy processing another request.

enum XMC_SCU_TRAP_t

Defines enumerations representing the status of trap cause. The cause of the trap gets automatically stored in the TRAPSTAT register and can be checked by user software to determine the state of the system and for debug purpose. Use type XMC_SCU_TRAP_t for accessing these enum parameters.

Enumerator
XMC_SCU_TRAP_OSC_WDG	OSC_HP Oscillator Watchdog trap.
XMC_SCU_TRAP_VCO_LOCK	PLL loss of lock trap.
XMC_SCU_TRAP_USB_VCO_LOCK	USB PLL loss of lock trap.
XMC_SCU_TRAP_PARITY_ERROR	Memory Parity error trap.
XMC_SCU_TRAP_BROWNOUT	Brownout trap.
XMC_SCU_TRAP_ULP_WDG	Unstable 32KHz clock trap.
XMC_SCU_TRAP_PER_BRIDGE0	Bad memory access of peripherals on Bridge-0.
XMC_SCU_TRAP_PER_BRIDGE1	Bad memory access of peripherals on Bridge-1.
XMC_SCU_TRAP_ECAT_RESET	EtherCat Reset

Function Documentation

void XMC_SCU_CalibrateTemperatureSensor	(	uint32_t	offset,
		uint32_t	gain
	)

Parameters

offset	Offset value for calibrating the DTS result. Range: 0 to 127.
gain	Gain value for calibrating the DTS conversion result. Range: 0 to 63.

Returns

None

Description

Calibrates the measurement of temperature by configuring the values of offset and gain of DTSCON register.

Allows to improve the accuracy of the temperature measurement with the adjustment of OFFSET and GAIN bit fields in the DTSCON register. Offset adjustment is defined as a shift of the conversion result. The range of the offset adjustment is 7 bits with a resolution that corresponds to +/- 12.5�C. The offset value gets added to the measure result. Offset is considered as a signed value. Gain adjustment helps in minimizing gain error. When the gain value is 0, result is generated with maximum gain. When the gain value is 63, result is generated with least gain, i.e, RESULT - 63 at the highest measured temperature.
It is recommended to use following steps:

• Call XMC_SCU_StopTempMeasurement to stop temperature measurement if it was started previously.
  
• Call XMC_SCU_CalibrateTempMonitor with desired offset and gain calibration values to the DTS.
  
• Call XMC_SCU_SetRawTempLimits with desired lower and upper temperature threshold limit values if it is needed.
  
• Call XMC_SCU_StartTempMeasurement to start temperature measurement.
  
• Check whether Die Temperature Sensor (DTS) is busy in conversion by calling XMC_SCU_IsTemperatureSensorBusy() and wait till conversion complete.
  
• Read the die temperature value using XMC_SCU_GetTemperatureMeasurement API.

Related APIs:

XMC_SCU_EnableTemperatureSensor(), XMC_SCU_StartTemperatureMeasurement(), XMC_SCU_GetTemperatureMeasurement()

void XMC_SCU_CLOCK_DisableClock

(

const XMC_SCU_CLOCK_t

clock

)

Parameters

clock

Peripheral for which the clock has to be disabled. Range: Use type XMC_SCU_CLOCK_t to select the peripheral.

Returns

None

Description

Disables source clock for the peripheral selected.

The various outputs of Clock Generation Unit (CGU) can be individually disabled by setting the peripheral specific bits in the CLKCLR register.
It is recommended to use following steps to verify whether clock source of the peripheral is enabled/disabled:

• Call XMC_SCU_CLOCK_DisableClock with desired peripheral identifier.
  
• Call XMC_SCU_CLOCK_IsClockEnabled with same peripheral identifier to verify whether peripheral is enabled/disabled.
  

Related APIs:

XMC_SCU_CLOCK_EnableClock(), XMC_SCU_RESET_AssertPeripheralReset()

void XMC_SCU_CLOCK_DisableHighPerformanceOscillator

(

void

)

Returns

None

Description

Disables the high precision oscillator by disabling the external oscillator.

The API configures MODE bits of OSCHPCTRL register to 1, there by disabling the external oscillator.

Related APIs:

XMC_SCU_CLOCK_EnableHighPerformanceOscillator()

void XMC_SCU_CLOCK_DisableHighPerformanceOscillatorGeneralPurposeInput

(

void

)

Returns

None

Description

Disables XTAL1 input of OSC_ULP as general purpose input.

Related APIs:

XMC_SCU_CLOCK_EnableHighPerformanceOscillatorGeneralPurposeInput()

void XMC_SCU_CLOCK_DisableLowPowerOscillator

(

void

)

Returns

None

Description

Disables ultra low power oscillator.

It is disabled by setting the MODE bits of OSCULCTRL register to value 2. By default on power up, the ultra low power osciallator is disabled.

Related APIs:

XMC_SCU_CLOCK_EnableLowPowerOscillator()

void XMC_SCU_CLOCK_DisableLowPowerOscillatorGeneralPurposeInput

(

void

)

Returns

None

Description

Disables XTAL1 input of OSC_ULP as general purpose input.

Related APIs:

Note

The register update in HIB domain is indicated by the MIRRST register which can be polled using XMC_SCU_GetMirrorStatus()

XMC_SCU_CLOCK_EnableLowPowerOscillatorGeneralPurposeInput()

void XMC_SCU_CLOCK_DisableSystemPll

(

void

)

Returns

None

Description

Disables main PLL for system clock.

System PLL is disabled by setting the PLLPWD and VCOPWD bits of PLLCON0 register. By default the system PLL is in power saving mode. If the system PLL is explicitly enabled, the API disables the PLL and the voltage controlled oscillator(VCO) associated with it.

Related APIs:

XMC_SCU_CLOCK_EnableSystemPll(), XMC_SCU_CLOCK_StopSystemPll()

void XMC_SCU_CLOCK_DisableUsbPll

(

void

)

Returns

None

Description

Disables USB PLL for USB clock.

USB PLL is disabled by setting the PLLPWD and VCOPWD bits of USBPLLCON register. By default the USB PLL is in power saving mode. If the USB PLL is explicitly enabled, the API disables the PLL and the voltage controlled oscillator(VCO) associated with it.

Related APIs:

XMC_SCU_CLOCK_EnableUsbPll(), XMC_SCU_CLOCK_StopUsbPll()

void XMC_SCU_CLOCK_EnableClock

(

const XMC_SCU_CLOCK_t

clock

)

Parameters

clock

Peripheral for which the clock has to be enabled. Range: Use type XMC_SCU_CLOCK_t to select the peripheral.

Returns

None

Description

Enables the source clock for selected peripheral.

The various outputs of Clock Generation Unit (CGU) can be individually enabled by setting the peripheral specific bit in the CLKSET register.
It is recommended to use following steps to verify whether a source clock of peripheral is enabled/disabled:

• Call XMC_SCU_CLOCK_EnableClock() with desired peripheral identifier.
  
• Call XMC_SCU_CLOCK_IsClockEnabled() with same peripheral identifier to verify whether the clock is enabled.
  

Related APIs:

XMC_SCU_CLOCK_DisableClock(), XMC_SCU_RESET_DeassertPeripheralReset()

void XMC_SCU_CLOCK_EnableHighPerformanceOscillator

(

void

)

Returns

None

Description

Enables the high precision oscillator by configuring external crystal mode.

The API configures MODE bits of OSCHPCTRL register to 0, there by configuring the external clock input. The System Oscillator Watchdog is enabled. The user should check the status of the oscillator using XMC_SCU_CLOCK_IsHighPerformanceOscillatorStable()

Related APIs:

XMC_SCU_CLOCK_DisableHighPerformanceOscillator()

void XMC_SCU_CLOCK_EnableHighPerformanceOscillatorGeneralPurposeInput

(

void

)

Returns

None

Description

Enables XTAL1 input of OSC_ULP as general purpose input. Use XMC_SCU_CLOCK_GetHighPerformanceOscillatorGeneralPurposeInputStatus to monitor the status of OSC_HP XTAL1 pin. OSC_ULP should be disabled previously using XMC_SCU_CLOCK_DisableHighPerformanceOscillator().

Related APIs:

XMC_SCU_CLOCK_DisableHighPerformanceOscillator()

void XMC_SCU_CLOCK_EnableLowPowerOscillator

(

void

)

Returns

None

Description

Enables ultra low power oscillator(ULP).

It enables the hibernate domain, configures the ultra low power oscillator uisng the MODE bits of the OSCULCTRL register. The Mode bits will be reset to 0 to enable the low power oscillator. Mirror register update delays are handled internally. The OSC_ULP Oscillator Watchdog is enabled. The user should check the status of the oscillator using XMC_SCU_CLOCK_IsLowPowerOscillatorStable()

Related APIs:

XMC_SCU_CLOCK_DisableLowPowerOscillator() XMC_SCU_CLOCK_IsLowPowerOscillatorStable()

void XMC_SCU_CLOCK_EnableLowPowerOscillatorGeneralPurposeInput

(

void

)

Returns

None

Description

Enables XTAL1 input of OSC_ULP as general purpose input. Use XMC_SCU_CLOCK_GetLowPowerOscillatorGeneralPurposeInputStatus to monitor the status of OSC_ULP XTAL1 pin. OSC_ULP should be disabled previously using XMC_SCU_CLOCK_DisableLowPowerOscillator().

Note

The register update in HIB domain is indicated by the MIRRST register which can be polled using XMC_SCU_GetMirrorStatus()

Related APIs:

XMC_SCU_CLOCK_DisableLowPowerOscillator()

void XMC_SCU_CLOCK_EnableSystemPll

(

void

)

Returns

None

Description

Enables main PLL for system clock.

System PLL is enabled by clearing the PLLPWD and VCOPWD bits of PLLCON0 register. By default the system PLL is in power saving mode. The API enables the PLL and the voltage controlled oscillator associated with it.

Related APIs:

XMC_SCU_CLOCK_DisableSystemPll(), XMC_SCU_CLOCK_StartSystemPll()

void XMC_SCU_CLOCK_EnableUsbPll

(

void

)

Returns

None

Description

Enables USB PLL for USB clock.

USB PLL is enabled by clearing the PLLPWD and VCOPWD bits of USBPLLCON register. By default the USB PLL is in power saving mode. The API enables the PLL and the voltage controlled oscillator associated with it.

Related APIs:

XMC_SCU_CLOCK_DisableUsbPll(), XMC_SCU_CLOCK_StartUsbPll()

void XMC_SCU_CLOCK_GatePeripheralClock

(

const XMC_SCU_PERIPHERAL_CLOCK_t

peripheral

)

Parameters

peripheral

The peripheral for which the clock has to be gated. Range: Use type XMC_SCU_PERIPHERAL_CLOCK_t to identify the peripheral clock to be gated.

Returns

None

Description

Blocks the supply of clock to the selected peripheral.

Clock gating helps in reducing the power consumption. User can selectively gate the clocks of unused peripherals. fPERI is the source of clock to various peripherals. Some peripherals support clock gate. Such a gate blocks the clock supply for the selected peripheral. Software can request for individual gating of such peripheral clocks by enabling one of the SCU_CGATSET0, SCU_CGATSET1 or SCU_CGATSET2 register bitfields.

Note: Clock gating shall not be activated unless the module is in reset state. So use XMC_SCU_CLOCK_IsPeripheralClockGated() API before enabling the gating of any peripheral.

Related APIs:

XMC_SCU_CLOCK_IsPeripheralClockGated(), XMC_SCU_CLOCK_UngatePeripheralClock()

uint32_t XMC_SCU_CLOCK_GetCcuClockDivider

(

void

)

Returns

uint32_t Ratio of fCCU clock source to the value of fCCU. Range: 0 or 1.
0-> fCCU= fSYS
1-> fCCU= fSYS/2.

Description

Provides the ratio of CCU clock(fCCU) to system clock(fSYS).

The value is obtained by reading CCUDIV bit of CCUCLKCR register.

Related APIs:

XMC_SCU_CLOCK_SetCcuClockDivider()

uint32_t XMC_SCU_CLOCK_GetCcuClockFrequency

(

void

)

Returns

uint32_t CCU clock frequency in Hertz.

Description

Provides the frequency of clock(fCPU) used for CCU4, CCU8, POSIF and HRPWM.

The value is obtained from CCUDIV bits of CCUCLKCR register and system clock (fSYS) frequency. Based on these values, fCCU clock frequency is calculated using following formula:
fCCU = fSYS >> CCUDIV.

Related APIs:

XMC_SCU_CLOCK_GetCcuClockDivider(), XMC_SCU_CLOCK_GetSystemClockFrequency()

uint32_t XMC_SCU_CLOCK_GetCpuClockDivider

(

void

)

Returns

uint32_t Ratio between system clock(fSYS) and CPU clock(fCPU). Range: 0 or 1.
0-> fCPU= fSYS.
1-> fCPU= fSYS/2.

Description

Provides the ratio between system clock(fSYS) and CPU clock(fCPU).

The value is obtained by reading CPUDIV bit of CPUCLKCR register.

Related APIs:

XMC_SCU_CLOCK_SetCpuClockDivider()

uint32_t XMC_SCU_CLOCK_GetCpuClockFrequency

(

void

)

Returns

uint32_t Value of CPU clock frequency.

Description

Provides the vlaue of CPU clock frequency.

The value is stored in a global variable SystemCoreClock. It is updated when the clock configuration is done using the SCU LLD APIs. The value represents the frequency of clock used for CPU operation. Range: Value is of type uint32_t, and gives the value of frequency in Hertz.

Related APIs:

XMC_SCU_CLOCK_GetPeripheralClockFrequency(), XMC_SCU_CLOCK_GatePeripheralClock()

uint32_t XMC_SCU_CLOCK_GetEbuClockDivider

(

void

)

Returns

uint32_t Ratio of PLL clock(fPLL) to EBU clock(fEBU).
Range: 0 to 63.

Description

Provides the ratio between PLL clock(fPLL) and EBU clock(fEBU).

The value is obtained by reading EBUDIV bits of EBUCLKCR register.

Related APIs:

XMC_SCU_CLOCK_SetEbuClockDivider()

uint32_t XMC_SCU_CLOCK_GetEbuClockFrequency

(

void

)

Returns

uint32_t EBU clock frequency in Hertz.

Description

Provides the frequency of EBU clock(fEBU).

The value is derived from system PLL clock frequency(fPLL) by applying the EBU divider. It is calculated using the following formula:
fETH = fPLL /(EBUDIV+1)

Related APIs:

XMC_SCU_CLOCK_GetEbuClockDivider(), XMC_SCU_CLOCK_GetSystemPllClockFrequency()

uint32_t XMC_SCU_CLOCK_GetECATClockDivider

(

void

)

Returns

uint32_t Ratio between the source of ECAT clock and the ECAT clock.
Range: 0 to 3.

Description

Provides the ratio between the ECAT parent clock and the ECAT clock.

The value is obtained by reading ECADIV bits of ECATCLKCR register.

Related APIs:

XMC_SCU_CLOCK_SetECATClockSource(), XMC_SCU_CLOCK_SetECATClockDivider()

XMC_SCU_CLOCK_ECATCLKSRC_t XMC_SCU_CLOCK_GetECATClockSource

(

void

)

Returns

XMC_SCU_CLOCK_ECATCLKSRC_t Source of ECAT clock.
Range: Use type XMC_SCU_CLOCK_ECATCLKSRC_t to identify the clock source.
XMC_SCU_CLOCK_ECATCLKSRC_USBPLL - USB PLL (fUSBPLL) as a source for ECAT clock.
XMC_SCU_CLOCK_ECATCLKSRC_SYSPLL - Main PLL output (fPLL) as a source for ECAT clock.

Description

Provides the source of ECAT clock (fECAT). The value is obtained by reading ECATSEL bit of ECATCLKCR register.

Related APIs:

XMC_SCU_HIB_SetRtcClockSource()

uint32_t XMC_SCU_CLOCK_GetEthernetClockFrequency

(

void

)

Returns

uint32_t Ethernet clock frequency in Hertz.

Description

Provides the frequency of Ethernet clock(fETH).

The value is derived from system clock frequency(fSYS). It is calculated using the following formula:
fETH = fSYS >> 1;

Related APIs:

XMC_SCU_CLOCK_GetSystemClockFrequency()

uint32_t XMC_SCU_CLOCK_GetExternalOutputClockDivider

(

void

)

Returns

uint32_t Ratio between the external output parent clock selected and the output clock.
Range: 0 to 511.

Description

Provides the divider value applied on parent clock before the generation of external output clock.

The value is obtained by reading EXTDIV bit of EXTCLKCR register.

Related APIs:

XMC_SCU_CLOCK_GetExternalOutputClockSource(), XMC_SCU_CLOCK_SetExternalOutputClockDivider()

uint32_t XMC_SCU_CLOCK_GetExternalOutputClockFrequency

(

void

)

Returns

uint32_t External clock out frequency in Hertz.

Description

Provides the frequency of external output clock(fEXT).

The value is derived using ECKDIV bits of EXCLKCR register and external clock out source. Based on these values, it is calculated using the following formula:
if external clock out source = System clock: fEXT = fSYS.
if external clock out source = PLL: fEXT = fPLL/(ECKDIV + 1).
if external clock out source = USBPLL: fEXT = fUSBPLL/(ECKDIV + 1).

Related APIs:

XMC_SCU_CLOCK_GetExternalOutputClockDivider(), XMC_SCU_CLOCK_GetExternalOutputClockSource()

XMC_SCU_CLOCK_EXTOUTCLKSRC_t XMC_SCU_CLOCK_GetExternalOutputClockSource

(

void

)

Returns

XMC_SCU_CLOCK_EXTOUTCLKSRC_t Source of external clock output(fEXT).
Range: Use type XMC_SCU_CLOCK_EXTOUTCLKSRC_t to identify the clock.
XMC_SCU_CLOCK_EXTOUTCLKSRC_SYS - system clock fSYS.
XMC_SCU_CLOCK_EXTOUTCLKSRC_USB - USB clock fUSB.
XMC_SCU_CLOCK_EXTOUTCLKSRC_PLL - PLL output fPLL.

Description

Provides the source of external clock output(fEXT).

The value is obtained by reading ECKSEL bits of EXTCLKCR register.

Related APIs:

XMC_SCU_CLOCK_SetExternalOutputClockSource(), XMC_SCU_CLOCK_SetExternalOutputClockDivider()

uint32_t XMC_SCU_CLOCK_GetHighPerformanceOscillatorGeneralPurposeInputStatus

(

void

)

Returns

Status OSC_HP XTAL1 pin

Description

Monitor the status of OSC_HP XTAL1 pin.

Related APIs:

XMC_SCU_CLOCK_EnableHighPerformanceOscillatorGeneralPurposeInput()

uint32_t XMC_SCU_CLOCK_GetLowPowerOscillatorGeneralPurposeInputStatus

(

void

)

Returns

Status OSC_ULP XTAL1 pin

Description

Monitor the status of OSC_ULP XTAL1 pin.

Related APIs:

XMC_SCU_CLOCK_EnableLowPowerOscillatorGeneralPurposeInput()

uint32_t XMC_SCU_CLOCK_GetPeripheralClockDivider

(

void

)

Returns

uint32_t Ratio of peripheral clock source to the value of peripheral clock.
Range: 0 or 1.
0-> fPERIPH= fCPU.
1-> fPERIPH= fCPU/2.

Description

Provides the ratio of CPU clock(fCPU) to peripheral clock(fPERIPH).

The value is obtained by reading PBDIV bit of PBCLKCR register.

Related APIs:

XMC_SCU_CLOCK_SetPeripheralClockDivider()

uint32_t XMC_SCU_CLOCK_GetPeripheralClockFrequency

(

void

)

Returns

uint32_t Value of peripheral clock frequency in Hertz.

Description

Provides the vlaue of clock frequency at which the peripherals are working.

The value is derived from the CPU frequency. Range: Value is of type uint32_t. It is represented in Hertz.

Related APIs:

XMC_SCU_CLOCK_GetCpuClockFrequency(),XMC_SCU_CLOCK_GatePeripheralClock()

uint32_t XMC_SCU_CLOCK_GetSystemClockDivider

(

void

)

Returns

uint32_t Ratio of fSYS clock source to the value of fSYS. Range: 0 to 255.

Description

Provides the value of ratio between the source of system clock to the the value of system clock frequency.

The value is obtained by reading SYSDIV bits of SYSCLKCR register.

Related APIs:

XMC_SCU_CLOCK_SetSystemClockDivider(), XMC_SCU_CLOCK_SetSystemClockSource()

uint32_t XMC_SCU_CLOCK_GetSystemClockFrequency

(

void

)

Returns

uint32_t System clock frequency in Hertz.

Description

Provides the frequency of system clock (fSYS).

The value obtained by dividing CPUDIV bits information of CPUCLKCR register with SystemCoreClock (fCPU) value.
Based on these values, fSYS clock frequency is derived using the following formula:
fSYS = fCPU << CPUDIV.

Related APIs:

XMC_SCU_CLOCK_GetUsbPllClockFrequency()

XMC_SCU_CLOCK_SYSCLKSRC_t XMC_SCU_CLOCK_GetSystemClockSource

(

void

)

Returns

XMC_SCU_CLOCK_SYSCLKSRC_t Source of clock for fSYS.
Range: Use type XMC_SCU_CLOCK_SYSCLKSRC_t to select the source of clock.
XMC_SCU_CLOCK_SYSCLKSRC_OFI - internal fast clock selected as fSYS.
XMC_SCU_CLOCK_SYSCLKSRC_PLL - output of PLL fPLL selected as fSYS.

Description

Provides the selected source of system clock (fSYS).

Selected source of fSYS is obtained by reading SYSSEL bits of SYSCLKCR register.

Related APIs:

XMC_SCU_CLOCK_SetSystemClockSource(), XMC_SCU_CLOCK_GetSystemPllClockSourceFrequency()

uint32_t XMC_SCU_CLOCK_GetSystemPllClockFrequency

(

void

)

Returns

uint32_t System frequency in Hertz.
Range: clock frequency in Hertz. Range of the value depends on the source clock frequency and the configured values of dividers.

Description

Provides the value of system PLL output clock frequency(fPLL).

The API uses N-DIV, P-DIV, K1-DIV, K2-DIV bits information from PLLCON1 register and VCOBYP bit information from PLLCON0 register. It calculates frequency of system pll clock using following formula: If normal Mode : fPLL = (fOSC * N)/(P * K2). If prescaler mode: fPLL = fOSC/ K1.

Related APIs:

XMC_SCU_CLOCK_SetSystemClockSource()

XMC_SCU_CLOCK_SYSPLLCLKSRC_t XMC_SCU_CLOCK_GetSystemPllClockSource

(

void

)

Returns

XMC_SCU_CLOCK_OSCCLKSRC_t Source of clock for system PLL.
Range: Use type XMC_SCU_CLOCK_SYSPLLCLKSRC_t for identifying the clock source.
XMC_SCU_CLOCK_SYSPLLCLKSRC_OSCHP - External High performance oscillator(fOHP).
XMC_SCU_CLOCK_SYSPLLCLKSRC_OFI - Internal fast clock (fOFI).

Description

Provides the source of system PLL clock (fPLL).

The value is obtained by reading VCOBYP bit of PLLCON0 register.

Related APIs:

XMC_SCU_CLOCK_EnableHighPerformanceOscillator(), XMC_SCU_CLOCK_SetSystemPllClockSource()

uint32_t XMC_SCU_CLOCK_GetSystemPllClockSourceFrequency

(

void

)

Returns

uint32_t Source clock used for deriving system clock.
Range: fOHP frequency if external high precision frequency is used.
fOFI fast internal clock frequency.

Description

Provides the value of the input clock frequency for deriving the system clock. The API retrieves frequency of system PLL input clock (fPLLin). Based on PINSEL bits information from PLLCON2 register, the parent clock source is obtained. This bit field specifies if fOHP or fOFI is used for deriving system clock. System clock frequency is obtained by dividing the source clock frequency with different divider values.

Related APIs:

XMC_SCU_CLOCK_GetSystemPllClockFrequency()

uint32_t XMC_SCU_CLOCK_GetUsbClockDivider

(

void

)

Returns

uint32_t Ratio of PLL output clock(fPLL) to USB clock(fUSB). Range: 0 to 7.

Description

Provides the ratio between PLL output frequency(fPLL) and USB clock(fUSB).

The value is obtained by reading USBDIV bit of USBCLKCR register.

Related APIs:

XMC_SCU_CLOCK_SetUsbClockDivider(), XMC_SCU_CLOCK_GetUsbClockSource()

uint32_t XMC_SCU_CLOCK_GetUsbClockFrequency

(

void

)

Returns

uint32_t USB clock frequency in Hertz.

Description

Provides the frequency of USB and SDMMC clock(fUSB/fSDMMC).

The value is obtained from USBDIV bits of USBCLKCR register and USB clock source. Based on these values fUSB/fSDMMC clock frequency is calculated using following formula:
if USB clock source = USBPLL: fUSB/fSDMMC = fUSBPLL/(USBDIV + 1).
if USB clock source = PLL: fUSB/fSDMMC = fPLL/(USBDIV + 1).

Related APIs:

XMC_SCU_CLOCK_GetUsbClockSource(), XMC_SCU_CLOCK_GetUsbClockDivider()

XMC_SCU_CLOCK_USBCLKSRC_t XMC_SCU_CLOCK_GetUsbClockSource

(

void

)

Returns

XMC_SCU_CLOCK_USBCLKSRC_t Source of clock for USB and SDMMC(fUSB/SDMMC).
Range: Use type XMC_SCU_CLOCK_USBCLKSRC_t to identify the source of clock.
XMC_SCU_CLOCK_USBCLKSRC_USBPLL - output of USB PLL is selected as source of USB clock(fUSB/SDMMC).
XMC_SCU_CLOCK_USBCLKSRC_SYSPLL - output of PLL fPLL is selected as source of USB clock(fUSB/SDMMC).

Description

Provides the selected source of USB and SDMMC clock frequency.

The clock source is read from from the USBSEL bits of USBCLKCR register.

Related APIs:

XMC_SCU_CLOCK_SetUsbClockDivider(), XMC_SCU_CLOCK_GetUsbPllClockFrequency()

uint32_t XMC_SCU_CLOCK_GetUsbPllClockFrequency

(

void

)

Returns

uint32_t USB PLL output clock frequency.

Description

Provides the frequency of USB PLL output clock (fUSBPLL).

It obtains the VCOBYP bits information from USBPLLCON register and decides if USB PLL mode is used. If USB PLL mode is used, the USB clock frequency is obtained by dividing the source clock by USB PLL dividers.
The frequency is obtained using following formula:
If Normal Mode : fUSBPLL = (fOSC * N)/(P * 2).
If Prescaler mode: fPLL = fOSC.

Related APIs:

XMC_SCU_CLOCK_GetSystemPllClockSourceFrequency()

uint32_t XMC_SCU_CLOCK_GetWdtClockDivider

(

void

)

Returns

uint32_t Ratio between the source of WDT clock and the WDT clock.
Range: 0 to 255.

Description

Provides the ratio between the WDT parent clock and the WDT clock.

The value is obtained by reading WDTDIV bits of WDTCLKCR register. Ensure that the WDT parent clock is considered before using the value of the divider value.

Related APIs:

XMC_SCU_CLOCK_SetWdtClockSource(), XMC_SCU_CLOCK_SetWdtClockDivider()

uint32_t XMC_SCU_CLOCK_GetWdtClockFrequency

(

void

)

Returns

uint32_t WDT clock frequency in Hertz.

Description

Provides the frequency of WDT clock(fWDT).

The value is derived using WDTDIV bits of WDTCLKCR register and WDT clock source. Based on these values it is calculated using the following formula:
if WDT clock source = PLL: fWDT = fUSBPLL/(WDTDIV + 1).
if WDT clock source = OFI: fWDT = fOFI/(WDTDIV + 1).
if WDT clock source = Standby: fWDT = fSTDBY/(WDTDIV + 1).

Related APIs:

XMC_SCU_CLOCK_GetWdtClockSource(), XMC_SCU_CLOCK_GetWdtClockDivider()

XMC_SCU_CLOCK_WDTCLKSRC_t XMC_SCU_CLOCK_GetWdtClockSource

(

void

)

Returns

XMC_SCU_CLOCK_WDTCLKSRC_t Clock source configured for watchdog timer.
Range: Use type XMC_SCU_CLOCK_WDTCLKSRC_t to identify the clock source.
XMC_SCU_CLOCK_WDTCLKSRC_OFI - internal fast oscillator (fOFI)
XMC_SCU_CLOCK_WDTCLKSRC_STDBY - backup standby clock (fSTDBY)
XMC_SCU_CLOCK_WDTCLKSRC_PLL - PLL output clock (fPLL)

Description

Provides the source of clock used for watchdog timer.

The value is obtained by reading WDTSEL bits of WDTCLKCR register. The time for timeout or pre-warning of watchdog has to be calculated based on the clock source selected.

Related APIs:

XMC_SCU_CLOCK_SetWdtClockDivider(), XMC_SCU_CLOCK_SetWdtClockSource()

void XMC_SCU_CLOCK_Init

(

const XMC_SCU_CLOCK_CONFIG_t *const

config

)

Parameters

config

Pointer to structure holding the clock prescaler values and divider values for configuring clock generators and clock tree. Range: Configure the members of structure XMC_SCU_CLOCK_CONFIG_t for various parameters of clock setup.

Returns

None

Description

Initializes clock generators and clock tree.

Enables the high precision oscillator(fOHP) input and configures the system and peripheral clock frequencies. Based on the system clock source selected in config, either fPLL or fOFI will be chosen as system clock. Based on PLL mode(normal or prescaler mode) used, PLL ramps up in steps to achieve target frequency. The clock dividers for CPU, CCU and peripheral clocks will be set based on the input configuration. The SystemCoreClock variable is set with the value of system clock frequency.

Related APIs:

XMC_SCU_CLOCK_GetPeripheralClockFrequency(), XMC_SCU_CLOCK_GetCpuClockFrequency()

bool XMC_SCU_CLOCK_IsClockEnabled

(

const XMC_SCU_CLOCK_t

clock

)

Parameters

clock

Peripheral for which the clock status has to be checked. Range: Use type XMC_SCU_CLOCK_t to select the peripheral.

Returns

bool Status of peripheral clock.
Range: true if peripheral clock is enabled. false if peripheral clock is disabled.

Description

Checks the status of peripheral source clock.

The status of peripheral source clock is read from the CLKSTATn register. Returns true if clock is enabled and returns false otherwise.

Related APIs:

XMC_SCU_CLOCK_EnableClock(), XMC_SCU_CLOCK_DisableClock()

bool XMC_SCU_CLOCK_IsHighPerformanceOscillatorStable

(

void

)

Returns

Status of high performance oscillator

Description

Checks if the OSC_HP oscillator is stable and usable

Related APIs:

XMC_SCU_CLOCK_EnableHighPerformanceOscillator()

bool XMC_SCU_CLOCK_IsLowPowerOscillatorStable

(

void

)

Returns

Status of low power oscillator

Description

Checks if the OSC_ULP oscillator is stable and usable

Related APIs:

XMC_SCU_CLOCK_EnableLowPowerOscillator()

bool XMC_SCU_CLOCK_IsPeripheralClockGated

(

const XMC_SCU_PERIPHERAL_CLOCK_t

peripheral

)

Parameters

peripheral

The peripheral for which the check for clock gating has to be done. Range: Use type XMC_SCU_PERIPHERAL_CLOCK_t to identify the peripheral.

Returns

bool Status of the peripheral clock gating. Range: true if the peripheral clock is gated. false if the peripheral clock ungated(gate de-asserted).

Description

Gives the status of peripheral clock gating.

Checks the status of peripheral clock gating using one of CGATSTAT0, CGATSTAT1 or CGATSTAT2 registers. It is recommended to use this API before enabling the gating of any peripherals through XMC_SCU_CLOCK_GatePeripheralClock() API.

Related APIs:

XMC_SCU_CLOCK_UngatePeripheralClock(), XMC_SCU_CLOCK_GatePeripheralClock()

bool XMC_SCU_CLOCK_IsSystemPllLocked

(

void

)

Parameters

None

Returns

Boolean value indicating if System PLL is locked

Description

Return status of System PLL VCO.

Related APIs:

XMC_SCU_CLOCK_StartSystemPll()

bool XMC_SCU_CLOCK_IsUsbPllLocked

(

void

)

Parameters

None

Returns

Boolean value indicating if USB PLL is locked

Description

Return status of USB PLL VCO.

Related APIs:

XMC_SCU_CLOCK_StartUsbPll()

void XMC_SCU_CLOCK_SetBackupClockCalibrationMode

(

XMC_SCU_CLOCK_FOFI_CALIBRATION_MODE_t

mode

)

Parameters

mode

Backup clock calibration mode. Range: Use type XMC_SCU_CLOCK_FOFI_CALIBRATION_MODE_t to identify the calibration mode. XMC_SCU_CLOCK_FOFI_CALIBRATION_MODE_FACTORY- Force trimming of internal oscillator with firmware configured values. XMC_SCU_CLOCK_FOFI_CALIBRATION_MODE_AUTOMATIC- Calibrate internal oscillator automatically using standby clock(fSTDBY).

Returns

None

Description

Configures the calibration mode of internal oscillator.

Based on the calibration mode selected, the internal oscillator calibration will be configured. The calibration is useful while using fast internal clock(fOFI). When factory mode calibration is used, the internal oscillator is trimmed using the firmware configured values. If automatic calibration is selected, the internal oscillator will be monitored using the backup clock.

Related APIs:

XMC_SCU_CLOCK_SetSystemClockSource()

void XMC_SCU_CLOCK_SetCcuClockDivider

(

const uint32_t

ratio

)

Parameters

ratio

Ratio of fCCU clock source to the value of fCCU. Range: 1 or 2. 1-> fCCU= fSYS 2-> fCCU= fSYS/2.

Returns

None

Description

Configures the divider for CCU clock source.

Capture compare unit(CCU) can take either fSYS or fSYS/2 as the source of clock. The configuration is set to CCUDIV bit of CCUCLKCR register. The CCUDIV bit is 1 bit wide.

Related APIs:

XMC_SCU_CLOCK_GetCcuClockDivider()

void XMC_SCU_CLOCK_SetCpuClockDivider

(

const uint32_t

ratio

)

Parameters

ratio

Ratio between system clock(fSYS) and CPU clock(fCPU). Range: 1 or 2. 1-> fCPU= fSYS. 2-> fCPU= fSYS/2.

Returns

None

Description

Configures the CPU clock by setting the divider value for the system clock.

The value is set to the CPUDIV bit of CPUCLKCR register.

Related APIs:

XMC_SCU_CLOCK_GetCpuClockDivider()

void XMC_SCU_CLOCK_SetDeepSleepConfig

(

int32_t

config

)

Parameters

config

Defines the source of the system clock and peripherals clock gating in DEEPSLEEP state. XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_t

Returns

None

Description

Defines the source of the system clock and peripherals clock gating in DEEPSLEEP state. In addition the state of FLASH, PLL and PLLVCO during DEEPSLEEP state. Use this enum as parameter of XMC_SCU_CLOCK_SetDeepSleepConfig before going to DEEPSLEEP state.

The DEEPSLEEP state of the system corresponds to the DEEPSLEEP state of the CPU. The state is entered via WFI or WFE instruction of the CPU. In this state the clock to the CPU is stopped.

In Deep Sleep state the OSC_HP and the PLL may be switched off. The wake-up logic in the NVIC is still clocked by a free-running clock. Peripherals are only clocked when configured to stay enabled. Configuration of peripherals and any SRAM content is preserved. The Flash module can be put into low-power mode to achieve a further power reduction. On wake-up Flash module will be restarted again before instructions or data access is possible. Any interrupt will bring the system back to operation via the NVIC.The clock setup before entering Deep Sleep state is restored upon wake-up.

// Configure system during SLEEP state
XMC_SCU_CLOCK_SetDeepSleepConfig(XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_SYSCLK_FOFI |
                                 XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_FLASH_POWERDOWN |
                                 XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_PLL_POWERDOWN); 

// Make sure that SLEEPDEEP bit is set
SCB->SCR |= SCB_SCR_DEEPSLEEP_Msk;

// Return to SLEEP mode after handling the wakeup event
SCB->SCR |= SCB_SCR_SLEEPONEXIT_Msk; 

// Put system in DEEPSLEEP state
__WFI();

Related APIs:

XMC_SCU_CLOCK_Init()

void XMC_SCU_CLOCK_SetEbuClockDivider

(

const uint32_t

ratio

)

Parameters

ratio

Ratio of PLL clock(fPLL) to EBU clock(fEBU). Range: 1 to 64.

Returns

None

Description

Configures the EBU clock(fEBU) by setting the divider value.

The clock divider is configured to the EBUDIV bits of EBUCLKCR register.

Related APIs:

XMC_SCU_CLOCK_GetEbuClockDivider()

void XMC_SCU_CLOCK_SetECATClockDivider

(

const uint32_t

divider

)

Parameters

ratio

Ratio between the source of ECAT clock and the ECAT clock. Range: 1 to 4.

Returns

None

Description

Configures the ECAT clock by setting the clock divider for the ECAT clock source.

The value is configured to ECADIV bits of ECATCLKCR register. The value of divider is decremented by 1 before configuring.

Related APIs:

XMC_SCU_CLOCK_SetECATClockSource(), XMC_SCU_CLOCK_GetECATClockDivider()

void XMC_SCU_CLOCK_SetECATClockSource

(

const XMC_SCU_CLOCK_ECATCLKSRC_t

source

)

Parameters

source

Source of ECAT clock. Range: Use type XMC_SCU_CLOCK_ECATCLKSRC_t to identify the clock source. XMC_SCU_CLOCK_ECATCLKSRC_USBPLL - USB PLL (fUSBPLL) as a source for ECAT clock. XMC_SCU_CLOCK_ECATCLKSRC_SYSPLL - Main PLL output (fPLL) as a source for ECAT clock.

Returns

None

Description

Selects the source of ECAT clock (fECAT).

The value is configured to ECATSEL bit of ECATCLKCR register.

Related APIs:

XMC_SCU_CLOCK_GetECATClockSource()

void XMC_SCU_CLOCK_SetExternalOutputClockDivider

(

const uint32_t

ratio

)

Parameters

ratio

Ratio between the external output parent clock selected and the output clock. Range: 1 to 512.

Returns

None

Description

Configures the external output clock by setting the divider value for the parent clock.

The value will be configured to ECKDIV bits of EXTCLKCR register. The divider value is decremented by 1 before storing it to the bit fields. Ensure that the source of external output clock is configured appropriately using the API XMC_SCU_CLOCK_SetExternalOutputClockSource().

Related APIs:

XMC_SCU_CLOCK_SetExternalOutputClockSource(), XMC_SCU_CLOCK_GetExternalOutputClockDivider()

void XMC_SCU_CLOCK_SetExternalOutputClockSource

(

const XMC_SCU_CLOCK_EXTOUTCLKSRC_t

clock

)

Parameters

clock

Source of external clock output(fEXT). Range: Use type XMC_SCU_CLOCK_EXTOUTCLKSRC_t to identify the clock. XMC_SCU_CLOCK_EXTOUTCLKSRC_SYS - system clock fSYS. XMC_SCU_CLOCK_EXTOUTCLKSRC_USB - USB clock fUSB. XMC_SCU_CLOCK_EXTOUTCLKSRC_PLL - PLL output fPLL.

Returns

None

Description

Selects the source of external clock out (fEXT).

The value will be configured to ECKSEL bits of EXTCLKCR register.

Related APIs:

XMC_SCU_CLOCK_GetExternalOutputClockSource(), XMC_SCU_CLOCK_SetExternalOutputClockDivider()

void XMC_SCU_CLOCK_SetPeripheralClockDivider

(

const uint32_t

ratio

)

Parameters

ratio

Ratio of peripheral clock source to the value of peripheral clock. Range: 1 or 2. 1-> fPERIPH= fCPU. 2-> fPERIPH= fCPU/2.

Returns

None

Description

Configures the peripheral clock by setting the divider for CPU clock(fCPU).

The peripheral clock can be equal to either fCPU or fCPU/2. The value is configured to PBDIV bit of PBCLKCR register.

Related APIs:

XMC_SCU_CLOCK_GetPeripheralClockDivider()

void XMC_SCU_CLOCK_SetSleepConfig

(

int32_t

config

)

Parameters

config

Defines the source of the system clock and peripherals clock gating in SLEEP state. XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_t

Returns

None

Description

Defines the source of the system clock and peripherals clock gating in SLEEP state.

The SLEEP state of the system corresponds to the SLEEP state of the CPU. The state is entered via WFI or WFE instruction of the CPU. In this state the clock to the CPU is stopped. Peripherals are only clocked when configured to stay enabled.

Peripherals can continue to operate unaffected and eventually generate an event to wake-up the CPU. Any interrupt to the NVIC will bring the CPU back to operation. The clock tree upon exit from SLEEP state is restored to what it was before entry into SLEEP state.

// Configure system during SLEEP state
XMC_SCU_CLOCK_SetSleepConfig(XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_SYSCLK_FOFI);

// Make sure that SLEEPDEEP bit is cleared
SCB->SCR &= ~ SCB_SCR_DEEPSLEEP_Msk;

// Return to SLEEP mode after handling the wakeup event
SCB->SCR |= SCB_SCR_SLEEPONEXIT_Msk; 

// Put system in SLEEP state
__WFI();

Related APIs:

XMC_SCU_CLOCK_Init()

void XMC_SCU_CLOCK_SetSystemClockDivider

(

const uint32_t

divider

)

Parameters

divider

Ratio of fSYS clock source to the value of fSYS. Range: 1 to 256.

Returns

None

Description

Configures the ratio of system clock source to the value of system clock frequency.

The value is configured as SYSDIV bits of SYSCLKCR register. The divider value is decremented by 1 before configuring.

Related APIs:

XMC_SCU_CLOCK_GetSystemClockDivider(), XMC_SCU_CLOCK_SetSystemClockSource()

void XMC_SCU_CLOCK_SetSystemClockSource

(

const XMC_SCU_CLOCK_SYSCLKSRC_t

source

)

Parameters

source

Source of clock for fSYS. Range: Use type XMC_SCU_CLOCK_SYSCLKSRC_t to select the source of clock. XMC_SCU_CLOCK_SYSCLKSRC_OFI for selecting internal fast clock as fSYS. XMC_SCU_CLOCK_SYSCLKSRC_PLL for selecting the output of PLL fPLL as fSYS.

Returns

None

Description

Selects the source for system clock (fSYS).

System clock is selected by setting SYSSEL bits in the SYSCLKCR register. If XMC_SCU_CLOCK_SYSCLKSRC_PLL is selected, then the dividers of the PLL have to be additionally configured to achieve the required system clock frequency.

Related APIs:

XMC_SCU_CLOCK_StartSystemPll(), XMC_SCU_CLOCK_EnableHighPerformanceOscillator()

void XMC_SCU_CLOCK_SetSystemPllClockSource

(

const XMC_SCU_CLOCK_SYSPLLCLKSRC_t

source

)

Parameters

source

Source of clock for system PLL. Range: Use type XMC_SCU_CLOCK_SYSPLLCLKSRC_t for identifying the clock source. XMC_SCU_CLOCK_SYSPLLCLKSRC_OSCHP - External High performance oscillator(fOHP). XMC_SCU_CLOCK_SYSPLLCLKSRC_OFI - Internal fast clock (fOFI).

Returns

None

Description

Selects the source of system PLL.

The value is configured to VCOBYP bit of PLLCON0 register. If XMC_SCU_CLOCK_SYSPLLCLKSRC_OSCHP is selected, ensure that the high performance oscillator is enabled by using the API XMC_SCU_CLOCK_EnableHighPerformanceOscillator().

Related APIs:

XMC_SCU_CLOCK_EnableHighPerformanceOscillator()

void XMC_SCU_CLOCK_SetUsbClockDivider

(

const uint32_t

ratio

)

Parameters

ratio

Ratio of PLL output clock(fPLL) to USB clock(fUSB). Range: 1 to 8.

Returns

None

Description

Configures the USB clock(fUSB) by setting the USB clock divider.

The value is decremented by 1 before setting it to USBDIV bits of USBCLKCR register.

Related APIs:

XMC_SCU_CLOCK_GetUsbClockDivider(), XMC_SCU_CLOCK_SetUsbClockSource()

void XMC_SCU_CLOCK_SetUsbClockSource

(

const XMC_SCU_CLOCK_USBCLKSRC_t

source

)

Parameters

source

Source of clock for USB and SDMMC(fUSB/SDMMC). Range: Use type XMC_SCU_CLOCK_USBCLKSRC_t to select the source of clock. XMC_SCU_CLOCK_USBCLKSRC_USBPLL - output of USB PLL as source of USB clock(fUSB/SDMMC). XMC_SCU_CLOCK_USBCLKSRC_SYSPLL - output of PLL fPLL as source of USB clock(fUSB/SDMMC).

Returns

None

Description

Selects the source of USB/SDMMC clock (fUSB/SDMMC).

USB and SDMMC use a common clock source. They can either use fUSB PLL or fPLL as the source of clock. The selection is done by configuring the USBSEL bits of USBCLKCR register.

Related APIs:

XMC_SCU_CLOCK_SetUsbClockDivider(), XMC_SCU_CLOCK_GetUsbPllClockFrequency()

void XMC_SCU_CLOCK_SetWdtClockDivider

(

const uint32_t

ratio

)

Parameters

ratio

Ratio between the source of WDT clock and the WDT clock. Range: 1 to 256.

Returns

None

Description

Configures the WDT clock by setting the clock divider for the WDT clock source.

The value is configured to WDTDIV bits of WDTCLKCR register. The value of divider is decremented by 1 before configuring. Check the selected clock source for the WDT clock before configuring the divider using the API XMC_SCU_CLOCK_SetWdtClockSource().

Related APIs:

XMC_SCU_CLOCK_SetWdtClockSource(), XMC_SCU_CLOCK_GetWdtClockDivider()

void XMC_SCU_CLOCK_SetWdtClockSource

(

const XMC_SCU_CLOCK_WDTCLKSRC_t

source

)

Parameters

source

Clock source for watchdog timer. Range: Use type XMC_SCU_CLOCK_WDTCLKSRC_t to identify the clock source. XMC_SCU_CLOCK_WDTCLKSRC_OFI - internal fast oscillator (fOFI) XMC_SCU_CLOCK_WDTCLKSRC_STDBY - backup standby clock (fSTDBY) XMC_SCU_CLOCK_WDTCLKSRC_PLL - PLL output clock (fPLL)

Returns

None

Description

Selects the source of WDT clock (fWDT).

The selected value is configured to the WDTSEL bits of WDTCLKCR register. The watchdog timer counts at the frequency selected using this API. So the time for timeout or pre-warning of watchdog has to be calculated based on this selection.

Related APIs:

XMC_SCU_CLOCK_SetWdtClockDivider(), XMC_SCU_CLOCK_GetWdtClockFrequency()

void XMC_SCU_CLOCK_StartSystemPll	(	XMC_SCU_CLOCK_SYSPLLCLKSRC_t	source,
		XMC_SCU_CLOCK_SYSPLL_MODE_t	mode,
		uint32_t	pdiv,
		uint32_t	ndiv,
		uint32_t	kdiv
	)

Parameters

source	PLL clock source. Range: Use type XMC_SCU_CLOCK_SYSPLLCLKSRC_t to identify the clock source. XMC_SCU_CLOCK_SYSPLLCLKSRC_OSCHP- External high precision oscillator input. XMC_SCU_CLOCK_SYSPLLCLKSRC_OFI- Internal fast clock input.
mode	Mode of PLL operation. Range: Use type XMC_SCU_CLOCK_SYSPLL_MODE_t to identify the PLL mode. XMC_SCU_CLOCK_SYSPLL_MODE_NORMAL- PLL frequency obtained from output of VCO(fVCO). XMC_SCU_CLOCK_SYSPLL_MODE_PRESCALAR- VCO is bypassed. Frequency obtained from fOSC.
pdiv	Input divider. Represents (PDIV+1) applied to external reference frequency. Range: 1 to 16.
ndiv	Feedback divider. Represents(NDIV+1) Range: 1 to 128.
kdiv	Output divider. Represents (K2DIV+1) in normal PLL mode or (K1DIV+1) in prescaler mode. Range: 1 to 128.

Returns

None

Description

Enables system PLL.

Based on the selected source of clock, either external frequency fOHP or internal clock fOFI will be used. Based on the selected PLL mode, either voltage controlled oscillator(VCO) output(fVCO) or direct input frequency is used for the output dividers.
The API implements the following sequence:

• Store the value of TRAPDIS register into a temporary variable before disabling all traps.
  
• Clear all PLL related traps.
  
• If external fOHP is selected as source, wait for the external oscillator to stabilize.
  
• If PLL normal mode is selected, calculate the value of K2DIV and configure the PDIV, NDIV and K2DIV values.
  
• Ramp up the PLL frequency in steps.
  
• If prescaler mode is selected, configure the value of K1DIV.
  
• Wait for LOCK.
  
• Restore the trap configuration from stored temporary variable.
  

Related APIs:

XMC_SCU_CLOCK_GetSystemPllClockFrequency(), XMC_SCU_CLOCK_StopSystemPll()

void XMC_SCU_CLOCK_StartUsbPll	(	uint32_t	pdiv,
		uint32_t	ndiv
	)

Parameters

pdiv	Input divider value. Represents (PDIV+1) divider for the USB PLL. Range: 1 to 16.
ndiv	VCO feedback divider for USB PLL. Represents (NDIV+1) feedback divider. Range: 1 to 128.

Returns

None

Description

Configures USB PLL dividers and enables the PLL.

The API follows the required sequence for safely configuring the divider values of USB PLL. Checks for PLL stabilization before enabling the same. After the configuring the dividers, it waits till the VCO lock is achieved. The sequence followed is as follows:

• Enable the USB PLL and configure VCO to be bypassed.
  
• Set up the HP oscillator clock input.
  
• Store the value of TRAPDIS register into a temporary variable before disabling all traps.
  
• Clear all USBPLL related traps.
  
• Disconnect the oscillator from USB PLL and configure the dividers PDIV and NDIV.
  
• Connect the oscillator to USB PLL and enable VCO.
  
• Wait for LOCK.
  
• Restore the trap configuration from stored temporary variable.
  

Related APIs:

XMC_SCU_CLOCK_StopUsbPll()

void XMC_SCU_CLOCK_StepSystemPllFrequency

(

uint32_t

kdiv

)

Parameters

kdiv	PLL output divider K2DIV. Range: 1 to 128. Represents (K2DIV+1).

Returns

None

Description

Ramps up or ramps down the PLL output frequency in provided step.

The PLL output frequency is divided by the kdiv value. This generates a step of ramp for the PLL output frequency. The API waits for the clock to stabilize before the completing its execution.

Related APIs:

XMC_SCU_CLOCK_StartSystemPll()

void XMC_SCU_CLOCK_StopSystemPll

(

void

)

Returns

None

Description

Disables the system PLL. PLL is placed in power saving mode. It disables the PLL by setting the PLLPWD bit of PLLCON0 register. If the PLL is put to power saving mode, it can no longer be used. It is recommended to ensure following steps before using XMC_SCU_CLOCK_StopSystemPll API:

• Store the value of TRAPDIS register into a temporary variable before disabling all traps.
  
• Clear all PLL related traps.
  
• Ramp down frequency until fPLL reaches backup clock frequency (fOFI).
  
• Disable PLL.
  
• Restore the trap configuration from stored temporary variable.
  

Related APIs:

XMC_SCU_CLOCK_GetSystemPllClockFrequency(), XMC_SCU_CLOCK_StartSystemPll()

void XMC_SCU_CLOCK_StopUsbPll

(

void

)

Returns

None

Description

Disables USB PLL operation.

USB PLL is disabled by placing the USB PLL in power saving mode. The VCO and USB PLL are put in power saving mode by setting the PLLPWD bit and VCOPWD bit of USBLLCON register to 1. VCO bypass mode is enabled by setting the VCOBYP bit of USBLLCON register to 1. It is recommended to ensure following steps before using XMC_SCU_CLOCK_StopUsbPll API:

• Store the value of TRAPDIS register into a temporary variable before disabling all traps.
  
• Clear all USBPLL related traps.
  
• Ramp down frequency.
  
• Disable PLL.
  
• Restore the trap configuration from stored temporary variable.
  

Related APIs:

XMC_SCU_CLOCK_StartUsbPll()

void XMC_SCU_CLOCK_UngatePeripheralClock

(

const XMC_SCU_PERIPHERAL_CLOCK_t

peripheral

)

Parameters

peripheral

The peripheral for which the clock has to be ungated. Range: Use type XMC_SCU_PERIPHERAL_CLOCK_t to identify the peripheral.

Returns

None

Description

Enables the supply of clock to the selected peripheral.

By default when the device powers on, the peripheral clock will be gated for the peripherals that support clock gating. The peripheral clock should be enabled before using it for any functionality. fPERI is the source of clock to various peripherals. Some peripherals support clock gate. Software can request for individual ungating of such peripheral clocks by setting the respective bits in one of SCU_CGATCLR0, SCU_CGATCLR1 or SCU_CGATCLR2 registers.

Related APIs:

XMC_SCU_CLOCK_IsPeripheralClockGated(), XMC_SCU_CLOCK_GatePeripheralClock()

void XMC_SCU_DisableOutOfRangeComparator	(	const uint32_t	group,
		const uint32_t	channel
	)

Parameters

group	ADC Group to which the channel being monitored belongs to. Range: 0 or 1.
channel	The channel whose voltage range has to be monitored. Range: 6 or 7. Value identifies the channel in the selected ADC group.

Returns

None

Description

Disables the out of range comparator for the selected ADC group and the channel.

Out of range comparator is disabled by clearing the enable bit in the GORCEN register.

Related APIs:

XMC_SCU_EnableOutOfRangeComparator()

void XMC_SCU_DisableTemperatureSensor

(

void

)

Returns

None

Description

Disables die temperature measurement by powering the DTS module off.

Die temperature sensor is disabled by clearing the PWD bit of DTSCON register.

Related APIs:

XMC_SCU_EnableTemperatureSensor(), XMC_SCU_IsTemperatureSensorEnabled(), XMC_SCU_CalibrateTemperatureSensor(), XMC_SCU_StartTemperatureMeasurement(), XMC_SCU_GetTemperatureMeasurement()

void XMC_SCU_EnableOutOfRangeComparator	(	const uint32_t	group,
		const uint32_t	channel
	)

Parameters

group	ADC Group to which the channel being monitored belongs to. Range: 0 or 1.
channel	The channel whose voltage range has to be monitored. Range: 6 or 7. Value identifies the channel in the selected ADC group.

Returns

None

Description

Enables out of range comparator for the selected ADC group and channel.

The ADC channel input is compared by Out of Range Comparator (ORC) for overvoltage monitoring or for detection of out of range analog inputs. ORC must be turned on explicitly to leverage the auditing feature. ORC is enabled by setting the enable bit in the GORCEN register.

Related APIs:

XMC_SCU_DisableOutOfRangeComparator()

void XMC_SCU_EnableTemperatureSensor

(

void

)

Returns

None

Description

Enables die temperature measurement by powering the DTS module.

Die temperature sensor is enabled by setting the PWD bit of DTSCON register.

Related APIs:

XMC_SCU_DisableTemperatureSensor(), XMC_SCU_IsTemperatureSensorEnabled(), XMC_SCU_CalibrateTemperatureSensor(), XMC_SCU_StartTemperatureMeasurement(), XMC_SCU_GetTemperatureMeasurement()

uint32_t XMC_SCU_GetBootMode

(

void

)

Returns

uint32_t Configured boot mode for the device.
Range: Use type XMC_SCU_BOOTMODE_t for enumeration of different boot modes.

Description

Provides the boot mode configured for the device.

The boot mode is read from the STCON register bit field SWCON.

Related APIs:

XMC_SCU_SetBootMode()

uint32_t XMC_SCU_GetMirrorStatus

(

void

)

Returns

uint32_t Status of the register mirror update.
Range: Use the bit mask of the SCU_GENERAL_MIRRSTS register for the mirror update event of interest. e.g.: SCU_GENERAL_MIRRSTS_RTC_CTR_Msk. Multiple update events can be combined using OR operation.

Description

Provides the status of hibernate domain register update, when the respective mirror registers are changed.

The hibernate domain is connected to the core domain via SPI serial communication. MIRRSTS is a status register representing the communication of changed value of a mirror register to its corresponding register in the hibernate domain. The bit fields of the register indicate that a corresponding register of the hibernate domain is ready to accept a write or that the communication interface is busy with executing the previous operation.
Note: There is no hibernate domain in XMC1x devices. This register is retained for legacy purpose.

uint32_t XMC_SCU_GetTemperatureMeasurement

(

void

)

Returns

uint32_t Measured temperature value.
Range: Valid temperature range is 0 to 1023.
If sensor is not enabled, 0x7FFFFFFFH is returned.

Description

Reads the measured value of die temperature.

Temperature measurement result is read from RESULT bit field of DTSSTAT register. The temperature measured in �C is given by (RESULT - 605) / 2.05 [�C]

Related APIs:

XMC_SCU_IsTemperatureSensorBusy()

void XMC_SCU_HIB_ClearEventStatus

(

int32_t

event

)

Parameters

event

Hibernate wakeup event XMC_SCU_HIB_EVENT_t

Returns

None

Description

Clear hibernate wakeup event status

Note

The register update in HIB domain is indicated by the MIRRST register which can be polled using XMC_SCU_GetMirrorStatus()

Related APIs:

XMC_SCU_HIB_TriggerEvent(), XMC_SCU_HIB_EnableEvent(), XMC_SCU_HIB_DisableEvent(), XMC_SCU_GetMirrorStatus()

void XMC_SCU_HIB_ClearWakeupEventDetectionStatus

(

void

)

Returns

None

Description

Clear detection status of wakeup from hibernate mode

void XMC_SCU_HIB_DisableEvent

(

int32_t

event

)

Parameters

event

Hibernate wakeup event XMC_SCU_HIB_EVENT_t

Returns

None

Description

Disable hibernate wakeup event source

Note

The register update in HIB domain is indicated by the MIRRST register which can be polled using XMC_SCU_GetMirrorStatus()

Related APIs:

XMC_SCU_HIB_TriggerEvent(), XMC_SCU_HIB_EnableEvent(), XMC_SCU_HIB_ClearEventStatus(), XMC_SCU_GetMirrorStatus()

void XMC_SCU_HIB_DisableHibernateDomain

(

void

)

Returns

None

Description

Powers down the hibernation domain.

After disabling the hibernate domain, none of the peripherals from the hibernte domain can be used. Hibernate domain is disabled by setting the HIB bit of PWRCLR register and \ HIBRS bit of RSTSET register.
It is recommended to use following steps to verify whether a hibernation domain is enabled/disabled:

• Call XMC_SCU_HIB_DisableHibernateDomain .
• Call XMC_SCU_HIB_IsHibernateDomainEnabled and check return value. If return value is true, it indicates that the hibernation domain is enabled otherwise disabled.
  

Related APIs:

XMC_SCU_HIB_EnableHibernateDomain(), XMC_SCU_HIB_IsHibernateDomainEnabled()

void XMC_SCU_HIB_DisableInternalSlowClock

(

void

)

Returns

None

Description

Disables slow internal oscillator(fOSI).

By default on device power up, the slow internall oscillator is enabled. It can be disabled only if the external oscillator(fULP) is enabled and toggling. It is recommended to enable fOSI to prevent deadlock if fULP fails. fOSI is disabled by setting the PWD bit of OSCSICTRL register. The API waits for the mirror register update of the configured register. The slow internal oscillator registers are in hibernate domain. Ensure that the hibernate domain is enabled before changing the configuration.

Note

The register update in HIB domain is indicated by the MIRRST register which can be polled using XMC_SCU_GetMirrorStatus()

Related APIs:

XMC_SCU_HIB_EnableInternalSlowClock(), XMC_SCU_CLOCK_SetBackupClockCalibrationMode(), XMC_SCU_HIB_EnableHibernateDomain(), XMC_SCU_GetMirrorStatus()

void XMC_SCU_HIB_EnableEvent

(

int32_t

event

)

Parameters

event

Hibernate wakeup event XMC_SCU_HIB_EVENT_t

Returns

None

Description

Enable hibernate wakeup event source

Note

The register update in HIB domain is indicated by the MIRRST register which can be polled using XMC_SCU_GetMirrorStatus()

Related APIs:

XMC_SCU_HIB_TriggerEvent(), XMC_SCU_HIB_ClearEventStatus(), XMC_SCU_HIB_DisableEvent(), XMC_SCU_GetMirrorStatus()

void XMC_SCU_HIB_EnableHibernateDomain

(

void

)

Returns

None

Description

Powers up the hibernation domain.

Hibernate domain should be enabled before using any peripheral from the hibernate domain. It enables the power to the hibernate domain and moves it out of reset state. Power to hibernate domain is enabled by setting the HIB bit of PWRSET register only if it is currently powered down. The API will wait until HIB domain is enabled. If hibernate domain is in a state of reset, HIBRS bit of RSTCLR register is set to move it out of reset state.
It is recommended to use following steps to verify whether a hibernation domain is enabled/disabled:

• Call XMC_SCU_HIB_EnableHibernateDomain .
• Call XMC_SCU_HIB_IsHibernateDomainEnabled and check the return value. If return value is true, it indicates that the hibernation domain is enabled otherwise disabled.
  

Related APIs:

XMC_SCU_HIB_DisableHibernateDomain(), XMC_SCU_HIB_IsHibernateDomainEnabled()

void XMC_SCU_HIB_EnableInternalSlowClock

(

void

)

Returns

None

Description

Enables slow internal oscillator(fOSI).

By default on device power up, the slow internall oscillator is enabled. It can be disabled only if the external oscillator(fULP) is enabled and toggling. It is recommended to enable fOSI to prevent deadlock if fULP fails. fOSI is enabled by clearing the PWD bit of OSCSICTRL register. The API waits for the mirror register update of the configured register. The slow internal oscillator registers are in hibernate domain. Ensure that the hibernate domain is enabled before changing the configuration.

Note

The register update in HIB domain is indicated by the MIRRST register which can be polled using XMC_SCU_GetMirrorStatus()

Related APIs:

XMC_SCU_HIB_DisableInternalSlowClock(), XMC_SCU_CLOCK_SetBackupClockCalibrationMode(), XMC_SCU_HIB_EnableHibernateDomain(), XMC_SCU_GetMirrorStatus()

void XMC_SCU_HIB_EnterHibernateState

(

void

)

Returns

None

Description

Request enter external hibernate state

Note

The register update in HIB domain is indicated by the MIRRST register which can be polled using XMC_SCU_GetMirrorStatus()

Related APIs:

XMC_SCU_GetMirrorStatus()

void XMC_SCU_HIB_EnterHibernateStateEx

(

XMC_SCU_HIB_HIBERNATE_MODE_t

mode

)

Parameters

mode	hibernate mode XMC_SCU_HIB_HIBERNATE_MODE_t

Returns

None

Description

Request enter external hibernate state

Note

The register update in HIB domain is indicated by the MIRRST register which can be polled using XMC_SCU_GetMirrorStatus()

Related APIs:

XMC_SCU_GetMirrorStatus()

int32_t XMC_SCU_HIB_GetEventStatus

(

void

)

Returns

XMC_SCU_HIB_EVENT_t

Description

Returns status of hibernate wakeup events.

int32_t XMC_SCU_HIB_GetHibernateControlStatus

(

void

)

Returns

XMC_SCU_HIB_CTRL_STATUS_t

Description

Returns status of the external hibernate control.

XMC_SCU_HIB_RTCCLKSRC_t XMC_SCU_HIB_GetRtcClockSource

(

void

)

Returns

XMC_SCU_HIB_RTCCLKSRC_t Source of RTC clock.
Range: Use type XMC_SCU_HIB_RTCCLKSRC_t to identify the clock source.
XMC_SCU_HIB_RTCCLKSRC_OSI - internal slow oscillator(fOSI).
XMC_SCU_HIB_RTCCLKSRC_ULP - ultra low power oscillator(fULP).

Description

Provides the source of RTC clock (fRTC). The value is obtained by reading RCS bit of HDCR register. The frequency of the clock will be 32.768 kHz.

Related APIs:

XMC_SCU_HIB_SetRtcClockSource()

XMC_SCU_HIB_RTCCLKSRC_t XMC_SCU_HIB_GetStdbyClockSource

(

void

)

Returns

XMC_SCU_HIB_RTCCLKSRC_t Source clock of standby clock(fSTDBY).
Range: Use type XMC_SCU_HIB_STDBYCLKSRC_t to identify the clock source.
XMC_SCU_HIB_STDBYCLKSRC_OSI - internal slow oscillator (fOSI)
XMC_SCU_HIB_STDBYCLKSRC_OSCULP - ultra low power osciallator (fULP)

Description

Provides the source of standby clock (fSTDBY).

The value is obtained by reading STDBYSEL bits of HDCR register.

Related APIs:

XMC_SCU_HIB_SetStandbyClockSource(), XMC_SCU_HIB_EnableHibernateDomain()

bool XMC_SCU_HIB_IsHibernateDomainEnabled

(

void

)

Returns

bool Power status of hibernate domain.
Range: Boolean state value.
true if hibernate domain is enabled.
false if hibernate domain is disabled.

Description

Checks whether hibernation domain is enabled/disabled.

The API can be used before using the peripherals from hibernation domain to ensure that the power is supplied to the peripherals and also that the hibernation domain is not in reset state. The status is obtained using the HIBEN bit of PWRSTAT register and HIBRS bit of RSTSET register.

Related APIs:

XMC_SCU_HIB_EnableHibernateDomain(), XMC_SCU_HIB_DisableHibernateDomain()

bool XMC_SCU_HIB_IsWakeupEventDetected

(

void

)

Returns

Detection of a wakeup from hibernate mode

Description

Detection of a wakeup from hibernate mode

void XMC_SCU_HIB_LPAC_ClearStatus

(

int32_t

status

)

Parameters

status

HIB LPAC status. Values from XMC_SCU_HIB_LPAC_STATUS_t can be ORed.

Returns

None

Description

Clear status of HIB LPAC.

Note

The register update in HIB domain is indicated by the MIRRST register which can be polled using XMC_SCU_GetMirrorStatus()

Only available in XMC44, XMC42 and XMC41 series

int32_t XMC_SCU_HIB_LPAC_GetStatus

(

void

)

Returns

HIB LPAC status XMC_SCU_HIB_LPAC_STATUS_t

Description

Return status of HIB LPAC.

Note

Only available in XMC44, XMC42 and XMC41 series and in certain packages

void XMC_SCU_HIB_LPAC_SetHIBIO0Thresholds	(	uint8_t	lower,
		uint8_t	upper
	)

Parameters

low	HIB_IO_0 low threshold
high	HIB_IO_0 high threshold

Returns

None

Description

Select compare thresholds for HIB_IO_0. After the reset of HCU the upper threshold is applied to LPAC for all consecutive measurements until it has been crossed upwards. Once upper threshold crossed upwards the lower threshold gets applied and remains applied for all consecutive measuremements until it has been crossed downwards and the threshold values gets swapped again.

Note

The register update in HIB domain is indicated by the MIRRST register which can be polled using XMC_SCU_GetMirrorStatus()

Only available in XMC44, XMC42 and XMC41 series

void XMC_SCU_HIB_LPAC_SetHIBIO1Thresholds	(	uint8_t	lower,
		uint8_t	upper
	)

Parameters

low	HIB_IO_1 low threshold
high	HIB_IO_1 high threshold

Returns

None

Description

Select compare thresholds for HIB_IO_1. After the reset of HCU the upper threshold is applied to LPAC for all consecutive measurements until it has been crossed upwards. Once upper threshold crossed upwards the lower threshold gets applied and remains applied for all consecutive measuremements until it has been crossed downwards and the threshold values gets swapped again.

Note

The register update in HIB domain is indicated by the MIRRST register which can be polled using XMC_SCU_GetMirrorStatus()

Only available in XMC44 series and LQFP100 package

void XMC_SCU_HIB_LPAC_SetInput

(

XMC_SCU_HIB_LPAC_INPUT_t

input

)

Parameters

input

LPAC compare input. Values from XMC_SCU_HIB_LPAC_INPUT_t can be ORed.

Returns

None

Description

Selects inputs to the LPAC comparator. Several inputs can be selected (time multiplexing).

Note

The register update in HIB domain is indicated by the MIRRST register which can be polled using XMC_SCU_GetMirrorStatus()

Only available in XMC44, XMC42 and XMC41 series

void XMC_SCU_HIB_LPAC_SetTiming	(	bool	enable_delay,
		uint16_t	interval_count,
		uint8_t	settle_count
	)

Parameters

enable_delay	Enable conversion delay
interval_count	compare interval (interval_count + 16) * 1/32768 (s)
settle_count	settleing time of LPAC after powered up (triggered) before measurement start (settle_count + 1) * 1/32768 (s)

Returns

None

Description

Configures timing behavior of comparator.

Note

The register update in HIB domain is indicated by the MIRRST register which can be polled using XMC_SCU_GetMirrorStatus()

Only available in XMC44, XMC42 and XMC41 series

void XMC_SCU_HIB_LPAC_SetTrigger

(

XMC_SCU_HIB_LPAC_TRIGGER_t

trigger

)

Parameters

trigger

LPAC compare trigger

Returns

None

Description

Selects trigger mechanism to start a comparison.

Note

The register update in HIB domain is indicated by the MIRRST register which can be polled using XMC_SCU_GetMirrorStatus()

Only available in XMC44, XMC42 and XMC41 series

void XMC_SCU_HIB_LPAC_SetVBATThresholds	(	uint8_t	lower,
		uint8_t	upper
	)

Parameters

low	VBAT low threshold
high	VBAT high threshold

Returns

None

Description

Select compare thresholds for VBAT. After the reset of HCU the upper threshold is applied to LPAC for all consecutive measurements until it has been crossed upwards. Once upper threshold crossed upwards the lower threshold gets applied and remains applied for all consecutive measuremements until it has been crossed downwards and the threshold values gets swapped again.

Note

The register update in HIB domain is indicated by the MIRRST register which can be polled using XMC_SCU_GetMirrorStatus()

Only available in XMC44, XMC42 and XMC41 series

void XMC_SCU_HIB_LPAC_TriggerCompare

(

XMC_SCU_HIB_LPAC_INPUT_t

input

)

Parameters

input

LPAC compare input. Values from XMC_SCU_HIB_LPAC_INPUT_t can be ORed.

Returns

None

Description

Trigger comparasion on the selected inputs.

Note

The register update in HIB domain is indicated by the MIRRST register which can be polled using XMC_SCU_GetMirrorStatus()

Only available in XMC44, XMC42 and XMC41 series

void XMC_SCU_HIB_SetInput0

(

XMC_SCU_HIB_IO_t

pin

)

Parameters

pin	Hibernate domain dedicated pin XMC_SCU_HIB_IO_t

Returns

None

Description

Selects input to ERU0 module (HIB_SR0) that optionally can be used with software as a general purpose input.

Note

The register update in HIB domain is indicated by the MIRRST register which can be polled using XMC_SCU_GetMirrorStatus()

Related APIs:

XMC_SCU_HIB_SetSR0Input(), XMC_SCU_GetMirrorStatus()

void XMC_SCU_HIB_SetPinMode	(	XMC_SCU_HIB_IO_t	pin,
		XMC_SCU_HIB_PIN_MODE_t	mode
	)

Parameters

pin	Hibernate domain dedicated pin XMC_SCU_HIB_IO_t
mode	Hibernate domain dedicated pin mode XMC_SCU_HIB_PIN_MODE_t

Returns

None

Description

Selects mode of hibernate domain dedicated pins HIB_IOx

Note

The register update in HIB domain is indicated by the MIRRST register which can be polled using XMC_SCU_GetMirrorStatus()

Related APIs:

XMC_SCU_GetMirrorStatus()

void XMC_SCU_HIB_SetPinOutputLevel	(	XMC_SCU_HIB_IO_t	pin,
		XMC_SCU_HIB_IO_OUTPUT_LEVEL_t	level
	)

Parameters

pin	Hibernate domain dedicated pin XMC_SCU_HIB_IO_t
level	Output polarity of the hibernate domain dedicated pins HIB_IOx XMC_SCU_HIB_IO_OUTPUT_LEVEL_t

Returns

None

Description

Selects the output polarity of the hibernate domain dedicated pins HIB_IOx

Note

The register update in HIB domain is indicated by the MIRRST register which can be polled using XMC_SCU_GetMirrorStatus()

Related APIs:

XMC_SCU_GetMirrorStatus()

void XMC_SCU_HIB_SetRtcClockSource

(

const XMC_SCU_HIB_RTCCLKSRC_t

source

)

Parameters

source

Source of RTC clock. Range: Use type XMC_SCU_HIB_RTCCLKSRC_t to identify the clock source. XMC_SCU_HIB_RTCCLKSRC_OSI - internal slow oscillator(fOSI). XMC_SCU_HIB_RTCCLKSRC_ULP - ultra low power oscillator(fULP).

Returns

None

Description

Selects the source of RTC clock (fRTC).

The value is configured to RCS bit of HDCR register. fULP needs external input powered by VBAT or VDDP. fOSI is internal clock. The frequency of the clock will be 32.768 kHz.

Note

The register update in HIB domain is indicated by the MIRRST register which can be polled using XMC_SCU_GetMirrorStatus()

Related APIs:

XMC_SCU_HIB_GetRtcClockSource()

void XMC_SCU_HIB_SetSR0Input

(

XMC_SCU_HIB_SR0_INPUT_t

input

)

Parameters

input

input signal HIB_SR0 of ERU0

Returns

None

Description

Selects input to ERU0 module (HIB_SR0).

Note

The register update in HIB domain is indicated by the MIRRST register which can be polled using XMC_SCU_GetMirrorStatus()

Related APIs:

XMC_SCU_HIB_SetInput0(),XMC_SCU_GetMirrorStatus()

void XMC_SCU_HIB_SetStandbyClockSource

(

const XMC_SCU_HIB_STDBYCLKSRC_t

source

)

Parameters

source

Source for standby clock. Range: Use type XMC_SCU_HIB_STDBYCLKSRC_t to identify the clock source. XMC_SCU_HIB_STDBYCLKSRC_OSI - internal slow oscillator (fOSI) XMC_SCU_HIB_STDBYCLKSRC_OSCULP - ultra low power osciallator (fULP)

Returns

None

Description

Selects the source of Standby clock (fSTDBY).

Clock source is configured by setting the STDBYSEL bits of HDCR register. Hibernate domain should be enabled explicitly before using the API.

Note

The register update in HIB domain is indicated by the MIRRST register which can be polled using XMC_SCU_GetMirrorStatus()

Related APIs:

XMC_SCU_HIB_GetStdbyClockSource(), XMC_SCU_HIB_EnableHibernateDomain()

void XMC_SCU_HIB_SetWakeupTriggerInput

(

XMC_SCU_HIB_IO_t

pin

)

Parameters

pin	Hibernate domain dedicated pin XMC_SCU_HIB_IO_t

Returns

None

Description

Selects input for Wake-Up from Hibernate

Note

The register update in HIB domain is indicated by the MIRRST register which can be polled using XMC_SCU_GetMirrorStatus()

Related APIs:

XMC_SCU_GetMirrorStatus()

void XMC_SCU_HIB_TriggerEvent

(

int32_t

event

)

Parameters

event

Hibernate wakeup event XMC_SCU_HIB_EVENT_t

Returns

None

Description

Trigger hibernate wakeup event

Note

The register update in HIB domain is indicated by the MIRRST register which can be polled using XMC_SCU_GetMirrorStatus()

Related APIs:

XMC_SCU_HIB_ClearEventStatus(), XMC_SCU_HIB_EnableEvent(), XMC_SCU_HIB_DisableEvent(), XMC_SCU_GetMirrorStatus()

bool XMC_SCU_HighTemperature

(

void

)

Returns

bool Indicates if the measured die temperature value has exceeded the configured upper limit.
Range: true if the temperature value has exceeded the configured upper limit. false if the temperature value is less than the configured upper limit.

Description

Checks if the measured temperature has exceeded the configured upper limit of temperature.

The API checks OVERFL bit (Upper Limit Overflow Status bit) of DTEMPALARM register. The OVERFL bit will be set if the measured temperature has exceeded the limit configured in the bitfield UPPER in the DTEMPLIM register.

Related APIs:

XMC_SCU_SetRawTempLimits(),XMC_SCU_LowTemperature()

void XMC_SCU_INTERRUPT_ClearEventStatus

(

const XMC_SCU_INTERRUPT_EVENT_t

event

)

Parameters

event

Bit mask of the events to clear. Range: Use type XMC_SCU_INTERRUPT_EVENT_t for providing the input value. Multiple events can be combined using the OR operation.

Returns

None

Description

Clears the event status bit in SRRAW register.

The events are cleared by writing value 1 to their bit positions in the SRCLR register. The API can be used when polling method is used. After detecting the event, the event status should be cleared using software to detect the event again.

Related APIs:

XMC_SCU_INTERUPT_GetEventStatus(), XMC_SCU_INTERRUPT_TriggerEvent()

void XMC_SCU_INTERRUPT_DisableEvent

(

const XMC_SCU_INTERRUPT_EVENT_t

event

)

Parameters

event

Bit mask of the event to disable. Range: Use type XMC_SCU_INTERRUPT_EVENT_t for providing the input value. Multiple events can be combined using the OR operation.

Returns

None

Description

Disables generation of interrupt on occurrence of the input event.

The events are disabled by resetting the respective bit fields in the SRMSK register.

Related APIs:

NVIC_DisableIRQ(), XMC_SCU_INTERRUPT_EnableEvent()

void XMC_SCU_INTERRUPT_DisableNmiRequest

(

const uint32_t

request

)

Parameters

request

Non-maskable interrupt (NMI) request source to be disabled. Range: Use type XMC_SCU_NMIREQ_t for selecting the source of NMI. Multiple sources can be combined using OR operation.

Returns

None

Description

Selectively disables interrupt sources from generating non maskable interrupt(NMI).

NMI assertion can be individually disabled by clearing corresponding bits in the NMIREQEN register.

Related APIs:

XMC_SCU_INTERRUPT_EnableNmiRequest()

void XMC_SCU_INTERRUPT_EnableEvent

(

const XMC_SCU_INTERRUPT_EVENT_t

event

)

Parameters

event

Bit mask of the event to enable. Range: Use type XMC_SCU_INTERRUPT_EVENT_t for providing the input value. Multiple events can be combined using the OR operation.

Returns

None

Description

Enables the generation of interrupt for the input events.

The events are enabled by setting the respective bit fields in the SRMSK register.
Note: User should separately enable the NVIC node responsible for handling the SCU interrupt. The interrupt will be generated when the respective event occurs.

Related APIs:

NVIC_EnableIRQ(), XMC_SCU_INTERRUPT_DisableEvent()

void XMC_SCU_INTERRUPT_EnableNmiRequest

(

const uint32_t

request

)

Parameters

request

Non-maskable interrupt (NMI) request source to be enabled. Range: Use type XMC_SCU_NMIREQ_t for selecting the source of NMI. Multiple sources can be combined using OR operation.

Returns

None

Description

Selectively enables interrupt sources to generate non maskable interrupt(NMI).

NMI assertion can be individually enabled by setting corresponding bit of an interrupt in the NMIREQEN register.

Related APIs:

XMC_SCU_INTERRUPT_DisableNmiRequest()

XMC_SCU_STATUS_t XMC_SCU_INTERRUPT_SetEventHandler	(	const XMC_SCU_INTERRUPT_EVENT_t	event,
		const XMC_SCU_INTERRUPT_EVENT_HANDLER_t	handler
	)

Parameters

event	The event for which the interrupt handler is to be configured. Range: Use type XMC_SCU_INTERRUPT_EVENT_t for identifying the event.
handler	Name of the function to be executed when the event if detected. Range: The function accepts no arguments and returns no value.

Returns

XMC_SCU_STATUS_t Status of configuring the event handler function for the selected event.
Range: XMC_SCU_STATUS_OK if the event handler is successfully configured.
XMC_SCU_STATUS_ERROR if the input event is invalid.

Description

Assigns the event handler function to be executed on occurrence of the selected event.

If the input event is valid, the handler function will be assigned to a table to be executed when the interrupt is generated and the event status is set in the event status register. By using this API, polling for a particular event can be avoided. This way the CPU utilization will be optimized. Multiple SCU events can generate a common interrupt. When the interrupt is generated, a common interrupt service routine is executed. It checks for status flags of events which can generate the interrupt. The handler function will be executed if the event flag is set.

Related APIs:

XMC_SCU_INTERRUPT_TriggerEvent(), XMC_SCU_INTERUPT_GetEventStatus()

void XMC_SCU_INTERRUPT_TriggerEvent

(

const XMC_SCU_INTERRUPT_EVENT_t

event

)

Parameters

event

Bit mask of the event to be triggered. Range: Use type XMC_SCU_INTERRUPT_EVENT_t for providing the input value. Multiple events can be combined using the OR operation.

Returns

None

Description

Triggers the event as if the hardware raised it.

Event will be triggered by setting the respective bitfield in the SRSET register.
Note: User should enable the NVIC node that handles the respective event for interrupt generation.

Related APIs:

NVIC_EnableIRQ(), XMC_SCU_INTERUPT_GetEventStatus(), XMC_SCU_INTERRUPT_ClearEventStatus()

XMC_SCU_INTERRUPT_EVENT_t XMC_SCU_INTERUPT_GetEventStatus

(

void

)

Returns

uint32_t Status of the SCU events.

Description

Provides the status of all SCU events.

The status is read from the SRRAW register. To check the status of a particular event, the returned value should be masked with the bit mask of the event. The bitmask of events can be obtained using the type XMC_SCU_INTERRUPT_EVENT_t. Multiple events' status can be checked by combining the bit masks using OR operation. After detecting the event, the event status should be cleared using software to detect the event again.

Related APIs:

XMC_SCU_INTERRUPT_ClearEventStatus(), XMC_SCU_INTERRUPT_TriggerEvent(), XMC_SCU_INTERRUPT_SetEventHandler()

void XMC_SCU_IRQHandler

(

uint32_t

sr_num

)

Parameters

sr_num

Service request number identifying the SCU interrupt generated. Range: 0 to 2. XMC4x devices have one common SCU interrupt, so the value should be 0. But XMC1x devices support 3 interrupt nodes.

Returns

None

Description

A common function to execute callback functions for multiple events.

It checks for the status of events which can generate the interrupt with the selected service request. If the event is set, the corresponding callback function will be executed. It also clears the event status bit.
Note: This is an internal function. It should not be called by the user application.

Related APIs:

XMC_SCU_INTERRUPT_SetEventHandler()

bool XMC_SCU_IsTemperatureSensorBusy

(

void

)

Returns

bool Indicates if the die temperature sensor is busy.
Range: true if sensor is busy in temperature measurement. false if sensor is free and can accept a new request for measurement.

Description

Checks whether Die Temperature Sensor (DTS) is busy in temperature measurement.

The status is read from the BUSY bit field of the DTSSTAT register.

Related APIs:

XMC_SCU_GetTemperatureMeasurement()

bool XMC_SCU_IsTemperatureSensorEnabled

(

void

)

Returns

Status of die temperature sensor.
Range: true - if temperature sensor is enabled.
false - if temperature sensor is disabled.

Description

Provides the die temperature sensor power status.

The status is obtained by reading the PWD bit of DTSCON register.

Related APIs:

XMC_SCU_EnableTemperatureSensor(), XMC_SCU_CalibrateTemperatureSensor(), XMC_SCU_StartTemperatureMeasurement(), XMC_SCU_GetTemperatureMeasurement()

bool XMC_SCU_IsTemperatureSensorReady

(

void

)

Returns

bool Status of die temperature sensor whether it is ready to start measurement.
Range:
true if temperature sensor is ready to start measurement.
false if temperature sensor is not ready to start measurement.

Description

Checks if the die temperature sensor is ready to start a measurement

The status is obtained by reading RDY bit of DTSSTAT register. It is recommended to check the ready status of die temperature sensor before starting it.

Related APIs:

XMC_SCU_StartTemperatureMeasurement(), XMC_SCU_IsTemperatureSensorBusy()

bool XMC_SCU_LowTemperature

(

void

)

Returns

bool Indicates if the measured die temperature value has dropped below the configured lower limit.
Range: true if the temperature value has dropped below the configured lower limit. false if the temperature value is higher than the configured lower limit.

Description

Checks if the measured temperature has dropped below the configured lower limit of temperature.

The API checks UNDERFL bit (Lower LimitUnderflow Status bit) of DTEMPALARM register. The UNDERFL bit will be set if the measured temperature has dropped below the limit configured in the bitfield LOWER in the DTEMPLIM register.

Related APIs:

XMC_SCU_SetRawTempLimits(),XMC_SCU_HighTemperature()

void XMC_SCU_PARITY_ClearStatus

(

const uint32_t

memory

)

Parameters

memory

The on-chip RAM type, for which the parity error status has to be cleared. Range: Use type XMC_SCU_PARITY_t to identify the on-chip RAM type. Multiple memory status bits can be cleared by using the OR operation.

Returns

None

Description

Clears the parity error status bit.

When a memory parity error is detected using the status bits in PEFLAG register. It has to be cleared by software to detect the parity error from the same memory next time. The API clears the parity error status bit of the selected peripheral by setting the respective bit in the PEFLAG register. Status of multiple memory parity errors can be cleared by combining the enum values using OR operation.

Related APIs:

XMC_SCU_PARITY_GetStatus(), XMC_SCU_PARITY_Enable(), XMC_SCU_PARITY_EnableTrapGeneration()

void XMC_SCU_PARITY_Disable

(

const uint32_t

memory

)

Parameters

memory

The on-chip RAM type, for which the parity error checking has to be disabled. Range: Use type XMC_SCU_PARITY_t to identify the on-chip RAM type. Multiple memory types can be combined using the OR operation.

Returns

None

Description

Disables parity error checking for the selected on-chip RAM type.

Parity error detection can be disabled by clearing the respective bit in the PEEN register.

Related APIs:

XMC_SCU_PARITY_Enable(), XMC_SCU_PARITY_DisableTrapGeneration()

void XMC_SCU_PARITY_DisableTrapGeneration

(

const uint32_t

memory

)

Parameters

memory

The on-chip RAM type, for which the parity error trap generation has to be disabled. Range: Use type XMC_SCU_PARITY_t to identify the on-chip RAM type. Multiple memory types can be combined using the OR operation.

Returns

None

Description

Disables the assertion of trap for the parity error source.

Trap assertion can be disabled by clearing the respective bit of the RAM type in the PETE register.

Related APIs:

XMC_SCU_PARITY_EnableTrapGeneration()

void XMC_SCU_PARITY_Enable

(

const uint32_t

memory

)

Parameters

memory

The on-chip RAM type, for which the parity error checking has to be enabled. Range: Use type XMC_SCU_PARITY_t to identify the on-chip RAM type. Multiple memory types can be combined using the OR operation.

Returns

None

Description

Enables parity error checking for the selected on-chip RAM type.

Parity error checking can be enabled by setting respective bits in the PEEN register. Additionally parity error can be configured to generate trap when the error is detected, using the API XMC_SCU_PARITY_EnableTrapGeneration(). Such a trap can be further configured to generate non maskable interrupt(NMI) using the API XMC_SCU_INTERRUPT_EnableNmiRequest().

Related APIs:

XMC_SCU_PARITY_EnableTrapGeneration(), XMC_SCU_INTERRUPT_EnableNmiRequest()

void XMC_SCU_PARITY_EnableTrapGeneration

(

const uint32_t

memory

)

Parameters

memory

The on-chip RAM type, for which the parity error trap generation has to be enabled. Range: Use type XMC_SCU_PARITY_t to identify the on-chip RAM type. Multiple memory types can be combined using the OR operation.

Returns

None

Description

Enables trap assertion for the parity error source.

Parity error detection for different types of on-chip RAM can generate trap. Trap assertion for parity error can be individually enabled by setting the respective bits in the PETE register. The generated trap can be additionally configured to generate non maskable interrupt(NMI) using the API XMC_SCU_INTERRUPT_EnableNmiRequest().

Related APIs:

XMC_SCU_INTERRUPT_EnableNmiRequest(), XMC_SCU_PARITY_DisableTrapGeneration()

uint32_t XMC_SCU_PARITY_GetStatus

(

void

)

Returns

uint32_t Status of parity error detection for the on-chip RAM modules.
Range: Use type XMC_SCU_PARITY_t to get the bit mask of each RAM module type.

Description

Provides the status of parity error detection for the on-chip RAM modules.

Parity error status information is obtained from the PEFLAG register. If a particular RAM module has parity error, its respective bit field will be set to 1 in the returned value. A check for the status of a particular RAM module can be done by masking the returned value with the RAM module identifier from the type XMC_SCU_PARITY_t.

Related APIs:

XMC_SCU_PARITY_ClearStatus()

void XMC_SCU_POWER_DisableMonitor

(

void

)

Returns

None

Disable power monitoring control register for brown-out detection.

void XMC_SCU_POWER_DisableUsb

(

void

)

Returns

None

Description

Disables the USB PHY and also OTG comparator if available.

Configures the USBPHYPDQ bit of PWRSET register to move the USB PHY to power down state. If USB OTG is available in the device, the USBOTGEN bit of PWRSET register is set to 0. This disables the USB on the go comparators.

Related APIs:

XMC_SCU_POWER_EnableUsb(), XMC_SCU_CLOCK_SetUsbClockSource()

void XMC_SCU_POWER_EnableMonitor	(	uint8_t	threshold,
		uint8_t	interval
	)

Parameters

threshold	Threshold value for comparison to VDDP for brownout detection. LSB33V is 22.5mV
interval	Interval value for comparison to VDDP expressed in cycles of system clock

Returns

None

Enable power monitoring control register for brown-out detection. Brown Out Trap need to be enabled using XMC_SCU_TRAP_Enable() and event handling done in NMI_Handler.

Related APIs:

XMC_SCU_TRAP_Enable()

void XMC_SCU_POWER_EnableUsb

(

void

)

Returns

None

Description

Enables the USB PHY and also OTG comparator if available.

Configures the USBPHYPDQ bit of PWRSET register to move the USB PHY from power down state. If USB OTG is available in the device, the USBOTGEN bit of PWRSET register is set to 1. This enables the USB on the go comparators.

Related APIs:

XMC_SCU_POWER_DisableUsb(), XMC_SCU_CLOCK_SetUsbClockSource()

float XMC_SCU_POWER_GetEVR13Voltage

(

void

)

Returns

EVR13 voltage in volts

Description

Returns EVR13 voltage in volts.

float XMC_SCU_POWER_GetEVR33Voltage

(

void

)

Returns

EVR33 voltage in volts

Description

Returns EVR33 voltage in volts

int32_t XMC_SCU_POWER_GetEVRStatus

(

void

)

Returns

XMC_SCU_POWER_EVR_STATUS_t

Description

Returns status of the EVR13.

void XMC_SCU_POWER_WaitForEvent

(

XMC_SCU_POWER_MODE_t

mode

)

Parameters

mode	Low power mode

Returns

None

Description

Enter selected low power mode and wait for event

Related APIs:

XMC_SCU_CLOCK_SetSleepConfig(), XMC_SCU_CLOCK_SetDeepSleepConfig()

void XMC_SCU_POWER_WaitForInterrupt	(	XMC_SCU_POWER_MODE_t	mode,
		bool	sleep_on_exit
	)

Parameters

mode	Low power mode
sleep_on_exit	Enter sleep, or deep sleep, on return from an ISR

Returns

None

Description

Enter selected low power mode and wait for interrupt

Related APIs:

XMC_SCU_CLOCK_SetSleepConfig(), XMC_SCU_CLOCK_SetDeepSleepConfig()

uint32_t XMC_SCU_ReadFromRetentionMemory

(

uint32_t

address

)

Parameters

address

Location in the retention memory to be read. Range: 4 bit address space is provided for selecting 16 words of 32 bits. equivalent to 64 bytes of data. address value should be from 0 to 15.

Returns

uint32_t 32 bit data read from retention memory. The API reads one word(4 bytes) of data from the address specified.
Range: 32 bit data.

Description

Reads data from selected address of retention memory in hibernate domain.

The retention memory is located in hibernate domain. It is used for the purpose of store/restore of context information. Access to the retention memory space is served over shared serial interface. Retention memory content is retained even in hibernate mode.

Related APIs:

XMC_SCU_WriteToRetentionMemory()

uint32_t XMC_SCU_ReadGPR

(

const uint32_t

index

)

Parameters

index

The SCU general purpose register to be read. Range: 0 and 1 corresponding to GPR0 and GPR1.

Returns

uint32_t Data read from the selected general purpose register.

Description

Provides stored data from general purpose SCU register.

SCU consists of 2 general purpose registers. These registers can be used for storing data. The API reads from either GPR0 or GPR1 based on the index value.

Related APIs:

XMC_SCU_WriteGPR()

void XMC_SCU_RESET_AssertPeripheralReset

(

const XMC_SCU_PERIPHERAL_RESET_t

peripheral

)

Parameters

peripheral

The peripheral to be reset. Range: Type XMC_SCU_PERIPHERAL_RESET_t enumerates all the peripherals that can be reset.

Returns

None

Description

Puts the specified peripheral in to reset state.

The API achieves reset of peripherals by setting the respective bit in the PRSET0, PRSET1 or PRSET2 register. Status of reset assertion automatically stored in the PRSTATn register and can be checked by user software to determine the state of the system and for debug purpose.
It is recommended to use following steps to assert a peripheral reset:

• Call XMC_SCU_RESET_AssertPeripheralReset() with desired peripheral identifier.
  
• Call XMC_SCU_RESET_IsPeripheralResetAsserted with same peripheral identifier to verify whether peripheral is in reset state.
  

Related APIs:

XMC_SCU_RESET_IsPeripheralResetAsserted()

void XMC_SCU_RESET_ClearDeviceResetReason

(

void

)

Returns

None

Description

Clears the reset reason bits in the reset status register.

Clearing of the reset status information in the SCU_RSTSTAT register via register bit RSTCLR.RSCLR is strongly recommended to ensure a clear indication of the cause of next reset.

Related APIs:

XMC_SCU_RESET_GetDeviceResetReason()

void XMC_SCU_RESET_DeassertPeripheralReset

(

const XMC_SCU_PERIPHERAL_RESET_t

peripheral

)

Parameters

peripheral

The peripheral to be moved out of reset state. Range: Type XMC_SCU_PERIPHERAL_RESET_t enumerates all the peripherals that can be reset.

Returns

None

Description

Enables the specified peripheral by moving it out of reset state.

Any peripheral should be moved out of reset state for executing its functionality. The API enables the peripheral by setting its respective bit in the PRCLR0, PRCLR1 or PRCLR2 register. Status of reset deassertion is automatically stored in the PRSTATn register and can be checked by the user software to determine the state of the system and for debug purpose.
It is recommended to use following steps to deassert a peripheral reset:

• Call XMC_SCU_RESET_DeassertPeripheralReset() with desired peripheral identifier.
  
• Call XMC_SCU_RESET_IsPeripheralResetAsserted() with desired peripheral identifier to verify whether peripheral has been enabled.
  

Related APIs:

XMC_SCU_RESET_AssertPeripheralReset()

uint32_t XMC_SCU_RESET_GetDeviceResetReason

(

void

)

Returns

uint32_t Status representing the reason for device reset.

Description

Provides the value representing the reason for device reset.

The return value is an encoded word, which can indicate multiple reasons for the last reset. Each bit position of the returned word is representative of a last reset cause. The returned value should be appropriately masked to check the cause of reset. The cause of the last reset gets automatically stored in the SCU_RSTSTAT register. The reset status shall be reset after each startup in order to ensure consistent source indication after the next reset. Range: The type XMC_SCU_RESET_REASON_t can be used to get the bit masks of the reset cause.

Related APIs:

XMC_SCU_RESET_ClearDeviceResetReason()

bool XMC_SCU_RESET_IsPeripheralResetAsserted

(

const XMC_SCU_PERIPHERAL_RESET_t

peripheral

)

Parameters

peripheral

The peripheral, whose reset status has to be checked. Range: Type XMC_SCU_PERIPHERAL_RESET_t enumerates all the peripherals.

Returns

bool Status of peripheral reset.
Range: true if peripheral is in reset state. false if peripheral is enabled and out of reset state.

Description

Checks the reset status of the selected peripheral.

The API reads the reset status from PRSTATn register. Returns true if the peripheral is in reset state. On power up of the device, all the peripherals will be in reset state. If the peripheral is enabled, false will be returned as the status.

Related APIs:

XMC_SCU_RESET_AssertPeripheralReset(), XMC_SCU_RESET_DeassertPeripheralReset()

void XMC_SCU_SetBootMode

(

const XMC_SCU_BOOTMODE_t

mode

)

Parameters

mode	Boot mode to be configured for the device. Range: Use type XMC_SCU_BOOTMODE_t for selecting the boot mode.

Returns

None

Description

Configures the desired boot mode for the device.

The XMC4 series devices support multiple boot modes. A running application can set a desired bootmode and launch it by means of software reset. Switching of boot modes should be handled carefully. User should ensure that the initial boot sequence is executed. A stable execution environment should be maintained when program control is eventually handed over to the application program.
It is recommended to use following steps to launch requested bootmode:

• Call XMC_SCU_SetBootMode() with desired boot mode value.
  
• Trigger a software reset using system reset request by enabling a bit SYSRESETREQ of AIRCR register (PPB->AIRCR |= PPB_AIRCR_SYSRESETREQ_Msk).
  

Related APIs:

XMC_SCU_GetBootMode()

void XMC_SCU_SetCcuTriggerHigh

(

const uint32_t

trigger

)

Parameters

trigger

CCU slices to be triggered synchronously via software. The value is a bitmask of CCU slice bits in the register CCUCON. Range: Use type XMC_SCU_CCU_TRIGGER_t for bitmask of individual CCU slices. Multiple slices can be combined using OR operation.

Returns

None

Description

Generates active edge(low to high) trigger for multiple CCU units at the same time.

Before executing this API, all the required CCU timers should configure external start. The edge of the start signal should be selected as active edge. The input signal for the CCU slice should be selected as SCU input. The above mentioned configurations can be made using the CCU LLD API XMC_CCU4_SLICE_StartConfig(). CCU timer slice should be started using XMC_CCU4_SLICE_StartTimer() before triggering the timer using this API.

Related APIs:

XMC_CCU4_SLICE_StartConfig(), XMC_CCU4_SLICE_SetInput(), XMC_SCU_SetCcuTriggerLow()

void XMC_SCU_SetCcuTriggerLow

(

const uint32_t

trigger

)

Parameters

trigger

CCU slices to be triggered synchronously via software. The value is a bitmask of CCU slice bits in the register CCUCON. Range: Use type XMC_SCU_CCU_TRIGGER_t for bitmask of individual CCU slices. Multiple slices can be combined using OR operation.

Returns

None

Description

Generates passive edge(high to low) trigger for multiple CCU units at the same time.

Before executing this API, all the required CCU timers should configure external start. The edge of the start signal should be selected as passive edge. The input signal for the CCU slice should be selected as SCU input. The above mentioned configurations can be made using the CCU LLD API XMC_CCU4_SLICE_StartConfig(). CCU timer slice should be started using XMC_CCU4_SLICE_StartTimer() before triggering the timer using this API.

Related APIs:

XMC_CCU4_SLICE_StartConfig(), XMC_CCU4_SLICE_SetInput(), XMC_SCU_SetCcuTriggerHigh()

void XMC_SCU_SetRawTempLimits	(	const uint32_t	lower_temp,
		const uint32_t	upper_temp
	)

Parameters

lower_temp	Lower threshold of die temperature. If measured temperature falls below this value, alarm bit will be set in UNDERFL bit field of DTEMPALARM register.
upper_temp	Upper threshold of die temperature. If measured temperature exceeds this value, alarm bit will be set in OVERFL bit field of DTEMPALARM register.

Returns

None

Description

Configures the lower and upper threshold of die temperature.

API configures DTEMPLIM register for upper and lower die temperature threshold limits. When the measured temperature is outside the range defined by the limits, alarm bits UNDERFL or OVERFL will be set in the register DTEMPALARM.
It is recommended to use following steps:

• Call XMC_SCU_StopTempMeasurement to stop temperature measurement if it was started previously.
  
• Call XMC_SCU_SetRawTempLimits with desired lower and upper temperature threshold limit values.
  
• Call XMC_SCU_StartTempMeasurement to start temperature measurement.
  
• Use XMC_SCU_HighTemperature() and XMC_SCU_LowTemperature() to monitor the temperature.
  

Related APIs:

XMC_SCU_HighTemperature(), XMC_SCU_LowTemperature()

XMC_SCU_STATUS_t XMC_SCU_StartTemperatureMeasurement

(

void

)

Returns

XMC_SCU_STATUS_t Result of starting the temperature measurement.
Range:
XMC_SCU_STATUS_OK if the measurement is started successfully.
XMC_SCU_STATUS_ERROR if temperature sensor is not enabled.
XMC_SCU_STATUS_BUSY if temperature sensor is busy measuring the temperature.

Description

Starts die temperature measurement using internal temperature sensor.

The API checks if the temperature sensor is enabled and is not busy in measurement.
It is recommended to use following steps:

• Call XMC_SCU_StopTempMeasurement to stop temperature measurement if it was started previously.
  
• Call XMC_SCU_SetRawTempLimits with desired lower and upper temperature threshold limit values if it is needed.
  
• Call XMC_SCU_StartTempMeasurement to start temperature measurement.
  
• Check whether Die Temperature Sensor (DTS) is busy in conversion by calling XMC_SCU_IsTemperatureSensorBusy() and wait till conversion complete.
  
• Read the die temperature value using XMC_SCU_GetTemperatureMeasurement API.

Related APIs:

XMC_SCU_EnableTemperatureSensor(), XMC_SCU_CalibrateTemperatureSensor(), XMC_SCU_GetTemperatureMeasurement()

void XMC_SCU_TRAP_ClearStatus

(

const uint32_t

trap

)

Parameters

trap	The event for which, trap status bit has to be cleared. Range: Use type XMC_SCU_TRAP_t to identify the event.

Returns

None

Description

Clears the trap status of input event.

Once a trap event is detected, it will have to be acknowledged and later serviced. The trap status bit should be cleared to detect the occurence of trap next time. This is useful while polling for TRAPSTAT without enabling the NMI for trap. Trap status can be cleared by setting the event bit in the TRAPCLR register.

Related APIs:

XMC_SCU_INTERRUPT_EnableNmiRequest(), XMC_SCU_TRAP_GetStatus()

void XMC_SCU_TRAP_Disable

(

const uint32_t

trap

)

Parameters

trap	The event for which, trap generation has to be disabled. Range: Use type XMC_SCU_TRAP_t to identify the event.

Returns

None

Description

Disables assertion of trap for the selected trap event.

Trap assertion can be individually disabled by setting the respective event bit in the TRAPDIS register in order to suppress trap generation.

Related APIs:

XMC_SCU_TRAP_Enable(), XMC_SCU_TRAP_ClearStatus(), XMC_SCU_TRAP_GetStatus()

void XMC_SCU_TRAP_Enable

(

const uint32_t

trap

)

Parameters

trap	The event for which, trap generation has to be enabled. Range: Use type XMC_SCU_TRAP_t to identify the event.

Returns

None

Description

Enables assertion of trap for the selected trap event.

Trap assertion can be individually enabled by clearing respective bit of the event in TRAPDIS register in order to get an exception.

Related APIs:

XMC_SCU_TRAP_Disable(), XMC_SCU_TRAP_ClearStatus(), XMC_SCU_TRAP_GetStatus()

uint32_t XMC_SCU_TRAP_GetStatus

(

void

)

Returns

uint32_t Status of trap generating events.
Range: Use type XMC_SCU_TRAP_t to identify the event. The returned value indicates the status of multiple events at their respective bit positions. User should mask the bits of the events of interest using the type specified.

Description

Provides the status of trap generating events.

The status is read from TRAPRAW register. Status of the specific events can be checked using their respective bits in the TRAPRAW register. The bit masks can be obtained from the enumeration type XMC_SCU_TRAP_t. Multiple events can be combined using OR operation. A trap event is considered to be asserted if the respective bit of the event is set to 1.

Related APIs:

XMC_SCU_INTERRUPT_EnableNmiRequest(), XMC_SCU_TRAP_ClearStatus()

void XMC_SCU_TRAP_Trigger

(

const uint32_t

trap

)

Parameters

trap	The event for which, trap has to be triggered. Range: Use type XMC_SCU_TRAP_t to identify the event.

Returns

None

Description

Triggers trap generation for the event specified.

The trap source has to be enabled before invocation of this API. Trap event can be triggered by setting its respective bit in the TRAPSET register. Trap event can be configured to generate a non maskable interrupt by using the API XMC_SCU_INTERRUPT_EnableNmiRequest().
It is recommended to use following steps to manually assert a trap event:

• Call XMC_SCU_TRAP_EnableEvent with desired trap request source ID.
  
• Call XMC_SCU_TRAP_SetEvent with same trap request source ID to manually assert a trap event.
  

Related APIs:

XMC_SCU_INTERRUPT_EnableNmiRequest(), XMC_SCU_TRAP_GetStatus()

void XMC_SCU_WriteGPR	(	const uint32_t	index,
		const uint32_t	data
	)

Parameters

index	The SCU general purpose register to be written. Range: 0 and 1 corresponding to GPR0 and GPR1.
data	Data to be written to the selected general purpose register.

Returns

None

Description

Stores data in the selected general purpose SCU register.

SCU consists of 2 general purpose registers. These registers can be used for storing data. The API writes data to either GPR0 or GPR1 based on the index value.

Related APIs:

XMC_SCU_ReadGPR()

void XMC_SCU_WriteToRetentionMemory	(	uint32_t	address,
		uint32_t	data
	)

Parameters

address	Location in the retention memory to be written. Range: 4 bit address space is provided for selecting 16 words of 32 bits. equivalent to 64 bytes of data. address value should be from 0 to 15.
data	32 bit data to be written into retention memory. The API writes one word(4 bytes) of data to the address specified. Range: 32 bit data.

Returns

None

Description

Writes input data to the selected address of Retention memory in hibernate domain.

The retention memory is located in hibernate domain. It is used for the purpose of store/restore of context information. Access to the retention memory space is served over shared serial interface. Retention memory content is retained even in hibernate mode.

Related APIs:

XMC_SCU_ReadFromRetentionMemory()