XMC Peripheral Library for XMC4000 Family: XMC_USIC_CH_t Struct Reference

XMC Peripheral Library for XMC4000 Family

XMC Peripheral Library for XMC4000 Family  2.1.16
XMC_USIC_CH_t Struct Reference

#include <xmc_usic.h>

Data Fields

__IO uint32_t BRG
 
__IO uint32_t BYP
 
__IO uint32_t BYPCR
 
__I uint32_t CCFG
 
__IO uint32_t CCR
 
__IO uint32_t CMTR
 
__IO uint32_t DXCR [6]
 
__IO uint32_t FDR
 
__O uint32_t FMR
 
__O uint32_t IN [32]
 
__IO uint32_t INPR
 
__IO uint32_t KSCFG
 
__I uint32_t OUTDR
 
__I uint32_t OUTR
 
__O uint32_t PSCR
 
__IO uint32_t RBCTR
 
__I uint32_t RBUF
 
__I uint32_t RBUF0
 
__I uint32_t RBUF01SR
 
__I uint32_t RBUF1
 
__I uint32_t RBUFD
 
__I uint32_t RBUFSR
 
__IO uint32_t SCTR
 
__IO uint32_t TBCTR
 
__IO uint32_t TBUF [32]
 
__I uint32_t TRBPTR
 
__O uint32_t TRBSCR
 
__IO uint32_t TRBSR
 
__IO uint32_t PCR
 
__IO uint32_t PCR_ASCMode
 
__IO uint32_t PCR_IICMode
 
__IO uint32_t PCR_IISMode
 
__IO uint32_t PCR_SSCMode
 
__IO uint32_t PSR
 
__IO uint32_t PSR_ASCMode
 
__IO uint32_t PSR_IICMode
 
__IO uint32_t PSR_IISMode
 
__IO uint32_t PSR_SSCMode
 

Detailed Description

USIC channel structure.
The members of the structure are same as in the device header file, except for some registers. DX0CR, DX1CR, DX2CR, DX3CR, DX4CR and DX5CR are replaced with the array DXCR[6]. TBUF0 to TBUF31 are replaced with TBUF[32]. IN0 to IN31 are replaced with IN[32].

Field Documentation

__IO uint32_t BRG

Baud rate generator register

__IO uint32_t BYP

FIFO bypass register

__IO uint32_t BYPCR

FIFO bypass control register

__I uint32_t CCFG

Channel configuration register

__IO uint32_t CCR

Channel control register

__IO uint32_t CMTR

Capture mode timer register

__IO uint32_t DXCR[6]

Input control registers DX0 to DX5.

__IO uint32_t FDR

Fractional divider configuration register

__O uint32_t FMR

Flag modification register

__O uint32_t IN[32]

Transmit FIFO input register

__IO uint32_t INPR

Interrupt node pointer register

__IO uint32_t KSCFG

Kernel state configuration register

__I uint32_t OUTDR

Receive FIFO debug output register

__I uint32_t OUTR

Receive FIFO output register

__IO uint32_t PCR

Protocol configuration register

__IO uint32_t PCR_ASCMode

UART protocol configuration register

__IO uint32_t PCR_IICMode

I2C protocol configuration register

__IO uint32_t PCR_IISMode

I2S protocol configuration register

__IO uint32_t PCR_SSCMode

SPI protocol configuration register

__O uint32_t PSCR

Protocol status clear register

__IO uint32_t PSR

Protocol status register

__IO uint32_t PSR_ASCMode

UART protocol status register

__IO uint32_t PSR_IICMode

I2C protocol status register

__IO uint32_t PSR_IISMode

I2S protocol status register

__IO uint32_t PSR_SSCMode

SPI protocol status register

__IO uint32_t RBCTR

Receive FIFO control register

__I uint32_t RBUF

Receive buffer register

__I uint32_t RBUF0

Receive buffer 0

__I uint32_t RBUF01SR

Receive buffer status register

__I uint32_t RBUF1

Receive buffer 1

__I uint32_t RBUFD

Debug mode receive buffer register

__I uint32_t RBUFSR

Receive buffer status register

__IO uint32_t SCTR

Shift control register

__IO uint32_t TBCTR

Transmit FIFO control register

__IO uint32_t TBUF[32]

Tranmsit buffer registers

__I uint32_t TRBPTR

Transmit/recive buffer pointer register

__O uint32_t TRBSCR

Transmit/receive buffer status clear register

__IO uint32_t TRBSR

Transmit/receive buffer status register


The documentation for this struct was generated from the following file:
Generated on Mon Aug 7 2017 11:33:58 for XMC Peripheral Library for XMC4000 Family by   doxygen 1.8.11