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XMC Peripheral Library for XMC4000 Family Documentation
XMC Peripheral Library for XMC4000 Family: Globals
XMC Peripheral Library for XMC4000 Family
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XMC Peripheral Library for XMC4000 Family
2.1.16
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- c -
CAN_MO_MOIPR_Msk :
xmc_can.h
CAN_NODE_NIPR_Msk :
xmc_can.h
Generated on Mon Aug 7 2017 11:33:59 for XMC Peripheral Library for XMC4000 Family by
1.8.11
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Table of contents
XMC Peripheral Library
Supported devices and toolchains
Overview
Coding Rules and Conventions
How to use the XMC Peripheral Library
Device Names
Directories and Files
XMC Lib examples
Keil MDK-ARM
IAR Embedded Workbench for ARM
DAVE
MISRA-C 2004 Compliance Exceptions
Test conditions
XMC Peripheral Library Licensing
Changelog
Version 2.1.16
COMMON
ETH_MAC
RTC
Version 2.1.14
CCU8
CCU4
ECAT
POSIF
EBU
SCU
Version 2.1.12
Version 2.1.10
ADC
DMA
ERU
LEDTS
SDMMC
USIC
Version 2.1.8
GENERAL
CAN
GPIO
I2C
I2S
SPI
UART
VADC
Version 2.1.6
FLASH
Version 2.1.4
ETH_PHY
Version 2.1.2
DSD
WDT
Version 2.0.0
HRPWM
USBD
Version 1.0.0
Modules
XMC Peripheral Library
CAN
XMC_CAN_FIFO_CONFIG_t
fifo_base
fifo_bottom
fifo_top
XMC_CAN_GATEWAY_CONFIG_t
gateway_base
gateway_bottom
gateway_data_copy
gateway_data_frame_send
gateway_data_length_code_copy
gateway_identifier_copy
gateway_top
XMC_CAN_MO_t
can_data
can_data_byte
can_data_length
can_data_word
can_id_mask
can_id_mode
can_ide_mask
can_identifier
can_mo_ptr
can_mo_type
can_priority
XMC_CAN_NODE_FRAME_COUNTER_t
can_frame_count_mode
can_frame_count_selection
XMC_CAN_NODE_NOMINAL_BIT_TIME_CONFIG_t
baudrate
can_frequency
sample_point
sjw
CAN_MO_MOIPR_Msk
CAN_NODE_NIPR_Msk
XMC_CAN_MO_MOAR_STDID_Msk
XMC_CAN_MO_MOAR_STDID_Pos
XMC_CAN_NODE_t
XMC_CAN_t
XMC_CAN_ARBITRATION_MODE_t
XMC_CAN_ARBITRATION_MODE_ORDER_BASED_PRIO_1
XMC_CAN_ARBITRATION_MODE_IDE_DIR_BASED_PRIO_2
XMC_CAN_ARBITRATION_MODE_ORDER_BASED_PRIO_3
XMC_CAN_CANCLKSRC_t
XMC_CAN_DM_t
XMC_CAN_DM_NORMAL
XMC_CAN_DM_FRACTIONAL
XMC_CAN_DM_OFF
XMC_CAN_FRAME_COUNT_MODE_t
XMC_CAN_FRAME_COUNT_MODE
XMC_CAN_FRAME_COUNT_MODE_TIME_STAMP
XMC_CAN_FRAME_COUNT_MODE_BIT_TIMING
XMC_CAN_FRAME_TYPE_t
XMC_CAN_FRAME_TYPE_STANDARD_11BITS
XMC_CAN_FRAME_TYPE_EXTENDED_29BITS
XMC_CAN_LOOKBACKMODE_t
XMC_CAN_LOOKBACKMODE_ENABLED
XMC_CAN_LOOKBACKMODE_DISABLED
XMC_CAN_MO_EVENT_t
XMC_CAN_MO_EVENT_TRANSMIT
XMC_CAN_MO_EVENT_RECEIVE
XMC_CAN_MO_EVENT_OVERFLOW
XMC_CAN_MO_POINTER_EVENT_t
XMC_CAN_MO_POINTER_EVENT_TRANSMIT
XMC_CAN_MO_POINTER_EVENT_RECEIVE
XMC_CAN_MO_RESET_STATUS_t
XMC_CAN_MO_RESET_STATUS_RX_PENDING
XMC_CAN_MO_RESET_STATUS_TX_PENDING
XMC_CAN_MO_RESET_STATUS_RX_UPDATING
XMC_CAN_MO_RESET_STATUS_NEW_DATA
XMC_CAN_MO_RESET_STATUS_MESSAGE_LOST
XMC_CAN_MO_RESET_STATUS_MESSAGE_VALID
XMC_CAN_MO_RESET_STATUS_RX_TX_SELECTED
XMC_CAN_MO_RESET_STATUS_RX_ENABLE
XMC_CAN_MO_RESET_STATUS_TX_REQUEST
XMC_CAN_MO_RESET_STATUS_TX_ENABLE0
XMC_CAN_MO_RESET_STATUS_TX_ENABLE1
XMC_CAN_MO_RESET_STATUS_MESSAGE_DIRECTION
XMC_CAN_MO_SET_STATUS_t
XMC_CAN_MO_SET_STATUS_RX_PENDING
XMC_CAN_MO_SET_STATUS_TX_PENDING
XMC_CAN_MO_SET_STATUS_RX_UPDATING
XMC_CAN_MO_SET_STATUS_NEW_DATA
XMC_CAN_MO_SET_STATUS_MESSAGE_LOST
XMC_CAN_MO_SET_STATUS_MESSAGE_VALID
XMC_CAN_MO_SET_STATUS_RX_TX_SELECTED
XMC_CAN_MO_SET_STATUS_RX_ENABLE
XMC_CAN_MO_SET_STATUS_TX_REQUEST
XMC_CAN_MO_SET_STATUS_TX_ENABLE0
XMC_CAN_MO_SET_STATUS_TX_ENABLE1
XMC_CAN_MO_SET_STATUS_MESSAGE_DIRECTION
XMC_CAN_MO_STATUS_t
XMC_CAN_MO_STATUS_RX_PENDING
XMC_CAN_MO_STATUS_TX_PENDING
XMC_CAN_MO_STATUS_RX_UPDATING
XMC_CAN_MO_STATUS_NEW_DATA
XMC_CAN_MO_STATUS_MESSAGE_LOST
XMC_CAN_MO_STATUS_MESSAGE_VALID
XMC_CAN_MO_STATUS_RX_TX_SELECTED
XMC_CAN_MO_STATUS_RX_ENABLE
XMC_CAN_MO_STATUS_TX_REQUEST
XMC_CAN_MO_STATUS_TX_ENABLE0
XMC_CAN_MO_STATUS_TX_ENABLE1
XMC_CAN_MO_STATUS_MESSAGE_DIRECTION
XMC_CAN_MO_STATUS_LIST
XMC_CAN_MO_STATUS_POINTER_TO_PREVIOUS_MO
XMC_CAN_MO_STATUS_POINTER_TO_NEXT_MO
XMC_CAN_MO_TYPE_t
XMC_CAN_MO_TYPE_RECMSGOBJ
XMC_CAN_MO_TYPE_TRANSMSGOBJ
XMC_CAN_NODE_CONTROL_t
XMC_CAN_NODE_CONTROL_NODE_INIT
XMC_CAN_NODE_CONTROL_TX_INT_ENABLE
XMC_CAN_NODE_CONTROL_LEC_INT_ENABLE
XMC_CAN_NODE_CONTROL_ALERT_INT_ENABLE
XMC_CAN_NODE_CONTROL_CAN_DISABLE
XMC_CAN_NODE_CONTROL_CONF_CHANGE_ENABLE
XMC_CAN_NODE_CONTROL_CAN_ANALYZER_NODEDE
XMC_CAN_NODE_CONTROL_SUSPENDED_ENABLE
XMC_CAN_NODE_EVENT_t
XMC_CAN_NODE_EVENT_TX_INT
XMC_CAN_NODE_EVENT_ALERT
XMC_CAN_NODE_EVENT_LEC
XMC_CAN_NODE_EVENT_CFCIE
XMC_CAN_NODE_INTERRUPT_TRIGGER_t
XMC_CAN_NODE_LAST_ERROR_DIR_t
XMC_CAN_NODE_LAST_ERROR_DIR_WHILE_NODE_RECEPCION
XMC_CAN_NODE_LAST_ERROR_DIR_WHILE_NODE_TRANSMISSION
XMC_CAN_NODE_LAST_ERROR_INC_t
XMC_CAN_NODE_LAST_ERROR_INC_1
XMC_CAN_NODE_LAST_ERROR_INC_8
XMC_CAN_NODE_POINTER_EVENT_t
XMC_CAN_NODE_POINTER_EVENT_ALERT
XMC_CAN_NODE_POINTER_EVENT_LEC
XMC_CAN_NODE_POINTER_EVENT_TRANSFER_OK
XMC_CAN_NODE_POINTER_EVENT_FRAME_COUNTER
XMC_CAN_NODE_RECEIVE_INPUT_t
XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
XMC_CAN_NODE_RECEIVE_INPUT_RXDCD
XMC_CAN_NODE_RECEIVE_INPUT_RXDCE
XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
XMC_CAN_NODE_RECEIVE_INPUT_RXDCG
XMC_CAN_NODE_RECEIVE_INPUT_RXDCH
XMC_CAN_NODE_STATUS_t
XMC_CAN_NODE_STATUS_LAST_ERROR_CODE
XMC_CAN_NODE_STATUS_TX_OK
XMC_CAN_NODE_STATUS_RX_OK
XMC_CAN_NODE_STATUS_ALERT_WARNING
XMC_CAN_NODE_STATUS_ERROR_WARNING_STATUS
XMC_CAN_NODE_STATUS_BUS_OFF
XMC_CAN_NODE_STATUS_LIST_LENGTH_ERROR
XMC_CAN_NODE_STATUS_LIST_OBJECT_ERROR
XMC_CAN_NODE_STATUS_SUSPENDED_ACK
XMC_CAN_PANCMD_t
XMC_CAN_PANCMD_INIT_LIST
XMC_CAN_PANCMD_STATIC_ALLOCATE
XMC_CAN_PANCMD_DYNAMIC_ALLOCATE
XMC_CAN_PANCMD_STATIC_INSERT_BEFORE
XMC_CAN_PANCMD_DYNAMIC_INSERT_BEFORE
XMC_CAN_PANCMD_STATIC_INSERT_BEHIND
XMC_CAN_PANCMD_DYNAMIC_INSERT_BEHIND
XMC_CAN_STATUS_t
XMC_CAN_STATUS_SUCCESS
XMC_CAN_STATUS_ERROR
XMC_CAN_STATUS_BUSY
XMC_CAN_STATUS_MO_NOT_ACCEPTABLE
XMC_CAN_STATUS_MO_DISABLED
XMC_CAN_AllocateMOtoNodeList
XMC_CAN_Disable
XMC_CAN_Enable
XMC_CAN_EventTrigger
XMC_CAN_FIFO_DisableForeingRemoteRequest
XMC_CAN_FIFO_DisableRemoteMonitoring
XMC_CAN_FIFO_DisableSingleDataTransfer
XMC_CAN_FIFO_EnableForeignRemoteRequest
XMC_CAN_FIFO_EnableRemoteMonitoring
XMC_CAN_FIFO_EnableSingleDataTransfer
XMC_CAN_FIFO_GetCurrentMO
XMC_CAN_FIFO_SetSELMO
XMC_CAN_GATEWAY_InitDesObject
XMC_CAN_GATEWAY_InitSourceObject
XMC_CAN_Init
XMC_CAN_IsPanelControlReady
XMC_CAN_MO_AcceptOnlyMatchingIDE
XMC_CAN_MO_AcceptStandardAndExtendedID
XMC_CAN_MO_Config
XMC_CAN_MO_DataLengthCode
XMC_CAN_MO_DisableEvent
XMC_CAN_MO_DisableSingleTransmitTrial
XMC_CAN_MO_EnableEvent
XMC_CAN_MO_EnableSingleTransmitTrial
XMC_CAN_MO_GetAcceptanceMask
XMC_CAN_MO_GetDataLengthCode
XMC_CAN_MO_GetIdentifier
XMC_CAN_MO_GetStatus
XMC_CAN_MO_Receive
XMC_CAN_MO_ReceiveData
XMC_CAN_MO_ResetStatus
XMC_CAN_MO_SetAcceptanceMask
XMC_CAN_MO_SetDataLengthCode
XMC_CAN_MO_SetEventNodePointer
XMC_CAN_MO_SetExtendedID
XMC_CAN_MO_SetIdentifier
XMC_CAN_MO_SetStandardID
XMC_CAN_MO_SetStatus
XMC_CAN_MO_Transmit
XMC_CAN_MO_UpdateData
XMC_CAN_NODE_ClearStatus
XMC_CAN_NODE_Disable
XMC_CAN_NODE_DisableConfigurationChange
XMC_CAN_NODE_DisableEvent
XMC_CAN_NODE_DisableLoopBack
XMC_CAN_NODE_Enable
XMC_CAN_NODE_EnableConfigurationChange
XMC_CAN_NODE_EnableEvent
XMC_CAN_NODE_EnableLoopBack
XMC_CAN_NODE_EnableSuspend
XMC_CAN_NODE_FrameCounterConfigure
XMC_CAN_NODE_GetCANFrameCounter
XMC_CAN_NODE_GetErrorWarningLevel
XMC_CAN_NODE_GetLastErrTransferDir
XMC_CAN_NODE_GetLastErrTransferInc
XMC_CAN_NODE_GetReceiveErrorCounter
XMC_CAN_NODE_GetStatus
XMC_CAN_NODE_GetTransmitErrorCounter
XMC_CAN_NODE_NominalBitTimeConfigure
XMC_CAN_NODE_ReSetAnalyzerMode
XMC_CAN_NODE_ResetInitBit
XMC_CAN_NODE_SetAnalyzerMode
XMC_CAN_NODE_SetErrorWarningLevel
XMC_CAN_NODE_SetEventNodePointer
XMC_CAN_NODE_SetInitBit
XMC_CAN_NODE_SetReceiveErrorCounter
XMC_CAN_NODE_SetReceiveInput
XMC_CAN_NODE_SetTransmitErrorCounter
XMC_CAN_PanelControl
XMC_CAN_RXFIFO_ConfigMOBaseObject
XMC_CAN_RXFIFO_ConfigMOSlaveObject
XMC_CAN_TXFIFO_ConfigMOBaseObject
XMC_CAN_TXFIFO_ConfigMOSlaveObject
XMC_CAN_TXFIFO_Transmit
CCU4
XMC_CCU4_SLICE_CAPTURE_CONFIG_t
fifo_enable
float_limit
ignore_full_flag
prescaler_initval
prescaler_mode
same_event
timer_clear_mode
timer_concatenation
XMC_CCU4_SLICE_COMPARE_CONFIG_t
dither_duty_cycle
dither_limit
dither_timer_period
float_limit
mcm_enable
monoshot
passive_level
prescaler_initval
prescaler_mode
shadow_xfer_clear
timer_concatenation
timer_mode
XMC_CCU4_SLICE_EVENT_CONFIG_t
duration
edge
level
mapped_input
XMC_CCU4_MODULE_t
XMC_CCU4_SLICE_INPUT_t
XMC_CCU4_SLICE_t
XMC_CCU4_CLOCK_t
XMC_CCU4_CLOCK_SCU
XMC_CCU4_CLOCK_EXTERNAL_A
XMC_CCU4_CLOCK_EXTERNAL_B
XMC_CCU4_CLOCK_EXTERNAL_C
XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_t
XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_SW_SLICE0
XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_SW_MCSS_SLICE0
XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_SW_SLICE1
XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_SW_MCSS_SLICE1
XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_SW_SLICE2
XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_SW_MCSS_SLICE2
XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_SW_SLICE3
XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_SW_MCSS_SLICE3
XMC_CCU4_SHADOW_TRANSFER_t
XMC_CCU4_SHADOW_TRANSFER_SLICE_0
XMC_CCU4_SHADOW_TRANSFER_DITHER_SLICE_0
XMC_CCU4_SHADOW_TRANSFER_PRESCALER_SLICE_0
XMC_CCU4_SHADOW_TRANSFER_SLICE_1
XMC_CCU4_SHADOW_TRANSFER_DITHER_SLICE_1
XMC_CCU4_SHADOW_TRANSFER_PRESCALER_SLICE_1
XMC_CCU4_SHADOW_TRANSFER_SLICE_2
XMC_CCU4_SHADOW_TRANSFER_DITHER_SLICE_2
XMC_CCU4_SHADOW_TRANSFER_PRESCALER_SLICE_2
XMC_CCU4_SHADOW_TRANSFER_SLICE_3
XMC_CCU4_SHADOW_TRANSFER_DITHER_SLICE_3
XMC_CCU4_SHADOW_TRANSFER_PRESCALER_SLICE_3
XMC_CCU4_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_t
XMC_CCU4_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_PERIOD_SHADOW
XMC_CCU4_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_COMPARE_SHADOW
XMC_CCU4_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_PASSIVE_LEVEL
XMC_CCU4_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_DITHER_SHADOW
XMC_CCU4_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_FLOATING_PRESCALER_SHADOW
XMC_CCU4_SLICE_CAP_REG_SET_t
XMC_CCU4_SLICE_CAP_REG_SET_LOW
XMC_CCU4_SLICE_CAP_REG_SET_HIGH
XMC_CCU4_SLICE_END_MODE_t
XMC_CCU4_SLICE_END_MODE_TIMER_STOP
XMC_CCU4_SLICE_END_MODE_TIMER_CLEAR
XMC_CCU4_SLICE_END_MODE_TIMER_STOP_CLEAR
XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_t
XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_NONE
XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_RISING_EDGE
XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_FALLING_EDGE
XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_DUAL_EDGE
XMC_CCU4_SLICE_EVENT_FILTER_t
XMC_CCU4_SLICE_EVENT_FILTER_DISABLED
XMC_CCU4_SLICE_EVENT_FILTER_3_CYCLES
XMC_CCU4_SLICE_EVENT_FILTER_5_CYCLES
XMC_CCU4_SLICE_EVENT_FILTER_7_CYCLES
XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_t
XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_HIGH
XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_LOW
XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_COUNT_UP_ON_LOW
XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_COUNT_UP_ON_HIGH
XMC_CCU4_SLICE_EVENT_t
XMC_CCU4_SLICE_EVENT_NONE
XMC_CCU4_SLICE_EVENT_0
XMC_CCU4_SLICE_EVENT_1
XMC_CCU4_SLICE_EVENT_2
XMC_CCU4_SLICE_FUNCTION_t
XMC_CCU4_SLICE_FUNCTION_START
XMC_CCU4_SLICE_FUNCTION_STOP
XMC_CCU4_SLICE_FUNCTION_CAPTURE_EVENT0
XMC_CCU4_SLICE_FUNCTION_CAPTURE_EVENT1
XMC_CCU4_SLICE_FUNCTION_GATING
XMC_CCU4_SLICE_FUNCTION_DIRECTION
XMC_CCU4_SLICE_FUNCTION_LOAD
XMC_CCU4_SLICE_FUNCTION_COUNT
XMC_CCU4_SLICE_FUNCTION_OVERRIDE
XMC_CCU4_SLICE_FUNCTION_MODULATION
XMC_CCU4_SLICE_FUNCTION_TRAP
XMC_CCU4_SLICE_IRQ_ID_t
XMC_CCU4_SLICE_IRQ_ID_PERIOD_MATCH
XMC_CCU4_SLICE_IRQ_ID_ONE_MATCH
XMC_CCU4_SLICE_IRQ_ID_COMPARE_MATCH_UP
XMC_CCU4_SLICE_IRQ_ID_COMPARE_MATCH_DOWN
XMC_CCU4_SLICE_IRQ_ID_EVENT0
XMC_CCU4_SLICE_IRQ_ID_EVENT1
XMC_CCU4_SLICE_IRQ_ID_EVENT2
XMC_CCU4_SLICE_IRQ_ID_TRAP
XMC_CCU4_SLICE_MASK_t
XMC_CCU4_SLICE_MASK_SLICE_0
XMC_CCU4_SLICE_MASK_SLICE_1
XMC_CCU4_SLICE_MASK_SLICE_2
XMC_CCU4_SLICE_MASK_SLICE_3
XMC_CCU4_SLICE_MCMS_ACTION_t
XMC_CCU4_SLICE_MCMS_ACTION_TRANSFER_PR_CR
XMC_CCU4_SLICE_MCMS_ACTION_TRANSFER_PR_CR_PCMP
XMC_CCU4_SLICE_MCMS_ACTION_TRANSFER_PR_CR_PCMP_DIT
XMC_CCU4_SLICE_MODE_t
XMC_CCU4_SLICE_MODE_COMPARE
XMC_CCU4_SLICE_MODE_CAPTURE
XMC_CCU4_SLICE_MODULATION_MODE_t
XMC_CCU4_SLICE_MODULATION_MODE_CLEAR_ST_OUT
XMC_CCU4_SLICE_MODULATION_MODE_CLEAR_OUT
XMC_CCU4_SLICE_MULTI_IRQ_ID_t
XMC_CCU4_SLICE_MULTI_IRQ_ID_PERIOD_MATCH
XMC_CCU4_SLICE_MULTI_IRQ_ID_ONE_MATCH
XMC_CCU4_SLICE_MULTI_IRQ_ID_COMPARE_MATCH_UP
XMC_CCU4_SLICE_MULTI_IRQ_ID_COMPARE_MATCH_DOWN
XMC_CCU4_SLICE_MULTI_IRQ_ID_EVENT0
XMC_CCU4_SLICE_MULTI_IRQ_ID_EVENT1
XMC_CCU4_SLICE_MULTI_IRQ_ID_EVENT2
XMC_CCU4_SLICE_OUTPUT_PASSIVE_LEVEL_t
XMC_CCU4_SLICE_OUTPUT_PASSIVE_LEVEL_LOW
XMC_CCU4_SLICE_OUTPUT_PASSIVE_LEVEL_HIGH
XMC_CCU4_SLICE_PRESCALER_MODE_t
XMC_CCU4_SLICE_PRESCALER_MODE_NORMAL
XMC_CCU4_SLICE_PRESCALER_MODE_FLOAT
XMC_CCU4_SLICE_PRESCALER_t
XMC_CCU4_SLICE_PRESCALER_1
XMC_CCU4_SLICE_PRESCALER_2
XMC_CCU4_SLICE_PRESCALER_4
XMC_CCU4_SLICE_PRESCALER_8
XMC_CCU4_SLICE_PRESCALER_16
XMC_CCU4_SLICE_PRESCALER_32
XMC_CCU4_SLICE_PRESCALER_64
XMC_CCU4_SLICE_PRESCALER_128
XMC_CCU4_SLICE_PRESCALER_256
XMC_CCU4_SLICE_PRESCALER_512
XMC_CCU4_SLICE_PRESCALER_1024
XMC_CCU4_SLICE_PRESCALER_2048
XMC_CCU4_SLICE_PRESCALER_4096
XMC_CCU4_SLICE_PRESCALER_8192
XMC_CCU4_SLICE_PRESCALER_16384
XMC_CCU4_SLICE_PRESCALER_32768
XMC_CCU4_SLICE_SHADOW_TRANSFER_MODE_t
XMC_CCU4_SLICE_SHADOW_TRANSFER_MODE_IN_PERIOD_MATCH_AND_ONE_MATCH
XMC_CCU4_SLICE_SHADOW_TRANSFER_MODE_ONLY_IN_PERIOD_MATCH
XMC_CCU4_SLICE_SHADOW_TRANSFER_MODE_ONLY_IN_ONE_MATCH
XMC_CCU4_SLICE_SR_ID_t
XMC_CCU4_SLICE_SR_ID_0
XMC_CCU4_SLICE_SR_ID_1
XMC_CCU4_SLICE_SR_ID_2
XMC_CCU4_SLICE_SR_ID_3
XMC_CCU4_SLICE_START_MODE_t
XMC_CCU4_SLICE_START_MODE_TIMER_START
XMC_CCU4_SLICE_START_MODE_TIMER_START_CLEAR
XMC_CCU4_SLICE_TIMER_CLEAR_MODE_t
XMC_CCU4_SLICE_TIMER_CLEAR_MODE_NEVER
XMC_CCU4_SLICE_TIMER_CLEAR_MODE_CAP_HIGH
XMC_CCU4_SLICE_TIMER_CLEAR_MODE_CAP_LOW
XMC_CCU4_SLICE_TIMER_CLEAR_MODE_ALWAYS
XMC_CCU4_SLICE_TIMER_COUNT_DIR_t
XMC_CCU4_SLICE_TIMER_COUNT_DIR_UP
XMC_CCU4_SLICE_TIMER_COUNT_DIR_DOWN
XMC_CCU4_SLICE_TIMER_COUNT_MODE_t
XMC_CCU4_SLICE_TIMER_COUNT_MODE_EA
XMC_CCU4_SLICE_TIMER_COUNT_MODE_CA
XMC_CCU4_SLICE_TIMER_REPEAT_MODE_t
XMC_CCU4_SLICE_TIMER_REPEAT_MODE_REPEAT
XMC_CCU4_SLICE_TIMER_REPEAT_MODE_SINGLE
XMC_CCU4_SLICE_TRAP_EXIT_MODE_t
XMC_CCU4_SLICE_TRAP_EXIT_MODE_AUTOMATIC
XMC_CCU4_SLICE_TRAP_EXIT_MODE_SW
XMC_CCU4_SLICE_WRITE_INTO_t
XMC_CCU4_SLICE_WRITE_INTO_PERIOD_CONFIGURATION
XMC_CCU4_SLICE_WRITE_INTO_COMPARE_CONFIGURATION
XMC_CCU4_SLICE_WRITE_INTO_PASSIVE_LEVEL_CONFIGURATION
XMC_CCU4_SLICE_WRITE_INTO_DITHER_VALUE_CONFIGURATION
XMC_CCU4_SLICE_WRITE_INTO_FLOATING_PRESCALER_VALUE_CONFIGURATION
XMC_CCU4_STATUS_t
XMC_CCU4_STATUS_OK
XMC_CCU4_STATUS_ERROR
XMC_CCU4_STATUS_RUNNING
XMC_CCU4_STATUS_IDLE
XMC_CCU4_DisableClock
XMC_CCU4_DisableModule
XMC_CCU4_EnableClock
XMC_CCU4_EnableModule
XMC_CCU4_EnableMultipleClocks
XMC_CCU4_EnableShadowTransfer
XMC_CCU4_Init
XMC_CCU4_IsPrescalerRunning
XMC_CCU4_SetModuleClock
XMC_CCU4_SetMultiChannelShadowTransferMode
XMC_CCU4_SLICE_Capture0Config
XMC_CCU4_SLICE_Capture1Config
XMC_CCU4_SLICE_CaptureInit
XMC_CCU4_SLICE_ClearEvent
XMC_CCU4_SLICE_ClearTimer
XMC_CCU4_SLICE_CompareInit
XMC_CCU4_SLICE_ConfigureEvent
XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent
XMC_CCU4_SLICE_CountConfig
XMC_CCU4_SLICE_DirectionConfig
XMC_CCU4_SLICE_DisableAutomaticShadowTransferRequest
XMC_CCU4_SLICE_DisableCascadedShadowTransfer
XMC_CCU4_SLICE_DisableDithering
XMC_CCU4_SLICE_DisableEvent
XMC_CCU4_SLICE_DisableFloatingPrescaler
XMC_CCU4_SLICE_DisableMultiChannelMode
XMC_CCU4_SLICE_DisableMultipleEvents
XMC_CCU4_SLICE_DisableTrap
XMC_CCU4_SLICE_EnableAutomaticShadowTransferRequest
XMC_CCU4_SLICE_EnableCascadedShadowTransfer
XMC_CCU4_SLICE_EnableDithering
XMC_CCU4_SLICE_EnableEvent
XMC_CCU4_SLICE_EnableFloatingPrescaler
XMC_CCU4_SLICE_EnableMultiChannelMode
XMC_CCU4_SLICE_EnableMultipleEvents
XMC_CCU4_SLICE_EnableTrap
XMC_CCU4_SLICE_GateConfig
XMC_CCU4_SLICE_GetCapturedValueFromFifo
XMC_CCU4_SLICE_GetCaptureRegisterValue
XMC_CCU4_SLICE_GetCountingDir
XMC_CCU4_SLICE_GetEvent
XMC_CCU4_SLICE_GetLastCapturedTimerValue
XMC_CCU4_SLICE_GetSliceMode
XMC_CCU4_SLICE_GetTimerCompareMatch
XMC_CCU4_SLICE_GetTimerCountingMode
XMC_CCU4_SLICE_GetTimerPeriodMatch
XMC_CCU4_SLICE_GetTimerRepeatMode
XMC_CCU4_SLICE_GetTimerValue
XMC_CCU4_SLICE_IsExtendedCapReadEnabled
XMC_CCU4_SLICE_IsTimerRunning
XMC_CCU4_SLICE_LoadConfig
XMC_CCU4_SLICE_ModulationConfig
XMC_CCU4_SLICE_SetDitherCompareValue
XMC_CCU4_SLICE_SetEvent
XMC_CCU4_SLICE_SetFloatingPrescalerCompareValue
XMC_CCU4_SLICE_SetInput
XMC_CCU4_SLICE_SetInterruptNode
XMC_CCU4_SLICE_SetPassiveLevel
XMC_CCU4_SLICE_SetPrescaler
XMC_CCU4_SLICE_SetShadowTransferMode
XMC_CCU4_SLICE_SetTimerCompareMatch
XMC_CCU4_SLICE_SetTimerCountingMode
XMC_CCU4_SLICE_SetTimerPeriodMatch
XMC_CCU4_SLICE_SetTimerRepeatMode
XMC_CCU4_SLICE_SetTimerValue
XMC_CCU4_SLICE_StartConfig
XMC_CCU4_SLICE_StartTimer
XMC_CCU4_SLICE_StatusBitOverrideConfig
XMC_CCU4_SLICE_StopClearTimer
XMC_CCU4_SLICE_StopConfig
XMC_CCU4_SLICE_StopTimer
XMC_CCU4_SLICE_TrapConfig
XMC_CCU4_SLICE_WriteCoherentlyWithPWMCycle
XMC_CCU4_SLICE_WriteImmediateAfterShadowTransfer
XMC_CCU4_StartPrescaler
XMC_CCU4_StopPrescaler
CCU8
XMC_CCU8_SLICE_CAPTURE_CONFIG_t
fifo_enable
float_limit
ignore_full_flag
prescaler_initval
prescaler_mode
same_event
timer_clear_mode
timer_concatenation
XMC_CCU8_SLICE_COMPARE_CONFIG_t
asymmetric_pwm
dither_duty_cycle
dither_limit
dither_timer_period
float_limit
invert_out0
invert_out1
invert_out2
invert_out3
mcm_ch1_enable
mcm_ch2_enable
monoshot
passive_level_out0
passive_level_out1
passive_level_out2
passive_level_out3
prescaler_initval
prescaler_mode
shadow_xfer_clear
slice_status
timer_concatenation
timer_mode
XMC_CCU8_SLICE_DEAD_TIME_CONFIG_t
channel1_inv_st_path
channel1_st_falling_edge_counter
channel1_st_path
channel1_st_rising_edge_counter
channel2_inv_st_path
channel2_st_falling_edge_counter
channel2_st_path
channel2_st_rising_edge_counter
div
enable_dead_time_channel1
enable_dead_time_channel2
XMC_CCU8_SLICE_EVENT_CONFIG_t
duration
edge
level
mapped_input
XMC_CCU8_MODULE_t
XMC_CCU8_SLICE_INPUT_t
XMC_CCU8_SLICE_t
XMC_CCU8_CLOCK_t
XMC_CCU8_CLOCK_SCU
XMC_CCU8_CLOCK_EXTERNAL_A
XMC_CCU8_CLOCK_EXTERNAL_B
XMC_CCU8_CLOCK_EXTERNAL_C
XMC_CCU8_MULTI_CHANNEL_SHADOW_TRANSFER_t
XMC_CCU8_MULTI_CHANNEL_SHADOW_TRANSFER_SW_SLICE0
XMC_CCU8_MULTI_CHANNEL_SHADOW_TRANSFER_SW_MCSS_SLICE0
XMC_CCU8_MULTI_CHANNEL_SHADOW_TRANSFER_SW_SLICE1
XMC_CCU8_MULTI_CHANNEL_SHADOW_TRANSFER_SW_MCSS_SLICE1
XMC_CCU8_MULTI_CHANNEL_SHADOW_TRANSFER_SW_SLICE2
XMC_CCU8_MULTI_CHANNEL_SHADOW_TRANSFER_SW_MCSS_SLICE2
XMC_CCU8_MULTI_CHANNEL_SHADOW_TRANSFER_SW_SLICE3
XMC_CCU8_MULTI_CHANNEL_SHADOW_TRANSFER_SW_MCSS_SLICE3
XMC_CCU8_OUT_PATH_t
XMC_CCU8_OUT_PATH_OUT0_ST1
XMC_CCU8_OUT_PATH_OUT0_INV_ST1
XMC_CCU8_OUT_PATH_OUT1_ST1
XMC_CCU8_OUT_PATH_OUT1_INV_ST1
XMC_CCU8_OUT_PATH_OUT2_ST2
XMC_CCU8_OUT_PATH_OUT2_INV_ST2
XMC_CCU8_OUT_PATH_OUT3_ST2
XMC_CCU8_OUT_PATH_OUT3_INV_ST1
XMC_CCU8_SHADOW_TRANSFER_t
XMC_CCU8_SHADOW_TRANSFER_SLICE_0
XMC_CCU8_SHADOW_TRANSFER_DITHER_SLICE_0
XMC_CCU8_SHADOW_TRANSFER_PRESCALER_SLICE_0
XMC_CCU8_SHADOW_TRANSFER_SLICE_1
XMC_CCU8_SHADOW_TRANSFER_DITHER_SLICE_1
XMC_CCU8_SHADOW_TRANSFER_PRESCALER_SLICE_1
XMC_CCU8_SHADOW_TRANSFER_SLICE_2
XMC_CCU8_SHADOW_TRANSFER_DITHER_SLICE_2
XMC_CCU8_SHADOW_TRANSFER_PRESCALER_SLICE_2
XMC_CCU8_SHADOW_TRANSFER_SLICE_3
XMC_CCU8_SHADOW_TRANSFER_DITHER_SLICE_3
XMC_CCU8_SHADOW_TRANSFER_PRESCALER_SLICE_3
XMC_CCU8_SLICE_CAP_REG_SET_t
XMC_CCU8_SLICE_CAP_REG_SET_LOW
XMC_CCU8_SLICE_CAP_REG_SET_HIGH
XMC_CCU8_SLICE_COMPARE_CHANNEL_t
XMC_CCU8_SLICE_COMPARE_CHANNEL_1
XMC_CCU8_SLICE_COMPARE_CHANNEL_2
XMC_CCU8_SLICE_DTC_DIV_t
XMC_CCU8_SLICE_DTC_DIV_1
XMC_CCU8_SLICE_DTC_DIV_2
XMC_CCU8_SLICE_DTC_DIV_4
XMC_CCU8_SLICE_DTC_DIV_8
XMC_CCU8_SLICE_END_MODE_t
XMC_CCU8_SLICE_END_MODE_TIMER_STOP
XMC_CCU8_SLICE_END_MODE_TIMER_CLEAR
XMC_CCU8_SLICE_END_MODE_TIMER_STOP_CLEAR
XMC_CCU8_SLICE_EVENT_EDGE_SENSITIVITY_t
XMC_CCU8_SLICE_EVENT_EDGE_SENSITIVITY_NONE
XMC_CCU8_SLICE_EVENT_EDGE_SENSITIVITY_RISING_EDGE
XMC_CCU8_SLICE_EVENT_EDGE_SENSITIVITY_FALLING_EDGE
XMC_CCU8_SLICE_EVENT_EDGE_SENSITIVITY_DUAL_EDGE
XMC_CCU8_SLICE_EVENT_FILTER_t
XMC_CCU8_SLICE_EVENT_FILTER_DISABLED
XMC_CCU8_SLICE_EVENT_FILTER_3_CYCLES
XMC_CCU8_SLICE_EVENT_FILTER_5_CYCLES
XMC_CCU8_SLICE_EVENT_FILTER_7_CYCLES
XMC_CCU8_SLICE_EVENT_LEVEL_SENSITIVITY_t
XMC_CCU8_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_HIGH
XMC_CCU8_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_LOW
XMC_CCU8_SLICE_EVENT_LEVEL_SENSITIVITY_COUNT_UP_ON_LOW
XMC_CCU8_SLICE_EVENT_LEVEL_SENSITIVITY_COUNT_UP_ON_HIGH
XMC_CCU8_SLICE_EVENT_t
XMC_CCU8_SLICE_EVENT_NONE
XMC_CCU8_SLICE_EVENT_0
XMC_CCU8_SLICE_EVENT_1
XMC_CCU8_SLICE_EVENT_2
XMC_CCU8_SLICE_FUNCTION_t
XMC_CCU8_SLICE_FUNCTION_START
XMC_CCU8_SLICE_FUNCTION_STOP
XMC_CCU8_SLICE_FUNCTION_CAPTURE_EVENT0
XMC_CCU8_SLICE_FUNCTION_CAPTURE_EVENT1
XMC_CCU8_SLICE_FUNCTION_GATING
XMC_CCU8_SLICE_FUNCTION_DIRECTION
XMC_CCU8_SLICE_FUNCTION_LOAD
XMC_CCU8_SLICE_FUNCTION_COUNT
XMC_CCU8_SLICE_FUNCTION_OVERRIDE
XMC_CCU8_SLICE_FUNCTION_MODULATION
XMC_CCU8_SLICE_FUNCTION_TRAP
XMC_CCU8_SLICE_IRQ_ID_t
XMC_CCU8_SLICE_IRQ_ID_PERIOD_MATCH
XMC_CCU8_SLICE_IRQ_ID_ONE_MATCH
XMC_CCU8_SLICE_IRQ_ID_COMPARE_MATCH_UP_CH_1
XMC_CCU8_SLICE_IRQ_ID_COMPARE_MATCH_DOWN_CH_1
XMC_CCU8_SLICE_IRQ_ID_COMPARE_MATCH_UP_CH_2
XMC_CCU8_SLICE_IRQ_ID_COMPARE_MATCH_DOWN_CH_2
XMC_CCU8_SLICE_IRQ_ID_EVENT0
XMC_CCU8_SLICE_IRQ_ID_EVENT1
XMC_CCU8_SLICE_IRQ_ID_EVENT2
XMC_CCU8_SLICE_IRQ_ID_TRAP
XMC_CCU8_SLICE_MASK_t
XMC_CCU8_SLICE_MASK_SLICE_0
XMC_CCU8_SLICE_MASK_SLICE_1
XMC_CCU8_SLICE_MASK_SLICE_2
XMC_CCU8_SLICE_MASK_SLICE_3
XMC_CCU8_SLICE_MCMS_ACTION_t
XMC_CCU8_SLICE_MCMS_ACTION_TRANSFER_PR_CR
XMC_CCU8_SLICE_MCMS_ACTION_TRANSFER_PR_CR_PCMP
XMC_CCU8_SLICE_MCMS_ACTION_TRANSFER_PR_CR_PCMP_DIT
XMC_CCU8_SLICE_MODE_t
XMC_CCU8_SLICE_MODE_COMPARE
XMC_CCU8_SLICE_MODE_CAPTURE
XMC_CCU8_SLICE_MODULATION_CHANNEL_t
XMC_CCU8_SLICE_MODULATION_CHANNEL_NONE
XMC_CCU8_SLICE_MODULATION_CHANNEL_1
XMC_CCU8_SLICE_MODULATION_CHANNEL_2
XMC_CCU8_SLICE_MODULATION_CHANNEL_1_AND_2
XMC_CCU8_SLICE_MODULATION_MODE_t
XMC_CCU8_SLICE_MODULATION_MODE_CLEAR_ST_OUT
XMC_CCU8_SLICE_MODULATION_MODE_CLEAR_OUT
XMC_CCU8_SLICE_MULTI_IRQ_ID_t
XMC_CCU8_SLICE_MULTI_IRQ_ID_PERIOD_MATCH
XMC_CCU8_SLICE_MULTI_IRQ_ID_ONE_MATCH
XMC_CCU8_SLICE_MULTI_IRQ_ID_COMPARE_MATCH_UP_CH_1
XMC_CCU8_SLICE_MULTI_IRQ_ID_COMPARE_MATCH_DOWN_CH_1
XMC_CCU8_SLICE_MULTI_IRQ_ID_COMPARE_MATCH_UP_CH_2
XMC_CCU8_SLICE_MULTI_IRQ_ID_COMPARE_MATCH_DOWN_CH_2
XMC_CCU8_SLICE_MULTI_IRQ_ID_EVENT0
XMC_CCU8_SLICE_MULTI_IRQ_ID_EVENT1
XMC_CCU8_SLICE_MULTI_IRQ_ID_EVENT2
XMC_CCU8_SLICE_OUTPUT_PASSIVE_LEVEL_t
XMC_CCU8_SLICE_OUTPUT_PASSIVE_LEVEL_LOW
XMC_CCU8_SLICE_OUTPUT_PASSIVE_LEVEL_HIGH
XMC_CCU8_SLICE_OUTPUT_t
XMC_CCU8_SLICE_OUTPUT_0
XMC_CCU8_SLICE_OUTPUT_1
XMC_CCU8_SLICE_OUTPUT_2
XMC_CCU8_SLICE_OUTPUT_3
XMC_CCU8_SLICE_PRESCALER_MODE_t
XMC_CCU8_SLICE_PRESCALER_MODE_NORMAL
XMC_CCU8_SLICE_PRESCALER_MODE_FLOAT
XMC_CCU8_SLICE_PRESCALER_t
XMC_CCU8_SLICE_PRESCALER_1
XMC_CCU8_SLICE_PRESCALER_2
XMC_CCU8_SLICE_PRESCALER_4
XMC_CCU8_SLICE_PRESCALER_8
XMC_CCU8_SLICE_PRESCALER_16
XMC_CCU8_SLICE_PRESCALER_32
XMC_CCU8_SLICE_PRESCALER_64
XMC_CCU8_SLICE_PRESCALER_128
XMC_CCU8_SLICE_PRESCALER_256
XMC_CCU8_SLICE_PRESCALER_512
XMC_CCU8_SLICE_PRESCALER_1024
XMC_CCU8_SLICE_PRESCALER_2048
XMC_CCU8_SLICE_PRESCALER_4096
XMC_CCU8_SLICE_PRESCALER_8192
XMC_CCU8_SLICE_PRESCALER_16384
XMC_CCU8_SLICE_PRESCALER_32768
XMC_CCU8_SLICE_SHADOW_TRANSFER_MODE_t
XMC_CCU8_SLICE_SHADOW_TRANSFER_MODE_IN_PERIOD_MATCH_AND_ONE_MATCH
XMC_CCU8_SLICE_SHADOW_TRANSFER_MODE_ONLY_IN_PERIOD_MATCH
XMC_CCU8_SLICE_SHADOW_TRANSFER_MODE_ONLY_IN_ONE_MATCH
XMC_CCU8_SLICE_SR_ID_t
XMC_CCU8_SLICE_SR_ID_0
XMC_CCU8_SLICE_SR_ID_1
XMC_CCU8_SLICE_SR_ID_2
XMC_CCU8_SLICE_SR_ID_3
XMC_CCU8_SLICE_START_MODE_t
XMC_CCU8_SLICE_START_MODE_TIMER_START
XMC_CCU8_SLICE_START_MODE_TIMER_START_CLEAR
XMC_CCU8_SLICE_STATUS_t
XMC_CCU8_SLICE_STATUS_CHANNEL_1
XMC_CCU8_SLICE_STATUS_CHANNEL_2
XMC_CCU8_SLICE_STATUS_CHANNEL_1_AND_2
XMC_CCU8_SLICE_STATUS_CHANNEL_1_OR_2
XMC_CCU8_SLICE_TIMER_CLEAR_MODE_t
XMC_CCU8_SLICE_TIMER_CLEAR_MODE_NEVER
XMC_CCU8_SLICE_TIMER_CLEAR_MODE_CAP_HIGH
XMC_CCU8_SLICE_TIMER_CLEAR_MODE_CAP_LOW
XMC_CCU8_SLICE_TIMER_CLEAR_MODE_ALWAYS
XMC_CCU8_SLICE_TIMER_COUNT_DIR_t
XMC_CCU8_SLICE_TIMER_COUNT_DIR_UP
XMC_CCU8_SLICE_TIMER_COUNT_DIR_DOWN
XMC_CCU8_SLICE_TIMER_COUNT_MODE_t
XMC_CCU8_SLICE_TIMER_COUNT_MODE_EA
XMC_CCU8_SLICE_TIMER_COUNT_MODE_CA
XMC_CCU8_SLICE_TIMER_REPEAT_MODE_t
XMC_CCU8_SLICE_TIMER_REPEAT_MODE_REPEAT
XMC_CCU8_SLICE_TIMER_REPEAT_MODE_SINGLE
XMC_CCU8_SLICE_TRAP_EXIT_MODE_t
XMC_CCU8_SLICE_TRAP_EXIT_MODE_AUTOMATIC
XMC_CCU8_SLICE_TRAP_EXIT_MODE_SW
XMC_CCU8_SOURCE_OUT0_t
XMC_CCU8_SOURCE_OUT0_ST1
XMC_CCU8_SOURCE_OUT0_INV_ST1
XMC_CCU8_SOURCE_OUT0_ST2
XMC_CCU8_SOURCE_OUT0_INV_ST2
XMC_CCU8_SOURCE_OUT1_t
XMC_CCU8_SOURCE_OUT1_ST1
XMC_CCU8_SOURCE_OUT1_INV_ST1
XMC_CCU8_SOURCE_OUT1_ST2
XMC_CCU8_SOURCE_OUT1_INV_ST2
XMC_CCU8_SOURCE_OUT2_t
XMC_CCU8_SOURCE_OUT2_ST2
XMC_CCU8_SOURCE_OUT2_INV_ST2
XMC_CCU8_SOURCE_OUT2_ST1
XMC_CCU8_SOURCE_OUT2_INV_ST1
XMC_CCU8_SOURCE_OUT3_t
XMC_CCU8_SOURCE_OUT3_ST2
XMC_CCU8_SOURCE_OUT3_INV_ST2
XMC_CCU8_SOURCE_OUT3_ST1
XMC_CCU8_SOURCE_OUT3_INV_ST1
XMC_CCU8_STATUS_t
XMC_CCU8_STATUS_OK
XMC_CCU8_STATUS_ERROR
XMC_CCU8_STATUS_RUNNING
XMC_CCU8_STATUS_IDLE
XMC_CCU8_DisableClock
XMC_CCU8_DisableModule
XMC_CCU8_EnableClock
XMC_CCU8_EnableModule
XMC_CCU8_EnableMultipleClocks
XMC_CCU8_EnableShadowTransfer
XMC_CCU8_Init
XMC_CCU8_IsPrescalerRunning
XMC_CCU8_SetModuleClock
XMC_CCU8_SetMultiChannelShadowTransferMode
XMC_CCU8_SLICE_Capture0Config
XMC_CCU8_SLICE_Capture1Config
XMC_CCU8_SLICE_CaptureInit
XMC_CCU8_SLICE_ClearEvent
XMC_CCU8_SLICE_ClearTimer
XMC_CCU8_SLICE_CompareInit
XMC_CCU8_SLICE_ConfigureDeadTime
XMC_CCU8_SLICE_ConfigureEvent
XMC_CCU8_SLICE_ConfigureStatusBitOutput
XMC_CCU8_SLICE_ConfigureStatusBitOverrideEvent
XMC_CCU8_SLICE_CountConfig
XMC_CCU8_SLICE_DeadTimeInit
XMC_CCU8_SLICE_DirectionConfig
XMC_CCU8_SLICE_DisableAutomaticShadowTransferRequest
XMC_CCU8_SLICE_DisableCascadedShadowTransfer
XMC_CCU8_SLICE_DisableDithering
XMC_CCU8_SLICE_DisableEvent
XMC_CCU8_SLICE_DisableFloatingPrescaler
XMC_CCU8_SLICE_DisableMultiChannelMode
XMC_CCU8_SLICE_DisableMultipleEvents
XMC_CCU8_SLICE_DisableTrap
XMC_CCU8_SLICE_EnableAsymmetricCompareMode
XMC_CCU8_SLICE_EnableAutomaticShadowTransferRequest
XMC_CCU8_SLICE_EnableCascadedShadowTransfer
XMC_CCU8_SLICE_EnableDithering
XMC_CCU8_SLICE_EnableEvent
XMC_CCU8_SLICE_EnableFloatingPrescaler
XMC_CCU8_SLICE_EnableMultiChannelMode
XMC_CCU8_SLICE_EnableMultipleEvents
XMC_CCU8_SLICE_EnableSymmetricCompareMode
XMC_CCU8_SLICE_EnableTrap
XMC_CCU8_SLICE_GateConfig
XMC_CCU8_SLICE_GetCapturedValueFromFifo
XMC_CCU8_SLICE_GetCaptureRegisterValue
XMC_CCU8_SLICE_GetCountingDir
XMC_CCU8_SLICE_GetEvent
XMC_CCU8_SLICE_GetLastCapturedTimerValue
XMC_CCU8_SLICE_GetSliceMode
XMC_CCU8_SLICE_GetTimerCompareMatch
XMC_CCU8_SLICE_GetTimerCountingMode
XMC_CCU8_SLICE_GetTimerPeriodMatch
XMC_CCU8_SLICE_GetTimerRepeatMode
XMC_CCU8_SLICE_GetTimerValue
XMC_CCU8_SLICE_IsDeadTimeCntr1Running
XMC_CCU8_SLICE_IsDeadTimeCntr2Running
XMC_CCU8_SLICE_IsExtendedCapReadEnabled
XMC_CCU8_SLICE_IsTimerRunning
XMC_CCU8_SLICE_LoadConfig
XMC_CCU8_SLICE_LoadSelector
XMC_CCU8_SLICE_ModulationConfig
XMC_CCU8_SLICE_SetDeadTimePrescaler
XMC_CCU8_SLICE_SetDeadTimeValue
XMC_CCU8_SLICE_SetDitherCompareValue
XMC_CCU8_SLICE_SetEvent
XMC_CCU8_SLICE_SetFloatingPrescalerCompareValue
XMC_CCU8_SLICE_SetInput
XMC_CCU8_SLICE_SetInterruptNode
XMC_CCU8_SLICE_SetOutPath
XMC_CCU8_SLICE_SetPassiveLevel
XMC_CCU8_SLICE_SetPrescaler
XMC_CCU8_SLICE_SetShadowTransferMode
XMC_CCU8_SLICE_SetTimerCompareMatch
XMC_CCU8_SLICE_SetTimerCompareMatchChannel1
XMC_CCU8_SLICE_SetTimerCompareMatchChannel2
XMC_CCU8_SLICE_SetTimerCountingMode
XMC_CCU8_SLICE_SetTimerPeriodMatch
XMC_CCU8_SLICE_SetTimerRepeatMode
XMC_CCU8_SLICE_SetTimerValue
XMC_CCU8_SLICE_StartConfig
XMC_CCU8_SLICE_StartTimer
XMC_CCU8_SLICE_StatusBitOverrideConfig
XMC_CCU8_SLICE_StopClearTimer
XMC_CCU8_SLICE_StopConfig
XMC_CCU8_SLICE_StopTimer
XMC_CCU8_SLICE_TrapConfig
XMC_CCU8_SLICE_WriteCoherentlyWithPWMCycle
XMC_CCU8_SLICE_WriteImmediateAfterShadowTransfer
XMC_CCU8_StartPrescaler
XMC_CCU8_StopPrescaler
DAC
XMC_DAC_CH_CONFIG_t
__pad0__
__pad1__
data_type
output_negation
output_offset
output_scale
XMC_DAC_t
XMC_DAC0
XMC_DAC_NO_CHANNELS
XMC_DAC_PATTERN_RECTANGLE
XMC_DAC_PATTERN_SINE
XMC_DAC_PATTERN_TRIANGLE
XMC_DAC_SAMPLES_PER_PERIOD
XMC_DAC_CH_DATA_TYPE_t
XMC_DAC_CH_DATA_TYPE_UNSIGNED
XMC_DAC_CH_DATA_TYPE_SIGNED
XMC_DAC_CH_MODE_t
XMC_DAC_CH_MODE_IDLE
XMC_DAC_CH_MODE_SINGLE
XMC_DAC_CH_MODE_DATA
XMC_DAC_CH_MODE_PATTERN
XMC_DAC_CH_MODE_NOISE
XMC_DAC_CH_MODE_RAMP
XMC_DAC_CH_OUTPUT_NEGATION_t
XMC_DAC_CH_OUTPUT_NEGATION_DISABLED
XMC_DAC_CH_OUTPUT_NEGATION_ENABLED
XMC_DAC_CH_OUTPUT_SCALE_t
XMC_DAC_CH_OUTPUT_SCALE_NONE
XMC_DAC_CH_OUTPUT_SCALE_MUL_2
XMC_DAC_CH_OUTPUT_SCALE_MUL_4
XMC_DAC_CH_OUTPUT_SCALE_MUL_8
XMC_DAC_CH_OUTPUT_SCALE_MUL_16
XMC_DAC_CH_OUTPUT_SCALE_MUL_32
XMC_DAC_CH_OUTPUT_SCALE_MUL_64
XMC_DAC_CH_OUTPUT_SCALE_MUL_128
XMC_DAC_CH_OUTPUT_SCALE_DIV_2
XMC_DAC_CH_OUTPUT_SCALE_DIV_4
XMC_DAC_CH_OUTPUT_SCALE_DIV_8
XMC_DAC_CH_OUTPUT_SCALE_DIV_16
XMC_DAC_CH_OUTPUT_SCALE_DIV_32
XMC_DAC_CH_OUTPUT_SCALE_DIV_64
XMC_DAC_CH_OUTPUT_SCALE_DIV_128
XMC_DAC_CH_PATTERN_SIGN_OUTPUT_t
XMC_DAC_CH_PATTERN_SIGN_OUTPUT_DISABLED
XMC_DAC_CH_PATTERN_SIGN_OUTPUT_ENABLED
XMC_DAC_CH_STATUS_t
XMC_DAC_CH_STATUS_OK
XMC_DAC_CH_STATUS_ERROR
XMC_DAC_CH_STATUS_BUSY
XMC_DAC_CH_STATUS_ERROR_FREQ2LOW
XMC_DAC_CH_STATUS_ERROR_FREQ2HIGH
XMC_DAC_CH_TRIGGER_t
XMC_DAC_CH_TRIGGER_INTERNAL
XMC_DAC_CH_TRIGGER_EXTERNAL_CCU80_SR1
XMC_DAC_CH_TRIGGER_EXTERNAL_CCU40_SR1
XMC_DAC_CH_TRIGGER_EXTERNAL_CCU41_SR1
XMC_DAC_CH_TRIGGER_EXTERNAL_P2_9
XMC_DAC_CH_TRIGGER_EXTERNAL_P2_8
XMC_DAC_CH_TRIGGER_EXTERNAL_U0C0_DX1INS
XMC_DAC_CH_TRIGGER_EXTERNAL_U1C0_DX1INS
XMC_DAC_CH_TRIGGER_SOFTWARE
XMC_DAC_CH_DisableEvent
XMC_DAC_CH_DisableOutput
XMC_DAC_CH_DisableOutputNegation
XMC_DAC_CH_DisablePatternSignOutput
XMC_DAC_CH_EnableEvent
XMC_DAC_CH_EnableOutput
XMC_DAC_CH_EnableOutputNegation
XMC_DAC_CH_EnablePatternSignOutput
XMC_DAC_CH_GetOutputScale
XMC_DAC_CH_GetRampStart
XMC_DAC_CH_GetRampStop
XMC_DAC_CH_Init
XMC_DAC_CH_IsFifoEmpty
XMC_DAC_CH_IsFifoFull
XMC_DAC_CH_IsOutputEnabled
XMC_DAC_CH_SetFrequency
XMC_DAC_CH_SetMode
XMC_DAC_CH_SetOutputOffset
XMC_DAC_CH_SetOutputScale
XMC_DAC_CH_SetPattern
XMC_DAC_CH_SetPatternFrequency
XMC_DAC_CH_SetRampFrequency
XMC_DAC_CH_SetRampStart
XMC_DAC_CH_SetRampStop
XMC_DAC_CH_SetSignedDataType
XMC_DAC_CH_SetTrigger
XMC_DAC_CH_SetUnsignedDataType
XMC_DAC_CH_SoftwareTrigger
XMC_DAC_CH_StartDataMode
XMC_DAC_CH_StartNoiseMode
XMC_DAC_CH_StartPatternMode
XMC_DAC_CH_StartRampMode
XMC_DAC_CH_StartSingleValueMode
XMC_DAC_CH_Write
XMC_DAC_Disable
XMC_DAC_DisableSimultaneousDataMode
XMC_DAC_Enable
XMC_DAC_EnableSimultaneousDataMode
XMC_DAC_IsEnabled
XMC_DAC_SimultaneousWrite
DMA
GPDMA_CH_t
XMC_DMA_CH_CONFIG_t
block_size
dst_addr
dst_address_count_mode
dst_burst_length
dst_handshaking
dst_peripheral_request
dst_scatter_count
dst_scatter_interval
dst_transfer_width
enable_dst_scatter
enable_interrupt
enable_src_gather
linked_list_pointer
priority
src_addr
src_address_count_mode
src_burst_length
src_gather_count
src_gather_interval
src_handshaking
src_peripheral_request
src_transfer_width
transfer_flow
transfer_type
XMC_DMA_LLI_t
__pad0__
__pad1__
__pad2__
block_size
dst_addr
dst_address_count_mode
dst_burst_length
dst_status
dst_transfer_width
enable_dst_linked_list
enable_dst_scatter
enable_interrupt
enable_src_gather
enable_src_linked_list
llp
src_addr
src_address_count_mode
src_burst_length
src_status
src_transfer_width
transfer_flow
XMC_DMA_t
XMC_DMA0
XMC_DMA1
XMC_DMA_CH_EVENT_HANDLER_t
XMC_DMA_LIST_t
XMC_DMA_CH_ADDRESS_COUNT_MODE_t
XMC_DMA_CH_ADDRESS_COUNT_MODE_INCREMENT
XMC_DMA_CH_ADDRESS_COUNT_MODE_DECREMENT
XMC_DMA_CH_ADDRESS_COUNT_MODE_NO_CHANGE
XMC_DMA_CH_BURST_LENGTH_t
XMC_DMA_CH_BURST_LENGTH_1
XMC_DMA_CH_BURST_LENGTH_4
XMC_DMA_CH_BURST_LENGTH_8
XMC_DMA_CH_DST_HANDSHAKING_t
XMC_DMA_CH_DST_HANDSHAKING_HARDWARE
XMC_DMA_CH_DST_HANDSHAKING_SOFTWARE
XMC_DMA_CH_EVENT_t
XMC_DMA_CH_EVENT_TRANSFER_COMPLETE
XMC_DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE
XMC_DMA_CH_EVENT_SRC_TRANSACTION_COMPLETE
XMC_DMA_CH_EVENT_DST_TRANSACTION_COMPLETE
XMC_DMA_CH_EVENT_ERROR
XMC_DMA_CH_HARDWARE_HANDSHAKING_IF_t
XMC_DMA_CH_HARDWARE_HANDSHAKING_IF_0
XMC_DMA_CH_HARDWARE_HANDSHAKING_IF_1
XMC_DMA_CH_HARDWARE_HANDSHAKING_IF_2
XMC_DMA_CH_HARDWARE_HANDSHAKING_IF_3
XMC_DMA_CH_HARDWARE_HANDSHAKING_IF_4
XMC_DMA_CH_HARDWARE_HANDSHAKING_IF_5
XMC_DMA_CH_HARDWARE_HANDSHAKING_IF_6
XMC_DMA_CH_HARDWARE_HANDSHAKING_IF_7
XMC_DMA_CH_PRIORITY_t
XMC_DMA_CH_PRIORITY_0
XMC_DMA_CH_PRIORITY_1
XMC_DMA_CH_PRIORITY_2
XMC_DMA_CH_PRIORITY_3
XMC_DMA_CH_PRIORITY_4
XMC_DMA_CH_PRIORITY_5
XMC_DMA_CH_PRIORITY_6
XMC_DMA_CH_PRIORITY_7
XMC_DMA_CH_SRC_HANDSHAKING_t
XMC_DMA_CH_SRC_HANDSHAKING_HARDWARE
XMC_DMA_CH_SRC_HANDSHAKING_SOFTWARE
XMC_DMA_CH_STATUS_t
XMC_DMA_CH_STATUS_OK
XMC_DMA_CH_STATUS_ERROR
XMC_DMA_CH_STATUS_BUSY
XMC_DMA_CH_TRANSACTION_TYPE_t
XMC_DMA_CH_TRANSACTION_TYPE_SINGLE
XMC_DMA_CH_TRANSACTION_TYPE_BURST
XMC_DMA_CH_TRANSFER_FLOW_t
XMC_DMA_CH_TRANSFER_FLOW_M2M_DMA
XMC_DMA_CH_TRANSFER_FLOW_M2P_DMA
XMC_DMA_CH_TRANSFER_FLOW_P2M_DMA
XMC_DMA_CH_TRANSFER_FLOW_P2P_DMA
XMC_DMA_CH_TRANSFER_FLOW_P2M_PER
XMC_DMA_CH_TRANSFER_FLOW_P2P_SRCPER
XMC_DMA_CH_TRANSFER_FLOW_M2P_PER
XMC_DMA_CH_TRANSFER_FLOW_P2P_DSTPER
XMC_DMA_CH_TRANSFER_TYPE_t
XMC_DMA_CH_TRANSFER_TYPE_SINGLE_BLOCK
XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_CONTIGUOUS_DSTADR_RELOAD
XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_RELOAD_DSTADR_CONTIGUOUS
XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_RELOAD_DSTADR_RELOAD
XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_CONTIGUOUS_DSTADR_LINKED
XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_RELOAD_DSTADR_LINKED
XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_LINKED_DSTADR_CONTIGUOUS
XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_LINKED_DSTADR_RELOAD
XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_LINKED_DSTADR_LINKED
XMC_DMA_CH_TRANSFER_WIDTH_t
XMC_DMA_CH_TRANSFER_WIDTH_8
XMC_DMA_CH_TRANSFER_WIDTH_16
XMC_DMA_CH_TRANSFER_WIDTH_32
XMC_DMA_CH_ClearDestinationPeripheralRequest
XMC_DMA_CH_ClearEventStatus
XMC_DMA_CH_ClearSourcePeripheralRequest
XMC_DMA_CH_Disable
XMC_DMA_CH_DisableDestinationAddressReload
XMC_DMA_CH_DisableDestinationScatter
XMC_DMA_CH_DisableEvent
XMC_DMA_CH_DisableSourceAddressReload
XMC_DMA_CH_DisableSourceGather
XMC_DMA_CH_Enable
XMC_DMA_CH_EnableDestinationAddressReload
XMC_DMA_CH_EnableDestinationScatter
XMC_DMA_CH_EnableEvent
XMC_DMA_CH_EnableSourceAddressReload
XMC_DMA_CH_EnableSourceGather
XMC_DMA_CH_GetEventStatus
XMC_DMA_CH_Init
XMC_DMA_CH_IsEnabled
XMC_DMA_CH_IsSuspended
XMC_DMA_CH_RequestLastMultiblockTransfer
XMC_DMA_CH_Resume
XMC_DMA_CH_SetBlockSize
XMC_DMA_CH_SetDestinationAddress
XMC_DMA_CH_SetEventHandler
XMC_DMA_CH_SetLinkedListPointer
XMC_DMA_CH_SetSourceAddress
XMC_DMA_CH_Suspend
XMC_DMA_CH_TriggerDestinationRequest
XMC_DMA_CH_TriggerSourceRequest
XMC_DMA_ClearOverrunStatus
XMC_DMA_ClearRequestLine
XMC_DMA_Disable
XMC_DMA_DisableRequestLine
XMC_DMA_Enable
XMC_DMA_EnableRequestLine
XMC_DMA_GetChannelsBlockCompleteStatus
XMC_DMA_GetChannelsDestinationTransactionCompleteStatus
XMC_DMA_GetChannelsErrorStatus
XMC_DMA_GetChannelsSourceTransactionCompleteStatus
XMC_DMA_GetChannelsTransferCompleteStatus
XMC_DMA_GetEventStatus
XMC_DMA_GetOverrunStatus
XMC_DMA_Init
XMC_DMA_IRQHandler
XMC_DMA_IsEnabled
DSD
XMC_DSD_CH_AUX_FILTER_CONFIG_t
__pad0__
decimation_factor
enable_integrator_coupling
filter_type
lower_boundary
result_event_type
upper_boundary
XMC_DSD_CH_CONFIG_t
aux
filter
integrator
rectify
timestamp
XMC_DSD_CH_FILTER_CONFIG_t
clock_divider
clock_source
data_source
decimation_factor
filter_start_value
filter_type
offset
result_event
strobe
XMC_DSD_CH_INTEGRATOR_CONFIG_t
counted_values
discarded_values
integration_loop
integrator_trigger
start_condition
stop_condition
trigger_source
XMC_DSD_CH_RECTIFY_CONFIG_t
rectify_config
sign_source
XMC_DSD_CH_TIMESTAMP_CONFIG_t
trigger_mode
trigger_source
XMC_DSD_GENERATOR_CONFIG_t
bit_reverse
frequency
generator_conf
inverted_polarity
mode
XMC_DSD_CH_t
XMC_DSD_t
XMC_DSD_CH_AUX_EVENT_t
XMC_DSD_CH_AUX_EVENT_DISABLED
XMC_DSD_CH_AUX_EVENT_EVERY_NEW_RESULT
XMC_DSD_CH_AUX_EVENT_CAPTURE_SIGN_DELAY
XMC_DSD_CH_AUX_EVENT_INSIDE_BOUNDARY
XMC_DSD_CH_AUX_EVENT_OUTSIDE_BOUNDARY
XMC_DSD_CH_CLK_t
XMC_DSD_CH_CLK_DIV_2
XMC_DSD_CH_CLK_DIV_4
XMC_DSD_CH_CLK_DIV_6
XMC_DSD_CH_CLK_DIV_8
XMC_DSD_CH_CLK_DIV_10
XMC_DSD_CH_CLK_DIV_12
XMC_DSD_CH_CLK_DIV_14
XMC_DSD_CH_CLK_DIV_16
XMC_DSD_CH_CLK_DIV_18
XMC_DSD_CH_CLK_DIV_20
XMC_DSD_CH_CLK_DIV_22
XMC_DSD_CH_CLK_DIV_24
XMC_DSD_CH_CLK_DIV_26
XMC_DSD_CH_CLK_DIV_28
XMC_DSD_CH_CLK_DIV_30
XMC_DSD_CH_CLK_DIV_32
XMC_DSD_CH_CLOCK_SOURCE_t
XMC_DSD_CH_CLOCK_SOURCE_A
XMC_DSD_CH_CLOCK_SOURCE_B
XMC_DSD_CH_CLOCK_SOURCE_C
XMC_DSD_CH_CLOCK_SOURCE_D
XMC_DSD_CH_CLOCK_SOURCE_INTERN
XMC_DSD_CH_DATA_SOURCE_t
XMC_DSD_CH_DATA_SOURCE_DISCONNECT
XMC_DSD_CH_DATA_SOURCE_A_DIRECT
XMC_DSD_CH_DATA_SOURCE_A_INVERTED
XMC_DSD_CH_DATA_SOURCE_B_DIRECT
XMC_DSD_CH_DATA_SOURCE_B_INVERTED
XMC_DSD_CH_FILTER_TYPE_t
XMC_DSD_CH_FILTER_TYPE_CIC1
XMC_DSD_CH_FILTER_TYPE_CIC2
XMC_DSD_CH_FILTER_TYPE_CIC3
XMC_DSD_CH_FILTER_TYPE_CICF
XMC_DSD_CH_ID_t
XMC_DSD_CH_ID_0
XMC_DSD_CH_ID_1
XMC_DSD_CH_ID_2
XMC_DSD_CH_ID_3
XMC_DSD_CH_INTEGRATOR_START_t
XMC_DSD_CH_INTEGRATOR_START_OFF
XMC_DSD_CH_INTEGRATOR_START_TRIGGER_FALL
XMC_DSD_CH_INTEGRATOR_START_TRIGGER_RISE
XMC_DSD_CH_INTEGRATOR_START_ALLWAYS_ON
XMC_DSD_CH_INTEGRATOR_STOP_t
XMC_DSD_CH_INTEGRATOR_STOP_END_OF_LOOPS
XMC_DSD_CH_INTEGRATOR_STOP_ENDLESS_OR_INVERSE_TRIGGER
XMC_DSD_CH_RESULT_EVENT_t
XMC_DSD_CH_RESULT_EVENT_DISABLE
XMC_DSD_CH_RESULT_EVENT_ENABLE
XMC_DSD_CH_SIGN_SOURCE_t
XMC_DSD_CH_SIGN_SOURCE_ON_CHIP_GENERATOR
XMC_DSD_CH_SIGN_SOURCE_NEXT_CHANNEL
XMC_DSD_CH_SIGN_SOURCE_EXTERNAL_A
XMC_DSD_CH_SIGN_SOURCE_EXTERNAL_B
XMC_DSD_CH_STROBE_t
XMC_DSD_CH_TIMESTAMP_TRIGGER_t
XMC_DSD_CH_TIMESTAMP_TRIGGER_DISABLE
XMC_DSD_CH_TIMESTAMP_TRIGGER_FALL
XMC_DSD_CH_TIMESTAMP_TRIGGER_RISE
XMC_DSD_CH_TIMESTAMP_TRIGGER_BOTH_EDGES
XMC_DSD_CH_TRIGGER_SOURCE_t
XMC_DSD_CH_TRIGGER_SOURCE_A
XMC_DSD_CH_TRIGGER_SOURCE_B
XMC_DSD_CH_TRIGGER_SOURCE_C
XMC_DSD_CH_TRIGGER_SOURCE_D
XMC_DSD_CH_TRIGGER_SOURCE_E
XMC_DSD_CH_TRIGGER_SOURCE_F
XMC_DSD_CH_TRIGGER_SOURCE_G
XMC_DSD_CH_TRIGGER_SOURCE_H
XMC_DSD_GENERATOR_CLKDIV_t
XMC_DSD_GENERATOR_CLKDIV_2048
XMC_DSD_GENERATOR_CLKDIV_4096
XMC_DSD_GENERATOR_CLKDIV_6144
XMC_DSD_GENERATOR_CLKDIV_8192
XMC_DSD_GENERATOR_CLKDIV_10240
XMC_DSD_GENERATOR_CLKDIV_12288
XMC_DSD_GENERATOR_CLKDIV_14336
XMC_DSD_GENERATOR_CLKDIV_16384
XMC_DSD_GENERATOR_CLKDIV_18432
XMC_DSD_GENERATOR_CLKDIV_20480
XMC_DSD_GENERATOR_CLKDIV_22528
XMC_DSD_GENERATOR_CLKDIV_24576
XMC_DSD_GENERATOR_CLKDIV_26624
XMC_DSD_GENERATOR_CLKDIV_28672
XMC_DSD_GENERATOR_CLKDIV_30720
XMC_DSD_GENERATOR_CLKDIV_32768
XMC_DSD_GENERATOR_MODE_t
XMC_DSD_GENERATOR_MODE_STOPPED
XMC_DSD_GENERATOR_MODE_RECTANGLE
XMC_DSD_GENERATOR_MODE_TRIANGLE
XMC_DSD_GENERATOR_MODE_SINE
XMC_DSD_STATUS_t
XMC_DSD_STATUS_OK
XMC_DSD_STATUS_ERROR
XMC_DSD_CH_AuxFilter_DisableEvent
XMC_DSD_CH_AuxFilter_EnableEvent
XMC_DSD_CH_AuxFilter_Init
XMC_DSD_CH_AuxFilter_SetBoundary
XMC_DSD_CH_GetRectifyDelay
XMC_DSD_CH_GetResult
XMC_DSD_CH_GetResult_AUX
XMC_DSD_CH_GetResult_TS
XMC_DSD_CH_GetResult_TS_Time
XMC_DSD_CH_Init
XMC_DSD_CH_Integrator_Init
XMC_DSD_CH_MainFilter_DisableEvent
XMC_DSD_CH_MainFilter_EnableEvent
XMC_DSD_CH_MainFilter_Init
XMC_DSD_CH_MainFilter_SetOffset
XMC_DSD_CH_Rectify_Init
XMC_DSD_CH_Timestamp_Init
XMC_DSD_ClearAlarmEventFlag
XMC_DSD_ClearResultEventFlag
XMC_DSD_Disable
XMC_DSD_DisableClock
XMC_DSD_Enable
XMC_DSD_EnableClock
XMC_DSD_Generator_Init
XMC_DSD_Generator_Start
XMC_DSD_Generator_Stop
XMC_DSD_Init
XMC_DSD_IsChannelStarted
XMC_DSD_IsEnabled
XMC_DSD_SetAlarmEventFlag
XMC_DSD_SetResultEventFlag
XMC_DSD_Start
XMC_DSD_Stop
EBU
XMC_EBU_BUS_READ_CONFIG_t
address_cycles
address_hold_cycles
command_delay_lines
ebu_asynchronous_address_phase
ebu_burst_address_wrapping
ebu_burst_buffer_sync_mode
ebu_burst_flash_clock_feedback
ebu_burst_flash_clock_mode
ebu_burst_length_sync
ebu_burst_signal_sync
ebu_byte_control
ebu_data_hold_cycles_for_read_accesses
ebu_device_addressing_mode
ebu_device_type
ebu_early_chip_select_sync_burst
ebu_ext_data
ebu_flash_non_array_access
ebu_freq_ext_clk_pin
ebu_programmed_wait_states_for_read_accesses
ebu_read_stages_synch
ebu_recovery_cycles_after_read_accesses
ebu_recovery_cycles_between_different_regions
ebu_wait_control
ebu_wait_signal_polarity
XMC_EBU_BUS_WRITE_CONFIG_t
address_cycles
address_hold_cycles
command_delay_lines
ebu_asynchronous_address_phase
ebu_burst_buffer_sync_mode
ebu_burst_length_sync
ebu_burst_signal_sync
ebu_byte_control
ebu_data_hold_cycles_for_write_accesses
ebu_device_addressing_mode
ebu_device_type
ebu_early_chip_select_sync_burst
ebu_ext_data
ebu_lock_chip_select
ebu_programmed_wait_states_for_write_accesses
ebu_recovery_cycles_after_write_accesses
ebu_recovery_cycles_between_different_regions
ebu_wait_control
ebu_wait_signal_polarity
XMC_EBU_CLK_CONFIG_t
ebu_clk_mode
ebu_clock_divide_ratio
ebu_div2_clk_mode
XMC_EBU_CONFIG_t
ebu_clk_config
ebu_free_pins_to_gpio
ebu_mode_config
XMC_EBU_FREE_PINS_TO_GPIO_t
address_pins_gpio
adv_pin_gpio
XMC_EBU_MODE_CONFIG_t
bus_timeout_control
ebu_ale_mode
ebu_arbitration_mode
ebu_arbsync
ebu_extlock
ebu_sdram_tristate
XMC_EBU_REGION_READ_CONFIG_t
ebu_bus_read_config
ebu_region_no
XMC_EBU_REGION_t
XMC_EBU_REGION_WRITE_CONFIG_t
ebu_bus_write_config
ebu_region_no
XMC_EBU_SDRAM_CONFIG_t
ebu_init_refresh_commands_counter
ebu_mode_register_set_up_time
ebu_row_precharge_delay_counter
ebu_row_precharge_time_counter
ebu_sdram_auto_refresh
ebu_sdram_auto_self_refresh
ebu_sdram_burst_length
ebu_sdram_casclk_mode
ebu_sdram_clk_mode
ebu_sdram_clk_output
ebu_sdram_cold_start
ebu_sdram_delay_on_power_down_exit
ebu_sdram_extended_operation_bank_select
ebu_sdram_extended_operation_mode
ebu_sdram_extended_refresh_counter_period
ebu_sdram_mask_for_bank_tag
ebu_sdram_mask_for_row_tag
ebu_sdram_num_refresh_cmnds
ebu_sdram_num_refresh_counter_period
ebu_sdram_pwr_mode
ebu_sdram_row_cycle_time_counter
ebu_sdram_row_cycle_time_counter_extension
ebu_sdram_row_to_column_delay_counter
ebu_sdram_self_refresh_entry
ebu_sdram_self_refresh_exit
ebu_sdram_self_refresh_exit_delay
ebu_sdram_width_of_column_address
XMC_EBU_t
XMC_EBU
XMC_EBU_ADDRESS_SELECT_t
XMC_EBU_ADDRESS_SELECT_MEMORY_REGION_ENABLE
XMC_EBU_ADDRESS_SELECT_ALTERNATE_REGION_ENABLE
XMC_EBU_ADDRESS_SELECT_MEMORY_REGION_WRITE_PROTECT
XMC_EBU_ALE_MODE_t
XMC_EBU_ALE_OUTPUT_IS_INV_ADV
XMC_EBU_ALE_OUTPUT_IS_ALE
XMC_EBU_ARB_MODE_t
XMC_EBU_ARB_MODE_NOT_SELECTED
XMC_EBU_ARB_MODE_ARBITER_MODE
XMC_EBU_ARB_MODE_PARTICIPANT_MODE
XMC_EBU_ARB_MODE_SOLE_MASTER_MODE
XMC_EBU_ASYNCHRONOUS_ADDRESS_PHASE_t
XMC_EBU_ASYNCHRONOUS_ADDRESS_PHASE_CLOCK_ENABLED_AT_BEGINNING_OF_ACCESS
XMC_EBU_ASYNCHRONOUS_ADDRESS_PHASE_CLOCK_ENABLED_AFTER_ADDRESS_PHASE
XMC_EBU_BURST_ADDRESS_WRAPPING_t
XMC_EBU_BURST_ADDRESS_WRAPPING_DISABLED
XMC_EBU_BURST_ADDRESS_WRAPPING_ENABLED
XMC_EBU_BURST_BUFFER_SYNC_MODE_t
XMC_EBU_BURST_BUFFER_SYNC_LENGTH_SYNC_ENABLE
XMC_EBU_BURST_BUFFER_SYNC_SINGLE_MODE
XMC_EBU_BURST_FLASH_CLOCK_FEEDBACK_t
XMC_EBU_BURST_FLASH_CLOCK_FEEDBACK_DISABLE
XMC_EBU_BURST_FLASH_CLOCK_FEEDBACK_ENABLE
XMC_EBU_BURST_FLASH_CLOCK_MODE_t
XMC_EBU_BURST_FLASH_CLOCK_MODE_RUN_CONTINUOSLY
XMC_EBU_BURST_FLASH_CLOCK_MODE_DISABLED_BETWEEN_ACCESSES
XMC_EBU_BURST_LENGTH_SYNC_t
XMC_EBU_BURST_LENGTH_SYNC_1_DATA_ACCESS
XMC_EBU_BURST_LENGTH_SYNC_2_DATA_ACCESSES
XMC_EBU_BURST_LENGTH_SYNC_4_DATA_ACCESSES
XMC_EBU_BURST_LENGTH_SYNC_8_DATA_ACCESSES
XMC_EBU_BURST_SIGNAL_SYNC_BURST_t
XMC_EBU_BURST_SIGNAL_SYNC_BURST_ADV_DELAYED
XMC_EBU_BURST_SIGNAL_SYNC_BURST_ADV_NOT_DELAYED
XMC_EBU_BUSWCON_SELECT_t
XMC_EBU_BUSWCON_SELECT_NAN_WORKAROUND
XMC_EBU_BUSWCON_SELECT_DEVICE_ADDRESSING_MODE
XMC_EBU_BYTE_CONTROL_t
XMC_EBU_BYTE_CONTROL_FOLLOWS_CHIP_SELECT_TIMMING
XMC_EBU_BYTE_CONTROL_FOLLOWS_CONTROL_SIGNAL_TIMMING
XMC_EBU_BYTE_CONTROL_FOLLOWS_WRITE_ENABLE_SIGNAL_TIMMING
XMC_EBU_CLK_MODE_t
XMC_EBU_CLK_MODE_ASYNCHRONOUS_TO_AHB
XMC_EBU_CLK_MODE_SYNCHRONOUS_TO_CPU
XMC_EBU_CLK_STATUS_t
XMC_EBU_CLK_STATUS_DISABLE_BIT
XMC_EBU_CLK_STATUS_MODE
XMC_EBU_CLK_STATUS_DIV2_MODE
XMC_EBU_CLK_STATUS_DIV_RATIO
XMC_EBU_CLOCK_DIVIDE_RATIO_t
XMC_EBU_CLOCK_DIVIDED_BY_1
XMC_EBU_CLOCK_DIVIDED_BY_2
XMC_EBU_CLOCK_DIVIDED_BY_3
XMC_EBU_CLOCK_DIVIDED_BY_4
XMC_EBU_DEVICE_ADDRESSING_MODE_t
XMC_EBU_DEVICE_ADDRESSING_MODE_16_BITS
XMC_EBU_DEVICE_ADDRESSING_MODE_TWIN_16_BITS_MULTIPLEXED
XMC_EBU_DEVICE_ADDRESSING_MODE_32_BITS_MULTIPLEXED
XMC_EBU_DEVICE_TYPE_t
XMC_EBU_DEVICE_TYPE_MUXED_ASYNCHRONOUS_TYPE
XMC_EBU_DEVICE_TYPE_MUXED_BURST_TYPE
XMC_EBU_DEVICE_TYPE_NAND_FLASH
XMC_EBU_DEVICE_TYPE_MUXED_CELLULAR_RAM
XMC_EBU_DEVICE_TYPE_DEMUXED_ASYNCHRONOUS_TYPE
XMC_EBU_DEVICE_TYPE_DEMUXED_BURST_TYPE
XMC_EBU_DEVICE_TYPE_DEMUXED_PAGE_MODE
XMC_EBU_DEVICE_TYPE_DEMUXED_CELLULAR_RAM
XMC_EBU_DEVICE_TYPE_SDRAM
XMC_EBU_DIV2_CLK_MODE_t
XMC_EBU_DIV2_CLK_MODE_OFF
XMC_EBU_DIV2_CLK_MODE_ON
XMC_EBU_EARLY_CHIP_SELECT_SYNC_BURST_t
XMC_EBU_EARLY_CHIP_SELECT_DELAYED
XMC_EBU_EARLY_CHIP_SELECT_NOT_DELAYED
XMC_EBU_EXT_DATA_t
XMC_EBU_EXT_DATA_OUTPUT_EVERY_1_BFCLK_CYCLES
XMC_EBU_EXT_DATA_OUTPUT_EVERY_2_BFCLK_CYCLES
XMC_EBU_EXT_DATA_OUTPUT_EVERY_4_BFCLK_CYCLES
XMC_EBU_EXT_DATA_OUTPUT_EVERY_8_BFCLK_CYCLES
XMC_EBU_FLASH_NON_ARRAY_ACCESS_t
XMC_EBU_FLASH_NON_ARRAY_ACCESS_DISNABLE
XMC_EBU_FLASH_NON_ARRAY_ACCESS_ENABLE
XMC_EBU_FREQ_EXT_CLK_PIN_t
XMC_EBU_FREQ_EXT_CLK_PIN_EQUAL_TO_INT_CLK
XMC_EBU_FREQ_EXT_CLK_PIN_HALF_OF_INT_CLK
XMC_EBU_FREQ_EXT_CLK_PIN_THIRD_OF_INT_CLK
XMC_EBU_FREQ_EXT_CLK_PIN_QUARTER_OF_INT_CLK
XMC_EBU_LOCK_CHIP_SELECT_t
XMC_EBU_LOCK_CHIP_SELECT_DISABLED
XMC_EBU_LOCK_CHIP_SELECT_ENABLED
XMC_EBU_READ_STAGES_SYNC_t
XMC_EBU_READ_STAGES_SYNC_TWO
XMC_EBU_READ_STAGES_SYNC_ONE
XMC_EBU_SDRAM_BURST_LENGTH_t
XMC_EBU_SDRAM_BURST_LENGTH_1_LOCATION
XMC_EBU_SDRAM_BURST_LENGTH_2_LOCATION
XMC_EBU_SDRAM_BURST_LENGTH_4_LOCATION
XMC_EBU_SDRAM_BURST_LENGTH_8_LOCATION
XMC_EBU_SDRAM_BURST_LENGTH_16_LOCATION
XMC_EBU_SDRAM_CAS_LATENCY_t
XMC_EBU_SDRAM_CAS_LATENCY_2_CLKS
XMC_EBU_SDRAM_CAS_LATENCY_3_CLKS
XMC_EBU_SDRAM_CLK_MODE_t
XMC_EBU_SDRAM_CLK_MODE_CONTINUOUSLY_RUNS
XMC_EBU_SDRAM_CLK_MODE_DISABLED_BETWEEN_ACCESSES
XMC_EBU_SDRAM_CLK_OUTPUT_t
XMC_EBU_SDRAM_CLK_OUTPUT_ENABLED
XMC_EBU_SDRAM_CLK_OUTPUT_DISABLED
XMC_EBU_SDRAM_MASK_FOR_BANK_TAG_t
XMC_EBU_SDRAM_MASK_FOR_BANK_TAG_ADDRESS_21_to_20
XMC_EBU_SDRAM_MASK_FOR_BANK_TAG_ADDRESS_22_to_21
XMC_EBU_SDRAM_MASK_FOR_BANK_TAG_ADDRESS_23_to_22
XMC_EBU_SDRAM_MASK_FOR_BANK_TAG_ADDRESS_24_to_23
XMC_EBU_SDRAM_MASK_FOR_BANK_TAG_ADDRESS_25_to_24
XMC_EBU_SDRAM_MASK_FOR_BANK_TAG_ADDRESS_26_to_25
XMC_EBU_SDRAM_MASK_FOR_BANK_TAG_ADDRESS_26
XMC_EBU_SDRAM_MASK_FOR_ROW_TAG_t
XMC_EBU_SDRAM_MASK_FOR_ROW_TAG_ADDRESS_26_to_9
XMC_EBU_SDRAM_MASK_FOR_ROW_TAG_ADDRESS_26_to_10
XMC_EBU_SDRAM_MASK_FOR_ROW_TAG_ADDRESS_26_to_11
XMC_EBU_SDRAM_MASK_FOR_ROW_TAG_ADDRESS_26_to_12
XMC_EBU_SDRAM_MASK_FOR_ROW_TAG_ADDRESS_26_to_13
XMC_EBU_SDRAM_PWR_MODE_t
XMC_EBU_SDRAM_PWR_MODE_PRECHARGE_BEFORE_CLK_STOP
XMC_EBU_SDRAM_PWR_MODE_AUTO_PRECHARGE_BEFORE_CLK_STOP
XMC_EBU_SDRAM_PWR_MODE_ACTIVE_PWR_DOWN
XMC_EBU_SDRAM_PWR_MODE_CLK_STOP_PWR_DOWN
XMC_EBU_SDRAM_RFRSH_STATUS_t
XMC_EBU_SDRAM_RFRSH_STATUS_SELF_REFRESH_ENTRY_STATUS
XMC_EBU_SDRAM_RFRSH_STATUS_SELF_REFRESH_EXIT_STATUS
XMC_EBU_SDRAM_STATUS_t
XMC_EBU_SDRAM_STATUS_RX_ERROR
XMC_EBU_SDRAM_STATUS_BUSY
XMC_EBU_SDRAM_STATUS_REFRESH_ERROR
XMC_EBU_SDRAM_WIDTH_OF_COLUMN_ADDRESS_t
XMC_EBU_SDRAM_WIDTH_OF_COLUMN_ADDRESS_8_to_0
XMC_EBU_SDRAM_WIDTH_OF_COLUMN_ADDRESS_9_to_0
XMC_EBU_SDRAM_WIDTH_OF_COLUMN_ADDRESS_10_to_0
XMC_EBU_STATUS_t
XMC_EBU_STATUS_OK
XMC_EBU_STATUS_BUSY
XMC_EBU_STATUS_ERROR
XMC_EBU_WAIT_CONTROL_t
XMC_EBU_WAIT_CONTROL_OFF
XMC_EBU_WAIT_CONTROL_SYNC_EARLY_WAIT_ASYNC_ASYNC_INPUT_AT_WAIT
XMC_EBU_WAIT_CONTROL_SYNC_WAIT_WITH_DATA_ASYNC_SYNC_INPUT_AT_WAIT
XMC_EBU_WAIT_CONTROL_SYNC_ABORT_AND_RETRY_ACCESS
XMC_EBU_WAIT_SIGNAL_POLARITY_t
XMC_EBU_WAIT_SIGNAL_POLARITY_PIN_ACTIVE_LOW
XMC_EBU_WAIT_SIGNAL_POLARITY_PIN_ACTIVE_HIGH
XMC_EBU_AddressSelectDisable
XMC_EBU_AddressSelectEnable
XMC_EBU_CLKDivideRatio
XMC_EBU_ConfigureRegion
XMC_EBU_ConfigureSdram
XMC_EBU_Disable
XMC_EBU_Enable
XMC_EBU_GetBusWriteConfStatus
XMC_EBU_GetCLKStatus
XMC_EBU_Init
XMC_EBU_IsBusAribitrationSelected
XMC_EBU_SdramDisableAutomaticSelfRefresh
XMC_EBU_SdramDisableAutoRefreshSelfRefreshExit
XMC_EBU_SdramEnableAutomaticSelfRefresh
XMC_EBU_SdramEnableAutoRefreshSelfRefreshExit
XMC_EBU_SdramGetRefreshStatus
XMC_EBU_SdramGetStatus
XMC_EBU_SdramResetSelfRefreshEntry
XMC_EBU_SdramResetSelfRefreshExit
XMC_EBU_SdramSetSelfRefreshEntry
XMC_EBU_SdramSetSelfRefreshExit
ECAT
XMC_ECAT_CONFIG_t
dword
station_alias
sync_pulse_length
XMC_ECAT_PORT_CTRL_t
__pad0__
__pad1__
__pad2__
__pad3__
__pad4__
enable_rstreq
latch_input0
latch_input1
link
mdio
phyaddr_offset
rx_clk
rx_dv
rx_err
rxd0
rxd1
rxd2
rxd3
tx_clk
tx_shift
XMC_ECAT_EVENT_t
XMC_ECAT_EVENT_AL_CONTROL
XMC_ECAT_EVENT_DC_LATCH
XMC_ECAT_EVENT_DC_SYNC0
XMC_ECAT_EVENT_DC_SYNC1
XMC_ECAT_EVENT_SM_ACTIVATION_REGISTER
XMC_ECAT_EVENT_EEPROM
XMC_ECAT_EVENT_WATCHDOG
XMC_ECAT_EVENT_SM0
XMC_ECAT_EVENT_SM1
XMC_ECAT_EVENT_SM2
XMC_ECAT_EVENT_SM3
XMC_ECAT_EVENT_SM4
XMC_ECAT_EVENT_SM5
XMC_ECAT_EVENT_SM6
XMC_ECAT_EVENT_SM7
XMC_ECAT_STATUS_t
XMC_ECAT_STATUS_OK
XMC_ECAT_STATUS_BUSY
XMC_ECAT_STATUS_ERROR
XMC_ECAT_Disable
XMC_ECAT_DisableEvent
XMC_ECAT_DisableSyncManChannel
XMC_ECAT_Enable
XMC_ECAT_EnableEvent
XMC_ECAT_EnableSyncManChannel
XMC_ECAT_GetALEventMask
XMC_ECAT_GetALEventRegister
XMC_ECAT_GetEventStatus
XMC_ECAT_Init
XMC_ECAT_ReadPhy
XMC_ECAT_SetALEventMask
XMC_ECAT_SetPortControl
XMC_ECAT_WritePhy
ERU
XMC_ERU_ETL_CONFIG_t
edge_detection
enable_output_trigger
input
input_a
input_b
output_trigger_channel
source
status_flag_mode
XMC_ERU_OGU_CONFIG_t
enable_pattern_detection
pattern_detection_input
peripheral_trigger
service_request
XMC_ERU_t
XMC_ERU_ETL_EDGE_DETECTION_t
XMC_ERU_ETL_EDGE_DETECTION_DISABLED
XMC_ERU_ETL_EDGE_DETECTION_RISING
XMC_ERU_ETL_EDGE_DETECTION_FALLING
XMC_ERU_ETL_EDGE_DETECTION_BOTH
XMC_ERU_ETL_INPUT_A_t
XMC_ERU_ETL_INPUT_A0
XMC_ERU_ETL_INPUT_A1
XMC_ERU_ETL_INPUT_A2
XMC_ERU_ETL_INPUT_A3
XMC_ERU_ETL_INPUT_B_t
XMC_ERU_ETL_INPUT_B0
XMC_ERU_ETL_INPUT_B1
XMC_ERU_ETL_INPUT_B2
XMC_ERU_ETL_INPUT_B3
XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL_t
XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL0
XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL1
XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL2
XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL3
XMC_ERU_ETL_OUTPUT_TRIGGER_t
XMC_ERU_ETL_OUTPUT_TRIGGER_DISABLED
XMC_ERU_ETL_OUTPUT_TRIGGER_ENABLED
XMC_ERU_ETL_SOURCE_t
XMC_ERU_ETL_SOURCE_A
XMC_ERU_ETL_SOURCE_B
XMC_ERU_ETL_SOURCE_A_OR_B
XMC_ERU_ETL_SOURCE_A_AND_B
XMC_ERU_ETL_SOURCE_NOT_A
XMC_ERU_ETL_SOURCE_NOT_A_OR_B
XMC_ERU_ETL_SOURCE_NOT_A_AND_B
XMC_ERU_ETL_SOURCE_NOT_B
XMC_ERU_ETL_SOURCE_A_OR_NOT_B
XMC_ERU_ETL_SOURCE_A_AND_NOT_B
XMC_ERU_ETL_SOURCE_NOT_A_OR_NOT_B
XMC_ERU_ETL_SOURCE_NOT_A_AND_NOT_B
XMC_ERU_ETL_STATUS_FLAG_MODE_t
XMC_ERU_ETL_STATUS_FLAG_MODE_SWCTRL
XMC_ERU_ETL_STATUS_FLAG_MODE_HWCTRL
XMC_ERU_OGU_PATTERN_DETECTION_INPUT_t
XMC_ERU_OGU_PATTERN_DETECTION_INPUT0
XMC_ERU_OGU_PATTERN_DETECTION_INPUT1
XMC_ERU_OGU_PATTERN_DETECTION_INPUT2
XMC_ERU_OGU_PATTERN_DETECTION_INPUT3
XMC_ERU_OGU_PATTERN_DETECTION_t
XMC_ERU_OGU_PATTERN_DETECTION_DISABLED
XMC_ERU_OGU_PATTERN_DETECTION_ENABLED
XMC_ERU_OGU_PERIPHERAL_TRIGGER_t
XMC_ERU_OGU_PERIPHERAL_TRIGGER1
XMC_ERU_OGU_PERIPHERAL_TRIGGER2
XMC_ERU_OGU_PERIPHERAL_TRIGGER3
XMC_ERU_OGU_SERVICE_REQUEST_t
XMC_ERU_OGU_SERVICE_REQUEST_DISABLED
XMC_ERU_OGU_SERVICE_REQUEST_ON_TRIGGER
XMC_ERU_OGU_SERVICE_REQUEST_ON_TRIGGER_AND_PATTERN_MATCH
XMC_ERU_OGU_SERVICE_REQUEST_ON_TRIGGER_AND_PATTERN_MISMATCH
XMC_ERU_Disable
XMC_ERU_Enable
XMC_ERU_ETL_ClearStatusFlag
XMC_ERU_ETL_DisableOutputTrigger
XMC_ERU_ETL_EnableOutputTrigger
XMC_ERU_ETL_GetEdgeDetection
XMC_ERU_ETL_GetStatusFlag
XMC_ERU_ETL_Init
XMC_ERU_ETL_SetEdgeDetection
XMC_ERU_ETL_SetInput
XMC_ERU_ETL_SetSource
XMC_ERU_ETL_SetStatusFlag
XMC_ERU_ETL_SetStatusFlagMode
XMC_ERU_OGU_DisablePatternDetection
XMC_ERU_OGU_DisablePeripheralTrigger
XMC_ERU_OGU_EnablePatternDetection
XMC_ERU_OGU_EnablePeripheralTrigger
XMC_ERU_OGU_GetPatternDetectionStatus
XMC_ERU_OGU_Init
XMC_ERU_OGU_SetServiceRequestMode
ETH_MAC
XMC_ETH_MAC_DMA_DESC_t
buffer1
buffer2
extended_status
length
reserved
status
time_stamp_nanoseconds
time_stamp_seconds
XMC_ETH_MAC_PORT_CTRL_t
__pad0__
__pad1__
clk_rmii
clk_tx
col
crs
crs_dv
mdio
mode
rxd0
rxd1
rxd2
rxd3
rxer
XMC_ETH_MAC_t
address
frame_end
num_rx_buf
num_tx_buf
regs
rx_buf
rx_desc
rx_index
tx_buf
tx_desc
tx_index
tx_ts_index
XMC_ETH_MAC_TIME_t
nanoseconds
seconds
ETH_MAC_DMA_RDES0_AFM
ETH_MAC_DMA_RDES0_CE
ETH_MAC_DMA_RDES0_DBE
ETH_MAC_DMA_RDES0_DE
ETH_MAC_DMA_RDES0_ES
ETH_MAC_DMA_RDES0_ESA
ETH_MAC_DMA_RDES0_FL
ETH_MAC_DMA_RDES0_FS
ETH_MAC_DMA_RDES0_FT
ETH_MAC_DMA_RDES0_LC
ETH_MAC_DMA_RDES0_LE
ETH_MAC_DMA_RDES0_LS
ETH_MAC_DMA_RDES0_OE
ETH_MAC_DMA_RDES0_OWN
ETH_MAC_DMA_RDES0_RE
ETH_MAC_DMA_RDES0_RWT
ETH_MAC_DMA_RDES0_SAF
ETH_MAC_DMA_RDES0_TSA
ETH_MAC_DMA_RDES0_VLAN
ETH_MAC_DMA_TDES0_CC
ETH_MAC_DMA_TDES0_CIC
ETH_MAC_DMA_TDES0_DB
ETH_MAC_DMA_TDES0_DC
ETH_MAC_DMA_TDES0_DP
ETH_MAC_DMA_TDES0_EC
ETH_MAC_DMA_TDES0_ED
ETH_MAC_DMA_TDES0_ES
ETH_MAC_DMA_TDES0_FF
ETH_MAC_DMA_TDES0_FS
ETH_MAC_DMA_TDES0_IC
ETH_MAC_DMA_TDES0_IHE
ETH_MAC_DMA_TDES0_IPE
ETH_MAC_DMA_TDES0_JT
ETH_MAC_DMA_TDES0_LC
ETH_MAC_DMA_TDES0_LOC
ETH_MAC_DMA_TDES0_LS
ETH_MAC_DMA_TDES0_NC
ETH_MAC_DMA_TDES0_OWN
ETH_MAC_DMA_TDES0_TCH
ETH_MAC_DMA_TDES0_TER
ETH_MAC_DMA_TDES0_TTSE
ETH_MAC_DMA_TDES0_TTSS
ETH_MAC_DMA_TDES0_UF
ETH_MAC_DMA_TDES0_VF
XMC_ETH_MAC_BUF_SIZE
XMC_ETH_MAC_PHY_MAX_RETRIES
XMC_ETH_WAKEUP_REGISTER_LENGTH
XMC_ETH_LINK_DUPLEX_t
XMC_ETH_LINK_DUPLEX_HALF
XMC_ETH_LINK_DUPLEX_FULL
XMC_ETH_LINK_INTERFACE_t
XMC_ETH_LINK_INTERFACE_MII
XMC_ETH_LINK_INTERFACE_RMII
XMC_ETH_LINK_SPEED_t
XMC_ETH_LINK_SPEED_10M
XMC_ETH_LINK_SPEED_100M
XMC_ETH_LINK_STATUS_t
XMC_ETH_LINK_STATUS_DOWN
XMC_ETH_LINK_STATUS_UP
XMC_ETH_MAC_ADDR_FILTER_t
XMC_ETH_MAC_ADDR_FILTER_MASK_BYTE0
XMC_ETH_MAC_ADDR_FILTER_MASK_BYTE1
XMC_ETH_MAC_ADDR_FILTER_MASK_BYTE2
XMC_ETH_MAC_ADDR_FILTER_MASK_BYTE3
XMC_ETH_MAC_ADDR_FILTER_MASK_BYTE4
XMC_ETH_MAC_ADDR_FILTER_MASK_BYTE5
XMC_ETH_MAC_ADDR_FILTER_SA
XMC_ETH_MAC_EVENT_t
XMC_ETH_MAC_EVENT_PMT
XMC_ETH_MAC_EVENT_TIMESTAMP
XMC_ETH_MAC_EVENT_EARLY_RECEIVE
XMC_ETH_MAC_EVENT_BUS_ERROR
XMC_ETH_MAC_EVENT_EARLY_TRANSMIT
XMC_ETH_MAC_EVENT_RECEIVE_WATCHDOG_TIMEOUT
XMC_ETH_MAC_EVENT_RECEIVE_PROCESS_STOPPED
XMC_ETH_MAC_EVENT_RECEIVE_BUFFER_UNAVAILABLE
XMC_ETH_MAC_EVENT_RECEIVE
XMC_ETH_MAC_EVENT_TRANSMIT_UNDERFLOW
XMC_ETH_MAC_EVENT_RECEIVE_OVERFLOW
XMC_ETH_MAC_EVENT_TRANSMIT_JABBER_TIMEOUT
XMC_ETH_MAC_EVENT_TRANSMIT_BUFFER_UNAVAILABLE
XMC_ETH_MAC_EVENT_TRANSMIT_PROCESS_STOPPED
XMC_ETH_MAC_EVENT_TRANSMIT
XMC_ETH_MAC_PMT_EVENT_t
XMC_ETH_MAC_PMT_EVENT_ON_WAKEUP_FRAME
XMC_ETH_MAC_PMT_EVENT_ON_MAGIC_PACKET
XMC_ETH_MAC_PMT_EVENT_ON_UNICAST_FRAME_FILTER
XMC_ETH_MAC_STATUS_t
XMC_ETH_MAC_STATUS_OK
XMC_ETH_MAC_STATUS_BUSY
XMC_ETH_MAC_STATUS_ERROR
XMC_ETH_MAC_TIMESTAMP_CONFIG_t
XMC_ETH_MAC_TIMESTAMP_CONFIG_FINE_UPDATE
XMC_ETH_MAC_TIMESTAMP_CONFIG_ENABLE_TS_INTERRUPT
XMC_ETH_MAC_TIMESTAMP_CONFIG_ENABLE_ALL_FRAMES
XMC_ETH_MAC_TIMESTAMP_CONFIG_ENABLE_PTPV2
XMC_ETH_MAC_TIMESTAMP_CONFIG_ENABLE_PTP_OVER_ETHERNET
XMC_ETH_MAC_TIMESTAMP_CONFIG_ENABLE_PTP_OVER_IPV6
XMC_ETH_MAC_TIMESTAMP_CONFIG_ENABLE_PTP_OVER_IPV4
XMC_ETH_MAC_TIMESTAMP_CONFIG_ENABLE_MAC_ADDRESS_FILTER
XMC_ETH_MAC_TIMESTAMP_STATUS_t
XMC_ETH_MAC_TIMESTAMP_STATUS_SECONDS_OVERFLOW
XMC_ETH_MAC_TIMESTAMP_STATUS_TARGET_TIME_REACHED
XMC_ETH_MAC_TIMESTAMP_STATUS_TARGET_TIMER_ERROR
XMC_ETH_MAC_TX_FRAME_t
XMC_ETH_MAC_TX_FRAME_FRAGMENT
XMC_ETH_MAC_TX_FRAME_EVENT
XMC_ETH_MAC_TX_FRAME_TIMESTAMP
XMC_ETH_MAC_AdjustPTPClock
XMC_ETH_MAC_ClearEventStatus
XMC_ETH_MAC_Disable
XMC_ETH_MAC_DisableDestinationAddressInverseFilter
XMC_ETH_MAC_DisableEvent
XMC_ETH_MAC_DisableFrameBurst
XMC_ETH_MAC_DisableFrameFilter
XMC_ETH_MAC_DisableJumboFrame
XMC_ETH_MAC_DisableLoopback
XMC_ETH_MAC_DisableMulticastHashFilter
XMC_ETH_MAC_DisablePowerDownMode
XMC_ETH_MAC_DisablePowerManagmentEvent
XMC_ETH_MAC_DisablePromiscuousMode
XMC_ETH_MAC_DisablePTPAlarm
XMC_ETH_MAC_DisableReceptionBroadcastFrames
XMC_ETH_MAC_DisableReceptionMulticastFrames
XMC_ETH_MAC_DisableRx
XMC_ETH_MAC_DisableRxOwn
XMC_ETH_MAC_DisableRxWatchdog
XMC_ETH_MAC_DisableSourceAddressFilter
XMC_ETH_MAC_DisableSourceAddressInverseFilter
XMC_ETH_MAC_DisableTx
XMC_ETH_MAC_DisableTxJabber
XMC_ETH_MAC_DisableUnicastHashFilter
XMC_ETH_MAC_Enable
XMC_ETH_MAC_EnableDestinationAddressInverseFilter
XMC_ETH_MAC_EnableEvent
XMC_ETH_MAC_EnableFrameBurst
XMC_ETH_MAC_EnableFrameFilter
XMC_ETH_MAC_EnableHashPerfectFilter
XMC_ETH_MAC_EnableJumboFrame
XMC_ETH_MAC_EnableLoopback
XMC_ETH_MAC_EnableMulticastHashFilter
XMC_ETH_MAC_EnablePerfectFilter
XMC_ETH_MAC_EnablePowerDownMode
XMC_ETH_MAC_EnablePowerManagmentEvent
XMC_ETH_MAC_EnablePromiscuousMode
XMC_ETH_MAC_EnablePTPAlarm
XMC_ETH_MAC_EnableReceptionBroadcastFrames
XMC_ETH_MAC_EnableReceptionMulticastFrames
XMC_ETH_MAC_EnableRx
XMC_ETH_MAC_EnableRxOwn
XMC_ETH_MAC_EnableRxWatchdog
XMC_ETH_MAC_EnableSourceAddressFilter
XMC_ETH_MAC_EnableSourceAddressInverseFilter
XMC_ETH_MAC_EnableTx
XMC_ETH_MAC_EnableTxJabber
XMC_ETH_MAC_EnableUnicastHashFilter
XMC_ETH_MAC_FlushRx
XMC_ETH_MAC_FlushTx
XMC_ETH_MAC_GetAddress
XMC_ETH_MAC_GetEventStatus
XMC_ETH_MAC_GetPTPStatus
XMC_ETH_MAC_GetPTPTime
XMC_ETH_MAC_GetRxBuffer
XMC_ETH_MAC_GetRxFrameSize
XMC_ETH_MAC_GetRxTimeStamp
XMC_ETH_MAC_GetTxBuffer
XMC_ETH_MAC_GetTxTimeStamp
XMC_ETH_MAC_Init
XMC_ETH_MAC_InitPTP
XMC_ETH_MAC_InitPTPEx
XMC_ETH_MAC_InitRxDescriptors
XMC_ETH_MAC_InitTxDescriptors
XMC_ETH_MAC_IsEnabled
XMC_ETH_MAC_IsMagicPacketReceived
XMC_ETH_MAC_IsRxDescriptorOwnedByDma
XMC_ETH_MAC_IsTxDescriptorOwnedByDma
XMC_ETH_MAC_IsWakeupFrameReceived
XMC_ETH_MAC_ReadFrame
XMC_ETH_MAC_ReadPhy
XMC_ETH_MAC_Reset
XMC_ETH_MAC_ResumeRx
XMC_ETH_MAC_ResumeTx
XMC_ETH_MAC_ReturnRxDescriptor
XMC_ETH_MAC_ReturnTxDescriptor
XMC_ETH_MAC_SendFrame
XMC_ETH_MAC_SetAddress
XMC_ETH_MAC_SetAddressHashFilter
XMC_ETH_MAC_SetAddressPerfectFilter
XMC_ETH_MAC_SetLink
XMC_ETH_MAC_SetManagmentClockDivider
XMC_ETH_MAC_SetPortControl
XMC_ETH_MAC_SetPTPAlarm
XMC_ETH_MAC_SetPTPTime
XMC_ETH_MAC_SetTxBufferSize
XMC_ETH_MAC_SetVLANTag
XMC_ETH_MAC_SetWakeUpFrameFilter
XMC_ETH_MAC_UpdateAddend
XMC_ETH_MAC_UpdatePTPTime
XMC_ETH_MAC_WritePhy
ETH_PHY
XMC_ETH_PHY_CONFIG_t
duplex
enable_auto_negotiate
enable_loop_back
interface
speed
XMC_ETH_PHY_STATUS_t
XMC_ETH_PHY_STATUS_OK
XMC_ETH_PHY_STATUS_BUSY
XMC_ETH_PHY_STATUS_ERROR
XMC_ETH_PHY_STATUS_ERROR_DEVICE_ID
XMC_ETH_PHY_STATUS_ERROR_TIMEOUT
XMC_ETH_PHY_ExitPowerDown
XMC_ETH_PHY_GetLinkDuplex
XMC_ETH_PHY_GetLinkSpeed
XMC_ETH_PHY_GetLinkStatus
XMC_ETH_PHY_Init
XMC_ETH_PHY_IsAutonegotiationCompleted
XMC_ETH_PHY_PowerDown
XMC_ETH_PHY_Reset
FCE
XMC_FCE_CONFIG_t
__pad1__
config_refin
config_refout
config_xsel
XMC_FCE_t
fce_cfg_update
kernel_ptr
seedvalue
XMC_FCE_CRC16
XMC_FCE_CRC32_0
XMC_FCE_CRC32_1
XMC_FCE_CRC8
XMC_FCE_INVSEL_RESET
XMC_FCE_INVSEL_SET
XMC_FCE_REFIN_RESET
XMC_FCE_REFIN_SET
XMC_FCE_REFOUT_RESET
XMC_FCE_REFOUT_SET
XMC_FCE_Kernel_t
XMC_FCE_CONFIG_ALGO_t
XMC_FCE_CFG_CONFIG_REFIN
XMC_FCE_CFG_CONFIG_REFOUT
XMC_FCE_CFG_CONFIG_XSEL
XMC_FCE_CONFIG_INTERRUPT_t
XMC_FCE_CFG_CONFIG_CMI
XMC_FCE_CFG_CONFIG_CEI
XMC_FCE_CFG_CONFIG_LEI
XMC_FCE_CFG_CONFIG_BEI
XMC_FCE_CONFIG_OPERATION_t
XMC_FCE_CFG_CONFIG_CCE
XMC_FCE_CFG_CONFIG_ALR
XMC_FCE_CTR_TEST_t
XMC_FCE_CTR_MISMATCH_CRC
XMC_FCE_CTR_MISMATCH_CFG
XMC_FCE_CTR_MISMATCH_CHECK
XMC_FCE_STATUS_t
XMC_FCE_STATUS_OK
XMC_FCE_STATUS_BUSY
XMC_FCE_STATUS_ERROR
XMC_FCE_STS_FLAG_t
XMC_FCE_STS_MISMATCH_CRC
XMC_FCE_STS_CONFIG_ERROR
XMC_FCE_STS_LENGTH_ERROR
XMC_FCE_STS_BUS_ERROR
XMC_FCE_CalculateCRC16
XMC_FCE_CalculateCRC32
XMC_FCE_CalculateCRC8
XMC_FCE_ClearEvent
XMC_FCE_Disable
XMC_FCE_DisableCRCAlgorithm
XMC_FCE_DisableEvent
XMC_FCE_DisableOperation
XMC_FCE_Enable
XMC_FCE_EnableCRCAlgorithm
XMC_FCE_EnableEvent
XMC_FCE_EnableOperation
XMC_FCE_Get_DisableStatus
XMC_FCE_GetCRCResult
XMC_FCE_GetEventStatus
XMC_FCE_Init
XMC_FCE_InitializeSeedValue
XMC_FCE_LittleEndian16bit
XMC_FCE_LittleEndian32bit
XMC_FCE_ReadModuleNumber
XMC_FCE_ReadModuleRev
XMC_FCE_ReadModuleType
XMC_FCE_TriggerMismatch
XMC_FCE_UpdateCRCCheck
XMC_FCE_UpdateLength
FLASH
XMC_FLASH_BYTES_PER_PAGE
XMC_FLASH_BYTES_PER_UCB
XMC_FLASH_PHY_SECTOR_0
XMC_FLASH_PHY_SECTOR_10
XMC_FLASH_PHY_SECTOR_11
XMC_FLASH_PHY_SECTOR_12
XMC_FLASH_PHY_SECTOR_13
XMC_FLASH_PHY_SECTOR_14
XMC_FLASH_PHY_SECTOR_15
XMC_FLASH_PHY_SECTOR_4
XMC_FLASH_PHY_SECTOR_8
XMC_FLASH_PHY_SECTOR_9
XMC_FLASH_SECTOR_0
XMC_FLASH_SECTOR_1
XMC_FLASH_SECTOR_10
XMC_FLASH_SECTOR_11
XMC_FLASH_SECTOR_12
XMC_FLASH_SECTOR_13
XMC_FLASH_SECTOR_14
XMC_FLASH_SECTOR_15
XMC_FLASH_SECTOR_2
XMC_FLASH_SECTOR_3
XMC_FLASH_SECTOR_4
XMC_FLASH_SECTOR_5
XMC_FLASH_SECTOR_6
XMC_FLASH_SECTOR_7
XMC_FLASH_SECTOR_8
XMC_FLASH_SECTOR_9
XMC_FLASH_UCB0
XMC_FLASH_UCB1
XMC_FLASH_UCB2
XMC_FLASH_UNCACHED_BASE
XMC_FLASH_WORDS_PER_PAGE
XMC_FLASH_EVENT_t
XMC_FLASH_EVENT_VERIFY_AND_OPERATION_ERROR
XMC_FLASH_EVENT_COMMAND_SEQUENCE_ERROR
XMC_FLASH_EVENT_PROTECTION_ERROR
XMC_FLASH_EVENT_SINGLE_BIT_ERROR
XMC_FLASH_EVENT_DOUBLE_BIT_ERROR
XMC_FLASH_EVENT_END_OF_BUSY
XMC_FLASH_MARGIN_t
XMC_FLASH_MARGIN_DEFAULT
XMC_FLASH_MARGIN_TIGHT0
XMC_FLASH_MARGIN_TIGHT1
XMC_FLASH_PROTECTION_t
XMC_FLASH_PROTECTION_WRITE_SECTOR_0
XMC_FLASH_PROTECTION_WRITE_SECTOR_1
XMC_FLASH_PROTECTION_WRITE_SECTOR_2
XMC_FLASH_PROTECTION_WRITE_SECTOR_3
XMC_FLASH_PROTECTION_WRITE_SECTOR_4
XMC_FLASH_PROTECTION_WRITE_SECTOR_5
XMC_FLASH_PROTECTION_WRITE_SECTOR_6
XMC_FLASH_PROTECTION_WRITE_SECTOR_7
XMC_FLASH_PROTECTION_WRITE_SECTOR_8
XMC_FLASH_PROTECTION_WRITE_SECTOR_9
XMC_FLASH_PROTECTION_WRITE_SECTORS_10_11
XMC_FLASH_PROTECTION_WRITE_SECTORS_12_13
XMC_FLASH_PROTECTION_WRITE_SECTORS_14_15
XMC_FLASH_PROTECTION_READ_GLOBAL
XMC_FLASH_STATUS_t
XMC_FLASH_STATUS_OK
XMC_FLASH_STATUS_BUSY
XMC_FLASH_STATUS_PROGRAMMING_STATE
XMC_FLASH_STATUS_ERASE_STATE
XMC_FLASH_STATUS_PAGE_MODE
XMC_FLASH_STATUS_OPERATION_ERROR
XMC_FLASH_STATUS_COMMAND_SEQUENCE_ERROR
XMC_FLASH_STATUS_PROTECTION_ERROR
XMC_FLASH_STATUS_SINGLE_BIT_ERROR_AND_CORRECTION
XMC_FLASH_STATUS_DOUBLE_BIT_ERROR
XMC_FLASH_STATUS_PROTECTION_INSTALLED
XMC_FLASH_STATUS_READ_PROTECTION_INSTALLED
XMC_FLASH_STATUS_READ_PROTECTION_DISABLED_STATE
XMC_FLASH_STATUS_WRITE_PROTECTION_INSTALLED_UCB0
XMC_FLASH_STATUS_WRITE_PROTECTION_INSTALLED_UCB1
XMC_FLASH_STATUS_WRITE_PROTECTION_INSTALLED_UCB2
XMC_FLASH_STATUS_WRITE_PROTECTION_DISABLED_UCB0
XMC_FLASH_STATUS_WRITE_PROTECTION_DISABLED_UCB1
XMC_FLASH_STATUS_SLEEP_MODE
XMC_FLASH_STATUS_VERIFY_ERROR
XMC_FLASH_ClearStatus
XMC_FLASH_ConfirmProtection
XMC_FLASH_DisableDoubleBitErrorTrap
XMC_FLASH_DisableDynamicIdle
XMC_FLASH_DisableEvent
XMC_FLASH_DisableSleepRequest
XMC_FLASH_DisableWaitStateForECC
XMC_FLASH_EnableDoubleBitErrorTrap
XMC_FLASH_EnableDynamicIdle
XMC_FLASH_EnableEvent
XMC_FLASH_EnableSleepRequest
XMC_FLASH_EnableWaitStateForECC
XMC_FLASH_ErasePhysicalSector
XMC_FLASH_EraseSector
XMC_FLASH_EraseUCB
XMC_FLASH_GetStatus
XMC_FLASH_InstallProtection
XMC_FLASH_IsBusy
XMC_FLASH_ProgramPage
XMC_FLASH_RepairPhysicalSector
XMC_FLASH_Reset
XMC_FLASH_ResumeProtection
XMC_FLASH_SetMargin
XMC_FLASH_SetWaitStates
XMC_FLASH_VerifyReadProtection
XMC_FLASH_VerifyWriteProtection
XMC_PREFETCH_DisableInstructionBuffer
XMC_PREFETCH_EnableInstructionBuffer
XMC_PREFETCH_InvalidateInstructionBuffer
GPIO
XMC_GPIO_CONFIG_t
mode
output_level
output_strength
XMC_GPIO_PORT_t
HWSEL
IN
IOCR
OMR
OUT
PDISC
PDR
PPS
XMC_GPIO_HWCTRL_t
XMC_GPIO_HWCTRL_DISABLED
XMC_GPIO_HWCTRL_PERIPHERAL1
XMC_GPIO_HWCTRL_PERIPHERAL2
XMC_GPIO_MODE_t
XMC_GPIO_MODE_INPUT_TRISTATE
XMC_GPIO_MODE_INPUT_PULL_DOWN
XMC_GPIO_MODE_INPUT_PULL_UP
XMC_GPIO_MODE_INPUT_SAMPLING
XMC_GPIO_MODE_INPUT_INVERTED_TRISTATE
XMC_GPIO_MODE_INPUT_INVERTED_PULL_DOWN
XMC_GPIO_MODE_INPUT_INVERTED_PULL_UP
XMC_GPIO_MODE_INPUT_INVERTED_SAMPLING
XMC_GPIO_MODE_OUTPUT_PUSH_PULL
XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN
XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT1
XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT2
XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT3
XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT4
XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT1
XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT2
XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT3
XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT4
XMC_GPIO_OUTPUT_LEVEL_t
XMC_GPIO_OUTPUT_LEVEL_LOW
XMC_GPIO_OUTPUT_LEVEL_HIGH
XMC_GPIO_OUTPUT_STRENGTH_t
XMC_GPIO_OUTPUT_STRENGTH_STRONG_SHARP_EDGE
XMC_GPIO_OUTPUT_STRENGTH_STRONG_MEDIUM_EDGE
XMC_GPIO_OUTPUT_STRENGTH_STRONG_SOFT_EDGE
XMC_GPIO_OUTPUT_STRENGTH_STRONG_SLOW_EDGE
XMC_GPIO_OUTPUT_STRENGTH_MEDIUM
XMC_GPIO_OUTPUT_STRENGTH_WEAK
XMC_GPIO_DisableDigitalInput
XMC_GPIO_DisablePowerSaveMode
XMC_GPIO_EnableDigitalInput
XMC_GPIO_EnablePowerSaveMode
XMC_GPIO_GetInput
XMC_GPIO_Init
XMC_GPIO_SetHardwareControl
XMC_GPIO_SetMode
XMC_GPIO_SetOutputHigh
XMC_GPIO_SetOutputLevel
XMC_GPIO_SetOutputLow
XMC_GPIO_SetOutputStrength
XMC_GPIO_ToggleOutput
HRPWM
XMC_HRPWM_CSG_CMP_t
blank_ext_enable
blanking_mode
blanking_val
cc
clamp_ctrl_lvl
clamp_enter_config
clamp_exit_config
clamp_exit_sw_config
clamp_level
cmp_ext_sw_enable
cmp_input_sel
cmp_input_sw
cmp_out_inv
filter_control
filter_enable
filter_window
plc
XMC_HRPWM_CSG_CONFIG_t
cmp_config
dac_config
sgen_config
XMC_HRPWM_CSG_DAC_t
dac_dsv1
dac_dsv2
start_mode
XMC_HRPWM_CSG_INPUT_CONFIG_t
edge
level
mapped_input
XMC_HRPWM_CSG_SGEN_t
ctrl_mode
ext_start_mode
ext_stop_mode
fixed_prescaler_enable
prescaler
prescaler_ext_start_mode
prescaler_ext_stop_mode
pulse_swallow_enable
pulse_swallow_val
pulse_swallow_win_mode
sc
slope_ref_val_mode
static_mode_ist_enable
step_gain
XMC_HRPWM_HRC_CONFIG_t
dt_enable
dt_shadow_xfer_linktoCCU8
dt_trigger_sel
gc
hr_out0_inv_enable
hr_out0_passive_level_out
hr_out0_trap_enable
hr_out1_inv_enable
hr_out1_passive_level_out
hr_out1_trap_enable
hrc_shadow_xfer_linktoCCU8
psl
XMC_HRPWM_HRC_SRC_CONFIG_t
clear_config
clear_edge_config
cmp_clear
cmp_set
high_res_mode
set_config
set_edge_config
src_trap_enable
timer_sel
XMC_HRPWM_CSG_t
XMC_HRPWM_HRC_t
XMC_HRPWM_t
XMC_HRPWM_CLK_FREQ_t
XMC_HRPWM_CLK_FREQ_NONE
XMC_HRPWM_CLK_FREQ_180MHZ
XMC_HRPWM_CLK_FREQ_120MHZ
XMC_HRPWM_CLK_FREQ_80MHZ
XMC_HRPWM_CSG_CLK_INPUT_t
XMC_HRPWM_CSG_CLK_INPUT_MCLK
XMC_HRPWM_CSG_CLK_INPUT_ECLKA
XMC_HRPWM_CSG_CLK_INPUT_ECLKB
XMC_HRPWM_CSG_CLK_INPUT_ECLKC
XMC_HRPWM_CSG_CLK_t
XMC_HRPWM_CSG_CLK_CSG0
XMC_HRPWM_CSG_CLK_CSG1
XMC_HRPWM_CSG_CLK_CSG2
XMC_HRPWM_CSG_CMP_FILTER_WINDOW_t
XMC_HRPWM_CSG_CMP_FILTER_WINDOW_2_CLK_CYCLES
XMC_HRPWM_CSG_CMP_FILTER_WINDOW_3_CLK_CYCLES
XMC_HRPWM_CSG_CMP_FILTER_WINDOW_4_CLK_CYCLES
XMC_HRPWM_CSG_CMP_FILTER_WINDOW_5_CLK_CYCLES
XMC_HRPWM_CSG_CMP_FILTER_WINDOW_6_CLK_CYCLES
XMC_HRPWM_CSG_CMP_FILTER_WINDOW_7_CLK_CYCLES
XMC_HRPWM_CSG_CMP_FILTER_WINDOW_8_CLK_CYCLES
XMC_HRPWM_CSG_CMP_FILTER_WINDOW_9_CLK_CYCLES
XMC_HRPWM_CSG_CMP_FILTER_WINDOW_10_CLK_CYCLES
XMC_HRPWM_CSG_CMP_FILTER_WINDOW_11_CLK_CYCLES
XMC_HRPWM_CSG_CMP_FILTER_WINDOW_12_CLK_CYCLES
XMC_HRPWM_CSG_CMP_FILTER_WINDOW_13_CLK_CYCLES
XMC_HRPWM_CSG_CMP_FILTER_WINDOW_14_CLK_CYCLES
XMC_HRPWM_CSG_CMP_FILTER_WINDOW_15_CLK_CYCLES
XMC_HRPWM_CSG_CMP_FILTER_WINDOW_16_CLK_CYCLES
XMC_HRPWM_CSG_CMP_FILTER_WINDOW_32_CLK_CYCLES
XMC_HRPWM_CSG_CMP_INPUT_t
XMC_HRPWM_CSG_CMP_INPUT_CINA
XMC_HRPWM_CSG_CMP_INPUT_CINB
XMC_HRPWM_CSG_CMP_INVERTING_INPUT_t
XMC_HRPWM_CSG_CMP_INVERTING_INPUT_CMP0
XMC_HRPWM_CSG_CMP_INVERTING_INPUT_CMP1
XMC_HRPWM_CSG_CMP_INVERTING_INPUT_CMP2
XMC_HRPWM_CSG_EDGE_SEL_t
XMC_HRPWM_CSG_EDGE_SEL_DISABLED
XMC_HRPWM_CSG_EDGE_SEL_RISING_EDGE
XMC_HRPWM_CSG_EDGE_SEL_FALLING_EDGE
XMC_HRPWM_CSG_EDGE_SEL_BOTH_EDGE
XMC_HRPWM_CSG_INPUT_SEL_t
XMC_HRPWM_CSG_INPUT_SEL_IA
XMC_HRPWM_CSG_INPUT_SEL_IB
XMC_HRPWM_CSG_INPUT_SEL_IC
XMC_HRPWM_CSG_INPUT_SEL_ID
XMC_HRPWM_CSG_INPUT_SEL_IE
XMC_HRPWM_CSG_INPUT_SEL_IF
XMC_HRPWM_CSG_INPUT_SEL_IG
XMC_HRPWM_CSG_INPUT_SEL_IH
XMC_HRPWM_CSG_INPUT_SEL_II
XMC_HRPWM_CSG_INPUT_SEL_IJ
XMC_HRPWM_CSG_INPUT_SEL_IK
XMC_HRPWM_CSG_INPUT_SEL_IL
XMC_HRPWM_CSG_INPUT_SEL_IM
XMC_HRPWM_CSG_INPUT_SEL_IN
XMC_HRPWM_CSG_INPUT_SEL_IO
XMC_HRPWM_CSG_INPUT_SEL_IP
XMC_HRPWM_CSG_IRQ_ID_t
XMC_HRPWM_CSG_IRQ_ID_VLS1
XMC_HRPWM_CSG_IRQ_ID_VLS2
XMC_HRPWM_CSG_IRQ_ID_TRGS
XMC_HRPWM_CSG_IRQ_ID_STRS
XMC_HRPWM_CSG_IRQ_ID_STPS
XMC_HRPWM_CSG_IRQ_ID_STD
XMC_HRPWM_CSG_IRQ_ID_CRSE
XMC_HRPWM_CSG_IRQ_ID_CFSE
XMC_HRPWM_CSG_IRQ_ID_CSEE
XMC_HRPWM_CSG_IRQ_SR_LINE_t
XMC_HRPWM_CSG_IRQ_SR_LINE_0
XMC_HRPWM_CSG_IRQ_SR_LINE_1
XMC_HRPWM_CSG_IRQ_SR_LINE_2
XMC_HRPWM_CSG_IRQ_SR_LINE_3
XMC_HRPWM_CSG_LVL_SEL_t
XMC_HRPWM_CSG_LVL_SEL_DISABLED
XMC_HRPWM_CSG_LVL_SEL_HIGH
XMC_HRPWM_CSG_LVL_SEL_LOW
XMC_HRPWM_CSG_POWER_MODE_t
XMC_HRPWM_CSG_POWER_MODE_OFF
XMC_HRPWM_CSG_POWER_MODE_LOW_SPEED
XMC_HRPWM_CSG_POWER_MODE_HI_SPEED
XMC_HRPWM_CSG_PRESCALER_CLR_t
XMC_HRPWM_CSG_PRESCALER_CLR_CSG0
XMC_HRPWM_CSG_PRESCALER_CLR_CSG1
XMC_HRPWM_CSG_PRESCALER_CLR_CSG2
XMC_HRPWM_CSG_PRESCALER_DIVISION_t
XMC_HRPWM_CSG_PRESCALER_DIVISION_BY_1
XMC_HRPWM_CSG_PRESCALER_DIVISION_BY_2
XMC_HRPWM_CSG_PRESCALER_DIVISION_BY_4
XMC_HRPWM_CSG_PRESCALER_DIVISION_BY_8
XMC_HRPWM_CSG_PRESCALER_EXT_START_t
XMC_HRPWM_CSG_PRESCALER_EXT_START_IGNORE
XMC_HRPWM_CSG_PRESCALER_EXT_START_STRT
XMC_HRPWM_CSG_PRESCALER_EXT_START_CLR
XMC_HRPWM_CSG_PRESCALER_EXT_START_CLR_N_STRT
XMC_HRPWM_CSG_PRESCALER_EXT_STOP_t
XMC_HRPWM_CSG_PRESCALER_EXT_STOP_IGNORE
XMC_HRPWM_CSG_PRESCALER_EXT_STOP_STP
XMC_HRPWM_CSG_PRESCALER_EXT_STOP_CLR
XMC_HRPWM_CSG_PRESCALER_EXT_STOP_CLR_N_STOP
XMC_HRPWM_CSG_PRESCALER_START_t
XMC_HRPWM_CSG_PRESCALER_START_CSG0
XMC_HRPWM_CSG_PRESCALER_START_CSG1
XMC_HRPWM_CSG_PRESCALER_START_CSG2
XMC_HRPWM_CSG_PRESCALER_STATUS_t
XMC_HRPWM_CSG_PRESCALER_STATUS_CSG0
XMC_HRPWM_CSG_PRESCALER_STATUS_CSG1
XMC_HRPWM_CSG_PRESCALER_STATUS_CSG2
XMC_HRPWM_CSG_PRESCALER_STOP_t
XMC_HRPWM_CSG_PRESCALER_STOP_CSG0
XMC_HRPWM_CSG_PRESCALER_STOP_CSG1
XMC_HRPWM_CSG_PRESCALER_STOP_CSG2
XMC_HRPWM_CSG_RUN_BIT_t
XMC_HRPWM_CSG_RUN_BIT_DAC0
XMC_HRPWM_CSG_RUN_BIT_CMP0
XMC_HRPWM_CSG_RUN_BIT_CMP0_PSL
XMC_HRPWM_CSG_RUN_BIT_DAC1
XMC_HRPWM_CSG_RUN_BIT_CMP1
XMC_HRPWM_CSG_RUN_BIT_CMP1_PSL
XMC_HRPWM_CSG_RUN_BIT_DAC2
XMC_HRPWM_CSG_RUN_BIT_CMP2
XMC_HRPWM_CSG_RUN_BIT_CMP2_PSL
XMC_HRPWM_CSG_SLICE_t
XMC_HRPWM_CSG_SLICE_0
XMC_HRPWM_CSG_SLICE_1
XMC_HRPWM_CSG_SLICE_2
XMC_HRPWM_CSG_SLOPE_CTRL_MODE_t
XMC_HRPWM_CSG_SLOPE_CTRL_MODE_STATIC
XMC_HRPWM_CSG_SLOPE_CTRL_MODE_DEC_GEN
XMC_HRPWM_CSG_SLOPE_CTRL_MODE_INC_GEN
XMC_HRPWM_CSG_SLOPE_CTRL_MODE_TRIANGULAR
XMC_HRPWM_CSG_SLOPE_EXT_START_t
XMC_HRPWM_CSG_SLOPE_EXT_START_IGNORE
XMC_HRPWM_CSG_SLOPE_EXT_START_STRT
XMC_HRPWM_CSG_SLOPE_EXT_START_RESUME
XMC_HRPWM_CSG_SLOPE_EXT_STOP_t
XMC_HRPWM_CSG_SLOPE_EXT_STOP_IGNORE
XMC_HRPWM_CSG_SLOPE_EXT_STOP_STP
XMC_HRPWM_CSG_SLOPE_EXT_STOP_FREEZE
XMC_HRPWM_CSG_SLOPE_START_t
XMC_HRPWM_CSG_SLOPE_START_DAC0
XMC_HRPWM_CSG_SLOPE_START_DAC1
XMC_HRPWM_CSG_SLOPE_START_DAC2
XMC_HRPWM_CSG_SLOPE_STEP_GAIN_t
XMC_HRPWM_CSG_SLOPE_STEP_GAIN_INC_DEC_BY_1
XMC_HRPWM_CSG_SLOPE_STEP_GAIN_INC_DEC_BY_2
XMC_HRPWM_CSG_SLOPE_STEP_GAIN_INC_DEC_BY_4
XMC_HRPWM_CSG_SLOPE_STEP_GAIN_INC_DEC_BY_8
XMC_HRPWM_CSG_SLOPE_STOP_t
XMC_HRPWM_CSG_SLOPE_STOP_DAC0
XMC_HRPWM_CSG_SLOPE_STOP_DAC1
XMC_HRPWM_CSG_SLOPE_STOP_DAC2
XMC_HRPWM_CSG_SWITCH_CMP_INPUT_t
XMC_HRPWM_CSG_SWITCH_CMP_INPUT_CMP0
XMC_HRPWM_CSG_SWITCH_CMP_INPUT_CMP1
XMC_HRPWM_CSG_SWITCH_CMP_INPUT_CMP2
XMC_HRPWM_CSG_SWSM_t
XMC_HRPWM_CSG_SWSM_DSV2_W_TRIGGER
XMC_HRPWM_CSG_SWSM_DSV1_W_TRIGGER
XMC_HRPWM_CSG_SWSM_DSV2_NO_TRIGGER
XMC_HRPWM_CSG_SWSM_DSV1_NO_TRIGGER
XMC_HRPWM_DAC_SLOPE_GEN_STATUS_t
XMC_HRPWM_DAC_SLOPE_GEN_STATUS_DAC0
XMC_HRPWM_DAC_SLOPE_GEN_STATUS_DAC1
XMC_HRPWM_DAC_SLOPE_GEN_STATUS_DAC2
XMC_HRPWM_FUNC_STATUS_t
XMC_HRPWM_FUNC_STATUS_DISABLE
XMC_HRPWM_FUNC_STATUS_ENABLE
XMC_HRPWM_HR_LOGIC_t
XMC_HRPWM_HR_LOGIC_NOT_WORKING
XMC_HRPWM_HR_LOGIC_WORKING
XMC_HRPWM_HR_PATH_t
XMC_HRPWM_HR_PATH_HRC0
XMC_HRPWM_HR_PATH_HRC1
XMC_HRPWM_HR_PATH_HRC2
XMC_HRPWM_HR_PATH_HRC3
XMC_HRPWM_HRC_CMP_SEL_t
XMC_HRPWM_HRC_CMP_SEL_CSG0
XMC_HRPWM_HRC_CMP_SEL_CSG1
XMC_HRPWM_HRC_CMP_SEL_CSG2
XMC_HRPWM_HRC_DT_TR_SEL_t
XMC_HRPWM_HRC_DT_TR_SEL_TIMER
XMC_HRPWM_HRC_DT_TR_SEL_OVERFLOW
XMC_HRPWM_HRC_HR_EDGE_t
XMC_HRPWM_HRC_HR_EDGE_SEL_RISING
XMC_HRPWM_HRC_HR_EDGE_SEL_FALLING
XMC_HRPWM_HRC_HR_EDGE_SEL_BOTH
XMC_HRPWM_HRC_HR_EDGE_SEL_NONE
XMC_HRPWM_HRC_OUT_PASSIVE_LVL_t
XMC_HRPWM_HRC_OUT_PASSIVE_LVL_LOW
XMC_HRPWM_HRC_OUT_PASSIVE_LVL_HIGH
XMC_HRPWM_HRC_SHADOW_TX_t
XMC_HRPWM_HRC_SHADOW_TX_HRC0_VALUE
XMC_HRPWM_HRC_SHADOW_TX_HRC0_DT_VALUE
XMC_HRPWM_HRC_SHADOW_TX_HRC1_VALUE
XMC_HRPWM_HRC_SHADOW_TX_HRC1_DT_VALUE
XMC_HRPWM_HRC_SHADOW_TX_HRC2_VALUE
XMC_HRPWM_HRC_SHADOW_TX_HRC2_DT_VALUE
XMC_HRPWM_HRC_SHADOW_TX_HRC3_VALUE
XMC_HRPWM_HRC_SHADOW_TX_HRC3_DT_VALUE
XMC_HRPWM_HRC_SOURCE_t
XMC_HRPWM_HRC_SOURCE_0
XMC_HRPWM_HRC_SOURCE_1
XMC_HRPWM_HRC_SRC_EDGE_SEL_t
XMC_HRPWM_HRC_SRC_EDGE_SEL_DISABLED
XMC_HRPWM_HRC_SRC_EDGE_SEL_RISING
XMC_HRPWM_HRC_SRC_EDGE_SEL_FALLING
XMC_HRPWM_HRC_SRC_EDGE_SEL_BOTH
XMC_HRPWM_HRC_SRC_INPUT_t
XMC_HRPWM_HRC_SRC_INPUT_CCU
XMC_HRPWM_HRC_SRC_INPUT_CSG
XMC_HRPWM_HRC_TIMER_SEL_t
XMC_HRPWM_HRC_TIMER_SEL_CCU_CC0
XMC_HRPWM_HRC_TIMER_SEL_CCU_CC1
XMC_HRPWM_HRC_TIMER_SEL_CCU_CC2
XMC_HRPWM_HRC_TIMER_SEL_CCU_CC3
XMC_HRPWM_LR_PATH_t
XMC_HRPWM_LR_PATH_HRC0
XMC_HRPWM_LR_PATH_HRC1
XMC_HRPWM_LR_PATH_HRC2
XMC_HRPWM_LR_PATH_HRC3
XMC_HRPWM_SHADOW_TX_DAC_t
XMC_HRPWM_SHADOW_TX_DAC0
XMC_HRPWM_SHADOW_TX_DAC1
XMC_HRPWM_SHADOW_TX_DAC2
XMC_HRPWM_STATUS_t
XMC_HRPWM_STATUS_OK
XMC_HRPWM_STATUS_BUSY
XMC_HRPWM_STATUS_ERROR
XMC_HRPWM_ClampComparatorOutput
XMC_HRPWM_ClearPreScaler
XMC_HRPWM_CSG_ClrEventSW
XMC_HRPWM_CSG_DACRefValSwitchingConfig
XMC_HRPWM_CSG_DisableEvent
XMC_HRPWM_CSG_EnableEvent
XMC_HRPWM_CSG_GetEventStatus
XMC_HRPWM_CSG_Init
XMC_HRPWM_CSG_SelBlankingInput
XMC_HRPWM_CSG_SelClampingInput
XMC_HRPWM_CSG_SelSlopeGenClkInput
XMC_HRPWM_CSG_SetCMPInput
XMC_HRPWM_CSG_SetEventSW
XMC_HRPWM_CSG_SetSRNode
XMC_HRPWM_CSG_StartSlopeGenConfig
XMC_HRPWM_CSG_StopSlopeGenConfig
XMC_HRPWM_CSG_TriggerDACConvConfig
XMC_HRPWM_CSG_TriggerShadowXferConfig
XMC_HRPWM_CSG_UpdateBlankingValue
XMC_HRPWM_CSG_UpdateDACPrescaler
XMC_HRPWM_CSG_UpdateDACRefDSV1
XMC_HRPWM_CSG_UpdateDACRefDSV2
XMC_HRPWM_CSG_UpdateDACStepGain
XMC_HRPWM_CSG_UpdateFilterWindow
XMC_HRPWM_CSG_UpdatePulseClk
XMC_HRPWM_DisableBias
XMC_HRPWM_DisableComparatorShadowTransfer
XMC_HRPWM_DisableCsgClock
XMC_HRPWM_DisableGlobalHR
XMC_HRPWM_DisableHighResolutionPath
XMC_HRPWM_DisableHighResolutionShadowTransfer
XMC_HRPWM_DisableHRPowerMode
XMC_HRPWM_DisableLowResolutionPath
XMC_HRPWM_EnableBias
XMC_HRPWM_EnableComparatorShadowTransfer
XMC_HRPWM_EnableGlobalHR
XMC_HRPWM_EnableHighResolutionPath
XMC_HRPWM_EnableHighResolutionShadowTransfer
XMC_HRPWM_EnableHRPowerMode
XMC_HRPWM_EnableLowResolutionPath
XMC_HRPWM_GetCMPInput
XMC_HRPWM_GetComparatorShadowTransferStatus
XMC_HRPWM_GetHighResolutionShadowTransferStatus
XMC_HRPWM_GetHRGenReadyStatus
XMC_HRPWM_GetRunBitStatus
XMC_HRPWM_HRC_ConfigSourceSelect0
XMC_HRPWM_HRC_ConfigSourceSelect1
XMC_HRPWM_HRC_Init
XMC_HRPWM_HRC_Set_HR_Source
XMC_HRPWM_HRC_SetCompare1
XMC_HRPWM_HRC_SetCompare2
XMC_HRPWM_HRC_SetDeadTimeFalling
XMC_HRPWM_HRC_SetDeadTimeRising
XMC_HRPWM_Init
XMC_HRPWM_IsComparatorClamped
XMC_HRPWM_IsComparatorRunning
XMC_HRPWM_IsDacRunning
XMC_HRPWM_IsPrescalerRunning
XMC_HRPWM_IsSlopeGenerationRunning
XMC_HRPWM_ModuleClkFreq
XMC_HRPWM_SetCsgPowerMode
XMC_HRPWM_StartComparator
XMC_HRPWM_StartDac
XMC_HRPWM_StartSlopeGeneration
XMC_HRPWM_StopComparator
XMC_HRPWM_StopDac
XMC_HRPWM_StopSlopeGeneration
XMC_HRPWM_UnClampComparatorOutput
I2C
XMC_I2C_CH_CONFIG_t
address
baudrate
XMC_I2C0_CH0
XMC_I2C0_CH1
XMC_I2C1_CH0
XMC_I2C1_CH1
XMC_I2C2_CH0
XMC_I2C2_CH1
XMC_I2C_10BIT_ADDR_GROUP
XMC_I2C_CH_CMD_t
XMC_I2C_CH_CMD_WRITE
XMC_I2C_CH_CMD_READ
XMC_I2C_CH_EVENT_t
XMC_I2C_CH_EVENT_RECEIVE_START
XMC_I2C_CH_EVENT_DATA_LOST
XMC_I2C_CH_EVENT_TRANSMIT_SHIFT
XMC_I2C_CH_EVENT_TRANSMIT_BUFFER
XMC_I2C_CH_EVENT_STANDARD_RECEIVE
XMC_I2C_CH_EVENT_ALTERNATIVE_RECEIVE
XMC_I2C_CH_EVENT_BAUD_RATE_GENERATOR
XMC_I2C_CH_EVENT_START_CONDITION_RECEIVED
XMC_I2C_CH_EVENT_REPEATED_START_CONDITION_RECEIVED
XMC_I2C_CH_EVENT_STOP_CONDITION_RECEIVED
XMC_I2C_CH_EVENT_NACK
XMC_I2C_CH_EVENT_ARBITRATION_LOST
XMC_I2C_CH_EVENT_SLAVE_READ_REQUEST
XMC_I2C_CH_EVENT_ERROR
XMC_I2C_CH_EVENT_ACK
XMC_I2C_CH_INPUT_t
XMC_I2C_CH_INPUT_SDA
XMC_I2C_CH_INPUT_SCL
XMC_I2C_CH_INTERRUPT_NODE_POINTER_t
XMC_I2C_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT
XMC_I2C_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER
XMC_I2C_CH_INTERRUPT_NODE_POINTER_RECEIVE
XMC_I2C_CH_INTERRUPT_NODE_POINTER_ALTERNATE_RECEIVE
XMC_I2C_CH_INTERRUPT_NODE_POINTER_PROTOCOL
XMC_I2C_CH_RECEIVER_STATUS_FLAG_t
XMC_I2C_CH_RECEIVER_STATUS_FLAG_ACK
XMC_I2C_CH_RECEIVER_STATUS_FLAG_FIN
XMC_I2C_CH_RECEIVER_STATUS_FLAG_MODE
XMC_I2C_CH_RECEIVER_STATUS_FLAG_ERR
XMC_I2C_CH_RECEIVER_STATUS_FLAG_ADR
XMC_I2C_CH_STATUS_FLAG_t
XMC_I2C_CH_STATUS_FLAG_SLAVE_SELECT
XMC_I2C_CH_STATUS_FLAG_WRONG_TDF_CODE_FOUND
XMC_I2C_CH_STATUS_FLAG_START_CONDITION_RECEIVED
XMC_I2C_CH_STATUS_FLAG_REPEATED_START_CONDITION_RECEIVED
XMC_I2C_CH_STATUS_FLAG_STOP_CONDITION_RECEIVED
XMC_I2C_CH_STATUS_FLAG_NACK_RECEIVED
XMC_I2C_CH_STATUS_FLAG_ARBITRATION_LOST
XMC_I2C_CH_STATUS_FLAG_SLAVE_READ_REQUESTED
XMC_I2C_CH_STATUS_FLAG_ERROR
XMC_I2C_CH_STATUS_FLAG_ACK_RECEIVED
XMC_I2C_CH_STATUS_FLAG_RECEIVER_START_INDICATION
XMC_I2C_CH_STATUS_FLAG_DATA_LOST_INDICATION
XMC_I2C_CH_STATUS_FLAG_TRANSMIT_SHIFT_INDICATION
XMC_I2C_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION
XMC_I2C_CH_STATUS_FLAG_RECEIVE_INDICATION
XMC_I2C_CH_STATUS_FLAG_ALTERNATIVE_RECEIVE_INDICATION
XMC_I2C_CH_STATUS_FLAG_BAUD_RATE_GENERATOR_INDICATION
XMC_I2C_CH_STATUS_t
XMC_I2C_CH_STATUS_OK
XMC_I2C_CH_STATUS_ERROR
XMC_I2C_CH_STATUS_BUSY
XMC_I2C_CH_ClearStatusFlag
XMC_I2C_CH_ConfigExternalInputSignalToBRG
XMC_I2C_CH_DisableAcknowledgeAddress0
XMC_I2C_CH_DisableDataTransmission
XMC_I2C_CH_DisableEvent
XMC_I2C_CH_EnableAcknowledgeAddress0
XMC_I2C_CH_EnableDataTransmission
XMC_I2C_CH_EnableEvent
XMC_I2C_CH_GetReceivedData
XMC_I2C_CH_GetReceiverStatusFlag
XMC_I2C_CH_GetSlaveAddress
XMC_I2C_CH_GetStatusFlag
XMC_I2C_CH_Init
XMC_I2C_CH_MasterReceiveAck
XMC_I2C_CH_MasterReceiveNack
XMC_I2C_CH_MasterRepeatedStart
XMC_I2C_CH_MasterStart
XMC_I2C_CH_MasterStop
XMC_I2C_CH_MasterTransmit
XMC_I2C_CH_SelectInterruptNodePointer
XMC_I2C_CH_SetBaudrate
XMC_I2C_CH_SetInputSource
XMC_I2C_CH_SetInterruptNodePointer
XMC_I2C_CH_SetSlaveAddress
XMC_I2C_CH_SlaveTransmit
XMC_I2C_CH_Start
XMC_I2C_CH_Stop
XMC_I2C_CH_TriggerServiceRequest
I2S
XMC_I2S_CH_CONFIG_t
baudrate
bus_mode
data_bits
data_delayed_sclk_periods
frame_length
wa_inversion
XMC_I2S0_CH0
XMC_I2S0_CH1
XMC_I2S1_CH0
XMC_I2S1_CH1
XMC_I2S2_CH0
XMC_I2S2_CH1
XMC_I2S_CH_BRG_SHIFT_CLOCK_OUTPUT_t
XMC_I2S_CH_BRG_SHIFT_CLOCK_OUTPUT_SCLK
XMC_I2S_CH_BRG_SHIFT_CLOCK_OUTPUT_DX1
XMC_I2S_CH_BUS_MODE_t
XMC_I2S_CH_BUS_MODE_MASTER
XMC_I2S_CH_BUS_MODE_SLAVE
XMC_I2S_CH_CHANNEL_t
XMC_I2S_CH_CHANNEL_1_LEFT
XMC_I2S_CH_CHANNEL_2_RIGHT
XMC_I2S_CH_EVENT_t
XMC_I2S_CH_EVENT_RECEIVE_START
XMC_I2S_CH_EVENT_DATA_LOST
XMC_I2S_CH_EVENT_TRANSMIT_SHIFT
XMC_I2S_CH_EVENT_TRANSMIT_BUFFER
XMC_I2S_CH_EVENT_STANDARD_RECEIVE
XMC_I2S_CH_EVENT_ALTERNATIVE_RECEIVE
XMC_I2S_CH_EVENT_BAUD_RATE_GENERATOR
XMC_I2S_CH_EVENT_WA_FALLING_EDGE
XMC_I2S_CH_EVENT_WA_RISING_EDGE
XMC_I2S_CH_EVENT_WA_GENERATION_END
XMC_I2S_CH_EVENT_DX2TIEN_ACTIVATED
XMC_I2S_CH_INPUT_t
XMC_I2S_CH_INPUT_DIN0
XMC_I2S_CH_INPUT_SLAVE_SCLKIN
XMC_I2S_CH_INPUT_SLAVE_WA
XMC_I2S_CH_INPUT_DIN1
XMC_I2S_CH_INPUT_DIN2
XMC_I2S_CH_INPUT_DIN3
XMC_I2S_CH_INTERRUPT_NODE_POINTER_t
XMC_I2S_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT
XMC_I2S_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER
XMC_I2S_CH_INTERRUPT_NODE_POINTER_RECEIVE
XMC_I2S_CH_INTERRUPT_NODE_POINTER_ALTERNATE_RECEIVE
XMC_I2S_CH_INTERRUPT_NODE_POINTER_PROTOCOL
XMC_I2S_CH_STATUS_FLAG_t
XMC_I2S_CH_STATUS_FLAG_WORD_ADDRESS
XMC_I2S_CH_STATUS_FLAG_DX2S
XMC_I2S_CH_STATUS_FLAG_DX2T_EVENT_DETECTED
XMC_I2S_CH_STATUS_FLAG_WA_FALLING_EDGE_EVENT
XMC_I2S_CH_STATUS_FLAG_WA_RISING_EDGE_EVENT
XMC_I2S_CH_STATUS_FLAG_WA_GENERATION_END
XMC_I2S_CH_STATUS_FLAG_RECEIVER_START_INDICATION
XMC_I2S_CH_STATUS_FLAG_DATA_LOST_INDICATION
XMC_I2S_CH_STATUS_FLAG_TRANSMIT_SHIFT_INDICATION
XMC_I2S_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION
XMC_I2S_CH_STATUS_FLAG_RECEIVE_INDICATION
XMC_I2S_CH_STATUS_FLAG_ALTERNATIVE_RECEIVE_INDICATION
XMC_I2S_CH_STATUS_FLAG_BAUD_RATE_GENERATOR_INDICATION
XMC_I2S_CH_STATUS_t
XMC_I2S_CH_STATUS_OK
XMC_I2S_CH_STATUS_ERROR
XMC_I2S_CH_STATUS_BUSY
XMC_I2S_CH_WA_POLARITY_t
XMC_I2S_CH_WA_POLARITY_DIRECT
XMC_I2S_CH_WA_POLARITY_INVERTED
XMC_I2S_CH_ClearStatusFlag
XMC_I2S_CH_ConfigureShiftClockOutput
XMC_I2S_CH_DisableDataTransmission
XMC_I2S_CH_DisableDelayCompensation
XMC_I2S_CH_DisableEvent
XMC_I2S_CH_DisableInputInversion
XMC_I2S_CH_DisableMasterClock
XMC_I2S_CH_EnableDataTransmission
XMC_I2S_CH_EnableDelayCompensation
XMC_I2S_CH_EnableEvent
XMC_I2S_CH_EnableInputInversion
XMC_I2S_CH_EnableMasterClock
XMC_I2S_CH_GetReceivedData
XMC_I2S_CH_GetStatusFlag
XMC_I2S_CH_Init
XMC_I2S_CH_Receive
XMC_I2S_CH_SelectInterruptNodePointer
XMC_I2S_CH_SetBaudrate
XMC_I2S_CH_SetBitOrderLsbFirst
XMC_I2S_CH_SetBitOrderMsbFirst
XMC_I2S_CH_SetFrameLength
XMC_I2S_CH_SetInputSource
XMC_I2S_CH_SetInterruptNodePointer
XMC_I2S_CH_SetSystemWordLength
XMC_I2S_CH_SetWordLength
XMC_I2S_CH_Start
XMC_I2S_CH_Stop
XMC_I2S_CH_Transmit
XMC_I2S_CH_TriggerServiceRequest
XMC_I2S_CH_WordAddressSignalPolarity
LEDTS
XMC_LEDTS_GLOBAL_CONFIG_t
autoscan_synchronization
clock_generation
suspend_response
XMC_LEDTS_GLOBAL_t
EVFR
FNCTL
GLOBCTL
ID
LDCMP
LINE
TSCMP
TSVAL
XMC_LEDTS_LED_CONFIG_t
column_active_level
no_of_led_columns
XMC_LEDTS_TS_CONFIG_ADVANCED_t
external_pullup
first_pad_turn
pad_turn_control
pin_low_extend
time_frame_validation
validation_mask
XMC_LEDTS_TS_CONFIG_BASIC_t
common_compare
counter_auto_reset
counter_saturation
no_of_accumulation
no_of_touch_inputs
XMC_LEDTS0
XMC_LEDTS0
XMC_LEDTS_t
XMC_LEDTS_ACCUMULATION_COUNT_t
XMC_LEDTS_ACCUMULATION_COUNT_1_TIME
XMC_LEDTS_ACCUMULATION_COUNT_2_TIMES
XMC_LEDTS_ACCUMULATION_COUNT_3_TIMES
XMC_LEDTS_ACCUMULATION_COUNT_4_TIMES
XMC_LEDTS_ACCUMULATION_COUNT_5_TIMES
XMC_LEDTS_ACCUMULATION_COUNT_6_TIMES
XMC_LEDTS_ACCUMULATION_COUNT_7_TIMES
XMC_LEDTS_ACCUMULATION_COUNT_8_TIMES
XMC_LEDTS_ACCUMULATION_COUNT_9_TIMES
XMC_LEDTS_ACCUMULATION_COUNT_10_TIMES
XMC_LEDTS_ACCUMULATION_COUNT_11_TIMES
XMC_LEDTS_ACCUMULATION_COUNT_12_TIMES
XMC_LEDTS_ACCUMULATION_COUNT_13_TIMES
XMC_LEDTS_ACCUMULATION_COUNT_14_TIMES
XMC_LEDTS_ACCUMULATION_COUNT_15_TIMES
XMC_LEDTS_ACCUMULATION_COUNT_16_TIMES
XMC_LEDTS_ACTIVE_LEVEL_LED_COL_t
XMC_LEDTS_ACTIVE_LEVEL_LED_COL_LOW
XMC_LEDTS_ACTIVE_LEVEL_LED_COL_HIGH
XMC_LEDTS_AUTOSCAN_INTERRUPT_FLAG_t
XMC_LEDTS_AUTOSCAN_INTERRUPT_FLAG_INACTIVE
XMC_LEDTS_AUTOSCAN_INTERRUPT_FLAG_ACTIVE
XMC_LEDTS_CLOCK_TYPE_t
XMC_LEDTS_CLOCK_TYPE_MASTER
XMC_LEDTS_CLOCK_TYPE_SLAVE
XMC_LEDTS_COMMON_COMPARE_t
XMC_LEDTS_COMMON_COMPARE_DISABLE
XMC_LEDTS_COMMON_COMPARE_ENABLE
XMC_LEDTS_EXT_PULLUP_COLA_t
XMC_LEDTS_EXT_PULLUP_COLA_DISABLE
XMC_LEDTS_EXT_PULLUP_COLA_ENABLE
XMC_LEDTS_EXTEND_TS_OUTPUT_t
XMC_LEDTS_EXTEND_TS_OUTPUT_BY_1_CLK
XMC_LEDTS_EXTEND_TS_OUTPUT_BY_4_CLK
XMC_LEDTS_EXTEND_TS_OUTPUT_BY_8_CLK
XMC_LEDTS_EXTEND_TS_OUTPUT_BY_16_CLK
XMC_LEDTS_FLAG_STATUS_t
XMC_LEDTS_FLAG_STATUS_NO
XMC_LEDTS_FLAG_STATUS_YES
XMC_LEDTS_INTERRUPT_t
XMC_LEDTS_INTERRUPT_TIMESLICE
XMC_LEDTS_INTERRUPT_TIMEFRAME
XMC_LEDTS_INTERRUPT_TIMEPERIOD
XMC_LEDTS_LED_COLUMN_t
XMC_LEDTS_LED_COLUMN_0
XMC_LEDTS_LED_COLUMN_1
XMC_LEDTS_LED_COLUMN_2
XMC_LEDTS_LED_COLUMN_3
XMC_LEDTS_LED_COLUMN_4
XMC_LEDTS_LED_COLUMN_5
XMC_LEDTS_LED_COLUMN_6
XMC_LEDTS_LED_COLUMN_A
XMC_LEDTS_LED_FUNC_t
XMC_LEDTS_LED_FUNC_DISABLE
XMC_LEDTS_LED_FUNC_ENABLE
XMC_LEDTS_NUMBER_LED_COLUMNS_t
XMC_LEDTS_NUMBER_LED_COLUMNS_1
XMC_LEDTS_NUMBER_LED_COLUMNS_2
XMC_LEDTS_NUMBER_LED_COLUMNS_3
XMC_LEDTS_NUMBER_LED_COLUMNS_4
XMC_LEDTS_NUMBER_LED_COLUMNS_5
XMC_LEDTS_NUMBER_LED_COLUMNS_6
XMC_LEDTS_NUMBER_LED_COLUMNS_7
XMC_LEDTS_NUMBER_LED_COLUMNS_8
XMC_LEDTS_NUMBER_TS_INPUT_t
XMC_LEDTS_NUMBER_TS_INPUT_1
XMC_LEDTS_NUMBER_TS_INPUT_2
XMC_LEDTS_NUMBER_TS_INPUT_3
XMC_LEDTS_NUMBER_TS_INPUT_4
XMC_LEDTS_NUMBER_TS_INPUT_5
XMC_LEDTS_NUMBER_TS_INPUT_6
XMC_LEDTS_NUMBER_TS_INPUT_7
XMC_LEDTS_NUMBER_TS_INPUT_8
XMC_LEDTS_PAD_TURN_SW_CONTROL_t
XMC_LEDTS_SW_CONTROL_DISABLE
XMC_LEDTS_SW_CONTROL_ENABLE
XMC_LEDTS_PAD_TURN_t
XMC_LEDTS_PAD_TURN_0
XMC_LEDTS_PAD_TURN_1
XMC_LEDTS_PAD_TURN_2
XMC_LEDTS_PAD_TURN_3
XMC_LEDTS_PAD_TURN_4
XMC_LEDTS_PAD_TURN_5
XMC_LEDTS_PAD_TURN_6
XMC_LEDTS_PAD_TURN_7
XMC_LEDTS_STATUS_t
XMC_LEDTS_STATUS_SUCCESS
XMC_LEDTS_STATUS_RUNNING
XMC_LEDTS_STATUS_ERROR
XMC_LEDTS_STATUS_IDLE
XMC_LEDTS_SUSPEND_t
XMC_LEDTS_SUSPEND_DISABLE
XMC_LEDTS_SUSPEND_ENABLE
XMC_LEDTS_TF_INTERRUPT_FLAG_t
XMC_LEDTS_TF_INTERRUPT_FLAG_INACTIVE
XMC_LEDTS_TF_INTERRUPT_FLAG_ACTIVE
XMC_LEDTS_TF_VALIDATION_t
XMC_LEDTS_TF_VALIDATION_DISABLE
XMC_LEDTS_TF_VALIDATION_ENABLE
XMC_LEDTS_TP_SYNC_t
XMC_LEDTS_TP_SYNC_DISABLE
XMC_LEDTS_TP_SYNC_ENABLE
XMC_LEDTS_TS_COUNTER_AUTO_RESET_t
XMC_LEDTS_TS_COUNTER_AUTO_RESET_DISABLE
XMC_LEDTS_TS_COUNTER_AUTO_RESET_ENABLE
XMC_LEDTS_TS_COUNTER_MASK_t
XMC_LEDTS_TS_COUNTER_MASK_1_LSB
XMC_LEDTS_TS_COUNTER_MASK_2_LSB
XMC_LEDTS_TS_COUNTER_MASK_3_LSB
XMC_LEDTS_TS_COUNTER_MASK_4_LSB
XMC_LEDTS_TS_COUNTER_MASK_5_LSB
XMC_LEDTS_TS_COUNTER_MASK_6_LSB
XMC_LEDTS_TS_COUNTER_MASK_7_LSB
XMC_LEDTS_TS_COUNTER_MASK_8_LSB
XMC_LEDTS_TS_COUNTER_OVERLOW_FLAG_t
XMC_LEDTS_TS_COUNTER_OVERLOW_FLAG_NO
XMC_LEDTS_TS_COUNTER_OVERLOW_FLAG_YES
XMC_LEDTS_TS_COUNTER_SATURATION_t
XMC_LEDTS_TS_COUNTER_SATURATION_DISABLE
XMC_LEDTS_TS_COUNTER_SATURATION_ENABLE
XMC_LEDTS_TS_FUNC_t
XMC_LEDTS_TS_FUNC_DISABLE
XMC_LEDTS_TS_FUNC_ENABLE
XMC_LEDTS_TS_INPUT_t
XMC_LEDTS_TS_INPUT_0
XMC_LEDTS_TS_INPUT_1
XMC_LEDTS_TS_INPUT_2
XMC_LEDTS_TS_INPUT_3
XMC_LEDTS_TS_INPUT_4
XMC_LEDTS_TS_INPUT_5
XMC_LEDTS_TS_INPUT_6
XMC_LEDTS_TS_INPUT_7
XMC_LEDTS_TS_INTERRUPT_FLAG_t
XMC_LEDTS_INTERRUPT_FLAG_TIMESLICE
XMC_LEDTS_INTERRUPT_FLAG_TIMEFRAME
XMC_LEDTS_INTERRUPT_FLAG_TIMEPERIOD
XMC_LEDTS_INTERRUPT_FLAG_TSCOUNTER_OVERFLOW
XMC_LEDTS_ClearInterruptFlag
XMC_LEDTS_DisableInterrupt
XMC_LEDTS_EnableInterrupt
XMC_LEDTS_InitGlobal
XMC_LEDTS_InitLED
XMC_LEDTS_InitTSAdvanced
XMC_LEDTS_InitTSBasic
XMC_LEDTS_ReadFNCOL
XMC_LEDTS_ReadInterruptFlag
XMC_LEDTS_ReadTSVAL
XMC_LEDTS_SetActivePADNo
XMC_LEDTS_SetColumnBrightness
XMC_LEDTS_SetCommonOscillationWindow
XMC_LEDTS_SetLEDLinePattern
XMC_LEDTS_SetNumOfLEDColumns
XMC_LEDTS_SetOscillationWindow
XMC_LEDTS_StartCounter
XMC_LEDTS_StopCounter
POSIF
XMC_POSIF_CONFIG_t
filter
input0
input1
input2
mode
XMC_POSIF_HSC_CONFIG_t
disable_idle_signal
external_error_enable
external_error_level
external_error_port
sampling_trigger
sampling_trigger_edge
XMC_POSIF_MCM_CONFIG_t
pattern_sw_update
pattern_trigger_edge
pattern_update_trigger
pwm_sync
XMC_POSIF_QD_CONFIG_t
index
mode
phase_a
phase_b
phase_leader
XMC_POSIF_t
XMC_POSIF_FILTER_t
XMC_POSIF_FILTER_DISABLED
XMC_POSIF_FILTER_1_CLOCK_CYCLE
XMC_POSIF_FILTER_2_CLOCK_CYCLE
XMC_POSIF_FILTER_4_CLOCK_CYCLE
XMC_POSIF_FILTER_8_CLOCK_CYCLE
XMC_POSIF_FILTER_16_CLOCK_CYCLE
XMC_POSIF_FILTER_32_CLOCK_CYCLE
XMC_POSIF_FILTER_64_CLOCK_CYCLE
XMC_POSIF_HSC_TRIGGER_EDGE_t
XMC_POSIF_HSC_TRIGGER_EDGE_RISING
XMC_POSIF_HSC_TRIGGER_EDGE_FALLING
XMC_POSIF_INPUT_ACTIVE_LEVEL_t
XMC_POSIF_INPUT_ACTIVE_LEVEL_HIGH
XMC_POSIF_INPUT_ACTIVE_LEVEL_LOW
XMC_POSIF_INPUT_PORT_t
XMC_POSIF_INPUT_PORT_A
XMC_POSIF_INPUT_PORT_B
XMC_POSIF_INPUT_PORT_C
XMC_POSIF_INPUT_PORT_D
XMC_POSIF_INPUT_PORT_E
XMC_POSIF_INPUT_PORT_F
XMC_POSIF_INPUT_PORT_G
XMC_POSIF_INPUT_PORT_H
XMC_POSIF_IRQ_EVENT_t
XMC_POSIF_IRQ_EVENT_CHE
XMC_POSIF_IRQ_EVENT_WHE
XMC_POSIF_IRQ_EVENT_HALL_INPUT
XMC_POSIF_IRQ_EVENT_MCP_SHADOW_TRANSFER
XMC_POSIF_IRQ_EVENT_INDX
XMC_POSIF_IRQ_EVENT_ERR
XMC_POSIF_IRQ_EVENT_CNT
XMC_POSIF_IRQ_EVENT_DIR
XMC_POSIF_IRQ_EVENT_PCLK
XMC_POSIF_MODE_t
XMC_POSIF_MODE_HALL_SENSOR
XMC_POSIF_MODE_QD
XMC_POSIF_MODE_MCM
XMC_POSIF_MODE_MCM_QD
XMC_POSIF_QD_DIR_t
XMC_POSIF_QD_DIR_COUNTERCLOCKWISE
XMC_POSIF_QD_DIR_CLOCKWISE
XMC_POSIF_QD_INDEX_GENERATION_t
XMC_POSIF_QD_INDEX_GENERATION_NEVER
XMC_POSIF_QD_INDEX_GENERATION_ONCE
XMC_POSIF_QD_INDEX_GENERATION_ALWAYS
XMC_POSIF_QD_MODE_t
XMC_POSIF_QD_MODE_QUADRATURE
XMC_POSIF_QD_MODE_DIRECTION_COUNT
XMC_POSIF_SR_ID_t
XMC_POSIF_SR_ID_0
XMC_POSIF_SR_ID_1
XMC_POSIF_STATUS_t
XMC_POSIF_STATUS_OK
XMC_POSIF_STATUS_ERROR
XMC_POSIF_ClearEvent
XMC_POSIF_Disable
XMC_POSIF_DisableEvent
XMC_POSIF_Enable
XMC_POSIF_EnableEvent
XMC_POSIF_GetEventStatus
XMC_POSIF_HSC_GetCurrentPattern
XMC_POSIF_HSC_GetExpectedPattern
XMC_POSIF_HSC_GetLastSampledPattern
XMC_POSIF_HSC_Init
XMC_POSIF_HSC_SetCurrentPattern
XMC_POSIF_HSC_SetExpectedPattern
XMC_POSIF_HSC_SetHallPatterns
XMC_POSIF_HSC_UpdateHallPattern
XMC_POSIF_Init
XMC_POSIF_IsRunning
XMC_POSIF_MCM_EnableMultiChannelPatternUpdate
XMC_POSIF_MCM_GetMultiChannelPattern
XMC_POSIF_MCM_GetShadowMultiChannelPattern
XMC_POSIF_MCM_Init
XMC_POSIF_MCM_SetMultiChannelPattern
XMC_POSIF_MCM_UpdateMultiChannelPattern
XMC_POSIF_QD_GetCurrentIndexValue
XMC_POSIF_QD_GetCurrentState
XMC_POSIF_QD_GetDirection
XMC_POSIF_QD_GetPreviousState
XMC_POSIF_QD_Init
XMC_POSIF_SelectInputSource
XMC_POSIF_SetEvent
XMC_POSIF_SetInterruptNode
XMC_POSIF_SetMode
XMC_POSIF_Start
XMC_POSIF_Stop
RTC
XMC_RTC_ALARM_t
days
hours
minutes
month
seconds
year
XMC_RTC_CONFIG_t
XMC_RTC_TIME_t
days
daysofweek
hours
minutes
month
seconds
year
XMC_RTC_EVENT_t
XMC_RTC_EVENT_PERIODIC_SECONDS
XMC_RTC_EVENT_PERIODIC_MINUTES
XMC_RTC_EVENT_PERIODIC_HOURS
XMC_RTC_EVENT_PERIODIC_DAYS
XMC_RTC_EVENT_PERIODIC_MONTHS
XMC_RTC_EVENT_PERIODIC_YEARS
XMC_RTC_EVENT_ALARM
XMC_RTC_MONTH_t
XMC_RTC_STATUS_t
XMC_RTC_STATUS_OK
XMC_RTC_STATUS_ERROR
XMC_RTC_STATUS_BUSY
XMC_RTC_WAKEUP_EVENT_t
XMC_RTC_WAKEUP_EVENT_ON_ALARM
XMC_RTC_WAKEUP_EVENT_ON_SECONDS
XMC_RTC_WAKEUP_EVENT_ON_MINUTES
XMC_RTC_WAKEUP_EVENT_ON_HOURS
XMC_RTC_WAKEUP_EVENT_ON_DAYS
XMC_RTC_WAKEUP_EVENT_ON_MONTHS
XMC_RTC_WAKEUP_EVENT_ON_YEARS
XMC_RTC_WEEKDAY_t
XMC_RTC_ClearEvent
XMC_RTC_Disable
XMC_RTC_DisableEvent
XMC_RTC_DisableHibernationWakeUp
XMC_RTC_Enable
XMC_RTC_EnableEvent
XMC_RTC_EnableHibernationWakeUp
XMC_RTC_GetAlarm
XMC_RTC_GetAlarmStdFormat
XMC_RTC_GetEventStatus
XMC_RTC_GetPrescaler
XMC_RTC_GetTime
XMC_RTC_GetTimeStdFormat
XMC_RTC_Init
XMC_RTC_IsEnabled
XMC_RTC_IsRunning
XMC_RTC_SetAlarm
XMC_RTC_SetAlarmStdFormat
XMC_RTC_SetPrescaler
XMC_RTC_SetTime
XMC_RTC_SetTimeStdFormat
XMC_RTC_Start
XMC_RTC_Stop
SCU
XMC_SCU_CLOCK_CONFIG_t
calibration_mode
enable_oschp
enable_osculp
fccu_clkdiv
fcpu_clkdiv
fperipheral_clkdiv
fstdby_clksrc
fsys_clkdiv
fsys_clksrc
syspll_config
XMC_SCU_CLOCK_SYSPLL_CONFIG_t
clksrc
k_div
mode
n_div
p_div
XMC_SCU_INTERRUPT_EVENT_DLR_OVERRUN
XMC_SCU_INTERRUPT_EVENT_HDCLR_UPDATED
XMC_SCU_INTERRUPT_EVENT_HDCR_UPDATED
XMC_SCU_INTERRUPT_EVENT_HDSET_UPDATED
XMC_SCU_INTERRUPT_EVENT_OSCSICTRL_UPDATED
XMC_SCU_INTERRUPT_EVENT_OSCULCTRL_UPDATED
XMC_SCU_INTERRUPT_EVENT_RMX_UPDATED
XMC_SCU_INTERRUPT_EVENT_RTC_ALARM
XMC_SCU_INTERRUPT_EVENT_RTC_PERIODIC
XMC_SCU_INTERRUPT_EVENT_RTCATIM0_UPDATED
XMC_SCU_INTERRUPT_EVENT_RTCATIM1_UPDATED
XMC_SCU_INTERRUPT_EVENT_RTCCTR_UPDATED
XMC_SCU_INTERRUPT_EVENT_RTCTIM0_UPDATED
XMC_SCU_INTERRUPT_EVENT_RTCTIM1_UPDATED
XMC_SCU_INTERRUPT_EVENT_WDT_WARN
XMC_SCU_INTERRUPT_EVENT_HANDLER_t
XMC_SCU_INTERRUPT_EVENT_t
XMC_SCU_BOOTMODE_t
XMC_SCU_BOOTMODE_NORMAL
XMC_SCU_BOOTMODE_ASC_BSL
XMC_SCU_BOOTMODE_BMI
XMC_SCU_BOOTMODE_CAN_BSL
XMC_SCU_BOOTMODE_PSRAM_BOOT
XMC_SCU_BOOTMODE_ABM0
XMC_SCU_BOOTMODE_ABM1
XMC_SCU_BOOTMODE_FABM
XMC_SCU_CCU_TRIGGER_t
XMC_SCU_CCU_TRIGGER_CCU40
XMC_SCU_CCU_TRIGGER_CCU80
XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_t
XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_SYSCLK_FOFI
XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_SYSCLK_FPLL
XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_FLASH_POWERDOWN
XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_PLL_POWERDOWN
XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_VCO_POWERDOWN
XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_DISABLE_USB
XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_ENABLE_USB
XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_DISABLE_SDMMC
XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_ENABLE_SDMMC
XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_DISABLE_ETH
XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_ENABLE_ETH
XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_DISABLE_EBU
XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_ENABLE_EBU
XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_DISABLE_CCU
XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_ENABLE_CCU
XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_DISABLE_WDT
XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_ENABLE_WDT
XMC_SCU_CLOCK_ECATCLKSRC_t
XMC_SCU_CLOCK_ECATCLKSRC_USBPLL
XMC_SCU_CLOCK_ECATCLKSRC_SYSPLL
XMC_SCU_CLOCK_EXTOUTCLKSRC_t
XMC_SCU_CLOCK_EXTOUTCLKSRC_SYS
XMC_SCU_CLOCK_EXTOUTCLKSRC_USB
XMC_SCU_CLOCK_EXTOUTCLKSRC_PLL
XMC_SCU_CLOCK_FOFI_CALIBRATION_MODE_t
XMC_SCU_CLOCK_FOFI_CALIBRATION_MODE_FACTORY
XMC_SCU_CLOCK_FOFI_CALIBRATION_MODE_AUTOMATIC
XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_t
XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_SYSCLK_FOFI
XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_SYSCLK_FPLL
XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_DISABLE_USB
XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_ENABLE_USB
XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_DISABLE_SDMMC
XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_ENABLE_SDMMC
XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_DISABLE_ETH
XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_ENABLE_ETH
XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_DISABLE_EBU
XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_ENABLE_EBU
XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_DISABLED_CCU
XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_ENABLE_CCU
XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_DISABLED_WDT
XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_ENABLE_WDT
XMC_SCU_CLOCK_SYSCLKSRC_t
XMC_SCU_CLOCK_SYSCLKSRC_OFI
XMC_SCU_CLOCK_SYSCLKSRC_PLL
XMC_SCU_CLOCK_SYSPLL_MODE_t
XMC_SCU_CLOCK_SYSPLL_MODE_DISABLED
XMC_SCU_CLOCK_SYSPLL_MODE_NORMAL
XMC_SCU_CLOCK_SYSPLL_MODE_PRESCALAR
XMC_SCU_CLOCK_SYSPLLCLKSRC_t
XMC_SCU_CLOCK_SYSPLLCLKSRC_OSCHP
XMC_SCU_CLOCK_SYSPLLCLKSRC_OFI
XMC_SCU_CLOCK_t
XMC_SCU_CLOCK_USB
XMC_SCU_CLOCK_MMC
XMC_SCU_CLOCK_ETH
XMC_SCU_CLOCK_EBU
XMC_SCU_CLOCK_CCU
XMC_SCU_CLOCK_WDT
XMC_SCU_CLOCK_USBCLKSRC_t
XMC_SCU_CLOCK_USBCLKSRC_USBPLL
XMC_SCU_CLOCK_USBCLKSRC_SYSPLL
XMC_SCU_CLOCK_WDTCLKSRC_t
XMC_SCU_CLOCK_WDTCLKSRC_OFI
XMC_SCU_CLOCK_WDTCLKSRC_STDBY
XMC_SCU_CLOCK_WDTCLKSRC_PLL
XMC_SCU_HIB_CTRL_STATUS_t
XMC_SCU_HIB_CTRL_STATUS_NO_ACTIVE
XMC_SCU_HIB_CTRL_STATUS_ACTIVE
XMC_SCU_HIB_EVENT_t
XMC_SCU_HIB_EVENT_WAKEUP_ON_POS_EDGE
XMC_SCU_HIB_EVENT_WAKEUP_ON_NEG_EDGE
XMC_SCU_HIB_EVENT_WAKEUP_ON_RTC
XMC_SCU_HIB_EVENT_ULPWDG
XMC_SCU_HIB_EVENT_LPAC_VBAT_POSEDGE
XMC_SCU_HIB_EVENT_LPAC_VBAT_NEGEDGE
XMC_SCU_HIB_EVENT_LPAC_HIB_IO_0_POSEDGE
XMC_SCU_HIB_EVENT_LPAC_HIB_IO_0_NEGEDGE
XMC_SCU_HIB_EVENT_LPAC_HIB_IO_1_POSEDGE
XMC_SCU_HIB_EVENT_LPAC_HIB_IO_1_NEGEDGE
XMC_SCU_HIB_HIBERNATE_MODE_t
XMC_SCU_HIB_HIBERNATE_MODE_EXTERNAL
XMC_SCU_HIB_HIBERNATE_MODE_INTERNAL
XMC_SCU_HIB_IO_OUTPUT_LEVEL_t
XMC_SCU_HIB_IO_OUTPUT_LEVEL_LOW
XMC_SCU_HIB_IO_OUTPUT_LEVEL_HIGH
XMC_SCU_HIB_IO_t
XMC_SCU_HIB_IO_0
XMC_SCU_HIB_IO_1
XMC_SCU_HIB_LPAC_INPUT_t
XMC_SCU_HIB_LPAC_INPUT_DISABLED
XMC_SCU_HIB_LPAC_INPUT_VBAT
XMC_SCU_HIB_LPAC_INPUT_HIB_IO_0
XMC_SCU_HIB_LPAC_INPUT_HIB_IO_1
XMC_SCU_HIB_LPAC_STATUS_t
XMC_SCU_HIB_LPAC_STATUS_VBAT_COMPARE_DONE
XMC_SCU_HIB_LPAC_STATUS_HIB_IO_0_COMPARE_DONE
XMC_SCU_HIB_LPAC_STATUS_HIB_IO_1_COMPARE_DONE
XMC_SCU_HIB_LPAC_STATUS_VBAT_ABOVE_THRESHOLD
XMC_SCU_HIB_LPAC_STATUS_HIB_IO_0_ABOVE_THRESHOLD
XMC_SCU_HIB_LPAC_STATUS_HIB_IO_1_ABOVE_THRESHOLD
XMC_SCU_HIB_LPAC_TRIGGER_t
XMC_SCU_HIB_LPAC_TRIGGER_SUBSECOND_INTERVAL_COUNTER
XMC_SCU_HIB_LPAC_TRIGGER_RTC_ALARM_EVENT
XMC_SCU_HIB_LPAC_TRIGGER_RTC_PERIODIC_EVENT
XMC_SCU_HIB_LPAC_TRIGGER_ON_WAKEUP_POSITIVE_EDGE_EVENT
XMC_SCU_HIB_LPAC_TRIGGER_ON_WAKEUP_NEGATIVE_EDGE_EVENT
XMC_SCU_HIB_LPAC_TRIGGER_CONTINOUS
XMC_SCU_HIB_LPAC_TRIGGER_SINGLE_SHOT
XMC_SCU_HIB_PIN_MODE_t
XMC_SCU_HIB_PIN_MODE_INPUT_PULL_NONE
XMC_SCU_HIB_PIN_MODE_INPUT_PULL_DOWN
XMC_SCU_HIB_PIN_MODE_INPUT_PULL_UP
XMC_SCU_HIB_PIN_MODE_OUTPUT_PUSH_PULL_HIBCTRL
XMC_SCU_HIB_PIN_MODE_OUTPUT_PUSH_PULL_WDTSRV
XMC_SCU_HIB_PIN_MODE_OUTPUT_PUSH_PULL_GPIO
XMC_SCU_HIB_PIN_MODE_OUTPUT_OPEN_DRAIN_HIBCTRL
XMC_SCU_HIB_PIN_MODE_OUTPUT_OPEN_DRAIN_WDTSRV
XMC_SCU_HIB_PIN_MODE_OUTPUT_OPEN_DRAIN_GPIO
XMC_SCU_HIB_RTCCLKSRC_t
XMC_SCU_HIB_RTCCLKSRC_OSI
XMC_SCU_HIB_RTCCLKSRC_ULP
XMC_SCU_HIB_SR0_INPUT_t
XMC_SCU_HIB_SR0_INPUT_HIB_IO_0
XMC_SCU_HIB_SR0_INPUT_HIB_IO_1
XMC_SCU_HIB_SR0_INPUT_ACMP0
XMC_SCU_HIB_STDBYCLKSRC_t
XMC_SCU_HIB_STDBYCLKSRC_OSI
XMC_SCU_HIB_STDBYCLKSRC_OSCULP
XMC_SCU_NMIREQ_t
XMC_SCU_NMIREQ_WDT_WARN
XMC_SCU_NMIREQ_RTC_PI
XMC_SCU_NMIREQ_RTC_AI
XMC_SCU_NMIREQ_ERU0_0
XMC_SCU_NMIREQ_ERU0_1
XMC_SCU_NMIREQ_ERU0_2
XMC_SCU_NMIREQ_ERU0_3
XMC_SCU_PARITY_t
XMC_SCU_PARITY_PSRAM_MEM
XMC_SCU_PARITY_DSRAM1_MEM
XMC_SCU_PARITY_USIC0_MEM
XMC_SCU_PARITY_MCAN_MEM
XMC_SCU_PARITY_PMU_MEM
XMC_SCU_PARITY_USB_MEM
XMC_SCU_PERIPHERAL_CLOCK_t
XMC_SCU_PERIPHERAL_CLOCK_VADC
XMC_SCU_PERIPHERAL_CLOCK_DSD
XMC_SCU_PERIPHERAL_CLOCK_CCU40
XMC_SCU_PERIPHERAL_CLOCK_CCU80
XMC_SCU_PERIPHERAL_CLOCK_POSIF0
XMC_SCU_PERIPHERAL_CLOCK_USIC0
XMC_SCU_PERIPHERAL_CLOCK_ERU1
XMC_SCU_PERIPHERAL_CLOCK_HRPWM0
XMC_SCU_PERIPHERAL_CLOCK_LEDTS0
XMC_SCU_PERIPHERAL_CLOCK_MCAN
XMC_SCU_PERIPHERAL_CLOCK_DAC
XMC_SCU_PERIPHERAL_CLOCK_SDMMC
XMC_SCU_PERIPHERAL_CLOCK_USIC1
XMC_SCU_PERIPHERAL_CLOCK_USIC2
XMC_SCU_PERIPHERAL_CLOCK_PORTS
XMC_SCU_PERIPHERAL_CLOCK_WDT
XMC_SCU_PERIPHERAL_CLOCK_ETH0
XMC_SCU_PERIPHERAL_CLOCK_GPDMA0
XMC_SCU_PERIPHERAL_CLOCK_GPDMA1
XMC_SCU_PERIPHERAL_CLOCK_FCE
XMC_SCU_PERIPHERAL_CLOCK_USB0
XMC_SCU_PERIPHERAL_CLOCK_ECAT0
XMC_SCU_PERIPHERAL_CLOCK_EBU
XMC_SCU_PERIPHERAL_RESET_t
XMC_SCU_PERIPHERAL_RESET_VADC
XMC_SCU_PERIPHERAL_RESET_DSD
XMC_SCU_PERIPHERAL_RESET_CCU40
XMC_SCU_PERIPHERAL_RESET_CCU80
XMC_SCU_PERIPHERAL_RESET_POSIF0
XMC_SCU_PERIPHERAL_RESET_USIC0
XMC_SCU_PERIPHERAL_RESET_ERU1
XMC_SCU_PERIPHERAL_RESET_HRPWM0
XMC_SCU_PERIPHERAL_RESET_LEDTS0
XMC_SCU_PERIPHERAL_RESET_MCAN
XMC_SCU_PERIPHERAL_RESET_DAC
XMC_SCU_PERIPHERAL_RESET_SDMMC
XMC_SCU_PERIPHERAL_RESET_USIC1
XMC_SCU_PERIPHERAL_RESET_USIC2
XMC_SCU_PERIPHERAL_RESET_PORTS
XMC_SCU_PERIPHERAL_RESET_WDT
XMC_SCU_PERIPHERAL_RESET_ETH0
XMC_SCU_PERIPHERAL_RESET_GPDMA0
XMC_SCU_PERIPHERAL_RESET_GPDMA1
XMC_SCU_PERIPHERAL_RESET_FCE
XMC_SCU_PERIPHERAL_RESET_USB0
XMC_SCU_PERIPHERAL_RESET_ECAT0
XMC_SCU_PERIPHERAL_RESET_EBU
XMC_SCU_POWER_EVR_STATUS_t
XMC_SCU_POWER_EVR_STATUS_OK
XMC_SCU_POWER_EVR_STATUS_EVR13_OVERVOLTAGE
XMC_SCU_POWER_MODE_t
XMC_SCU_POWER_MODE_SLEEP
XMC_SCU_POWER_MODE_DEEPSLEEP
XMC_SCU_RESET_REASON_t
XMC_SCU_RESET_REASON_PORST
XMC_SCU_RESET_REASON_SWD
XMC_SCU_RESET_REASON_PV
XMC_SCU_RESET_REASON_SW
XMC_SCU_RESET_REASON_LOCKUP
XMC_SCU_RESET_REASON_WATCHDOG
XMC_SCU_RESET_REASON_PARITY_ERROR
XMC_SCU_STATUS_t
XMC_SCU_STATUS_OK
XMC_SCU_STATUS_ERROR
XMC_SCU_STATUS_BUSY
XMC_SCU_TRAP_t
XMC_SCU_TRAP_OSC_WDG
XMC_SCU_TRAP_VCO_LOCK
XMC_SCU_TRAP_USB_VCO_LOCK
XMC_SCU_TRAP_PARITY_ERROR
XMC_SCU_TRAP_BROWNOUT
XMC_SCU_TRAP_ULP_WDG
XMC_SCU_TRAP_PER_BRIDGE0
XMC_SCU_TRAP_PER_BRIDGE1
XMC_SCU_TRAP_ECAT_RESET
XMC_SCU_CalibrateTemperatureSensor
XMC_SCU_CLOCK_DisableClock
XMC_SCU_CLOCK_DisableHighPerformanceOscillator
XMC_SCU_CLOCK_DisableHighPerformanceOscillatorGeneralPurposeInput
XMC_SCU_CLOCK_DisableLowPowerOscillator
XMC_SCU_CLOCK_DisableLowPowerOscillatorGeneralPurposeInput
XMC_SCU_CLOCK_DisableSystemPll
XMC_SCU_CLOCK_DisableUsbPll
XMC_SCU_CLOCK_EnableClock
XMC_SCU_CLOCK_EnableHighPerformanceOscillator
XMC_SCU_CLOCK_EnableHighPerformanceOscillatorGeneralPurposeInput
XMC_SCU_CLOCK_EnableLowPowerOscillator
XMC_SCU_CLOCK_EnableLowPowerOscillatorGeneralPurposeInput
XMC_SCU_CLOCK_EnableSystemPll
XMC_SCU_CLOCK_EnableUsbPll
XMC_SCU_CLOCK_GatePeripheralClock
XMC_SCU_CLOCK_GetCcuClockDivider
XMC_SCU_CLOCK_GetCcuClockFrequency
XMC_SCU_CLOCK_GetCpuClockDivider
XMC_SCU_CLOCK_GetCpuClockFrequency
XMC_SCU_CLOCK_GetEbuClockDivider
XMC_SCU_CLOCK_GetEbuClockFrequency
XMC_SCU_CLOCK_GetECATClockDivider
XMC_SCU_CLOCK_GetECATClockSource
XMC_SCU_CLOCK_GetEthernetClockFrequency
XMC_SCU_CLOCK_GetExternalOutputClockDivider
XMC_SCU_CLOCK_GetExternalOutputClockFrequency
XMC_SCU_CLOCK_GetExternalOutputClockSource
XMC_SCU_CLOCK_GetHighPerformanceOscillatorGeneralPurposeInputStatus
XMC_SCU_CLOCK_GetLowPowerOscillatorGeneralPurposeInputStatus
XMC_SCU_CLOCK_GetPeripheralClockDivider
XMC_SCU_CLOCK_GetPeripheralClockFrequency
XMC_SCU_CLOCK_GetSystemClockDivider
XMC_SCU_CLOCK_GetSystemClockFrequency
XMC_SCU_CLOCK_GetSystemClockSource
XMC_SCU_CLOCK_GetSystemPllClockFrequency
XMC_SCU_CLOCK_GetSystemPllClockSource
XMC_SCU_CLOCK_GetSystemPllClockSourceFrequency
XMC_SCU_CLOCK_GetUsbClockDivider
XMC_SCU_CLOCK_GetUsbClockFrequency
XMC_SCU_CLOCK_GetUsbClockSource
XMC_SCU_CLOCK_GetUsbPllClockFrequency
XMC_SCU_CLOCK_GetWdtClockDivider
XMC_SCU_CLOCK_GetWdtClockFrequency
XMC_SCU_CLOCK_GetWdtClockSource
XMC_SCU_CLOCK_Init
XMC_SCU_CLOCK_IsClockEnabled
XMC_SCU_CLOCK_IsHighPerformanceOscillatorStable
XMC_SCU_CLOCK_IsLowPowerOscillatorStable
XMC_SCU_CLOCK_IsPeripheralClockGated
XMC_SCU_CLOCK_IsSystemPllLocked
XMC_SCU_CLOCK_IsUsbPllLocked
XMC_SCU_CLOCK_SetBackupClockCalibrationMode
XMC_SCU_CLOCK_SetCcuClockDivider
XMC_SCU_CLOCK_SetCpuClockDivider
XMC_SCU_CLOCK_SetDeepSleepConfig
XMC_SCU_CLOCK_SetEbuClockDivider
XMC_SCU_CLOCK_SetECATClockDivider
XMC_SCU_CLOCK_SetECATClockSource
XMC_SCU_CLOCK_SetExternalOutputClockDivider
XMC_SCU_CLOCK_SetExternalOutputClockSource
XMC_SCU_CLOCK_SetPeripheralClockDivider
XMC_SCU_CLOCK_SetSleepConfig
XMC_SCU_CLOCK_SetSystemClockDivider
XMC_SCU_CLOCK_SetSystemClockSource
XMC_SCU_CLOCK_SetSystemPllClockSource
XMC_SCU_CLOCK_SetUsbClockDivider
XMC_SCU_CLOCK_SetUsbClockSource
XMC_SCU_CLOCK_SetWdtClockDivider
XMC_SCU_CLOCK_SetWdtClockSource
XMC_SCU_CLOCK_StartSystemPll
XMC_SCU_CLOCK_StartUsbPll
XMC_SCU_CLOCK_StepSystemPllFrequency
XMC_SCU_CLOCK_StopSystemPll
XMC_SCU_CLOCK_StopUsbPll
XMC_SCU_CLOCK_UngatePeripheralClock
XMC_SCU_DisableOutOfRangeComparator
XMC_SCU_DisableTemperatureSensor
XMC_SCU_EnableOutOfRangeComparator
XMC_SCU_EnableTemperatureSensor
XMC_SCU_GetBootMode
XMC_SCU_GetMirrorStatus
XMC_SCU_GetTemperatureMeasurement
XMC_SCU_HIB_ClearEventStatus
XMC_SCU_HIB_ClearWakeupEventDetectionStatus
XMC_SCU_HIB_DisableEvent
XMC_SCU_HIB_DisableHibernateDomain
XMC_SCU_HIB_DisableInternalSlowClock
XMC_SCU_HIB_EnableEvent
XMC_SCU_HIB_EnableHibernateDomain
XMC_SCU_HIB_EnableInternalSlowClock
XMC_SCU_HIB_EnterHibernateState
XMC_SCU_HIB_EnterHibernateStateEx
XMC_SCU_HIB_GetEventStatus
XMC_SCU_HIB_GetHibernateControlStatus
XMC_SCU_HIB_GetRtcClockSource
XMC_SCU_HIB_GetStdbyClockSource
XMC_SCU_HIB_IsHibernateDomainEnabled
XMC_SCU_HIB_IsWakeupEventDetected
XMC_SCU_HIB_LPAC_ClearStatus
XMC_SCU_HIB_LPAC_GetStatus
XMC_SCU_HIB_LPAC_SetHIBIO0Thresholds
XMC_SCU_HIB_LPAC_SetHIBIO1Thresholds
XMC_SCU_HIB_LPAC_SetInput
XMC_SCU_HIB_LPAC_SetTiming
XMC_SCU_HIB_LPAC_SetTrigger
XMC_SCU_HIB_LPAC_SetVBATThresholds
XMC_SCU_HIB_LPAC_TriggerCompare
XMC_SCU_HIB_SetInput0
XMC_SCU_HIB_SetPinMode
XMC_SCU_HIB_SetPinOutputLevel
XMC_SCU_HIB_SetRtcClockSource
XMC_SCU_HIB_SetSR0Input
XMC_SCU_HIB_SetStandbyClockSource
XMC_SCU_HIB_SetWakeupTriggerInput
XMC_SCU_HIB_TriggerEvent
XMC_SCU_HighTemperature
XMC_SCU_INTERRUPT_ClearEventStatus
XMC_SCU_INTERRUPT_DisableEvent
XMC_SCU_INTERRUPT_DisableNmiRequest
XMC_SCU_INTERRUPT_EnableEvent
XMC_SCU_INTERRUPT_EnableNmiRequest
XMC_SCU_INTERRUPT_SetEventHandler
XMC_SCU_INTERRUPT_TriggerEvent
XMC_SCU_INTERUPT_GetEventStatus
XMC_SCU_IRQHandler
XMC_SCU_IsTemperatureSensorBusy
XMC_SCU_IsTemperatureSensorEnabled
XMC_SCU_IsTemperatureSensorReady
XMC_SCU_LowTemperature
XMC_SCU_PARITY_ClearStatus
XMC_SCU_PARITY_Disable
XMC_SCU_PARITY_DisableTrapGeneration
XMC_SCU_PARITY_Enable
XMC_SCU_PARITY_EnableTrapGeneration
XMC_SCU_PARITY_GetStatus
XMC_SCU_POWER_DisableMonitor
XMC_SCU_POWER_DisableUsb
XMC_SCU_POWER_EnableMonitor
XMC_SCU_POWER_EnableUsb
XMC_SCU_POWER_GetEVR13Voltage
XMC_SCU_POWER_GetEVR33Voltage
XMC_SCU_POWER_GetEVRStatus
XMC_SCU_POWER_WaitForEvent
XMC_SCU_POWER_WaitForInterrupt
XMC_SCU_ReadFromRetentionMemory
XMC_SCU_ReadGPR
XMC_SCU_RESET_AssertPeripheralReset
XMC_SCU_RESET_ClearDeviceResetReason
XMC_SCU_RESET_DeassertPeripheralReset
XMC_SCU_RESET_GetDeviceResetReason
XMC_SCU_RESET_IsPeripheralResetAsserted
XMC_SCU_SetBootMode
XMC_SCU_SetCcuTriggerHigh
XMC_SCU_SetCcuTriggerLow
XMC_SCU_SetRawTempLimits
XMC_SCU_StartTemperatureMeasurement
XMC_SCU_TRAP_ClearStatus
XMC_SCU_TRAP_Disable
XMC_SCU_TRAP_Enable
XMC_SCU_TRAP_GetStatus
XMC_SCU_TRAP_Trigger
XMC_SCU_WriteGPR
XMC_SCU_WriteToRetentionMemory
SDMMC
XMC_SDMMC_COMMAND_t
cmd_index
cmd_type
crc_check_en
dat_present_sel
index_check_en
response_type_sel
XMC_SDMMC_CONFIG_t
bus_width
clock_divider
XMC_SDMMC_PRESENT_STATE_t
buffer_read_enable
buffer_write_enable
card_detect_pin_level
card_inserted
card_state_stable
cmd_line_level
command_inihibit_cmd
command_inihibit_dat
dat7_4_pin_level
dat_3_0_pin_level
dat_line_active
read_transfer_active
write_protect_pin_level
write_transfer_active
XMC_SDMMC_RESPONSE_t
XMC_SDMMC_t
XMC_SDMMC_TRANSFER_MODE_t
XMC_SDMMC
XMC_SDMMC_ACMD_ERR_t
XMC_SDMMC_ACMD12_NOT_EXEC_ERR
XMC_SDMMC_ACMD_TIMEOUT_ERR
XMC_SDMMC_ACMD_CRC_ERR
XMC_SDMMC_ACMD_END_BIT_ERR
XMC_SDMMC_ACMD_IND_ERR
XMC_SDMMC_CMD_NOT_ISSUED_BY_ACMD12_ERR
XMC_SDMMC_BUS_VOLTAGE_t
XMC_SDMMC_CD_SOURCE_t
XMC_SDMMC_CD_STATUS_t
XMC_SDMMC_COMMAND_RESPONSE_t
XMC_SDMMC_COMMAND_RESPONSE_NONE
XMC_SDMMC_COMMAND_RESPONSE_LONG
XMC_SDMMC_COMMAND_RESPONSE_SHORT
XMC_SDMMC_COMMAND_RESPONSE_SHORT_BUSY
XMC_SDMMC_COMMAND_TYPE_t
XMC_SDMMC_COMMAND_TYPE_NORMAL
XMC_SDMMC_COMMAND_TYPE_SUSPEND
XMC_SDMMC_COMMAND_TYPE_RESUME
XMC_SDMMC_COMMAND_TYPE_ABORT
XMC_SDMMC_DAT_TIMEOUT_COUNTER_t
XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_14
XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_15
XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_16
XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_17
XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_18
XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_19
XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_20
XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_21
XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_22
XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_23
XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_24
XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_25
XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_26
XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_27
XMC_SDMMC_DATA_LINES_t
XMC_SDMMC_DATA_LINES_1
XMC_SDMMC_DATA_LINES_4
XMC_SDMMC_DATA_LINES_8
XMC_SDMMC_DATA_TRANSFER_DIR_t
XMC_SDMMC_DATA_TRANSFER_CARD_TO_HOST
XMC_SDMMC_EVENT_t
XMC_SDMMC_CMD_COMPLETE
XMC_SDMMC_TX_COMPLETE
XMC_SDMMC_BLOCK_GAP_EVENT
XMC_SDMMC_BUFFER_WRITE_READY
XMC_SDMMC_BUFFER_READ_READY
XMC_SDMMC_CARD_INS
XMC_SDMMC_CARD_REMOVAL
XMC_SDMMC_CARD_INT
XMC_SDMMC_CARD_ERR
XMC_SDMMC_CMD_TIMEOUT_ERR
XMC_SDMMC_CMD_CRC_ERR
XMC_SDMMC_CMD_END_BIT_ERR
XMC_SDMMC_CMD_IND_ERR
XMC_SDMMC_DATA_TIMEOUT_ERR
XMC_SDMMC_DATA_CRC_ERR
XMC_SDMMC_DATA_END_BIT_ERR
XMC_SDMMC_CURRENT_LIMIT_ERR
XMC_SDMMC_ACMD_ERR
XMC_SDMMC_TARGET_RESP_ERR
XMC_SDMMC_RESPONSE_TYPE_t
XMC_SDMMC_RESPONSE_TYPE_NO_RESPONSE
XMC_SDMMC_RESPONSE_TYPE_R1
XMC_SDMMC_RESPONSE_TYPE_R1b
XMC_SDMMC_RESPONSE_TYPE_R2
XMC_SDMMC_RESPONSE_TYPE_R3
XMC_SDMMC_RESPONSE_TYPE_R6
XMC_SDMMC_RESPONSE_TYPE_R7
XMC_SDMMC_SDCLK_FREQ_SEL_t
XMC_SDMMC_CLK_DIV_1
XMC_SDMMC_CLK_DIV_2
XMC_SDMMC_CLK_DIV_4
XMC_SDMMC_CLK_DIV_8
XMC_SDMMC_CLK_DIV_16
XMC_SDMMC_CLK_DIV_32
XMC_SDMMC_CLK_DIV_64
XMC_SDMMC_CLK_DIV_128
XMC_SDMMC_CLK_DIV_256
XMC_SDMMC_STATUS_t
XMC_SDMMC_STATUS_SUCCESS
XMC_SDMMC_STATUS_CMD_LINE_BUSY
XMC_SDMMC_STATUS_DAT_LINE_BUSY
XMC_SDMMC_SW_RESET_t
XMC_SDMMC_SW_RESET_ALL
XMC_SDMMC_SW_RST_CMD_LINE
XMC_SDMMC_SW_RST_DAT_LINE
XMC_SDMMC_TRANSFER_MODE_AUTO_CMD_t
XMC_SDMMC_TRANSFER_MODE_AUTO_CMD_DISABLED
XMC_SDMMC_TRANSFER_MODE_AUTO_CMD_12
XMC_SDMMC_TRANSFER_MODE_TYPE_t
XMC_SDMMC_TRANSFER_MODE_TYPE_SINGLE
XMC_SDMMC_TRANSFER_MODE_TYPE_INFINITE
XMC_SDMMC_TRANSFER_MODE_TYPE_MULTIPLE
XMC_SDMMC_TRANSFER_MODE_TYPE_STOP_MULTIPLE
XMC_SDMMC_WAKEUP_EVENT_t
XMC_SDMMC_WAKEUP_EN_CARD_INT
XMC_SDMMC_WAKEUP_EN_CARD_INS
XMC_SDMMC_WAKEUP_EN_CARD_REM
XMC_SDMMC_BusPowerOff
XMC_SDMMC_BusPowerOn
XMC_SDMMC_ClearEvent
XMC_SDMMC_Disable
XMC_SDMMC_DisableDelayCmdDatLines
XMC_SDMMC_DisableEvent
XMC_SDMMC_DisableEventStatus
XMC_SDMMC_DisableHighSpeed
XMC_SDMMC_DisableInterruptAtBlockGap
XMC_SDMMC_DisableWakeupEvent
XMC_SDMMC_Enable
XMC_SDMMC_EnableDelayCmdDatLines
XMC_SDMMC_EnableEvent
XMC_SDMMC_EnableEventStatus
XMC_SDMMC_EnableHighSpeed
XMC_SDMMC_EnableInterruptAtBlockGap
XMC_SDMMC_EnableWakeupEvent
XMC_SDMMC_GetACMDErrStatus
XMC_SDMMC_GetAutoCommandResponse
XMC_SDMMC_GetClockStability
XMC_SDMMC_GetCommandResponse
XMC_SDMMC_GetContinueRequest
XMC_SDMMC_GetEvent
XMC_SDMMC_GetPowerStatus
XMC_SDMMC_GetPresentState
XMC_SDMMC_GetR2Response
XMC_SDMMC_GetSWResetStatus
XMC_SDMMC_GetTransferBlocksNum
XMC_SDMMC_Init
XMC_SDMMC_IsAllDataLinesHigh
XMC_SDMMC_IsAnyErrorEvent
XMC_SDMMC_IsCommandLineBusy
XMC_SDMMC_IsDataLineBusy
XMC_SDMMC_ReadFIFO
XMC_SDMMC_SDClockDisable
XMC_SDMMC_SDClockEnable
XMC_SDMMC_SDClockFreqSelect
XMC_SDMMC_SendCommand
XMC_SDMMC_SetBusVoltage
XMC_SDMMC_SetCardDetectionSource
XMC_SDMMC_SetCardDetectionStatus
XMC_SDMMC_SetContinueRequest
XMC_SDMMC_SetDataLineTimeout
XMC_SDMMC_SetDataTransferDirection
XMC_SDMMC_SetDataTransferMode
XMC_SDMMC_SetDataTransferWidth
XMC_SDMMC_SetDelay
XMC_SDMMC_SetReadWaitControl
XMC_SDMMC_SetStopAtBlockGap
XMC_SDMMC_SetSWReset
XMC_SDMMC_Start
XMC_SDMMC_Stop
XMC_SDMMC_TriggerACMDErr
XMC_SDMMC_TriggerEvent
XMC_SDMMC_WriteFIFO
SPI
XMC_SPI_CH_CONFIG_t
baudrate
bus_mode
parity_mode
selo_inversion
XMC_SPI0_CH0
XMC_SPI0_CH1
XMC_SPI1_CH0
XMC_SPI1_CH1
XMC_SPI2_CH0
XMC_SPI2_CH1
XMC_SPI_CH_BRG_SHIFT_CLOCK_OUTPUT_t
XMC_SPI_CH_BRG_SHIFT_CLOCK_OUTPUT_SCLK
XMC_SPI_CH_BRG_SHIFT_CLOCK_OUTPUT_DX1
XMC_SPI_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_t
XMC_SPI_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_0_DELAY_DISABLED
XMC_SPI_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_1_DELAY_DISABLED
XMC_SPI_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_0_DELAY_ENABLED
XMC_SPI_CH_BUS_MODE_t
XMC_SPI_CH_BUS_MODE_MASTER
XMC_SPI_CH_BUS_MODE_SLAVE
XMC_SPI_CH_DATA_POLARITY_t
XMC_SPI_CH_DATA_POLARITY_DIRECT
XMC_SPI_CH_DATA_POLARITY_INVERT
XMC_SPI_CH_EVENT_t
XMC_SPI_CH_EVENT_RECEIVE_START
XMC_SPI_CH_EVENT_DATA_LOST
XMC_SPI_CH_EVENT_TRANSMIT_SHIFT
XMC_SPI_CH_EVENT_TRANSMIT_BUFFER
XMC_SPI_CH_EVENT_STANDARD_RECEIVE
XMC_SPI_CH_EVENT_ALTERNATIVE_RECEIVE
XMC_SPI_CH_EVENT_BAUD_RATE_GENERATOR
XMC_SPI_CH_EVENT_PARITY_ERROR
XMC_SPI_CH_EVENT_MSLS_CHANGE
XMC_SPI_CH_EVENT_DX2TIEN_ACTIVATED
XMC_SPI_CH_INPUT_FREQ_SLAVE_SELECT_DELAY_t
XMC_SPI_CH_INPUT_FREQ_SLAVE_SELECT_DELAY_FPDIV
XMC_SPI_CH_INPUT_FREQ_SLAVE_SELECT_DELAY_FPPP
XMC_SPI_CH_INPUT_FREQ_SLAVE_SELECT_DELAY_FSCLK
XMC_SPI_CH_INPUT_FREQ_SLAVE_SELECT_DELAY_FMCLK
XMC_SPI_CH_INPUT_t
XMC_SPI_CH_INPUT_DIN0
XMC_SPI_CH_INPUT_SLAVE_SCLKIN
XMC_SPI_CH_INPUT_SLAVE_SELIN
XMC_SPI_CH_INPUT_DIN1
XMC_SPI_CH_INPUT_DIN2
XMC_SPI_CH_INPUT_DIN3
XMC_SPI_CH_INTERRUPT_NODE_POINTER_t
XMC_SPI_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT
XMC_SPI_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER
XMC_SPI_CH_INTERRUPT_NODE_POINTER_RECEIVE
XMC_SPI_CH_INTERRUPT_NODE_POINTER_ALTERNATE_RECEIVE
XMC_SPI_CH_INTERRUPT_NODE_POINTER_PROTOCOL
XMC_SPI_CH_MODE_t
XMC_SPI_CH_MODE_STANDARD
XMC_SPI_CH_MODE_STANDARD_HALFDUPLEX
XMC_SPI_CH_MODE_DUAL
XMC_SPI_CH_MODE_QUAD
XMC_SPI_CH_SLAVE_SEL_MSLS_INV_t
XMC_SPI_CH_SLAVE_SEL_SAME_AS_MSLS
XMC_SPI_CH_SLAVE_SEL_INV_TO_MSLS
XMC_SPI_CH_SLAVE_SELECT_t
XMC_SPI_CH_SLAVE_SELECT_0
XMC_SPI_CH_SLAVE_SELECT_1
XMC_SPI_CH_SLAVE_SELECT_2
XMC_SPI_CH_SLAVE_SELECT_3
XMC_SPI_CH_SLAVE_SELECT_4
XMC_SPI_CH_SLAVE_SELECT_5
XMC_SPI_CH_SLAVE_SELECT_6
XMC_SPI_CH_SLAVE_SELECT_7
XMC_SPI_CH_STATUS_FLAG_t
XMC_SPI_CH_STATUS_FLAG_MSLS
XMC_SPI_CH_STATUS_FLAG_DX2S
XMC_SPI_CH_STATUS_FLAG_MSLS_EVENT_DETECTED
XMC_SPI_CH_STATUS_FLAG_DX2T_EVENT_DETECTED
XMC_SPI_CH_STATUS_FLAG_PARITY_ERROR_EVENT_DETECTED
XMC_SPI_CH_STATUS_FLAG_RECEIVER_START_INDICATION
XMC_SPI_CH_STATUS_FLAG_DATA_LOST_INDICATION
XMC_SPI_CH_STATUS_FLAG_TRANSMIT_SHIFT_INDICATION
XMC_SPI_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION
XMC_SPI_CH_STATUS_FLAG_RECEIVE_INDICATION
XMC_SPI_CH_STATUS_FLAG_ALTERNATIVE_RECEIVE_INDICATION
XMC_SPI_CH_STATUS_FLAG_BAUD_RATE_GENERATOR_INDICATION
XMC_SPI_CH_STATUS_t
XMC_SPI_CH_STATUS_OK
XMC_SPI_CH_STATUS_ERROR
XMC_SPI_CH_STATUS_BUSY
XMC_SPI_CH_ClearStatusFlag
XMC_SPI_CH_ConfigExternalInputSignalToBRG
XMC_SPI_CH_ConfigureShiftClockOutput
XMC_SPI_CH_DisableDataTransmission
XMC_SPI_CH_DisableDelayCompensation
XMC_SPI_CH_DisableEOF
XMC_SPI_CH_DisableEvent
XMC_SPI_CH_DisableFEM
XMC_SPI_CH_DisableInputInversion
XMC_SPI_CH_DisableInterwordDelay
XMC_SPI_CH_DisableMasterClock
XMC_SPI_CH_DisableSlaveSelect
XMC_SPI_CH_DisableSlaveSelectCodedMode
XMC_SPI_CH_DisableSOF
XMC_SPI_CH_EnableDataTransmission
XMC_SPI_CH_EnableDelayCompensation
XMC_SPI_CH_EnableEOF
XMC_SPI_CH_EnableEvent
XMC_SPI_CH_EnableFEM
XMC_SPI_CH_EnableInputInversion
XMC_SPI_CH_EnableInterwordDelay
XMC_SPI_CH_EnableMasterClock
XMC_SPI_CH_EnableSlaveSelect
XMC_SPI_CH_EnableSlaveSelectCodedMode
XMC_SPI_CH_EnableSOF
XMC_SPI_CH_GetReceivedData
XMC_SPI_CH_GetStatusFlag
XMC_SPI_CH_Init
XMC_SPI_CH_Receive
XMC_SPI_CH_SelectInterruptNodePointer
XMC_SPI_CH_SetBaudrate
XMC_SPI_CH_SetBitOrderLsbFirst
XMC_SPI_CH_SetBitOrderMsbFirst
XMC_SPI_CH_SetFrameLength
XMC_SPI_CH_SetInputSource
XMC_SPI_CH_SetInterruptNodePointer
XMC_SPI_CH_SetInterwordDelay
XMC_SPI_CH_SetInterwordDelaySCLK
XMC_SPI_CH_SetSlaveSelectDelay
XMC_SPI_CH_SetSlaveSelectPolarity
XMC_SPI_CH_SetTransmitMode
XMC_SPI_CH_SetWordLength
XMC_SPI_CH_Start
XMC_SPI_CH_Stop
XMC_SPI_CH_Transmit
XMC_SPI_CH_TriggerServiceRequest
UART
XMC_UART_CH_CONFIG_t
baudrate
data_bits
frame_length
oversampling
parity_mode
stop_bits
XMC_UART0_CH0
XMC_UART0_CH1
XMC_UART1_CH0
XMC_UART1_CH1
XMC_UART2_CH0
XMC_UART2_CH1
XMC_UART_CH_EVENT_t
XMC_UART_CH_EVENT_RECEIVE_START
XMC_UART_CH_EVENT_DATA_LOST
XMC_UART_CH_EVENT_TRANSMIT_SHIFT
XMC_UART_CH_EVENT_TRANSMIT_BUFFER
XMC_UART_CH_EVENT_STANDARD_RECEIVE
XMC_UART_CH_EVENT_ALTERNATIVE_RECEIVE
XMC_UART_CH_EVENT_BAUD_RATE_GENERATOR
XMC_UART_CH_EVENT_SYNCHRONIZATION_BREAK
XMC_UART_CH_EVENT_COLLISION
XMC_UART_CH_EVENT_RECEIVER_NOISE
XMC_UART_CH_EVENT_FORMAT_ERROR
XMC_UART_CH_EVENT_FRAME_FINISHED
XMC_UART_CH_INPUT_SAMPLING_FREQ_t
XMC_UART_CH_INPUT_SAMPLING_FREQ_FPERIPH
XMC_UART_CH_INPUT_SAMPLING_FREQ_FRACTIONAL_DIVIDER
XMC_UART_CH_INPUT_t
XMC_UART_CH_INPUT_RXD
XMC_UART_CH_INPUT_RXD1
XMC_UART_CH_INPUT_RXD2
XMC_UART_CH_INTERRUPT_NODE_POINTER_t
XMC_UART_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT
XMC_UART_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER
XMC_UART_CH_INTERRUPT_NODE_POINTER_RECEIVE
XMC_UART_CH_INTERRUPT_NODE_POINTER_ALTERNATE_RECEIVE
XMC_UART_CH_INTERRUPT_NODE_POINTER_PROTOCOL
XMC_UART_CH_STATUS_FLAG_t
XMC_UART_CH_STATUS_FLAG_TRANSMISSION_IDLE
XMC_UART_CH_STATUS_FLAG_RECEPTION_IDLE
XMC_UART_CH_STATUS_FLAG_SYNCHRONIZATION_BREAK_DETECTED
XMC_UART_CH_STATUS_FLAG_COLLISION_DETECTED
XMC_UART_CH_STATUS_FLAG_RECEIVER_NOISE_DETECTED
XMC_UART_CH_STATUS_FLAG_FORMAT_ERROR_IN_STOP_BIT_0
XMC_UART_CH_STATUS_FLAG_FORMAT_ERROR_IN_STOP_BIT_1
XMC_UART_CH_STATUS_FLAG_RECEIVE_FRAME_FINISHED
XMC_UART_CH_STATUS_FLAG_TRANSMITTER_FRAME_FINISHED
XMC_UART_CH_STATUS_FLAG_TRANSFER_STATUS_BUSY
XMC_UART_CH_STATUS_FLAG_RECEIVER_START_INDICATION
XMC_UART_CH_STATUS_FLAG_DATA_LOST_INDICATION
XMC_UART_CH_STATUS_FLAG_TRANSMIT_SHIFT_INDICATION
XMC_UART_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION
XMC_UART_CH_STATUS_FLAG_RECEIVE_INDICATION
XMC_UART_CH_STATUS_FLAG_ALTERNATIVE_RECEIVE_INDICATION
XMC_UART_CH_STATUS_FLAG_BAUD_RATE_GENERATOR_INDICATION
XMC_UART_CH_STATUS_t
XMC_UART_CH_STATUS_OK
XMC_UART_CH_STATUS_ERROR
XMC_UART_CH_STATUS_BUSY
XMC_UART_CH_ClearStatusFlag
XMC_UART_CH_DisableDataTransmission
XMC_UART_CH_DisableEvent
XMC_UART_CH_DisableInputDigitalFilter
XMC_UART_CH_DisableInputInversion
XMC_UART_CH_DisableInputSync
XMC_UART_CH_EnableDataTransmission
XMC_UART_CH_EnableEvent
XMC_UART_CH_EnableInputDigitalFilter
XMC_UART_CH_EnableInputInversion
XMC_UART_CH_EnableInputSync
XMC_UART_CH_GetReceivedData
XMC_UART_CH_GetStatusFlag
XMC_UART_CH_Init
XMC_UART_CH_SelectInterruptNodePointer
XMC_UART_CH_SetBaudrate
XMC_UART_CH_SetFrameLength
XMC_UART_CH_SetInputSamplingFreq
XMC_UART_CH_SetInputSource
XMC_UART_CH_SetInterruptNodePointer
XMC_UART_CH_SetPulseLength
XMC_UART_CH_SetSamplePoint
XMC_UART_CH_SetWordLength
XMC_UART_CH_Start
XMC_UART_CH_Stop
XMC_UART_CH_Transmit
XMC_UART_CH_TriggerServiceRequest
USBD
XMC_USBD_CAPABILITIES_t
event_connect
event_disconnect
event_high_speed
event_power_off
event_power_on
event_remote_wakeup
event_reset
event_resume
event_suspend
reserved
XMC_USBD_DEVICE_t
device_register
DeviceEvent_cb
endpoint_in_register
endpoint_out_register
EndpointEvent_cb
ep
fifo
global_register
IsActive
IsConnected
IsPowered
txfifomsk
XMC_USBD_DRIVER_t
DeviceConnect
DeviceDisconnect
DeviceGetState
DeviceSetAddress
EndpointAbort
EndpointConfigure
EndpointRead
EndpointReadStart
EndpointStall
EndpointUnconfigure
EndpointWrite
GetCapabilities
GetFrameNumber
Initialize
IsEnumDone
Uninitialize
XMC_USBD_EP_t
address
direction
inBuffer
inBufferSize
inInUse
isConfigured
isStalled
maxPacketSize
maxTransferSize
number
outBuffer
outBufferSize
outBytesAvailable
outInUse
outOffset
pading
sendZeroLengthPacket
txFifoNum
type
xferBuffer
xferCount
xferLength
xferTotal
XMC_USBD_STATE_t
active
connected
powered
speed
XMC_USBD_t
cb_endpoint_event
cb_xmc_device_event
usbd
usbd_max_num_eps
usbd_transfer_mode
XMC_USBD_ENDPOINT_DIRECTION_MASK
XMC_USBD_ENDPOINT_MAX_PACKET_SIZE_MASK
XMC_USBD_ENDPOINT_NUMBER_MASK
XMC_USBD_EP_DIR_MASK
XMC_USBD_EP_NUM_MASK
XMC_USBD_MAX_FIFO_SIZE
XMC_USBD_MAX_PACKET_SIZE
XMC_USBD_MAX_TRANSFER_SIZE_EP0
XMC_USBD_NUM_EPS
XMC_USBD_NUM_TX_FIFOS
XMC_USBD_SETUP_COUNT
XMC_USBD_SETUP_SIZE
XMC_USBD_SPEED_FULL
XMC_USBD_SignalDeviceEvent_t
XMC_USBD_SignalEndpointEvent_t
XMC_USBD_ENDPOINT_TYPE_t
XMC_USBD_ENDPOINT_TYPE_CONTROL
XMC_USBD_ENDPOINT_TYPE_ISOCHRONOUS
XMC_USBD_ENDPOINT_TYPE_BULK
XMC_USBD_ENDPOINT_TYPE_INTERRUPT
XMC_USBD_EP_EVENT_t
XMC_USBD_EP_EVENT_SETUP
XMC_USBD_EP_EVENT_OUT
XMC_USBD_EP_EVENT_IN
XMC_USBD_EVENT_IN_EP_t
XMC_USBD_EVENT_IN_EP_TX_COMPLET
XMC_USBD_EVENT_IN_EP_DISABLED
XMC_USBD_EVENT_IN_EP_AHB_ERROR
XMC_USBD_EVENT_IN_EP_TIMEOUT
XMC_USBD_EVENT_OUT_EP_t
XMC_USBD_EVENT_OUT_EP_TX_COMPLET
XMC_USBD_EVENT_OUT_EP_DISABLED
XMC_USBD_EVENT_OUT_EP_AHB_ERROR
XMC_USBD_EVENT_OUT_EP_SETUP
XMC_USBD_EVENT_t
XMC_USBD_EVENT_POWER_ON
XMC_USBD_EVENT_POWER_OFF
XMC_USBD_EVENT_CONNECT
XMC_USBD_EVENT_DISCONNECT
XMC_USBD_EVENT_RESET
XMC_USBD_EVENT_HIGH_SPEED
XMC_USBD_EVENT_SUSPEND
XMC_USBD_EVENT_RESUME
XMC_USBD_EVENT_REMOTE_WAKEUP
XMC_USBD_EVENT_SOF
XMC_USBD_EVENT_EARLYSUSPEND
XMC_USBD_EVENT_ENUMDONE
XMC_USBD_EVENT_ENUMNOTDONE
XMC_USBD_EVENT_OUTEP
XMC_USBD_EVENT_INEP
XMC_USBD_GRXSTS_PKTSTS_t
XMC_USBD_GRXSTS_PKTSTS_GOUTNAK
XMC_USBD_GRXSTS_PKTSTS_OUTDATA
XMC_USBD_GRXSTS_PKTSTS_OUTCMPL
XMC_USBD_GRXSTS_PKTSTS_SETUPCMPL
XMC_USBD_GRXSTS_PKTSTS_SETUP
XMC_USBD_MAX_NUM_EPS_t
XMC_USBD_MAX_NUM_EPS_1
XMC_USBD_MAX_NUM_EPS_2
XMC_USBD_MAX_NUM_EPS_3
XMC_USBD_MAX_NUM_EPS_4
XMC_USBD_MAX_NUM_EPS_5
XMC_USBD_MAX_NUM_EPS_6
XMC_USBD_MAX_NUM_EPS_7
XMC_USBD_SET_ADDRESS_STAGE_t
XMC_USBD_SET_ADDRESS_STAGE_SETUP
XMC_USBD_SET_ADDRESS_STAGE_STATUS
XMC_USBD_STATUS_t
XMC_USBD_STATUS_OK
XMC_USBD_STATUS_BUSY
XMC_USBD_STATUS_ERROR
XMC_USBD_TRANSFER_MODE_t
XMC_USBD_USE_DMA
XMC_USBD_USE_FIFO
XMC_USBD_ClearEvent
XMC_USBD_ClearEventINEP
XMC_USBD_ClearEventOUTEP
XMC_USBD_DeviceConnect
XMC_USBD_DeviceDisconnect
XMC_USBD_DeviceGetState
XMC_USBD_DeviceSetAddress
XMC_USBD_Disable
XMC_USBD_Enable
XMC_USBD_EnableEventINEP
XMC_USBD_EnableEventOUTEP
XMC_USBD_EndpointAbort
XMC_USBD_EndpointConfigure
XMC_USBD_EndpointRead
XMC_USBD_EndpointReadStart
XMC_USBD_EndpointStall
XMC_USBD_EndpointUnconfigure
XMC_USBD_EndpointWrite
XMC_USBD_GetCapabilities
XMC_USBD_GetFrameNumber
XMC_USBD_Init
XMC_USBD_IRQHandler
XMC_USBD_IsEnumDone
XMC_USBD_Uninitialize
Driver_USBD0
xmc_device
USBH
XMC_USBH0_DEVICE_t
global_register
host_channel_registers
init_done
port_reset_active
power_state
SignalPipeEvent_cb
SignalPortEvent_cb
XMC_USBH0_pipe_t
data
ep_max_packet_size
ep_type
event
in_use
interrupt_triggered
interval
interval_reload
num
num_transferred_total
num_transferring
packet
transfer_active
XMC_USBH_CAPABILITIES_t
auto_split
event_connect
event_disconnect
event_overcurrent
port_mask
XMC_USBH_DRIVER_t
GetCapabilities
GetFrameNumber
GetVersion
Initialize
PipeCreate
PipeDelete
PipeModify
PipeReset
PipeTransfer
PipeTransferAbort
PipeTransferGetResult
PortGetState
PortReset
PortResume
PortSuspend
PortVbusOnOff
PowerControl
Uninitialize
XMC_USBH_DRIVER_VERSION_t
api
drv
XMC_USBH_PORT_STATE_t
connected
overcurrent
speed
USB_CH_HCCHARx_DEVADDR
USB_CH_HCCHARx_EPDIR
USB_CH_HCCHARx_EPNUM
USB_CH_HCCHARx_EPTYPE
USB_CH_HCCHARx_MCEC
USB_CH_HCCHARx_MPS
USB_CH_HCFG_FSLSPCS
USB_CH_HCFG_FSLSSUP
USB_CH_HCINTx_ALL
USB_CH_HCINTx_ERRORS
USB_CH_HCTSIZx_DPID
USB_CH_HCTSIZx_DPID_DATA0
USB_CH_HCTSIZx_DPID_DATA1
USB_CH_HCTSIZx_DPID_DATA2
USB_CH_HCTSIZx_DPID_MDATA
USB_CH_HCTSIZx_DPID_SETUP
USB_GRXSTSR_HOSTMODE_PktSts_IN_DATA_PKT
USB_GRXSTSR_HOSTMODE_PktSts_IN_TRSF_CPL
USBH0_MAX_PIPE_NUM
USBH_PIPE_GET_INDEX
XMC_USB_DRIVE_PORT1
XMC_USB_DRIVE_PORT2
XMC_USBH_API_VERSION
XMC_USBH_CLOCK_GATING_DISABLE
XMC_USBH_CLOCK_GATING_ENABLE
XMC_USBH_DRIVER_ERROR
XMC_USBH_DRIVER_ERROR_BUSY
XMC_USBH_DRIVER_ERROR_PARAMETER
XMC_USBH_DRIVER_ERROR_SPECIFIC
XMC_USBH_DRIVER_ERROR_TIMEOUT
XMC_USBH_DRIVER_ERROR_UNSUPPORTED
XMC_USBH_DRIVER_OK
XMC_USBH_ENDPOINT_BULK
XMC_USBH_ENDPOINT_CONTROL
XMC_USBH_ENDPOINT_INTERRUPT
XMC_USBH_ENDPOINT_ISOCHRONOUS
XMC_USBH_EP_HANDLE
XMC_USBH_EVENT_BUS_ERROR
XMC_USBH_EVENT_CONNECT
XMC_USBH_EVENT_DISCONNECT
XMC_USBH_EVENT_HANDSHAKE_ERR
XMC_USBH_EVENT_HANDSHAKE_MDATA
XMC_USBH_EVENT_HANDSHAKE_NAK
XMC_USBH_EVENT_HANDSHAKE_NYET
XMC_USBH_EVENT_HANDSHAKE_STALL
XMC_USBH_EVENT_OVERCURRENT
XMC_USBH_EVENT_REMOTE_WAKEUP
XMC_USBH_EVENT_RESET
XMC_USBH_EVENT_RESUME
XMC_USBH_EVENT_SUSPEND
XMC_USBH_EVENT_TRANSFER_COMPLETE
XMC_USBH_PACKET_CSPLIT
XMC_USBH_PACKET_DATA0
XMC_USBH_PACKET_DATA1
XMC_USBH_PACKET_DATA_Msk
XMC_USBH_PACKET_DATA_Pos
XMC_USBH_PACKET_IN
XMC_USBH_PACKET_OUT
XMC_USBH_PACKET_PING
XMC_USBH_PACKET_PRE
XMC_USBH_PACKET_SETUP
XMC_USBH_PACKET_SSPLIT
XMC_USBH_PACKET_SSPLIT_E
XMC_USBH_PACKET_SSPLIT_S
XMC_USBH_PACKET_SSPLIT_S_E
XMC_USBH_PACKET_TOKEN_Msk
XMC_USBH_PACKET_TOKEN_Pos
XMC_USBH_SignalEndpointEvent_t
XMC_USBH_SPEED_FULL
XMC_USBH_SPEED_HIGH
XMC_USBH_SPEED_LOW
XMC_USBH_PIPE_HANDLE
XMC_USBH_SignalPipeEvent_t
XMC_USBH_SignalPortEvent_t
XMC_USBH_POWER_STATE_t
XMC_USBH_POWER_OFF
XMC_USBH_POWER_LOW
XMC_USBH_POWER_FULL
XMC_USBH_GetInterruptStatus
XMC_USBH_HandleIrq
XMC_USBH_osDelay
XMC_USBH_Select_VBUS
XMC_USBH_TurnOffResumeBit
USIC
XMC_USIC_CH_t
BRG
BYP
BYPCR
CCFG
CCR
CMTR
DXCR
FDR
FMR
IN
INPR
KSCFG
OUTDR
OUTR
PCR
PCR_ASCMode
PCR_IICMode
PCR_IISMode
PCR_SSCMode
PSCR
PSR
PSR_ASCMode
PSR_IICMode
PSR_IISMode
PSR_SSCMode
RBCTR
RBUF
RBUF0
RBUF01SR
RBUF1
RBUFD
RBUFSR
SCTR
TBCTR
TBUF
TRBPTR
TRBSCR
TRBSR
USIC_CH_DXCR_CM_Msk
USIC_CH_DXCR_CM_Pos
USIC_CH_DXCR_DFEN_Msk
USIC_CH_DXCR_DPOL_Msk
USIC_CH_DXCR_DSEL_Msk
USIC_CH_DXCR_DSEL_Pos
USIC_CH_DXCR_DSEN_Msk
USIC_CH_DXCR_INSW_Msk
USIC_CH_DXCR_INSW_pos
USIC_CH_DXCR_SFSEL_Msk
USIC_CH_DXCR_SFSEL_Pos
XMC_USIC0
XMC_USIC0_CH0
XMC_USIC0_CH1
XMC_USIC1
XMC_USIC1_CH0
XMC_USIC1_CH1
XMC_USIC2
XMC_USIC2_CH0
XMC_USIC2_CH1
XMC_USIC_t
XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_t
XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_DISABLED
XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_NORMAL
XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_FRACTIONAL
XMC_USIC_CH_BRG_CLOCK_SOURCE_t
XMC_USIC_CH_BRG_CLOCK_SOURCE_DIVIDER
XMC_USIC_CH_BRG_CLOCK_SOURCE_DX1T
XMC_USIC_CH_BRG_MASTER_CLOCK_PASSIVE_LEVEL_t
XMC_USIC_CH_BRG_MASTER_CLOCK_PASSIVE_LEVEL_0
XMC_USIC_CH_BRG_MASTER_CLOCK_PASSIVE_LEVEL_1
XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_t
XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_SCLK
XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_DX1
XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_t
XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_0_DELAY_DISABLED
XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_1_DELAY_DISABLED
XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_0_DELAY_ENABLED
XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_1_DELAY_ENABLED
XMC_USIC_CH_DATA_OUTPUT_MODE_t
XMC_USIC_CH_DATA_OUTPUT_MODE_NORMAL
XMC_USIC_CH_DATA_OUTPUT_MODE_INVERTED
XMC_USIC_CH_EVENT_t
XMC_USIC_CH_EVENT_RECEIVE_START
XMC_USIC_CH_EVENT_DATA_LOST
XMC_USIC_CH_EVENT_TRANSMIT_SHIFT
XMC_USIC_CH_EVENT_TRANSMIT_BUFFER
XMC_USIC_CH_EVENT_STANDARD_RECEIVE
XMC_USIC_CH_EVENT_ALTERNATIVE_RECEIVE
XMC_USIC_CH_EVENT_BAUD_RATE_GENERATOR
XMC_USIC_CH_FIFO_SIZE_t
XMC_USIC_CH_FIFO_DISABLED
XMC_USIC_CH_FIFO_SIZE_2WORDS
XMC_USIC_CH_FIFO_SIZE_4WORDS
XMC_USIC_CH_FIFO_SIZE_8WORDS
XMC_USIC_CH_FIFO_SIZE_16WORDS
XMC_USIC_CH_FIFO_SIZE_32WORDS
XMC_USIC_CH_FIFO_SIZE_64WORDS
XMC_USIC_CH_INPUT_COMBINATION_MODE_t
XMC_USIC_CH_INPUT_COMBINATION_MODE_TRIGGER_DISABLED
XMC_USIC_CH_INPUT_COMBINATION_MODE_RISING_EDGE
XMC_USIC_CH_INPUT_COMBINATION_MODE_FALLING_EDGE
XMC_USIC_CH_INPUT_COMBINATION_MODE_BOTH_EDGES
XMC_USIC_CH_INPUT_SAMPLING_FREQ_t
XMC_USIC_CH_INPUT_SAMPLING_FREQ_FPERIPH
XMC_USIC_CH_INPUT_SAMPLING_FREQ_FRACTIONAL_DIVIDER
XMC_USIC_CH_INPUT_t
XMC_USIC_CH_INPUT_DX0
XMC_USIC_CH_INPUT_DX1
XMC_USIC_CH_INPUT_DX2
XMC_USIC_CH_INPUT_DX3
XMC_USIC_CH_INPUT_DX4
XMC_USIC_CH_INPUT_DX5
XMC_USIC_CH_INTERRUPT_NODE_POINTER_t
XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT
XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER
XMC_USIC_CH_INTERRUPT_NODE_POINTER_RECEIVE
XMC_USIC_CH_INTERRUPT_NODE_POINTER_ALTERNATE_RECEIVE
XMC_USIC_CH_INTERRUPT_NODE_POINTER_PROTOCOL
XMC_USIC_CH_KERNEL_MODE_t
XMC_USIC_CH_KERNEL_MODE_RUN_0
XMC_USIC_CH_KERNEL_MODE_RUN_1
XMC_USIC_CH_KERNEL_MODE_STOP_0
XMC_USIC_CH_KERNEL_MODE_STOP_1
XMC_USIC_CH_OPERATING_MODE_t
XMC_USIC_CH_OPERATING_MODE_IDLE
XMC_USIC_CH_OPERATING_MODE_SPI
XMC_USIC_CH_OPERATING_MODE_UART
XMC_USIC_CH_OPERATING_MODE_I2S
XMC_USIC_CH_OPERATING_MODE_I2C
XMC_USIC_CH_PARITY_MODE_t
XMC_USIC_CH_PARITY_MODE_NONE
XMC_USIC_CH_PARITY_MODE_EVEN
XMC_USIC_CH_PARITY_MODE_ODD
XMC_USIC_CH_PASSIVE_DATA_LEVEL_t
XMC_USIC_CH_PASSIVE_DATA_LEVEL0
XMC_USIC_CH_PASSIVE_DATA_LEVEL1
XMC_USIC_CH_RBUF_STATUS_t
XMC_USIC_CH_RBUF_STATUS_DATA_VALID0
XMC_USIC_CH_RBUF_STATUS_DATA_VALID1
XMC_USIC_CH_RXFIFO_EVENT_CONF_t
XMC_USIC_CH_RXFIFO_EVENT_CONF_STANDARD
XMC_USIC_CH_RXFIFO_EVENT_CONF_ERROR
XMC_USIC_CH_RXFIFO_EVENT_CONF_ALTERNATE
XMC_USIC_CH_RXFIFO_EVENT_t
XMC_USIC_CH_RXFIFO_EVENT_STANDARD
XMC_USIC_CH_RXFIFO_EVENT_ERROR
XMC_USIC_CH_RXFIFO_EVENT_ALTERNATE
XMC_USIC_CH_RXFIFO_INTERRUPT_NODE_POINTER_t
XMC_USIC_CH_RXFIFO_INTERRUPT_NODE_POINTER_STANDARD
XMC_USIC_CH_RXFIFO_INTERRUPT_NODE_POINTER_ALTERNATE
XMC_USIC_CH_SHIFT_DIRECTION_t
XMC_USIC_CH_SHIFT_DIRECTION_LSB_FIRST
XMC_USIC_CH_SHIFT_DIRECTION_MSB_FIRST
XMC_USIC_CH_START_TRANSMISION_MODE_t
XMC_USIC_CH_START_TRANSMISION_DISABLED
XMC_USIC_CH_START_TRANSMISION_ON_TDV
XMC_USIC_CH_START_TRANSMISION_ON_TDV_DX2S_0
XMC_USIC_CH_START_TRANSMISION_ON_TDV_DX2S_1
XMC_USIC_CH_STATUS_t
XMC_USIC_CH_STATUS_OK
XMC_USIC_CH_STATUS_ERROR
XMC_USIC_CH_STATUS_BUSY
XMC_USIC_CH_TBUF_STATUS_SET_t
XMC_USIC_CH_TBUF_STATUS_SET_BUSY
XMC_USIC_CH_TBUF_STATUS_SET_IDLE
XMC_USIC_CH_TBUF_STATUS_t
XMC_USIC_CH_TBUF_STATUS_IDLE
XMC_USIC_CH_TBUF_STATUS_BUSY
XMC_USIC_CH_TXFIFO_EVENT_CONF_t
XMC_USIC_CH_TXFIFO_EVENT_CONF_STANDARD
XMC_USIC_CH_TXFIFO_EVENT_CONF_ERROR
XMC_USIC_CH_TXFIFO_EVENT_t
XMC_USIC_CH_TXFIFO_EVENT_STANDARD
XMC_USIC_CH_TXFIFO_EVENT_ERROR
XMC_USIC_CH_TXFIFO_INTERRUPT_NODE_POINTER_t
XMC_USIC_CH_TXFIFO_INTERRUPT_NODE_POINTER_STANDARD
XMC_USIC_CH_TXFIFO_INTERRUPT_NODE_POINTER_ALTERNATE
XMC_USIC_CH_ConfigExternalInputSignalToBRG
XMC_USIC_CH_ConfigureShiftClockOutput
XMC_USIC_CH_ConnectInputDataShiftToDataInput
XMC_USIC_CH_ConnectInputDataShiftToPPP
XMC_USIC_CH_Disable
XMC_USIC_CH_DisableDelayCompensation
XMC_USIC_CH_DisableEvent
XMC_USIC_CH_DisableFrameLengthControl
XMC_USIC_CH_DisableInputDigitalFilter
XMC_USIC_CH_DisableInputInversion
XMC_USIC_CH_DisableInputSync
XMC_USIC_CH_DisableTBUFDataValidTrigger
XMC_USIC_CH_DisableTimeMeasurement
XMC_USIC_CH_Enable
XMC_USIC_CH_EnableDelayCompensation
XMC_USIC_CH_EnableEvent
XMC_USIC_CH_EnableFrameLengthControl
XMC_USIC_CH_EnableInputDigitalFilter
XMC_USIC_CH_EnableInputInversion
XMC_USIC_CH_EnableInputSync
XMC_USIC_CH_EnableTBUFDataValidTrigger
XMC_USIC_CH_EnableTimeMeasurement
XMC_USIC_CH_GetCaptureTimerValue
XMC_USIC_CH_GetReceiveBufferStatus
XMC_USIC_CH_GetTransmitBufferStatus
XMC_USIC_CH_RXFIFO_ClearEvent
XMC_USIC_CH_RXFIFO_Configure
XMC_USIC_CH_RXFIFO_DisableEvent
XMC_USIC_CH_RXFIFO_EnableEvent
XMC_USIC_CH_RXFIFO_Flush
XMC_USIC_CH_RXFIFO_GetData
XMC_USIC_CH_RXFIFO_GetEvent
XMC_USIC_CH_RXFIFO_GetLevel
XMC_USIC_CH_RXFIFO_IsEmpty
XMC_USIC_CH_RXFIFO_IsFull
XMC_USIC_CH_RXFIFO_SetInterruptNodePointer
XMC_USIC_CH_RXFIFO_SetSizeTriggerLimit
XMC_USIC_CH_SetBaudrate
XMC_USIC_CH_SetBRGInputClockSource
XMC_USIC_CH_SetDataOutputMode
XMC_USIC_CH_SetFractionalDivider
XMC_USIC_CH_SetFrameLength
XMC_USIC_CH_SetInputSamplingFreq
XMC_USIC_CH_SetInputSource
XMC_USIC_CH_SetInputTriggerCombinationMode
XMC_USIC_CH_SetInterruptNodePointer
XMC_USIC_CH_SetMclkOutputPassiveLevel
XMC_USIC_CH_SetMode
XMC_USIC_CH_SetPassiveDataLevel
XMC_USIC_CH_SetShiftDirection
XMC_USIC_CH_SetStartTransmisionMode
XMC_USIC_CH_SetTransmitBufferStatus
XMC_USIC_CH_SetWordLength
XMC_USIC_CH_TriggerServiceRequest
XMC_USIC_CH_TXFIFO_ClearEvent
XMC_USIC_CH_TXFIFO_Configure
XMC_USIC_CH_TXFIFO_DisableEvent
XMC_USIC_CH_TXFIFO_EnableEvent
XMC_USIC_CH_TXFIFO_Flush
XMC_USIC_CH_TXFIFO_GetEvent
XMC_USIC_CH_TXFIFO_GetLevel
XMC_USIC_CH_TXFIFO_IsEmpty
XMC_USIC_CH_TXFIFO_IsFull
XMC_USIC_CH_TXFIFO_PutData
XMC_USIC_CH_TXFIFO_PutDataFLEMode
XMC_USIC_CH_TXFIFO_PutDataHPCMode
XMC_USIC_CH_TXFIFO_SetInterruptNodePointer
XMC_USIC_CH_TXFIFO_SetSizeTriggerLimit
XMC_USIC_CH_WriteToTBUF
XMC_USIC_CH_WriteToTBUFTCI
XMC_USIC_Disable
XMC_USIC_Enable
XMC_USIC_IsChannelValid
XMC_USIC_IsModuleValid
VADC
XMC_VADC_CHANNEL_CONFIG_t
alias_channel
alternate_reference
boundary_flag_mode_ch0
boundary_flag_mode_ch1
boundary_flag_mode_ch2
boundary_flag_mode_ch3
broken_wire_detect
broken_wire_detect_channel
channel_priority
event_gen_criteria
flag_output_condition_ch0
flag_output_condition_ch1
flag_output_condition_ch2
flag_output_condition_ch3
input_class
invert_boundary_flag_ch0
invert_boundary_flag_ch1
invert_boundary_flag_ch2
invert_boundary_flag_ch3
lower_boundary_select
result_alignment
result_reg_number
sync_conversion
upper_boundary_select
use_global_result
XMC_VADC_DETAILED_RESULT_t
channel_number
converted_request_source
data_reduction_counter
emux_channel_number
fast_compare_result
result
vaild_result
XMC_VADC_GLOBAL_CLASS_t
conversion_mode_emux
conversion_mode_standard
sample_time_std_conv
sampling_phase_emux_channel
XMC_VADC_GLOBAL_CLOCK_t
analog_clock_divider
arbiter_clock_divider
msb_conversion_clock
XMC_VADC_GLOBAL_CONFIG_t
boundary0
boundary1
class0
class1
clock_config
data_reduction_control
disable_sleep_mode_control
event_gen_enable
module_disable
wait_for_read_mode
XMC_VADC_GROUP_CLASS_t
conversion_mode_emux
conversion_mode_standard
sample_time_std_conv
sampling_phase_emux_channel
XMC_VADC_GROUP_CONFIG_t
arbiter_mode
arbitration_round_length
boundary0
boundary1
class0
class1
emux_config
XMC_VADC_GROUP_EMUXCFG_t
connected_channel
emux_coding
emux_mode
starting_external_channel
stce_usage
XMC_VADC_QUEUE_CONFIG_t
conv_start_mode
external_trigger
gate_signal
req_src_priority
src_specific_result_reg
timer_mode
trigger_edge
trigger_signal
XMC_VADC_QUEUE_ENTRY_t
channel_num
external_trigger
generate_interrupt
refill_needed
XMC_VADC_RESULT_CONFIG_t
data_reduction_control
event_gen_enable
part_of_fifo
post_processing_mode
wait_for_read_mode
XMC_VADC_SCAN_CONFIG_t
conv_start_mode
enable_auto_scan
external_trigger
gate_signal
load_mode
req_src_interrupt
req_src_priority
src_specific_result_reg
timer_mode
trigger_edge
trigger_signal
XMC_VADC_NUM_CHANNELS_PER_GROUP
XMC_VADC_BACKGROUND_CONFIG_t
XMC_VADC_GLOBAL_t
XMC_VADC_GROUP_t
XMC_VADC_RESULT_SIZE_t
XMC_VADC_BOUNDARY_NODE_t
XMC_VADC_BOUNDARY_NODE_COMMON_BOUNDARY_FLAG_0
XMC_VADC_BOUNDARY_NODE_COMMON_BOUNDARY_FLAG_1
XMC_VADC_BOUNDARY_NODE_COMMON_BOUNDARY_FLAG_2
XMC_VADC_BOUNDARY_NODE_COMMON_BOUNDARY_FLAG_3
XMC_VADC_BOUNDARY_NODE_COMMON_SR_LINE_0
XMC_VADC_BOUNDARY_NODE_COMMON_SR_LINE_1
XMC_VADC_BOUNDARY_NODE_COMMON_SR_LINE_2
XMC_VADC_BOUNDARY_NODE_COMMON_SR_LINE_3
XMC_VADC_BOUNDARY_SELECT_t
XMC_VADC_BOUNDARY_SELECT_LOWER_BOUND
XMC_VADC_BOUNDARY_SELECT_UPPER_BOUND
XMC_VADC_CHANNEL_ALIAS_t
XMC_VADC_CHANNEL_BOUNDARY_CONDITION_t
XMC_VADC_CHANNEL_BOUNDARY_CONDITION_ABOVE_BAND
XMC_VADC_CHANNEL_BOUNDARY_CONDITION_BELOW_BAND
XMC_VADC_CHANNEL_BOUNDARY_t
XMC_VADC_CHANNEL_BOUNDARY_GROUP_BOUND0
XMC_VADC_CHANNEL_BOUNDARY_GROUP_BOUND1
XMC_VADC_CHANNEL_BOUNDARY_GLOBAL_BOUND0
XMC_VADC_CHANNEL_BOUNDARY_GLOBAL_BOUND1
XMC_VADC_CHANNEL_BWDCH_t
XMC_VADC_CHANNEL_BWDCH_VAGND
XMC_VADC_CHANNEL_BWDCH_VAREF
XMC_VADC_CHANNEL_CONV_t
XMC_VADC_CHANNEL_CONV_GROUP_CLASS0
XMC_VADC_CHANNEL_CONV_GROUP_CLASS1
XMC_VADC_CHANNEL_CONV_GLOBAL_CLASS0
XMC_VADC_CHANNEL_CONV_GLOBAL_CLASS1
XMC_VADC_CHANNEL_EVGEN_t
XMC_VADC_CHANNEL_EVGEN_NEVER
XMC_VADC_CHANNEL_EVGEN_INBOUND
XMC_VADC_CHANNEL_EVGEN_COMPHIGH
XMC_VADC_CHANNEL_EVGEN_OUTBOUND
XMC_VADC_CHANNEL_EVGEN_COMPLOW
XMC_VADC_CHANNEL_EVGEN_ALWAYS
XMC_VADC_CHANNEL_REF_t
XMC_VADC_CHANNEL_REF_INTREF
XMC_VADC_CHANNEL_REF_ALT_CH0
XMC_VADC_CONVMODE_t
XMC_VADC_CONVMODE_12BIT
XMC_VADC_CONVMODE_10BIT
XMC_VADC_CONVMODE_8BIT
XMC_VADC_CONVMODE_FASTCOMPARE
XMC_VADC_DMM_t
XMC_VADC_DMM_REDUCTION_MODE
XMC_VADC_DMM_FILTERING_MODE
XMC_VADC_DMM_DIFFERENCE_MODE
XMC_VADC_FAST_COMPARE_t
XMC_VADC_FAST_COMPARE_LOW
XMC_VADC_FAST_COMPARE_HIGH
XMC_VADC_FAST_COMPARE_UNKNOWN
XMC_VADC_GATE_INPUT_SELECT_t
XMC_VADC_REQ_GT_A
XMC_VADC_REQ_GT_B
XMC_VADC_REQ_GT_C
XMC_VADC_REQ_GT_D
XMC_VADC_REQ_GT_E
XMC_VADC_REQ_GT_F
XMC_VADC_REQ_GT_G
XMC_VADC_REQ_GT_H
XMC_VADC_REQ_GT_I
XMC_VADC_REQ_GT_J
XMC_VADC_REQ_GT_K
XMC_VADC_REQ_GT_L
XMC_VADC_REQ_GT_M
XMC_VADC_REQ_GT_N
XMC_VADC_REQ_GT_O
XMC_VADC_REQ_GT_P
XMC_VADC_GATEMODE_t
XMC_VADC_GATEMODE_BLOCK
XMC_VADC_GATEMODE_IGNORE
XMC_VADC_GATEMODE_ACTIVEHIGH
XMC_VADC_GATEMODE_ACTIVELOW
XMC_VADC_GLOBAL_EVENT_t
XMC_VADC_GLOBAL_EVENT_BKGNDSOURCE
XMC_VADC_GLOBAL_EVENT_RESULT
XMC_VADC_GROUP_ARBMODE_t
XMC_VADC_GROUP_ARBMODE_ALWAYS
XMC_VADC_GROUP_ARBMODE_ONDEMAND
XMC_VADC_GROUP_BOUNDARY_FLAG_MODE_t
XMC_VADC_GROUP_BOUNDARY_FLAG_MODE_DISABLED
XMC_VADC_GROUP_BOUNDARY_FLAG_MODE_ENABLED
XMC_VADC_GROUP_BOUNDARY_FLAG_MODE_ENABLED_ACTIVE_LOW
XMC_VADC_GROUP_BOUNDARY_FLAG_MODE_ENABLED_ACTIVE_HIGH
XMC_VADC_GROUP_CONV_t
XMC_VADC_GROUP_CONV_STD
XMC_VADC_GROUP_CONV_EMUX
XMC_VADC_GROUP_EMUXCODE_t
XMC_VADC_GROUP_EMUXCODE_BINARY
XMC_VADC_GROUP_EMUXCODE_GRAY
XMC_VADC_GROUP_EMUXMODE_t
XMC_VADC_GROUP_EMUXMODE_SWCTRL
XMC_VADC_GROUP_EMUXMODE_STEADYMODE
XMC_VADC_GROUP_EMUXMODE_SINGLEMODE
XMC_VADC_GROUP_EMUXMODE_SEQUENCEMODE
XMC_VADC_GROUP_INDEX_t
XMC_VADC_GROUP_IRQ_t
XMC_VADC_GROUP_IRQ_KERNEL
XMC_VADC_GROUP_IRQ_SHARED
XMC_VADC_GROUP_POWERMODE_t
XMC_VADC_GROUP_POWERMODE_OFF
XMC_VADC_GROUP_POWERMODE_RESERVED1
XMC_VADC_GROUP_POWERMODE_RESERVED2
XMC_VADC_GROUP_POWERMODE_NORMAL
XMC_VADC_GROUP_RS_PRIORITY_t
XMC_VADC_GROUP_RS_PRIORITY_0
XMC_VADC_GROUP_RS_PRIORITY_1
XMC_VADC_GROUP_RS_PRIORITY_2
XMC_VADC_GROUP_RS_PRIORITY_3
XMC_VADC_GROUP_STATE_t
XMC_VADC_GROUP_STATE_IDLE
XMC_VADC_GROUP_STATE_BUSY
XMC_VADC_RESULT_ALIGN_t
XMC_VADC_RESULT_ALIGN_LEFT
XMC_VADC_RESULT_ALIGN_RIGHT
XMC_VADC_RESULT_SUBTRATION_t
XMC_VADC_RESULT_SUBTRATION_12BIT_LEFT_ALIGN
XMC_VADC_RESULT_SUBTRATION_12BIT_RIGHT_ALIGN
XMC_VADC_RESULT_SUBTRATION_10BIT_LEFT_ALIGN
XMC_VADC_RESULT_SUBTRATION_10BIT_RIGHT_ALIGN
XMC_VADC_RESULT_SUBTRATION_8BIT_LEFT_ALIGN
XMC_VADC_RESULT_SUBTRATION_8BIT_RIGHT_ALIGN
XMC_VADC_SCAN_LOAD_t
XMC_VADC_SCAN_LOAD_OVERWRITE
XMC_VADC_SCAN_LOAD_COMBINE
XMC_VADC_SCAN_TYPE_t
XMC_VADC_SCAN_TYPE_GROUPSCAN
XMC_VADC_SCAN_TYPE_BACKGROUND
XMC_VADC_SR_t
XMC_VADC_SR_GROUP_SR0
XMC_VADC_SR_GROUP_SR1
XMC_VADC_SR_GROUP_SR2
XMC_VADC_SR_GROUP_SR3
XMC_VADC_SR_SHARED_SR0
XMC_VADC_SR_SHARED_SR1
XMC_VADC_SR_SHARED_SR2
XMC_VADC_SR_SHARED_SR3
XMC_VADC_STARTMODE_t
XMC_VADC_STARTMODE_WFS
XMC_VADC_STARTMODE_CIR
XMC_VADC_STARTMODE_CNR
XMC_VADC_STATUS_t
XMC_VADC_STATUS_SUCCESS
XMC_VADC_STATUS_ERROR
XMC_VADC_SYNCTR_EVAL_t
XMC_VADC_SYNCTR_EVAL_1
XMC_VADC_TRIGGER_EDGE_t
XMC_VADC_TRIGGER_EDGE_NONE
XMC_VADC_TRIGGER_EDGE_FALLING
XMC_VADC_TRIGGER_EDGE_RISING
XMC_VADC_TRIGGER_EDGE_ANY
XMC_VADC_TRIGGER_INPUT_SELECT_t
XMC_VADC_REQ_TR_A
XMC_VADC_REQ_TR_B
XMC_VADC_REQ_TR_C
XMC_VADC_REQ_TR_D
XMC_VADC_REQ_TR_E
XMC_VADC_REQ_TR_F
XMC_VADC_REQ_TR_G
XMC_VADC_REQ_TR_H
XMC_VADC_REQ_TR_I
XMC_VADC_REQ_TR_J
XMC_VADC_REQ_TR_K
XMC_VADC_REQ_TR_L
XMC_VADC_REQ_TR_M
XMC_VADC_REQ_TR_N
XMC_VADC_REQ_TR_O
XMC_VADC_REQ_TR_P
XMC_VADC_GLOBAL_BackgndAddMultipleChannels
XMC_VADC_GLOBAL_BackgndRemoveMultipleChannels
XMC_VADC_GLOBAL_BackgroundAbortSequence
XMC_VADC_GLOBAL_BackgroundAddChannelToSequence
XMC_VADC_GLOBAL_BackgroundClearReqSrcEvent
XMC_VADC_GLOBAL_BackgroundDisableContinuousMode
XMC_VADC_GLOBAL_BackgroundDisableEvent
XMC_VADC_GLOBAL_BackgroundDisableExternalTrigger
XMC_VADC_GLOBAL_BackgroundEnableContinuousMode
XMC_VADC_GLOBAL_BackgroundEnableEvent
XMC_VADC_GLOBAL_BackgroundEnableExternalTrigger
XMC_VADC_GLOBAL_BackgroundGetNumChannelsPending
XMC_VADC_GLOBAL_BackgroundGetReqSrcEventStatus
XMC_VADC_GLOBAL_BackgroundInit
XMC_VADC_GLOBAL_BackgroundIsChannelPending
XMC_VADC_GLOBAL_BackgroundRemoveChannelFromSequence
XMC_VADC_GLOBAL_BackgroundSelectGating
XMC_VADC_GLOBAL_BackgroundSelectTrigger
XMC_VADC_GLOBAL_BackgroundSelectTriggerEdge
XMC_VADC_GLOBAL_BackgroundSetGatingMode
XMC_VADC_GLOBAL_BackgroundSetReqSrcEventInterruptNode
XMC_VADC_GLOBAL_BackgroundTriggerConversion
XMC_VADC_GLOBAL_BackgroundTriggerReqSrcEvent
XMC_VADC_GLOBAL_BindGroupToEMux
XMC_VADC_GLOBAL_ClearEvent
XMC_VADC_GLOBAL_ClockInit
XMC_VADC_GLOBAL_DisableModule
XMC_VADC_GLOBAL_DisableModuleClock
XMC_VADC_GLOBAL_DisablePostCalibration
XMC_VADC_GLOBAL_DisableSleepMode
XMC_VADC_GLOBAL_DisableStartupCalibration
XMC_VADC_GLOBAL_EnableModule
XMC_VADC_GLOBAL_EnableModuleClock
XMC_VADC_GLOBAL_EnablePostCalibration
XMC_VADC_GLOBAL_EnableSleepMode
XMC_VADC_GLOBAL_GetCompareResult
XMC_VADC_GLOBAL_GetDetailedResult
XMC_VADC_GLOBAL_GetResult
XMC_VADC_GLOBAL_Init
XMC_VADC_GLOBAL_InputClassInit
XMC_VADC_GLOBAL_ResultInit
XMC_VADC_GLOBAL_SetBoundaries
XMC_VADC_GLOBAL_SetCompareValue
XMC_VADC_GLOBAL_SetIndividualBoundary
XMC_VADC_GLOBAL_SetResultEventInterruptNode
XMC_VADC_GLOBAL_StartupCalibration
XMC_VADC_GLOBAL_TriggerEvent
XMC_VADC_GROUP_AddResultToFifo
XMC_VADC_GROUP_BackgroundDisableArbitrationSlot
XMC_VADC_GROUP_BackgroundEnableArbitrationSlot
XMC_VADC_GROUP_ChannelClearEvent
XMC_VADC_GROUP_ChannelGetAssertedEvents
XMC_VADC_GROUP_ChannelGetInputClass
XMC_VADC_GROUP_ChannelGetResultAlignment
XMC_VADC_GROUP_ChannelGetResultRegister
XMC_VADC_GROUP_ChannelInit
XMC_VADC_GROUP_ChannelIsResultOutOfBounds
XMC_VADC_GROUP_ChannelSetBoundarySelection
XMC_VADC_GROUP_ChannelSetEventInterruptNode
XMC_VADC_GROUP_ChannelSetIclass
XMC_VADC_GROUP_ChannelSetInputReference
XMC_VADC_GROUP_ChannelSetResultRegister
XMC_VADC_GROUP_ChannelTriggerEvent
XMC_VADC_GROUP_ChannelTriggerEventGenCriteria
XMC_VADC_GROUP_CheckSlaveReadiness
XMC_VADC_GROUP_ClearResultEvent
XMC_VADC_GROUP_DisableChannelSyncRequest
XMC_VADC_GROUP_DisableResultEvent
XMC_VADC_GROUP_EnableChannelSyncRequest
XMC_VADC_GROUP_EnableResultEvent
XMC_VADC_GROUP_ExternalMuxControlInit
XMC_VADC_GROUP_GetAlias
XMC_VADC_GROUP_GetAssertedResultEvents
XMC_VADC_GROUP_GetDetailedResult
XMC_VADC_GROUP_GetFastCompareResult
XMC_VADC_GROUP_GetInputClass
XMC_VADC_GROUP_GetResult
XMC_VADC_GROUP_GetResultFifoHead
XMC_VADC_GROUP_GetResultFifoTail
XMC_VADC_GROUP_GetSyncReadySignal
XMC_VADC_GROUP_IgnoreSlaveReadiness
XMC_VADC_GROUP_Init
XMC_VADC_GROUP_InputClassInit
XMC_VADC_GROUP_IsConverterBusy
XMC_VADC_GROUP_IsResultRegisterFifoHead
XMC_VADC_GROUP_IsResultRegisterInFifo
XMC_VADC_GROUP_QueueAbortSequence
XMC_VADC_GROUP_QueueClearReqSrcEvent
XMC_VADC_GROUP_QueueDisableArbitrationSlot
XMC_VADC_GROUP_QueueDisableExternalTrigger
XMC_VADC_GROUP_QueueEnableArbitrationSlot
XMC_VADC_GROUP_QueueEnableExternalTrigger
XMC_VADC_GROUP_QueueFlushEntries
XMC_VADC_GROUP_QueueGetInterruptedChannel
XMC_VADC_GROUP_QueueGetLength
XMC_VADC_GROUP_QueueGetNextChannel
XMC_VADC_GROUP_QueueGetReqSrcEventStatus
XMC_VADC_GROUP_QueueInit
XMC_VADC_GROUP_QueueInsertChannel
XMC_VADC_GROUP_QueueIsArbitrationSlotEnabled
XMC_VADC_GROUP_QueueRemoveChannel
XMC_VADC_GROUP_QueueSelectGating
XMC_VADC_GROUP_QueueSelectTrigger
XMC_VADC_GROUP_QueueSelectTriggerEdge
XMC_VADC_GROUP_QueueSetGatingMode
XMC_VADC_GROUP_QueueSetReqSrcEventInterruptNode
XMC_VADC_GROUP_QueueTriggerConversion
XMC_VADC_GROUP_QueueTriggerReqSrcEvent
XMC_VADC_GROUP_ResultInit
XMC_VADC_GROUP_ScanAddChannelToSequence
XMC_VADC_GROUP_ScanAddMultipleChannels
XMC_VADC_GROUP_ScanClearReqSrcEvent
XMC_VADC_GROUP_ScanDisableArbitrationSlot
XMC_VADC_GROUP_ScanDisableContinuousMode
XMC_VADC_GROUP_ScanDisableEvent
XMC_VADC_GROUP_ScanDisableExternalTrigger
XMC_VADC_GROUP_ScanEnableArbitrationSlot
XMC_VADC_GROUP_ScanEnableContinuousMode
XMC_VADC_GROUP_ScanEnableEvent
XMC_VADC_GROUP_ScanEnableExternalTrigger
XMC_VADC_GROUP_ScanGetNumChannelsPending
XMC_VADC_GROUP_ScanGetReqSrcEventStatus
XMC_VADC_GROUP_ScanInit
XMC_VADC_GROUP_ScanIsArbitrationSlotEnabled
XMC_VADC_GROUP_ScanIsChannelPending
XMC_VADC_GROUP_ScanRemoveChannel
XMC_VADC_GROUP_ScanSelectGating
XMC_VADC_GROUP_ScanSelectTrigger
XMC_VADC_GROUP_ScanSelectTriggerEdge
XMC_VADC_GROUP_ScanSequenceAbort
XMC_VADC_GROUP_ScanSetGatingMode
XMC_VADC_GROUP_ScanSetReqSrcEventInterruptNode
XMC_VADC_GROUP_ScanTriggerConversion
XMC_VADC_GROUP_ScanTriggerReqSrcEvent
XMC_VADC_GROUP_SetBoundaries
XMC_VADC_GROUP_SetBoundaryEventInterruptNode
XMC_VADC_GROUP_SetChannelAlias
XMC_VADC_GROUP_SetIndividualBoundary
XMC_VADC_GROUP_SetPowerMode
XMC_VADC_GROUP_SetResultFastCompareValue
XMC_VADC_GROUP_SetResultInterruptNode
XMC_VADC_GROUP_SetResultSubtractionValue
XMC_VADC_GROUP_SetSyncMaster
XMC_VADC_GROUP_SetSyncReadySignal
XMC_VADC_GROUP_SetSyncSlave
XMC_VADC_GROUP_SetSyncSlaveReadySignal
XMC_VADC_GROUP_TriggerResultEvent
XMC_VADC_GROUP_TriggerServiceRequest
WDT
XMC_WDT_CONFIG_t
prewarn_mode
run_in_debug_mode
service_pulse_width
window_lower_bound
window_upper_bound
XMC_WDT_DEBUG_MODE_t
XMC_WDT_DEBUG_MODE_STOP
XMC_WDT_DEBUG_MODE_RUN
XMC_WDT_MODE_t
XMC_WDT_MODE_TIMEOUT
XMC_WDT_MODE_PREWARNING
XMC_WDT_ClearAlarm
XMC_WDT_Disable
XMC_WDT_Enable
XMC_WDT_GetCounter
XMC_WDT_Init
XMC_WDT_Service
XMC_WDT_SetDebugMode
XMC_WDT_SetMode
XMC_WDT_SetServicePulseWidth
XMC_WDT_SetWindowBounds
XMC_WDT_Start
XMC_WDT_Stop
Files
File List
xmc4_flash.h
XMC_FLASH_BYTES_PER_PAGE
XMC_FLASH_BYTES_PER_UCB
XMC_FLASH_PHY_SECTOR_0
XMC_FLASH_PHY_SECTOR_10
XMC_FLASH_PHY_SECTOR_11
XMC_FLASH_PHY_SECTOR_12
XMC_FLASH_PHY_SECTOR_13
XMC_FLASH_PHY_SECTOR_14
XMC_FLASH_PHY_SECTOR_15
XMC_FLASH_PHY_SECTOR_4
XMC_FLASH_PHY_SECTOR_8
XMC_FLASH_PHY_SECTOR_9
XMC_FLASH_SECTOR_0
XMC_FLASH_SECTOR_1
XMC_FLASH_SECTOR_10
XMC_FLASH_SECTOR_11
XMC_FLASH_SECTOR_12
XMC_FLASH_SECTOR_13
XMC_FLASH_SECTOR_14
XMC_FLASH_SECTOR_15
XMC_FLASH_SECTOR_2
XMC_FLASH_SECTOR_3
XMC_FLASH_SECTOR_4
XMC_FLASH_SECTOR_5
XMC_FLASH_SECTOR_6
XMC_FLASH_SECTOR_7
XMC_FLASH_SECTOR_8
XMC_FLASH_SECTOR_9
XMC_FLASH_UCB0
XMC_FLASH_UCB1
XMC_FLASH_UCB2
XMC_FLASH_UNCACHED_BASE
XMC_FLASH_WORDS_PER_PAGE
XMC_FLASH_EVENT_t
XMC_FLASH_EVENT_VERIFY_AND_OPERATION_ERROR
XMC_FLASH_EVENT_COMMAND_SEQUENCE_ERROR
XMC_FLASH_EVENT_PROTECTION_ERROR
XMC_FLASH_EVENT_SINGLE_BIT_ERROR
XMC_FLASH_EVENT_DOUBLE_BIT_ERROR
XMC_FLASH_EVENT_END_OF_BUSY
XMC_FLASH_MARGIN_t
XMC_FLASH_MARGIN_DEFAULT
XMC_FLASH_MARGIN_TIGHT0
XMC_FLASH_MARGIN_TIGHT1
XMC_FLASH_PROTECTION_t
XMC_FLASH_PROTECTION_WRITE_SECTOR_0
XMC_FLASH_PROTECTION_WRITE_SECTOR_1
XMC_FLASH_PROTECTION_WRITE_SECTOR_2
XMC_FLASH_PROTECTION_WRITE_SECTOR_3
XMC_FLASH_PROTECTION_WRITE_SECTOR_4
XMC_FLASH_PROTECTION_WRITE_SECTOR_5
XMC_FLASH_PROTECTION_WRITE_SECTOR_6
XMC_FLASH_PROTECTION_WRITE_SECTOR_7
XMC_FLASH_PROTECTION_WRITE_SECTOR_8
XMC_FLASH_PROTECTION_WRITE_SECTOR_9
XMC_FLASH_PROTECTION_WRITE_SECTORS_10_11
XMC_FLASH_PROTECTION_WRITE_SECTORS_12_13
XMC_FLASH_PROTECTION_WRITE_SECTORS_14_15
XMC_FLASH_PROTECTION_READ_GLOBAL
XMC_FLASH_STATUS_t
XMC_FLASH_STATUS_OK
XMC_FLASH_STATUS_BUSY
XMC_FLASH_STATUS_PROGRAMMING_STATE
XMC_FLASH_STATUS_ERASE_STATE
XMC_FLASH_STATUS_PAGE_MODE
XMC_FLASH_STATUS_OPERATION_ERROR
XMC_FLASH_STATUS_COMMAND_SEQUENCE_ERROR
XMC_FLASH_STATUS_PROTECTION_ERROR
XMC_FLASH_STATUS_SINGLE_BIT_ERROR_AND_CORRECTION
XMC_FLASH_STATUS_DOUBLE_BIT_ERROR
XMC_FLASH_STATUS_PROTECTION_INSTALLED
XMC_FLASH_STATUS_READ_PROTECTION_INSTALLED
XMC_FLASH_STATUS_READ_PROTECTION_DISABLED_STATE
XMC_FLASH_STATUS_WRITE_PROTECTION_INSTALLED_UCB0
XMC_FLASH_STATUS_WRITE_PROTECTION_INSTALLED_UCB1
XMC_FLASH_STATUS_WRITE_PROTECTION_INSTALLED_UCB2
XMC_FLASH_STATUS_WRITE_PROTECTION_DISABLED_UCB0
XMC_FLASH_STATUS_WRITE_PROTECTION_DISABLED_UCB1
XMC_FLASH_STATUS_SLEEP_MODE
XMC_FLASH_STATUS_VERIFY_ERROR
XMC_FLASH_ConfirmProtection
XMC_FLASH_DisableDoubleBitErrorTrap
XMC_FLASH_DisableDynamicIdle
XMC_FLASH_DisableSleepRequest
XMC_FLASH_DisableWaitStateForECC
XMC_FLASH_EnableDoubleBitErrorTrap
XMC_FLASH_EnableDynamicIdle
XMC_FLASH_EnableSleepRequest
XMC_FLASH_EnableWaitStateForECC
XMC_FLASH_ErasePhysicalSector
XMC_FLASH_EraseUCB
XMC_FLASH_InstallProtection
XMC_FLASH_RepairPhysicalSector
XMC_FLASH_Reset
XMC_FLASH_ResumeProtection
XMC_FLASH_SetMargin
XMC_FLASH_SetWaitStates
XMC_FLASH_VerifyReadProtection
XMC_FLASH_VerifyWriteProtection
XMC_PREFETCH_DisableInstructionBuffer
XMC_PREFETCH_EnableInstructionBuffer
XMC_PREFETCH_InvalidateInstructionBuffer
xmc4_gpio.h
XMC_GPIO_MODE_t
XMC_GPIO_MODE_INPUT_TRISTATE
XMC_GPIO_MODE_INPUT_PULL_DOWN
XMC_GPIO_MODE_INPUT_PULL_UP
XMC_GPIO_MODE_INPUT_SAMPLING
XMC_GPIO_MODE_INPUT_INVERTED_TRISTATE
XMC_GPIO_MODE_INPUT_INVERTED_PULL_DOWN
XMC_GPIO_MODE_INPUT_INVERTED_PULL_UP
XMC_GPIO_MODE_INPUT_INVERTED_SAMPLING
XMC_GPIO_MODE_OUTPUT_PUSH_PULL
XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN
XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT1
XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT2
XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT3
XMC_GPIO_MODE_OUTPUT_PUSH_PULL_ALT4
XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT1
XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT2
XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT3
XMC_GPIO_MODE_OUTPUT_OPEN_DRAIN_ALT4
XMC_GPIO_OUTPUT_STRENGTH_t
XMC_GPIO_OUTPUT_STRENGTH_STRONG_SHARP_EDGE
XMC_GPIO_OUTPUT_STRENGTH_STRONG_MEDIUM_EDGE
XMC_GPIO_OUTPUT_STRENGTH_STRONG_SOFT_EDGE
XMC_GPIO_OUTPUT_STRENGTH_STRONG_SLOW_EDGE
XMC_GPIO_OUTPUT_STRENGTH_MEDIUM
XMC_GPIO_OUTPUT_STRENGTH_WEAK
XMC_GPIO_SetOutputStrength
xmc4_rtc.h
XMC_RTC_WAKEUP_EVENT_t
XMC_RTC_WAKEUP_EVENT_ON_ALARM
XMC_RTC_WAKEUP_EVENT_ON_SECONDS
XMC_RTC_WAKEUP_EVENT_ON_MINUTES
XMC_RTC_WAKEUP_EVENT_ON_HOURS
XMC_RTC_WAKEUP_EVENT_ON_DAYS
XMC_RTC_WAKEUP_EVENT_ON_MONTHS
XMC_RTC_WAKEUP_EVENT_ON_YEARS
XMC_RTC_DisableHibernationWakeUp
XMC_RTC_EnableHibernationWakeUp
xmc4_scu.h
XMC_SCU_INTERRUPT_EVENT_DLR_OVERRUN
XMC_SCU_INTERRUPT_EVENT_HDCLR_UPDATED
XMC_SCU_INTERRUPT_EVENT_HDCR_UPDATED
XMC_SCU_INTERRUPT_EVENT_HDSET_UPDATED
XMC_SCU_INTERRUPT_EVENT_OSCSICTRL_UPDATED
XMC_SCU_INTERRUPT_EVENT_OSCULCTRL_UPDATED
XMC_SCU_INTERRUPT_EVENT_RMX_UPDATED
XMC_SCU_INTERRUPT_EVENT_RTC_ALARM
XMC_SCU_INTERRUPT_EVENT_RTC_PERIODIC
XMC_SCU_INTERRUPT_EVENT_RTCATIM0_UPDATED
XMC_SCU_INTERRUPT_EVENT_RTCATIM1_UPDATED
XMC_SCU_INTERRUPT_EVENT_RTCCTR_UPDATED
XMC_SCU_INTERRUPT_EVENT_RTCTIM0_UPDATED
XMC_SCU_INTERRUPT_EVENT_RTCTIM1_UPDATED
XMC_SCU_INTERRUPT_EVENT_WDT_WARN
XMC_SCU_INTERRUPT_EVENT_t
XMC_SCU_BOOTMODE_t
XMC_SCU_BOOTMODE_NORMAL
XMC_SCU_BOOTMODE_ASC_BSL
XMC_SCU_BOOTMODE_BMI
XMC_SCU_BOOTMODE_CAN_BSL
XMC_SCU_BOOTMODE_PSRAM_BOOT
XMC_SCU_BOOTMODE_ABM0
XMC_SCU_BOOTMODE_ABM1
XMC_SCU_BOOTMODE_FABM
XMC_SCU_CCU_TRIGGER_t
XMC_SCU_CCU_TRIGGER_CCU40
XMC_SCU_CCU_TRIGGER_CCU80
XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_t
XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_SYSCLK_FOFI
XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_SYSCLK_FPLL
XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_FLASH_POWERDOWN
XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_PLL_POWERDOWN
XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_VCO_POWERDOWN
XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_DISABLE_USB
XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_ENABLE_USB
XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_DISABLE_SDMMC
XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_ENABLE_SDMMC
XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_DISABLE_ETH
XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_ENABLE_ETH
XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_DISABLE_EBU
XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_ENABLE_EBU
XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_DISABLE_CCU
XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_ENABLE_CCU
XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_DISABLE_WDT
XMC_SCU_CLOCK_DEEPSLEEP_MODE_CONFIG_ENABLE_WDT
XMC_SCU_CLOCK_ECATCLKSRC_t
XMC_SCU_CLOCK_ECATCLKSRC_USBPLL
XMC_SCU_CLOCK_ECATCLKSRC_SYSPLL
XMC_SCU_CLOCK_EXTOUTCLKSRC_t
XMC_SCU_CLOCK_EXTOUTCLKSRC_SYS
XMC_SCU_CLOCK_EXTOUTCLKSRC_USB
XMC_SCU_CLOCK_EXTOUTCLKSRC_PLL
XMC_SCU_CLOCK_FOFI_CALIBRATION_MODE_t
XMC_SCU_CLOCK_FOFI_CALIBRATION_MODE_FACTORY
XMC_SCU_CLOCK_FOFI_CALIBRATION_MODE_AUTOMATIC
XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_t
XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_SYSCLK_FOFI
XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_SYSCLK_FPLL
XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_DISABLE_USB
XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_ENABLE_USB
XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_DISABLE_SDMMC
XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_ENABLE_SDMMC
XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_DISABLE_ETH
XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_ENABLE_ETH
XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_DISABLE_EBU
XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_ENABLE_EBU
XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_DISABLED_CCU
XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_ENABLE_CCU
XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_DISABLED_WDT
XMC_SCU_CLOCK_SLEEP_MODE_CONFIG_ENABLE_WDT
XMC_SCU_CLOCK_SYSCLKSRC_t
XMC_SCU_CLOCK_SYSCLKSRC_OFI
XMC_SCU_CLOCK_SYSCLKSRC_PLL
XMC_SCU_CLOCK_SYSPLL_MODE_t
XMC_SCU_CLOCK_SYSPLL_MODE_DISABLED
XMC_SCU_CLOCK_SYSPLL_MODE_NORMAL
XMC_SCU_CLOCK_SYSPLL_MODE_PRESCALAR
XMC_SCU_CLOCK_SYSPLLCLKSRC_t
XMC_SCU_CLOCK_SYSPLLCLKSRC_OSCHP
XMC_SCU_CLOCK_SYSPLLCLKSRC_OFI
XMC_SCU_CLOCK_t
XMC_SCU_CLOCK_USB
XMC_SCU_CLOCK_MMC
XMC_SCU_CLOCK_ETH
XMC_SCU_CLOCK_EBU
XMC_SCU_CLOCK_CCU
XMC_SCU_CLOCK_WDT
XMC_SCU_CLOCK_USBCLKSRC_t
XMC_SCU_CLOCK_USBCLKSRC_USBPLL
XMC_SCU_CLOCK_USBCLKSRC_SYSPLL
XMC_SCU_CLOCK_WDTCLKSRC_t
XMC_SCU_CLOCK_WDTCLKSRC_OFI
XMC_SCU_CLOCK_WDTCLKSRC_STDBY
XMC_SCU_CLOCK_WDTCLKSRC_PLL
XMC_SCU_HIB_CTRL_STATUS_t
XMC_SCU_HIB_CTRL_STATUS_NO_ACTIVE
XMC_SCU_HIB_CTRL_STATUS_ACTIVE
XMC_SCU_HIB_EVENT_t
XMC_SCU_HIB_EVENT_WAKEUP_ON_POS_EDGE
XMC_SCU_HIB_EVENT_WAKEUP_ON_NEG_EDGE
XMC_SCU_HIB_EVENT_WAKEUP_ON_RTC
XMC_SCU_HIB_EVENT_ULPWDG
XMC_SCU_HIB_EVENT_LPAC_VBAT_POSEDGE
XMC_SCU_HIB_EVENT_LPAC_VBAT_NEGEDGE
XMC_SCU_HIB_EVENT_LPAC_HIB_IO_0_POSEDGE
XMC_SCU_HIB_EVENT_LPAC_HIB_IO_0_NEGEDGE
XMC_SCU_HIB_EVENT_LPAC_HIB_IO_1_POSEDGE
XMC_SCU_HIB_EVENT_LPAC_HIB_IO_1_NEGEDGE
XMC_SCU_HIB_HIBERNATE_MODE_t
XMC_SCU_HIB_HIBERNATE_MODE_EXTERNAL
XMC_SCU_HIB_HIBERNATE_MODE_INTERNAL
XMC_SCU_HIB_IO_OUTPUT_LEVEL_t
XMC_SCU_HIB_IO_OUTPUT_LEVEL_LOW
XMC_SCU_HIB_IO_OUTPUT_LEVEL_HIGH
XMC_SCU_HIB_IO_t
XMC_SCU_HIB_IO_0
XMC_SCU_HIB_IO_1
XMC_SCU_HIB_LPAC_INPUT_t
XMC_SCU_HIB_LPAC_INPUT_DISABLED
XMC_SCU_HIB_LPAC_INPUT_VBAT
XMC_SCU_HIB_LPAC_INPUT_HIB_IO_0
XMC_SCU_HIB_LPAC_INPUT_HIB_IO_1
XMC_SCU_HIB_LPAC_STATUS_t
XMC_SCU_HIB_LPAC_STATUS_VBAT_COMPARE_DONE
XMC_SCU_HIB_LPAC_STATUS_HIB_IO_0_COMPARE_DONE
XMC_SCU_HIB_LPAC_STATUS_HIB_IO_1_COMPARE_DONE
XMC_SCU_HIB_LPAC_STATUS_VBAT_ABOVE_THRESHOLD
XMC_SCU_HIB_LPAC_STATUS_HIB_IO_0_ABOVE_THRESHOLD
XMC_SCU_HIB_LPAC_STATUS_HIB_IO_1_ABOVE_THRESHOLD
XMC_SCU_HIB_LPAC_TRIGGER_t
XMC_SCU_HIB_LPAC_TRIGGER_SUBSECOND_INTERVAL_COUNTER
XMC_SCU_HIB_LPAC_TRIGGER_RTC_ALARM_EVENT
XMC_SCU_HIB_LPAC_TRIGGER_RTC_PERIODIC_EVENT
XMC_SCU_HIB_LPAC_TRIGGER_ON_WAKEUP_POSITIVE_EDGE_EVENT
XMC_SCU_HIB_LPAC_TRIGGER_ON_WAKEUP_NEGATIVE_EDGE_EVENT
XMC_SCU_HIB_LPAC_TRIGGER_CONTINOUS
XMC_SCU_HIB_LPAC_TRIGGER_SINGLE_SHOT
XMC_SCU_HIB_PIN_MODE_t
XMC_SCU_HIB_PIN_MODE_INPUT_PULL_NONE
XMC_SCU_HIB_PIN_MODE_INPUT_PULL_DOWN
XMC_SCU_HIB_PIN_MODE_INPUT_PULL_UP
XMC_SCU_HIB_PIN_MODE_OUTPUT_PUSH_PULL_HIBCTRL
XMC_SCU_HIB_PIN_MODE_OUTPUT_PUSH_PULL_WDTSRV
XMC_SCU_HIB_PIN_MODE_OUTPUT_PUSH_PULL_GPIO
XMC_SCU_HIB_PIN_MODE_OUTPUT_OPEN_DRAIN_HIBCTRL
XMC_SCU_HIB_PIN_MODE_OUTPUT_OPEN_DRAIN_WDTSRV
XMC_SCU_HIB_PIN_MODE_OUTPUT_OPEN_DRAIN_GPIO
XMC_SCU_HIB_RTCCLKSRC_t
XMC_SCU_HIB_RTCCLKSRC_OSI
XMC_SCU_HIB_RTCCLKSRC_ULP
XMC_SCU_HIB_SR0_INPUT_t
XMC_SCU_HIB_SR0_INPUT_HIB_IO_0
XMC_SCU_HIB_SR0_INPUT_HIB_IO_1
XMC_SCU_HIB_SR0_INPUT_ACMP0
XMC_SCU_HIB_STDBYCLKSRC_t
XMC_SCU_HIB_STDBYCLKSRC_OSI
XMC_SCU_HIB_STDBYCLKSRC_OSCULP
XMC_SCU_NMIREQ_t
XMC_SCU_NMIREQ_WDT_WARN
XMC_SCU_NMIREQ_RTC_PI
XMC_SCU_NMIREQ_RTC_AI
XMC_SCU_NMIREQ_ERU0_0
XMC_SCU_NMIREQ_ERU0_1
XMC_SCU_NMIREQ_ERU0_2
XMC_SCU_NMIREQ_ERU0_3
XMC_SCU_PARITY_t
XMC_SCU_PARITY_PSRAM_MEM
XMC_SCU_PARITY_DSRAM1_MEM
XMC_SCU_PARITY_USIC0_MEM
XMC_SCU_PARITY_MCAN_MEM
XMC_SCU_PARITY_PMU_MEM
XMC_SCU_PARITY_USB_MEM
XMC_SCU_PERIPHERAL_CLOCK_t
XMC_SCU_PERIPHERAL_CLOCK_VADC
XMC_SCU_PERIPHERAL_CLOCK_DSD
XMC_SCU_PERIPHERAL_CLOCK_CCU40
XMC_SCU_PERIPHERAL_CLOCK_CCU80
XMC_SCU_PERIPHERAL_CLOCK_POSIF0
XMC_SCU_PERIPHERAL_CLOCK_USIC0
XMC_SCU_PERIPHERAL_CLOCK_ERU1
XMC_SCU_PERIPHERAL_CLOCK_HRPWM0
XMC_SCU_PERIPHERAL_CLOCK_LEDTS0
XMC_SCU_PERIPHERAL_CLOCK_MCAN
XMC_SCU_PERIPHERAL_CLOCK_DAC
XMC_SCU_PERIPHERAL_CLOCK_SDMMC
XMC_SCU_PERIPHERAL_CLOCK_USIC1
XMC_SCU_PERIPHERAL_CLOCK_USIC2
XMC_SCU_PERIPHERAL_CLOCK_PORTS
XMC_SCU_PERIPHERAL_CLOCK_WDT
XMC_SCU_PERIPHERAL_CLOCK_ETH0
XMC_SCU_PERIPHERAL_CLOCK_GPDMA0
XMC_SCU_PERIPHERAL_CLOCK_GPDMA1
XMC_SCU_PERIPHERAL_CLOCK_FCE
XMC_SCU_PERIPHERAL_CLOCK_USB0
XMC_SCU_PERIPHERAL_CLOCK_ECAT0
XMC_SCU_PERIPHERAL_CLOCK_EBU
XMC_SCU_PERIPHERAL_RESET_t
XMC_SCU_PERIPHERAL_RESET_VADC
XMC_SCU_PERIPHERAL_RESET_DSD
XMC_SCU_PERIPHERAL_RESET_CCU40
XMC_SCU_PERIPHERAL_RESET_CCU80
XMC_SCU_PERIPHERAL_RESET_POSIF0
XMC_SCU_PERIPHERAL_RESET_USIC0
XMC_SCU_PERIPHERAL_RESET_ERU1
XMC_SCU_PERIPHERAL_RESET_HRPWM0
XMC_SCU_PERIPHERAL_RESET_LEDTS0
XMC_SCU_PERIPHERAL_RESET_MCAN
XMC_SCU_PERIPHERAL_RESET_DAC
XMC_SCU_PERIPHERAL_RESET_SDMMC
XMC_SCU_PERIPHERAL_RESET_USIC1
XMC_SCU_PERIPHERAL_RESET_USIC2
XMC_SCU_PERIPHERAL_RESET_PORTS
XMC_SCU_PERIPHERAL_RESET_WDT
XMC_SCU_PERIPHERAL_RESET_ETH0
XMC_SCU_PERIPHERAL_RESET_GPDMA0
XMC_SCU_PERIPHERAL_RESET_GPDMA1
XMC_SCU_PERIPHERAL_RESET_FCE
XMC_SCU_PERIPHERAL_RESET_USB0
XMC_SCU_PERIPHERAL_RESET_ECAT0
XMC_SCU_PERIPHERAL_RESET_EBU
XMC_SCU_POWER_EVR_STATUS_t
XMC_SCU_POWER_EVR_STATUS_OK
XMC_SCU_POWER_EVR_STATUS_EVR13_OVERVOLTAGE
XMC_SCU_POWER_MODE_t
XMC_SCU_POWER_MODE_SLEEP
XMC_SCU_POWER_MODE_DEEPSLEEP
XMC_SCU_RESET_REASON_t
XMC_SCU_RESET_REASON_PORST
XMC_SCU_RESET_REASON_SWD
XMC_SCU_RESET_REASON_PV
XMC_SCU_RESET_REASON_SW
XMC_SCU_RESET_REASON_LOCKUP
XMC_SCU_RESET_REASON_WATCHDOG
XMC_SCU_RESET_REASON_PARITY_ERROR
XMC_SCU_TRAP_t
XMC_SCU_TRAP_OSC_WDG
XMC_SCU_TRAP_VCO_LOCK
XMC_SCU_TRAP_USB_VCO_LOCK
XMC_SCU_TRAP_PARITY_ERROR
XMC_SCU_TRAP_BROWNOUT
XMC_SCU_TRAP_ULP_WDG
XMC_SCU_TRAP_PER_BRIDGE0
XMC_SCU_TRAP_PER_BRIDGE1
XMC_SCU_TRAP_ECAT_RESET
XMC_SCU_CalibrateTemperatureSensor
XMC_SCU_CLOCK_DisableClock
XMC_SCU_CLOCK_DisableHighPerformanceOscillator
XMC_SCU_CLOCK_DisableHighPerformanceOscillatorGeneralPurposeInput
XMC_SCU_CLOCK_DisableLowPowerOscillator
XMC_SCU_CLOCK_DisableLowPowerOscillatorGeneralPurposeInput
XMC_SCU_CLOCK_DisableSystemPll
XMC_SCU_CLOCK_DisableUsbPll
XMC_SCU_CLOCK_EnableClock
XMC_SCU_CLOCK_EnableHighPerformanceOscillator
XMC_SCU_CLOCK_EnableHighPerformanceOscillatorGeneralPurposeInput
XMC_SCU_CLOCK_EnableLowPowerOscillator
XMC_SCU_CLOCK_EnableLowPowerOscillatorGeneralPurposeInput
XMC_SCU_CLOCK_EnableSystemPll
XMC_SCU_CLOCK_EnableUsbPll
XMC_SCU_CLOCK_GetCcuClockDivider
XMC_SCU_CLOCK_GetCcuClockFrequency
XMC_SCU_CLOCK_GetCpuClockDivider
XMC_SCU_CLOCK_GetEbuClockDivider
XMC_SCU_CLOCK_GetEbuClockFrequency
XMC_SCU_CLOCK_GetECATClockDivider
XMC_SCU_CLOCK_GetECATClockSource
XMC_SCU_CLOCK_GetEthernetClockFrequency
XMC_SCU_CLOCK_GetExternalOutputClockDivider
XMC_SCU_CLOCK_GetExternalOutputClockFrequency
XMC_SCU_CLOCK_GetExternalOutputClockSource
XMC_SCU_CLOCK_GetHighPerformanceOscillatorGeneralPurposeInputStatus
XMC_SCU_CLOCK_GetLowPowerOscillatorGeneralPurposeInputStatus
XMC_SCU_CLOCK_GetPeripheralClockDivider
XMC_SCU_CLOCK_GetSystemClockDivider
XMC_SCU_CLOCK_GetSystemClockFrequency
XMC_SCU_CLOCK_GetSystemClockSource
XMC_SCU_CLOCK_GetSystemPllClockFrequency
XMC_SCU_CLOCK_GetSystemPllClockSource
XMC_SCU_CLOCK_GetSystemPllClockSourceFrequency
XMC_SCU_CLOCK_GetUsbClockDivider
XMC_SCU_CLOCK_GetUsbClockFrequency
XMC_SCU_CLOCK_GetUsbClockSource
XMC_SCU_CLOCK_GetUsbPllClockFrequency
XMC_SCU_CLOCK_GetWdtClockDivider
XMC_SCU_CLOCK_GetWdtClockFrequency
XMC_SCU_CLOCK_GetWdtClockSource
XMC_SCU_CLOCK_IsClockEnabled
XMC_SCU_CLOCK_IsHighPerformanceOscillatorStable
XMC_SCU_CLOCK_IsLowPowerOscillatorStable
XMC_SCU_CLOCK_IsSystemPllLocked
XMC_SCU_CLOCK_IsUsbPllLocked
XMC_SCU_CLOCK_SetBackupClockCalibrationMode
XMC_SCU_CLOCK_SetCcuClockDivider
XMC_SCU_CLOCK_SetCpuClockDivider
XMC_SCU_CLOCK_SetDeepSleepConfig
XMC_SCU_CLOCK_SetEbuClockDivider
XMC_SCU_CLOCK_SetECATClockDivider
XMC_SCU_CLOCK_SetECATClockSource
XMC_SCU_CLOCK_SetExternalOutputClockDivider
XMC_SCU_CLOCK_SetExternalOutputClockSource
XMC_SCU_CLOCK_SetPeripheralClockDivider
XMC_SCU_CLOCK_SetSleepConfig
XMC_SCU_CLOCK_SetSystemClockDivider
XMC_SCU_CLOCK_SetSystemClockSource
XMC_SCU_CLOCK_SetSystemPllClockSource
XMC_SCU_CLOCK_SetUsbClockDivider
XMC_SCU_CLOCK_SetUsbClockSource
XMC_SCU_CLOCK_SetWdtClockDivider
XMC_SCU_CLOCK_SetWdtClockSource
XMC_SCU_CLOCK_StartSystemPll
XMC_SCU_CLOCK_StartUsbPll
XMC_SCU_CLOCK_StepSystemPllFrequency
XMC_SCU_CLOCK_StopSystemPll
XMC_SCU_CLOCK_StopUsbPll
XMC_SCU_DisableOutOfRangeComparator
XMC_SCU_DisableTemperatureSensor
XMC_SCU_EnableOutOfRangeComparator
XMC_SCU_EnableTemperatureSensor
XMC_SCU_GetBootMode
XMC_SCU_GetTemperatureMeasurement
XMC_SCU_HIB_ClearEventStatus
XMC_SCU_HIB_ClearWakeupEventDetectionStatus
XMC_SCU_HIB_DisableEvent
XMC_SCU_HIB_DisableHibernateDomain
XMC_SCU_HIB_DisableInternalSlowClock
XMC_SCU_HIB_EnableEvent
XMC_SCU_HIB_EnableHibernateDomain
XMC_SCU_HIB_EnableInternalSlowClock
XMC_SCU_HIB_EnterHibernateState
XMC_SCU_HIB_EnterHibernateStateEx
XMC_SCU_HIB_GetEventStatus
XMC_SCU_HIB_GetHibernateControlStatus
XMC_SCU_HIB_GetRtcClockSource
XMC_SCU_HIB_GetStdbyClockSource
XMC_SCU_HIB_IsHibernateDomainEnabled
XMC_SCU_HIB_IsWakeupEventDetected
XMC_SCU_HIB_LPAC_ClearStatus
XMC_SCU_HIB_LPAC_GetStatus
XMC_SCU_HIB_LPAC_SetHIBIO0Thresholds
XMC_SCU_HIB_LPAC_SetHIBIO1Thresholds
XMC_SCU_HIB_LPAC_SetInput
XMC_SCU_HIB_LPAC_SetTiming
XMC_SCU_HIB_LPAC_SetTrigger
XMC_SCU_HIB_LPAC_SetVBATThresholds
XMC_SCU_HIB_LPAC_TriggerCompare
XMC_SCU_HIB_SetInput0
XMC_SCU_HIB_SetPinMode
XMC_SCU_HIB_SetPinOutputLevel
XMC_SCU_HIB_SetRtcClockSource
XMC_SCU_HIB_SetSR0Input
XMC_SCU_HIB_SetStandbyClockSource
XMC_SCU_HIB_SetWakeupTriggerInput
XMC_SCU_HIB_TriggerEvent
XMC_SCU_HighTemperature
XMC_SCU_INTERRUPT_DisableNmiRequest
XMC_SCU_INTERRUPT_EnableNmiRequest
XMC_SCU_IsTemperatureSensorBusy
XMC_SCU_IsTemperatureSensorEnabled
XMC_SCU_IsTemperatureSensorReady
XMC_SCU_LowTemperature
XMC_SCU_PARITY_ClearStatus
XMC_SCU_PARITY_Disable
XMC_SCU_PARITY_DisableTrapGeneration
XMC_SCU_PARITY_Enable
XMC_SCU_PARITY_EnableTrapGeneration
XMC_SCU_PARITY_GetStatus
XMC_SCU_POWER_DisableMonitor
XMC_SCU_POWER_DisableUsb
XMC_SCU_POWER_EnableMonitor
XMC_SCU_POWER_EnableUsb
XMC_SCU_POWER_GetEVR13Voltage
XMC_SCU_POWER_GetEVR33Voltage
XMC_SCU_POWER_GetEVRStatus
XMC_SCU_POWER_WaitForEvent
XMC_SCU_POWER_WaitForInterrupt
XMC_SCU_ReadFromRetentionMemory
XMC_SCU_ReadGPR
XMC_SCU_RESET_AssertPeripheralReset
XMC_SCU_RESET_DeassertPeripheralReset
XMC_SCU_RESET_IsPeripheralResetAsserted
XMC_SCU_SetBootMode
XMC_SCU_SetRawTempLimits
XMC_SCU_StartTemperatureMeasurement
XMC_SCU_TRAP_ClearStatus
XMC_SCU_TRAP_Disable
XMC_SCU_TRAP_Enable
XMC_SCU_TRAP_GetStatus
XMC_SCU_TRAP_Trigger
XMC_SCU_WriteGPR
XMC_SCU_WriteToRetentionMemory
xmc_can.h
CAN_MO_MOIPR_Msk
CAN_NODE_NIPR_Msk
XMC_CAN_MO_MOAR_STDID_Msk
XMC_CAN_MO_MOAR_STDID_Pos
XMC_CAN_NODE_t
XMC_CAN_t
XMC_CAN_ARBITRATION_MODE_t
XMC_CAN_ARBITRATION_MODE_ORDER_BASED_PRIO_1
XMC_CAN_ARBITRATION_MODE_IDE_DIR_BASED_PRIO_2
XMC_CAN_ARBITRATION_MODE_ORDER_BASED_PRIO_3
XMC_CAN_CANCLKSRC_t
XMC_CAN_DM_t
XMC_CAN_DM_NORMAL
XMC_CAN_DM_FRACTIONAL
XMC_CAN_DM_OFF
XMC_CAN_FRAME_COUNT_MODE_t
XMC_CAN_FRAME_COUNT_MODE
XMC_CAN_FRAME_COUNT_MODE_TIME_STAMP
XMC_CAN_FRAME_COUNT_MODE_BIT_TIMING
XMC_CAN_FRAME_TYPE_t
XMC_CAN_FRAME_TYPE_STANDARD_11BITS
XMC_CAN_FRAME_TYPE_EXTENDED_29BITS
XMC_CAN_LOOKBACKMODE_t
XMC_CAN_LOOKBACKMODE_ENABLED
XMC_CAN_LOOKBACKMODE_DISABLED
XMC_CAN_MO_EVENT_t
XMC_CAN_MO_EVENT_TRANSMIT
XMC_CAN_MO_EVENT_RECEIVE
XMC_CAN_MO_EVENT_OVERFLOW
XMC_CAN_MO_POINTER_EVENT_t
XMC_CAN_MO_POINTER_EVENT_TRANSMIT
XMC_CAN_MO_POINTER_EVENT_RECEIVE
XMC_CAN_MO_RESET_STATUS_t
XMC_CAN_MO_RESET_STATUS_RX_PENDING
XMC_CAN_MO_RESET_STATUS_TX_PENDING
XMC_CAN_MO_RESET_STATUS_RX_UPDATING
XMC_CAN_MO_RESET_STATUS_NEW_DATA
XMC_CAN_MO_RESET_STATUS_MESSAGE_LOST
XMC_CAN_MO_RESET_STATUS_MESSAGE_VALID
XMC_CAN_MO_RESET_STATUS_RX_TX_SELECTED
XMC_CAN_MO_RESET_STATUS_RX_ENABLE
XMC_CAN_MO_RESET_STATUS_TX_REQUEST
XMC_CAN_MO_RESET_STATUS_TX_ENABLE0
XMC_CAN_MO_RESET_STATUS_TX_ENABLE1
XMC_CAN_MO_RESET_STATUS_MESSAGE_DIRECTION
XMC_CAN_MO_SET_STATUS_t
XMC_CAN_MO_SET_STATUS_RX_PENDING
XMC_CAN_MO_SET_STATUS_TX_PENDING
XMC_CAN_MO_SET_STATUS_RX_UPDATING
XMC_CAN_MO_SET_STATUS_NEW_DATA
XMC_CAN_MO_SET_STATUS_MESSAGE_LOST
XMC_CAN_MO_SET_STATUS_MESSAGE_VALID
XMC_CAN_MO_SET_STATUS_RX_TX_SELECTED
XMC_CAN_MO_SET_STATUS_RX_ENABLE
XMC_CAN_MO_SET_STATUS_TX_REQUEST
XMC_CAN_MO_SET_STATUS_TX_ENABLE0
XMC_CAN_MO_SET_STATUS_TX_ENABLE1
XMC_CAN_MO_SET_STATUS_MESSAGE_DIRECTION
XMC_CAN_MO_STATUS_t
XMC_CAN_MO_STATUS_RX_PENDING
XMC_CAN_MO_STATUS_TX_PENDING
XMC_CAN_MO_STATUS_RX_UPDATING
XMC_CAN_MO_STATUS_NEW_DATA
XMC_CAN_MO_STATUS_MESSAGE_LOST
XMC_CAN_MO_STATUS_MESSAGE_VALID
XMC_CAN_MO_STATUS_RX_TX_SELECTED
XMC_CAN_MO_STATUS_RX_ENABLE
XMC_CAN_MO_STATUS_TX_REQUEST
XMC_CAN_MO_STATUS_TX_ENABLE0
XMC_CAN_MO_STATUS_TX_ENABLE1
XMC_CAN_MO_STATUS_MESSAGE_DIRECTION
XMC_CAN_MO_STATUS_LIST
XMC_CAN_MO_STATUS_POINTER_TO_PREVIOUS_MO
XMC_CAN_MO_STATUS_POINTER_TO_NEXT_MO
XMC_CAN_MO_TYPE_t
XMC_CAN_MO_TYPE_RECMSGOBJ
XMC_CAN_MO_TYPE_TRANSMSGOBJ
XMC_CAN_NODE_CONTROL_t
XMC_CAN_NODE_CONTROL_NODE_INIT
XMC_CAN_NODE_CONTROL_TX_INT_ENABLE
XMC_CAN_NODE_CONTROL_LEC_INT_ENABLE
XMC_CAN_NODE_CONTROL_ALERT_INT_ENABLE
XMC_CAN_NODE_CONTROL_CAN_DISABLE
XMC_CAN_NODE_CONTROL_CONF_CHANGE_ENABLE
XMC_CAN_NODE_CONTROL_CAN_ANALYZER_NODEDE
XMC_CAN_NODE_CONTROL_SUSPENDED_ENABLE
XMC_CAN_NODE_EVENT_t
XMC_CAN_NODE_EVENT_TX_INT
XMC_CAN_NODE_EVENT_ALERT
XMC_CAN_NODE_EVENT_LEC
XMC_CAN_NODE_EVENT_CFCIE
XMC_CAN_NODE_INTERRUPT_TRIGGER_t
XMC_CAN_NODE_LAST_ERROR_DIR_t
XMC_CAN_NODE_LAST_ERROR_DIR_WHILE_NODE_RECEPCION
XMC_CAN_NODE_LAST_ERROR_DIR_WHILE_NODE_TRANSMISSION
XMC_CAN_NODE_LAST_ERROR_INC_t
XMC_CAN_NODE_LAST_ERROR_INC_1
XMC_CAN_NODE_LAST_ERROR_INC_8
XMC_CAN_NODE_POINTER_EVENT_t
XMC_CAN_NODE_POINTER_EVENT_ALERT
XMC_CAN_NODE_POINTER_EVENT_LEC
XMC_CAN_NODE_POINTER_EVENT_TRANSFER_OK
XMC_CAN_NODE_POINTER_EVENT_FRAME_COUNTER
XMC_CAN_NODE_RECEIVE_INPUT_t
XMC_CAN_NODE_RECEIVE_INPUT_RXDCA
XMC_CAN_NODE_RECEIVE_INPUT_RXDCB
XMC_CAN_NODE_RECEIVE_INPUT_RXDCC
XMC_CAN_NODE_RECEIVE_INPUT_RXDCD
XMC_CAN_NODE_RECEIVE_INPUT_RXDCE
XMC_CAN_NODE_RECEIVE_INPUT_RXDCF
XMC_CAN_NODE_RECEIVE_INPUT_RXDCG
XMC_CAN_NODE_RECEIVE_INPUT_RXDCH
XMC_CAN_NODE_STATUS_t
XMC_CAN_NODE_STATUS_LAST_ERROR_CODE
XMC_CAN_NODE_STATUS_TX_OK
XMC_CAN_NODE_STATUS_RX_OK
XMC_CAN_NODE_STATUS_ALERT_WARNING
XMC_CAN_NODE_STATUS_ERROR_WARNING_STATUS
XMC_CAN_NODE_STATUS_BUS_OFF
XMC_CAN_NODE_STATUS_LIST_LENGTH_ERROR
XMC_CAN_NODE_STATUS_LIST_OBJECT_ERROR
XMC_CAN_NODE_STATUS_SUSPENDED_ACK
XMC_CAN_PANCMD_t
XMC_CAN_PANCMD_INIT_LIST
XMC_CAN_PANCMD_STATIC_ALLOCATE
XMC_CAN_PANCMD_DYNAMIC_ALLOCATE
XMC_CAN_PANCMD_STATIC_INSERT_BEFORE
XMC_CAN_PANCMD_DYNAMIC_INSERT_BEFORE
XMC_CAN_PANCMD_STATIC_INSERT_BEHIND
XMC_CAN_PANCMD_DYNAMIC_INSERT_BEHIND
XMC_CAN_STATUS_t
XMC_CAN_STATUS_SUCCESS
XMC_CAN_STATUS_ERROR
XMC_CAN_STATUS_BUSY
XMC_CAN_STATUS_MO_NOT_ACCEPTABLE
XMC_CAN_STATUS_MO_DISABLED
XMC_CAN_AllocateMOtoNodeList
XMC_CAN_Disable
XMC_CAN_Enable
XMC_CAN_EventTrigger
XMC_CAN_FIFO_DisableForeingRemoteRequest
XMC_CAN_FIFO_DisableRemoteMonitoring
XMC_CAN_FIFO_DisableSingleDataTransfer
XMC_CAN_FIFO_EnableForeignRemoteRequest
XMC_CAN_FIFO_EnableRemoteMonitoring
XMC_CAN_FIFO_EnableSingleDataTransfer
XMC_CAN_FIFO_GetCurrentMO
XMC_CAN_FIFO_SetSELMO
XMC_CAN_GATEWAY_InitDesObject
XMC_CAN_GATEWAY_InitSourceObject
XMC_CAN_Init
XMC_CAN_IsPanelControlReady
XMC_CAN_MO_AcceptOnlyMatchingIDE
XMC_CAN_MO_AcceptStandardAndExtendedID
XMC_CAN_MO_Config
XMC_CAN_MO_DataLengthCode
XMC_CAN_MO_DisableEvent
XMC_CAN_MO_DisableSingleTransmitTrial
XMC_CAN_MO_EnableEvent
XMC_CAN_MO_EnableSingleTransmitTrial
XMC_CAN_MO_GetAcceptanceMask
XMC_CAN_MO_GetDataLengthCode
XMC_CAN_MO_GetIdentifier
XMC_CAN_MO_GetStatus
XMC_CAN_MO_Receive
XMC_CAN_MO_ReceiveData
XMC_CAN_MO_ResetStatus
XMC_CAN_MO_SetAcceptanceMask
XMC_CAN_MO_SetDataLengthCode
XMC_CAN_MO_SetEventNodePointer
XMC_CAN_MO_SetExtendedID
XMC_CAN_MO_SetIdentifier
XMC_CAN_MO_SetStandardID
XMC_CAN_MO_SetStatus
XMC_CAN_MO_Transmit
XMC_CAN_MO_UpdateData
XMC_CAN_NODE_ClearStatus
XMC_CAN_NODE_Disable
XMC_CAN_NODE_DisableConfigurationChange
XMC_CAN_NODE_DisableEvent
XMC_CAN_NODE_DisableLoopBack
XMC_CAN_NODE_Enable
XMC_CAN_NODE_EnableConfigurationChange
XMC_CAN_NODE_EnableEvent
XMC_CAN_NODE_EnableLoopBack
XMC_CAN_NODE_EnableSuspend
XMC_CAN_NODE_FrameCounterConfigure
XMC_CAN_NODE_GetCANFrameCounter
XMC_CAN_NODE_GetErrorWarningLevel
XMC_CAN_NODE_GetLastErrTransferDir
XMC_CAN_NODE_GetLastErrTransferInc
XMC_CAN_NODE_GetReceiveErrorCounter
XMC_CAN_NODE_GetStatus
XMC_CAN_NODE_GetTransmitErrorCounter
XMC_CAN_NODE_NominalBitTimeConfigure
XMC_CAN_NODE_ReSetAnalyzerMode
XMC_CAN_NODE_ResetInitBit
XMC_CAN_NODE_SetAnalyzerMode
XMC_CAN_NODE_SetErrorWarningLevel
XMC_CAN_NODE_SetEventNodePointer
XMC_CAN_NODE_SetInitBit
XMC_CAN_NODE_SetReceiveErrorCounter
XMC_CAN_NODE_SetReceiveInput
XMC_CAN_NODE_SetTransmitErrorCounter
XMC_CAN_PanelControl
XMC_CAN_RXFIFO_ConfigMOBaseObject
XMC_CAN_RXFIFO_ConfigMOSlaveObject
XMC_CAN_TXFIFO_ConfigMOBaseObject
XMC_CAN_TXFIFO_ConfigMOSlaveObject
XMC_CAN_TXFIFO_Transmit
xmc_ccu4.h
XMC_CCU4_MODULE_t
XMC_CCU4_SLICE_INPUT_t
XMC_CCU4_SLICE_t
XMC_CCU4_CLOCK_t
XMC_CCU4_CLOCK_SCU
XMC_CCU4_CLOCK_EXTERNAL_A
XMC_CCU4_CLOCK_EXTERNAL_B
XMC_CCU4_CLOCK_EXTERNAL_C
XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_t
XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_SW_SLICE0
XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_SW_MCSS_SLICE0
XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_SW_SLICE1
XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_SW_MCSS_SLICE1
XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_SW_SLICE2
XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_SW_MCSS_SLICE2
XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_SW_SLICE3
XMC_CCU4_MULTI_CHANNEL_SHADOW_TRANSFER_SW_MCSS_SLICE3
XMC_CCU4_SHADOW_TRANSFER_t
XMC_CCU4_SHADOW_TRANSFER_SLICE_0
XMC_CCU4_SHADOW_TRANSFER_DITHER_SLICE_0
XMC_CCU4_SHADOW_TRANSFER_PRESCALER_SLICE_0
XMC_CCU4_SHADOW_TRANSFER_SLICE_1
XMC_CCU4_SHADOW_TRANSFER_DITHER_SLICE_1
XMC_CCU4_SHADOW_TRANSFER_PRESCALER_SLICE_1
XMC_CCU4_SHADOW_TRANSFER_SLICE_2
XMC_CCU4_SHADOW_TRANSFER_DITHER_SLICE_2
XMC_CCU4_SHADOW_TRANSFER_PRESCALER_SLICE_2
XMC_CCU4_SHADOW_TRANSFER_SLICE_3
XMC_CCU4_SHADOW_TRANSFER_DITHER_SLICE_3
XMC_CCU4_SHADOW_TRANSFER_PRESCALER_SLICE_3
XMC_CCU4_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_t
XMC_CCU4_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_PERIOD_SHADOW
XMC_CCU4_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_COMPARE_SHADOW
XMC_CCU4_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_PASSIVE_LEVEL
XMC_CCU4_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_DITHER_SHADOW
XMC_CCU4_SLICE_AUTOMAIC_SHADOW_TRANSFER_WRITE_INTO_FLOATING_PRESCALER_SHADOW
XMC_CCU4_SLICE_CAP_REG_SET_t
XMC_CCU4_SLICE_CAP_REG_SET_LOW
XMC_CCU4_SLICE_CAP_REG_SET_HIGH
XMC_CCU4_SLICE_END_MODE_t
XMC_CCU4_SLICE_END_MODE_TIMER_STOP
XMC_CCU4_SLICE_END_MODE_TIMER_CLEAR
XMC_CCU4_SLICE_END_MODE_TIMER_STOP_CLEAR
XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_t
XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_NONE
XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_RISING_EDGE
XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_FALLING_EDGE
XMC_CCU4_SLICE_EVENT_EDGE_SENSITIVITY_DUAL_EDGE
XMC_CCU4_SLICE_EVENT_FILTER_t
XMC_CCU4_SLICE_EVENT_FILTER_DISABLED
XMC_CCU4_SLICE_EVENT_FILTER_3_CYCLES
XMC_CCU4_SLICE_EVENT_FILTER_5_CYCLES
XMC_CCU4_SLICE_EVENT_FILTER_7_CYCLES
XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_t
XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_HIGH
XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_LOW
XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_COUNT_UP_ON_LOW
XMC_CCU4_SLICE_EVENT_LEVEL_SENSITIVITY_COUNT_UP_ON_HIGH
XMC_CCU4_SLICE_EVENT_t
XMC_CCU4_SLICE_EVENT_NONE
XMC_CCU4_SLICE_EVENT_0
XMC_CCU4_SLICE_EVENT_1
XMC_CCU4_SLICE_EVENT_2
XMC_CCU4_SLICE_FUNCTION_t
XMC_CCU4_SLICE_FUNCTION_START
XMC_CCU4_SLICE_FUNCTION_STOP
XMC_CCU4_SLICE_FUNCTION_CAPTURE_EVENT0
XMC_CCU4_SLICE_FUNCTION_CAPTURE_EVENT1
XMC_CCU4_SLICE_FUNCTION_GATING
XMC_CCU4_SLICE_FUNCTION_DIRECTION
XMC_CCU4_SLICE_FUNCTION_LOAD
XMC_CCU4_SLICE_FUNCTION_COUNT
XMC_CCU4_SLICE_FUNCTION_OVERRIDE
XMC_CCU4_SLICE_FUNCTION_MODULATION
XMC_CCU4_SLICE_FUNCTION_TRAP
XMC_CCU4_SLICE_IRQ_ID_t
XMC_CCU4_SLICE_IRQ_ID_PERIOD_MATCH
XMC_CCU4_SLICE_IRQ_ID_ONE_MATCH
XMC_CCU4_SLICE_IRQ_ID_COMPARE_MATCH_UP
XMC_CCU4_SLICE_IRQ_ID_COMPARE_MATCH_DOWN
XMC_CCU4_SLICE_IRQ_ID_EVENT0
XMC_CCU4_SLICE_IRQ_ID_EVENT1
XMC_CCU4_SLICE_IRQ_ID_EVENT2
XMC_CCU4_SLICE_IRQ_ID_TRAP
XMC_CCU4_SLICE_MASK_t
XMC_CCU4_SLICE_MASK_SLICE_0
XMC_CCU4_SLICE_MASK_SLICE_1
XMC_CCU4_SLICE_MASK_SLICE_2
XMC_CCU4_SLICE_MASK_SLICE_3
XMC_CCU4_SLICE_MCMS_ACTION_t
XMC_CCU4_SLICE_MCMS_ACTION_TRANSFER_PR_CR
XMC_CCU4_SLICE_MCMS_ACTION_TRANSFER_PR_CR_PCMP
XMC_CCU4_SLICE_MCMS_ACTION_TRANSFER_PR_CR_PCMP_DIT
XMC_CCU4_SLICE_MODE_t
XMC_CCU4_SLICE_MODE_COMPARE
XMC_CCU4_SLICE_MODE_CAPTURE
XMC_CCU4_SLICE_MODULATION_MODE_t
XMC_CCU4_SLICE_MODULATION_MODE_CLEAR_ST_OUT
XMC_CCU4_SLICE_MODULATION_MODE_CLEAR_OUT
XMC_CCU4_SLICE_MULTI_IRQ_ID_t
XMC_CCU4_SLICE_MULTI_IRQ_ID_PERIOD_MATCH
XMC_CCU4_SLICE_MULTI_IRQ_ID_ONE_MATCH
XMC_CCU4_SLICE_MULTI_IRQ_ID_COMPARE_MATCH_UP
XMC_CCU4_SLICE_MULTI_IRQ_ID_COMPARE_MATCH_DOWN
XMC_CCU4_SLICE_MULTI_IRQ_ID_EVENT0
XMC_CCU4_SLICE_MULTI_IRQ_ID_EVENT1
XMC_CCU4_SLICE_MULTI_IRQ_ID_EVENT2
XMC_CCU4_SLICE_OUTPUT_PASSIVE_LEVEL_t
XMC_CCU4_SLICE_OUTPUT_PASSIVE_LEVEL_LOW
XMC_CCU4_SLICE_OUTPUT_PASSIVE_LEVEL_HIGH
XMC_CCU4_SLICE_PRESCALER_MODE_t
XMC_CCU4_SLICE_PRESCALER_MODE_NORMAL
XMC_CCU4_SLICE_PRESCALER_MODE_FLOAT
XMC_CCU4_SLICE_PRESCALER_t
XMC_CCU4_SLICE_PRESCALER_1
XMC_CCU4_SLICE_PRESCALER_2
XMC_CCU4_SLICE_PRESCALER_4
XMC_CCU4_SLICE_PRESCALER_8
XMC_CCU4_SLICE_PRESCALER_16
XMC_CCU4_SLICE_PRESCALER_32
XMC_CCU4_SLICE_PRESCALER_64
XMC_CCU4_SLICE_PRESCALER_128
XMC_CCU4_SLICE_PRESCALER_256
XMC_CCU4_SLICE_PRESCALER_512
XMC_CCU4_SLICE_PRESCALER_1024
XMC_CCU4_SLICE_PRESCALER_2048
XMC_CCU4_SLICE_PRESCALER_4096
XMC_CCU4_SLICE_PRESCALER_8192
XMC_CCU4_SLICE_PRESCALER_16384
XMC_CCU4_SLICE_PRESCALER_32768
XMC_CCU4_SLICE_SHADOW_TRANSFER_MODE_t
XMC_CCU4_SLICE_SHADOW_TRANSFER_MODE_IN_PERIOD_MATCH_AND_ONE_MATCH
XMC_CCU4_SLICE_SHADOW_TRANSFER_MODE_ONLY_IN_PERIOD_MATCH
XMC_CCU4_SLICE_SHADOW_TRANSFER_MODE_ONLY_IN_ONE_MATCH
XMC_CCU4_SLICE_SR_ID_t
XMC_CCU4_SLICE_SR_ID_0
XMC_CCU4_SLICE_SR_ID_1
XMC_CCU4_SLICE_SR_ID_2
XMC_CCU4_SLICE_SR_ID_3
XMC_CCU4_SLICE_START_MODE_t
XMC_CCU4_SLICE_START_MODE_TIMER_START
XMC_CCU4_SLICE_START_MODE_TIMER_START_CLEAR
XMC_CCU4_SLICE_TIMER_CLEAR_MODE_t
XMC_CCU4_SLICE_TIMER_CLEAR_MODE_NEVER
XMC_CCU4_SLICE_TIMER_CLEAR_MODE_CAP_HIGH
XMC_CCU4_SLICE_TIMER_CLEAR_MODE_CAP_LOW
XMC_CCU4_SLICE_TIMER_CLEAR_MODE_ALWAYS
XMC_CCU4_SLICE_TIMER_COUNT_DIR_t
XMC_CCU4_SLICE_TIMER_COUNT_DIR_UP
XMC_CCU4_SLICE_TIMER_COUNT_DIR_DOWN
XMC_CCU4_SLICE_TIMER_COUNT_MODE_t
XMC_CCU4_SLICE_TIMER_COUNT_MODE_EA
XMC_CCU4_SLICE_TIMER_COUNT_MODE_CA
XMC_CCU4_SLICE_TIMER_REPEAT_MODE_t
XMC_CCU4_SLICE_TIMER_REPEAT_MODE_REPEAT
XMC_CCU4_SLICE_TIMER_REPEAT_MODE_SINGLE
XMC_CCU4_SLICE_TRAP_EXIT_MODE_t
XMC_CCU4_SLICE_TRAP_EXIT_MODE_AUTOMATIC
XMC_CCU4_SLICE_TRAP_EXIT_MODE_SW
XMC_CCU4_SLICE_WRITE_INTO_t
XMC_CCU4_SLICE_WRITE_INTO_PERIOD_CONFIGURATION
XMC_CCU4_SLICE_WRITE_INTO_COMPARE_CONFIGURATION
XMC_CCU4_SLICE_WRITE_INTO_PASSIVE_LEVEL_CONFIGURATION
XMC_CCU4_SLICE_WRITE_INTO_DITHER_VALUE_CONFIGURATION
XMC_CCU4_SLICE_WRITE_INTO_FLOATING_PRESCALER_VALUE_CONFIGURATION
XMC_CCU4_STATUS_t
XMC_CCU4_STATUS_OK
XMC_CCU4_STATUS_ERROR
XMC_CCU4_STATUS_RUNNING
XMC_CCU4_STATUS_IDLE
XMC_CCU4_DisableClock
XMC_CCU4_DisableModule
XMC_CCU4_EnableClock
XMC_CCU4_EnableModule
XMC_CCU4_EnableMultipleClocks
XMC_CCU4_EnableShadowTransfer
XMC_CCU4_Init
XMC_CCU4_IsPrescalerRunning
XMC_CCU4_SetModuleClock
XMC_CCU4_SetMultiChannelShadowTransferMode
XMC_CCU4_SLICE_Capture0Config
XMC_CCU4_SLICE_Capture1Config
XMC_CCU4_SLICE_CaptureInit
XMC_CCU4_SLICE_ClearEvent
XMC_CCU4_SLICE_ClearTimer
XMC_CCU4_SLICE_CompareInit
XMC_CCU4_SLICE_ConfigureEvent
XMC_CCU4_SLICE_ConfigureStatusBitOverrideEvent
XMC_CCU4_SLICE_CountConfig
XMC_CCU4_SLICE_DirectionConfig
XMC_CCU4_SLICE_DisableAutomaticShadowTransferRequest
XMC_CCU4_SLICE_DisableCascadedShadowTransfer
XMC_CCU4_SLICE_DisableDithering
XMC_CCU4_SLICE_DisableEvent
XMC_CCU4_SLICE_DisableFloatingPrescaler
XMC_CCU4_SLICE_DisableMultiChannelMode
XMC_CCU4_SLICE_DisableMultipleEvents
XMC_CCU4_SLICE_DisableTrap
XMC_CCU4_SLICE_EnableAutomaticShadowTransferRequest
XMC_CCU4_SLICE_EnableCascadedShadowTransfer
XMC_CCU4_SLICE_EnableDithering
XMC_CCU4_SLICE_EnableEvent
XMC_CCU4_SLICE_EnableFloatingPrescaler
XMC_CCU4_SLICE_EnableMultiChannelMode
XMC_CCU4_SLICE_EnableMultipleEvents
XMC_CCU4_SLICE_EnableTrap
XMC_CCU4_SLICE_GateConfig
XMC_CCU4_SLICE_GetCapturedValueFromFifo
XMC_CCU4_SLICE_GetCaptureRegisterValue
XMC_CCU4_SLICE_GetCountingDir
XMC_CCU4_SLICE_GetEvent
XMC_CCU4_SLICE_GetLastCapturedTimerValue
XMC_CCU4_SLICE_GetSliceMode
XMC_CCU4_SLICE_GetTimerCompareMatch
XMC_CCU4_SLICE_GetTimerCountingMode
XMC_CCU4_SLICE_GetTimerPeriodMatch
XMC_CCU4_SLICE_GetTimerRepeatMode
XMC_CCU4_SLICE_GetTimerValue
XMC_CCU4_SLICE_IsExtendedCapReadEnabled
XMC_CCU4_SLICE_IsTimerRunning
XMC_CCU4_SLICE_LoadConfig
XMC_CCU4_SLICE_ModulationConfig
XMC_CCU4_SLICE_SetDitherCompareValue
XMC_CCU4_SLICE_SetEvent
XMC_CCU4_SLICE_SetFloatingPrescalerCompareValue
XMC_CCU4_SLICE_SetInput
XMC_CCU4_SLICE_SetInterruptNode
XMC_CCU4_SLICE_SetPassiveLevel
XMC_CCU4_SLICE_SetPrescaler
XMC_CCU4_SLICE_SetShadowTransferMode
XMC_CCU4_SLICE_SetTimerCompareMatch
XMC_CCU4_SLICE_SetTimerCountingMode
XMC_CCU4_SLICE_SetTimerPeriodMatch
XMC_CCU4_SLICE_SetTimerRepeatMode
XMC_CCU4_SLICE_SetTimerValue
XMC_CCU4_SLICE_StartConfig
XMC_CCU4_SLICE_StartTimer
XMC_CCU4_SLICE_StatusBitOverrideConfig
XMC_CCU4_SLICE_StopClearTimer
XMC_CCU4_SLICE_StopConfig
XMC_CCU4_SLICE_StopTimer
XMC_CCU4_SLICE_TrapConfig
XMC_CCU4_SLICE_WriteCoherentlyWithPWMCycle
XMC_CCU4_SLICE_WriteImmediateAfterShadowTransfer
XMC_CCU4_StartPrescaler
XMC_CCU4_StopPrescaler
xmc_ccu8.h
XMC_CCU8_MODULE_t
XMC_CCU8_SLICE_INPUT_t
XMC_CCU8_SLICE_t
XMC_CCU8_CLOCK_t
XMC_CCU8_CLOCK_SCU
XMC_CCU8_CLOCK_EXTERNAL_A
XMC_CCU8_CLOCK_EXTERNAL_B
XMC_CCU8_CLOCK_EXTERNAL_C
XMC_CCU8_MULTI_CHANNEL_SHADOW_TRANSFER_t
XMC_CCU8_MULTI_CHANNEL_SHADOW_TRANSFER_SW_SLICE0
XMC_CCU8_MULTI_CHANNEL_SHADOW_TRANSFER_SW_MCSS_SLICE0
XMC_CCU8_MULTI_CHANNEL_SHADOW_TRANSFER_SW_SLICE1
XMC_CCU8_MULTI_CHANNEL_SHADOW_TRANSFER_SW_MCSS_SLICE1
XMC_CCU8_MULTI_CHANNEL_SHADOW_TRANSFER_SW_SLICE2
XMC_CCU8_MULTI_CHANNEL_SHADOW_TRANSFER_SW_MCSS_SLICE2
XMC_CCU8_MULTI_CHANNEL_SHADOW_TRANSFER_SW_SLICE3
XMC_CCU8_MULTI_CHANNEL_SHADOW_TRANSFER_SW_MCSS_SLICE3
XMC_CCU8_OUT_PATH_t
XMC_CCU8_OUT_PATH_OUT0_ST1
XMC_CCU8_OUT_PATH_OUT0_INV_ST1
XMC_CCU8_OUT_PATH_OUT1_ST1
XMC_CCU8_OUT_PATH_OUT1_INV_ST1
XMC_CCU8_OUT_PATH_OUT2_ST2
XMC_CCU8_OUT_PATH_OUT2_INV_ST2
XMC_CCU8_OUT_PATH_OUT3_ST2
XMC_CCU8_OUT_PATH_OUT3_INV_ST1
XMC_CCU8_SHADOW_TRANSFER_t
XMC_CCU8_SHADOW_TRANSFER_SLICE_0
XMC_CCU8_SHADOW_TRANSFER_DITHER_SLICE_0
XMC_CCU8_SHADOW_TRANSFER_PRESCALER_SLICE_0
XMC_CCU8_SHADOW_TRANSFER_SLICE_1
XMC_CCU8_SHADOW_TRANSFER_DITHER_SLICE_1
XMC_CCU8_SHADOW_TRANSFER_PRESCALER_SLICE_1
XMC_CCU8_SHADOW_TRANSFER_SLICE_2
XMC_CCU8_SHADOW_TRANSFER_DITHER_SLICE_2
XMC_CCU8_SHADOW_TRANSFER_PRESCALER_SLICE_2
XMC_CCU8_SHADOW_TRANSFER_SLICE_3
XMC_CCU8_SHADOW_TRANSFER_DITHER_SLICE_3
XMC_CCU8_SHADOW_TRANSFER_PRESCALER_SLICE_3
XMC_CCU8_SLICE_CAP_REG_SET_t
XMC_CCU8_SLICE_CAP_REG_SET_LOW
XMC_CCU8_SLICE_CAP_REG_SET_HIGH
XMC_CCU8_SLICE_COMPARE_CHANNEL_t
XMC_CCU8_SLICE_COMPARE_CHANNEL_1
XMC_CCU8_SLICE_COMPARE_CHANNEL_2
XMC_CCU8_SLICE_DTC_DIV_t
XMC_CCU8_SLICE_DTC_DIV_1
XMC_CCU8_SLICE_DTC_DIV_2
XMC_CCU8_SLICE_DTC_DIV_4
XMC_CCU8_SLICE_DTC_DIV_8
XMC_CCU8_SLICE_END_MODE_t
XMC_CCU8_SLICE_END_MODE_TIMER_STOP
XMC_CCU8_SLICE_END_MODE_TIMER_CLEAR
XMC_CCU8_SLICE_END_MODE_TIMER_STOP_CLEAR
XMC_CCU8_SLICE_EVENT_EDGE_SENSITIVITY_t
XMC_CCU8_SLICE_EVENT_EDGE_SENSITIVITY_NONE
XMC_CCU8_SLICE_EVENT_EDGE_SENSITIVITY_RISING_EDGE
XMC_CCU8_SLICE_EVENT_EDGE_SENSITIVITY_FALLING_EDGE
XMC_CCU8_SLICE_EVENT_EDGE_SENSITIVITY_DUAL_EDGE
XMC_CCU8_SLICE_EVENT_FILTER_t
XMC_CCU8_SLICE_EVENT_FILTER_DISABLED
XMC_CCU8_SLICE_EVENT_FILTER_3_CYCLES
XMC_CCU8_SLICE_EVENT_FILTER_5_CYCLES
XMC_CCU8_SLICE_EVENT_FILTER_7_CYCLES
XMC_CCU8_SLICE_EVENT_LEVEL_SENSITIVITY_t
XMC_CCU8_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_HIGH
XMC_CCU8_SLICE_EVENT_LEVEL_SENSITIVITY_ACTIVE_LOW
XMC_CCU8_SLICE_EVENT_LEVEL_SENSITIVITY_COUNT_UP_ON_LOW
XMC_CCU8_SLICE_EVENT_LEVEL_SENSITIVITY_COUNT_UP_ON_HIGH
XMC_CCU8_SLICE_EVENT_t
XMC_CCU8_SLICE_EVENT_NONE
XMC_CCU8_SLICE_EVENT_0
XMC_CCU8_SLICE_EVENT_1
XMC_CCU8_SLICE_EVENT_2
XMC_CCU8_SLICE_FUNCTION_t
XMC_CCU8_SLICE_FUNCTION_START
XMC_CCU8_SLICE_FUNCTION_STOP
XMC_CCU8_SLICE_FUNCTION_CAPTURE_EVENT0
XMC_CCU8_SLICE_FUNCTION_CAPTURE_EVENT1
XMC_CCU8_SLICE_FUNCTION_GATING
XMC_CCU8_SLICE_FUNCTION_DIRECTION
XMC_CCU8_SLICE_FUNCTION_LOAD
XMC_CCU8_SLICE_FUNCTION_COUNT
XMC_CCU8_SLICE_FUNCTION_OVERRIDE
XMC_CCU8_SLICE_FUNCTION_MODULATION
XMC_CCU8_SLICE_FUNCTION_TRAP
XMC_CCU8_SLICE_IRQ_ID_t
XMC_CCU8_SLICE_IRQ_ID_PERIOD_MATCH
XMC_CCU8_SLICE_IRQ_ID_ONE_MATCH
XMC_CCU8_SLICE_IRQ_ID_COMPARE_MATCH_UP_CH_1
XMC_CCU8_SLICE_IRQ_ID_COMPARE_MATCH_DOWN_CH_1
XMC_CCU8_SLICE_IRQ_ID_COMPARE_MATCH_UP_CH_2
XMC_CCU8_SLICE_IRQ_ID_COMPARE_MATCH_DOWN_CH_2
XMC_CCU8_SLICE_IRQ_ID_EVENT0
XMC_CCU8_SLICE_IRQ_ID_EVENT1
XMC_CCU8_SLICE_IRQ_ID_EVENT2
XMC_CCU8_SLICE_IRQ_ID_TRAP
XMC_CCU8_SLICE_MASK_t
XMC_CCU8_SLICE_MASK_SLICE_0
XMC_CCU8_SLICE_MASK_SLICE_1
XMC_CCU8_SLICE_MASK_SLICE_2
XMC_CCU8_SLICE_MASK_SLICE_3
XMC_CCU8_SLICE_MCMS_ACTION_t
XMC_CCU8_SLICE_MCMS_ACTION_TRANSFER_PR_CR
XMC_CCU8_SLICE_MCMS_ACTION_TRANSFER_PR_CR_PCMP
XMC_CCU8_SLICE_MCMS_ACTION_TRANSFER_PR_CR_PCMP_DIT
XMC_CCU8_SLICE_MODE_t
XMC_CCU8_SLICE_MODE_COMPARE
XMC_CCU8_SLICE_MODE_CAPTURE
XMC_CCU8_SLICE_MODULATION_CHANNEL_t
XMC_CCU8_SLICE_MODULATION_CHANNEL_NONE
XMC_CCU8_SLICE_MODULATION_CHANNEL_1
XMC_CCU8_SLICE_MODULATION_CHANNEL_2
XMC_CCU8_SLICE_MODULATION_CHANNEL_1_AND_2
XMC_CCU8_SLICE_MODULATION_MODE_t
XMC_CCU8_SLICE_MODULATION_MODE_CLEAR_ST_OUT
XMC_CCU8_SLICE_MODULATION_MODE_CLEAR_OUT
XMC_CCU8_SLICE_MULTI_IRQ_ID_t
XMC_CCU8_SLICE_MULTI_IRQ_ID_PERIOD_MATCH
XMC_CCU8_SLICE_MULTI_IRQ_ID_ONE_MATCH
XMC_CCU8_SLICE_MULTI_IRQ_ID_COMPARE_MATCH_UP_CH_1
XMC_CCU8_SLICE_MULTI_IRQ_ID_COMPARE_MATCH_DOWN_CH_1
XMC_CCU8_SLICE_MULTI_IRQ_ID_COMPARE_MATCH_UP_CH_2
XMC_CCU8_SLICE_MULTI_IRQ_ID_COMPARE_MATCH_DOWN_CH_2
XMC_CCU8_SLICE_MULTI_IRQ_ID_EVENT0
XMC_CCU8_SLICE_MULTI_IRQ_ID_EVENT1
XMC_CCU8_SLICE_MULTI_IRQ_ID_EVENT2
XMC_CCU8_SLICE_OUTPUT_PASSIVE_LEVEL_t
XMC_CCU8_SLICE_OUTPUT_PASSIVE_LEVEL_LOW
XMC_CCU8_SLICE_OUTPUT_PASSIVE_LEVEL_HIGH
XMC_CCU8_SLICE_OUTPUT_t
XMC_CCU8_SLICE_OUTPUT_0
XMC_CCU8_SLICE_OUTPUT_1
XMC_CCU8_SLICE_OUTPUT_2
XMC_CCU8_SLICE_OUTPUT_3
XMC_CCU8_SLICE_PRESCALER_MODE_t
XMC_CCU8_SLICE_PRESCALER_MODE_NORMAL
XMC_CCU8_SLICE_PRESCALER_MODE_FLOAT
XMC_CCU8_SLICE_PRESCALER_t
XMC_CCU8_SLICE_PRESCALER_1
XMC_CCU8_SLICE_PRESCALER_2
XMC_CCU8_SLICE_PRESCALER_4
XMC_CCU8_SLICE_PRESCALER_8
XMC_CCU8_SLICE_PRESCALER_16
XMC_CCU8_SLICE_PRESCALER_32
XMC_CCU8_SLICE_PRESCALER_64
XMC_CCU8_SLICE_PRESCALER_128
XMC_CCU8_SLICE_PRESCALER_256
XMC_CCU8_SLICE_PRESCALER_512
XMC_CCU8_SLICE_PRESCALER_1024
XMC_CCU8_SLICE_PRESCALER_2048
XMC_CCU8_SLICE_PRESCALER_4096
XMC_CCU8_SLICE_PRESCALER_8192
XMC_CCU8_SLICE_PRESCALER_16384
XMC_CCU8_SLICE_PRESCALER_32768
XMC_CCU8_SLICE_SHADOW_TRANSFER_MODE_t
XMC_CCU8_SLICE_SHADOW_TRANSFER_MODE_IN_PERIOD_MATCH_AND_ONE_MATCH
XMC_CCU8_SLICE_SHADOW_TRANSFER_MODE_ONLY_IN_PERIOD_MATCH
XMC_CCU8_SLICE_SHADOW_TRANSFER_MODE_ONLY_IN_ONE_MATCH
XMC_CCU8_SLICE_SR_ID_t
XMC_CCU8_SLICE_SR_ID_0
XMC_CCU8_SLICE_SR_ID_1
XMC_CCU8_SLICE_SR_ID_2
XMC_CCU8_SLICE_SR_ID_3
XMC_CCU8_SLICE_START_MODE_t
XMC_CCU8_SLICE_START_MODE_TIMER_START
XMC_CCU8_SLICE_START_MODE_TIMER_START_CLEAR
XMC_CCU8_SLICE_STATUS_t
XMC_CCU8_SLICE_STATUS_CHANNEL_1
XMC_CCU8_SLICE_STATUS_CHANNEL_2
XMC_CCU8_SLICE_STATUS_CHANNEL_1_AND_2
XMC_CCU8_SLICE_STATUS_CHANNEL_1_OR_2
XMC_CCU8_SLICE_TIMER_CLEAR_MODE_t
XMC_CCU8_SLICE_TIMER_CLEAR_MODE_NEVER
XMC_CCU8_SLICE_TIMER_CLEAR_MODE_CAP_HIGH
XMC_CCU8_SLICE_TIMER_CLEAR_MODE_CAP_LOW
XMC_CCU8_SLICE_TIMER_CLEAR_MODE_ALWAYS
XMC_CCU8_SLICE_TIMER_COUNT_DIR_t
XMC_CCU8_SLICE_TIMER_COUNT_DIR_UP
XMC_CCU8_SLICE_TIMER_COUNT_DIR_DOWN
XMC_CCU8_SLICE_TIMER_COUNT_MODE_t
XMC_CCU8_SLICE_TIMER_COUNT_MODE_EA
XMC_CCU8_SLICE_TIMER_COUNT_MODE_CA
XMC_CCU8_SLICE_TIMER_REPEAT_MODE_t
XMC_CCU8_SLICE_TIMER_REPEAT_MODE_REPEAT
XMC_CCU8_SLICE_TIMER_REPEAT_MODE_SINGLE
XMC_CCU8_SLICE_TRAP_EXIT_MODE_t
XMC_CCU8_SLICE_TRAP_EXIT_MODE_AUTOMATIC
XMC_CCU8_SLICE_TRAP_EXIT_MODE_SW
XMC_CCU8_SOURCE_OUT0_t
XMC_CCU8_SOURCE_OUT0_ST1
XMC_CCU8_SOURCE_OUT0_INV_ST1
XMC_CCU8_SOURCE_OUT0_ST2
XMC_CCU8_SOURCE_OUT0_INV_ST2
XMC_CCU8_SOURCE_OUT1_t
XMC_CCU8_SOURCE_OUT1_ST1
XMC_CCU8_SOURCE_OUT1_INV_ST1
XMC_CCU8_SOURCE_OUT1_ST2
XMC_CCU8_SOURCE_OUT1_INV_ST2
XMC_CCU8_SOURCE_OUT2_t
XMC_CCU8_SOURCE_OUT2_ST2
XMC_CCU8_SOURCE_OUT2_INV_ST2
XMC_CCU8_SOURCE_OUT2_ST1
XMC_CCU8_SOURCE_OUT2_INV_ST1
XMC_CCU8_SOURCE_OUT3_t
XMC_CCU8_SOURCE_OUT3_ST2
XMC_CCU8_SOURCE_OUT3_INV_ST2
XMC_CCU8_SOURCE_OUT3_ST1
XMC_CCU8_SOURCE_OUT3_INV_ST1
XMC_CCU8_STATUS_t
XMC_CCU8_STATUS_OK
XMC_CCU8_STATUS_ERROR
XMC_CCU8_STATUS_RUNNING
XMC_CCU8_STATUS_IDLE
XMC_CCU8_DisableClock
XMC_CCU8_DisableModule
XMC_CCU8_EnableClock
XMC_CCU8_EnableModule
XMC_CCU8_EnableMultipleClocks
XMC_CCU8_EnableShadowTransfer
XMC_CCU8_Init
XMC_CCU8_IsPrescalerRunning
XMC_CCU8_SetModuleClock
XMC_CCU8_SetMultiChannelShadowTransferMode
XMC_CCU8_SLICE_Capture0Config
XMC_CCU8_SLICE_Capture1Config
XMC_CCU8_SLICE_CaptureInit
XMC_CCU8_SLICE_ClearEvent
XMC_CCU8_SLICE_ClearTimer
XMC_CCU8_SLICE_CompareInit
XMC_CCU8_SLICE_ConfigureDeadTime
XMC_CCU8_SLICE_ConfigureEvent
XMC_CCU8_SLICE_ConfigureStatusBitOutput
XMC_CCU8_SLICE_ConfigureStatusBitOverrideEvent
XMC_CCU8_SLICE_CountConfig
XMC_CCU8_SLICE_DeadTimeInit
XMC_CCU8_SLICE_DirectionConfig
XMC_CCU8_SLICE_DisableAutomaticShadowTransferRequest
XMC_CCU8_SLICE_DisableCascadedShadowTransfer
XMC_CCU8_SLICE_DisableDithering
XMC_CCU8_SLICE_DisableEvent
XMC_CCU8_SLICE_DisableFloatingPrescaler
XMC_CCU8_SLICE_DisableMultiChannelMode
XMC_CCU8_SLICE_DisableMultipleEvents
XMC_CCU8_SLICE_DisableTrap
XMC_CCU8_SLICE_EnableAsymmetricCompareMode
XMC_CCU8_SLICE_EnableAutomaticShadowTransferRequest
XMC_CCU8_SLICE_EnableCascadedShadowTransfer
XMC_CCU8_SLICE_EnableDithering
XMC_CCU8_SLICE_EnableEvent
XMC_CCU8_SLICE_EnableFloatingPrescaler
XMC_CCU8_SLICE_EnableMultiChannelMode
XMC_CCU8_SLICE_EnableMultipleEvents
XMC_CCU8_SLICE_EnableSymmetricCompareMode
XMC_CCU8_SLICE_EnableTrap
XMC_CCU8_SLICE_GateConfig
XMC_CCU8_SLICE_GetCapturedValueFromFifo
XMC_CCU8_SLICE_GetCaptureRegisterValue
XMC_CCU8_SLICE_GetCountingDir
XMC_CCU8_SLICE_GetEvent
XMC_CCU8_SLICE_GetLastCapturedTimerValue
XMC_CCU8_SLICE_GetSliceMode
XMC_CCU8_SLICE_GetTimerCompareMatch
XMC_CCU8_SLICE_GetTimerCountingMode
XMC_CCU8_SLICE_GetTimerPeriodMatch
XMC_CCU8_SLICE_GetTimerRepeatMode
XMC_CCU8_SLICE_GetTimerValue
XMC_CCU8_SLICE_IsDeadTimeCntr1Running
XMC_CCU8_SLICE_IsDeadTimeCntr2Running
XMC_CCU8_SLICE_IsExtendedCapReadEnabled
XMC_CCU8_SLICE_IsTimerRunning
XMC_CCU8_SLICE_LoadConfig
XMC_CCU8_SLICE_LoadSelector
XMC_CCU8_SLICE_ModulationConfig
XMC_CCU8_SLICE_SetDeadTimePrescaler
XMC_CCU8_SLICE_SetDeadTimeValue
XMC_CCU8_SLICE_SetDitherCompareValue
XMC_CCU8_SLICE_SetEvent
XMC_CCU8_SLICE_SetFloatingPrescalerCompareValue
XMC_CCU8_SLICE_SetInput
XMC_CCU8_SLICE_SetInterruptNode
XMC_CCU8_SLICE_SetOutPath
XMC_CCU8_SLICE_SetPassiveLevel
XMC_CCU8_SLICE_SetPrescaler
XMC_CCU8_SLICE_SetShadowTransferMode
XMC_CCU8_SLICE_SetTimerCompareMatch
XMC_CCU8_SLICE_SetTimerCompareMatchChannel1
XMC_CCU8_SLICE_SetTimerCompareMatchChannel2
XMC_CCU8_SLICE_SetTimerCountingMode
XMC_CCU8_SLICE_SetTimerPeriodMatch
XMC_CCU8_SLICE_SetTimerRepeatMode
XMC_CCU8_SLICE_SetTimerValue
XMC_CCU8_SLICE_StartConfig
XMC_CCU8_SLICE_StartTimer
XMC_CCU8_SLICE_StatusBitOverrideConfig
XMC_CCU8_SLICE_StopClearTimer
XMC_CCU8_SLICE_StopConfig
XMC_CCU8_SLICE_StopTimer
XMC_CCU8_SLICE_TrapConfig
XMC_CCU8_SLICE_WriteCoherentlyWithPWMCycle
XMC_CCU8_SLICE_WriteImmediateAfterShadowTransfer
XMC_CCU8_StartPrescaler
XMC_CCU8_StopPrescaler
xmc_dac.h
XMC_DAC0
XMC_DAC_NO_CHANNELS
XMC_DAC_PATTERN_RECTANGLE
XMC_DAC_PATTERN_SINE
XMC_DAC_PATTERN_TRIANGLE
XMC_DAC_SAMPLES_PER_PERIOD
XMC_DAC_CH_DATA_TYPE_t
XMC_DAC_CH_DATA_TYPE_UNSIGNED
XMC_DAC_CH_DATA_TYPE_SIGNED
XMC_DAC_CH_MODE_t
XMC_DAC_CH_MODE_IDLE
XMC_DAC_CH_MODE_SINGLE
XMC_DAC_CH_MODE_DATA
XMC_DAC_CH_MODE_PATTERN
XMC_DAC_CH_MODE_NOISE
XMC_DAC_CH_MODE_RAMP
XMC_DAC_CH_OUTPUT_NEGATION_t
XMC_DAC_CH_OUTPUT_NEGATION_DISABLED
XMC_DAC_CH_OUTPUT_NEGATION_ENABLED
XMC_DAC_CH_OUTPUT_SCALE_t
XMC_DAC_CH_OUTPUT_SCALE_NONE
XMC_DAC_CH_OUTPUT_SCALE_MUL_2
XMC_DAC_CH_OUTPUT_SCALE_MUL_4
XMC_DAC_CH_OUTPUT_SCALE_MUL_8
XMC_DAC_CH_OUTPUT_SCALE_MUL_16
XMC_DAC_CH_OUTPUT_SCALE_MUL_32
XMC_DAC_CH_OUTPUT_SCALE_MUL_64
XMC_DAC_CH_OUTPUT_SCALE_MUL_128
XMC_DAC_CH_OUTPUT_SCALE_DIV_2
XMC_DAC_CH_OUTPUT_SCALE_DIV_4
XMC_DAC_CH_OUTPUT_SCALE_DIV_8
XMC_DAC_CH_OUTPUT_SCALE_DIV_16
XMC_DAC_CH_OUTPUT_SCALE_DIV_32
XMC_DAC_CH_OUTPUT_SCALE_DIV_64
XMC_DAC_CH_OUTPUT_SCALE_DIV_128
XMC_DAC_CH_PATTERN_SIGN_OUTPUT_t
XMC_DAC_CH_PATTERN_SIGN_OUTPUT_DISABLED
XMC_DAC_CH_PATTERN_SIGN_OUTPUT_ENABLED
XMC_DAC_CH_STATUS_t
XMC_DAC_CH_STATUS_OK
XMC_DAC_CH_STATUS_ERROR
XMC_DAC_CH_STATUS_BUSY
XMC_DAC_CH_STATUS_ERROR_FREQ2LOW
XMC_DAC_CH_STATUS_ERROR_FREQ2HIGH
XMC_DAC_CH_TRIGGER_t
XMC_DAC_CH_TRIGGER_INTERNAL
XMC_DAC_CH_TRIGGER_EXTERNAL_CCU80_SR1
XMC_DAC_CH_TRIGGER_EXTERNAL_CCU40_SR1
XMC_DAC_CH_TRIGGER_EXTERNAL_CCU41_SR1
XMC_DAC_CH_TRIGGER_EXTERNAL_P2_9
XMC_DAC_CH_TRIGGER_EXTERNAL_P2_8
XMC_DAC_CH_TRIGGER_EXTERNAL_U0C0_DX1INS
XMC_DAC_CH_TRIGGER_EXTERNAL_U1C0_DX1INS
XMC_DAC_CH_TRIGGER_SOFTWARE
XMC_DAC_CH_DisableEvent
XMC_DAC_CH_DisableOutput
XMC_DAC_CH_DisableOutputNegation
XMC_DAC_CH_DisablePatternSignOutput
XMC_DAC_CH_EnableEvent
XMC_DAC_CH_EnableOutput
XMC_DAC_CH_EnableOutputNegation
XMC_DAC_CH_EnablePatternSignOutput
XMC_DAC_CH_GetOutputScale
XMC_DAC_CH_GetRampStart
XMC_DAC_CH_GetRampStop
XMC_DAC_CH_Init
XMC_DAC_CH_IsFifoEmpty
XMC_DAC_CH_IsFifoFull
XMC_DAC_CH_IsOutputEnabled
XMC_DAC_CH_SetFrequency
XMC_DAC_CH_SetMode
XMC_DAC_CH_SetOutputOffset
XMC_DAC_CH_SetOutputScale
XMC_DAC_CH_SetPattern
XMC_DAC_CH_SetPatternFrequency
XMC_DAC_CH_SetRampFrequency
XMC_DAC_CH_SetRampStart
XMC_DAC_CH_SetRampStop
XMC_DAC_CH_SetSignedDataType
XMC_DAC_CH_SetTrigger
XMC_DAC_CH_SetUnsignedDataType
XMC_DAC_CH_SoftwareTrigger
XMC_DAC_CH_StartDataMode
XMC_DAC_CH_StartNoiseMode
XMC_DAC_CH_StartPatternMode
XMC_DAC_CH_StartRampMode
XMC_DAC_CH_StartSingleValueMode
XMC_DAC_CH_Write
XMC_DAC_Disable
XMC_DAC_DisableSimultaneousDataMode
XMC_DAC_Enable
XMC_DAC_EnableSimultaneousDataMode
XMC_DAC_IsEnabled
XMC_DAC_SimultaneousWrite
xmc_dma.h
XMC_DMA0
XMC_DMA1
XMC_DMA_CH_EVENT_HANDLER_t
XMC_DMA_LIST_t
XMC_DMA_CH_ADDRESS_COUNT_MODE_t
XMC_DMA_CH_ADDRESS_COUNT_MODE_INCREMENT
XMC_DMA_CH_ADDRESS_COUNT_MODE_DECREMENT
XMC_DMA_CH_ADDRESS_COUNT_MODE_NO_CHANGE
XMC_DMA_CH_BURST_LENGTH_t
XMC_DMA_CH_BURST_LENGTH_1
XMC_DMA_CH_BURST_LENGTH_4
XMC_DMA_CH_BURST_LENGTH_8
XMC_DMA_CH_DST_HANDSHAKING_t
XMC_DMA_CH_DST_HANDSHAKING_HARDWARE
XMC_DMA_CH_DST_HANDSHAKING_SOFTWARE
XMC_DMA_CH_EVENT_t
XMC_DMA_CH_EVENT_TRANSFER_COMPLETE
XMC_DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE
XMC_DMA_CH_EVENT_SRC_TRANSACTION_COMPLETE
XMC_DMA_CH_EVENT_DST_TRANSACTION_COMPLETE
XMC_DMA_CH_EVENT_ERROR
XMC_DMA_CH_HARDWARE_HANDSHAKING_IF_t
XMC_DMA_CH_HARDWARE_HANDSHAKING_IF_0
XMC_DMA_CH_HARDWARE_HANDSHAKING_IF_1
XMC_DMA_CH_HARDWARE_HANDSHAKING_IF_2
XMC_DMA_CH_HARDWARE_HANDSHAKING_IF_3
XMC_DMA_CH_HARDWARE_HANDSHAKING_IF_4
XMC_DMA_CH_HARDWARE_HANDSHAKING_IF_5
XMC_DMA_CH_HARDWARE_HANDSHAKING_IF_6
XMC_DMA_CH_HARDWARE_HANDSHAKING_IF_7
XMC_DMA_CH_PRIORITY_t
XMC_DMA_CH_PRIORITY_0
XMC_DMA_CH_PRIORITY_1
XMC_DMA_CH_PRIORITY_2
XMC_DMA_CH_PRIORITY_3
XMC_DMA_CH_PRIORITY_4
XMC_DMA_CH_PRIORITY_5
XMC_DMA_CH_PRIORITY_6
XMC_DMA_CH_PRIORITY_7
XMC_DMA_CH_SRC_HANDSHAKING_t
XMC_DMA_CH_SRC_HANDSHAKING_HARDWARE
XMC_DMA_CH_SRC_HANDSHAKING_SOFTWARE
XMC_DMA_CH_STATUS_t
XMC_DMA_CH_STATUS_OK
XMC_DMA_CH_STATUS_ERROR
XMC_DMA_CH_STATUS_BUSY
XMC_DMA_CH_TRANSACTION_TYPE_t
XMC_DMA_CH_TRANSACTION_TYPE_SINGLE
XMC_DMA_CH_TRANSACTION_TYPE_BURST
XMC_DMA_CH_TRANSFER_FLOW_t
XMC_DMA_CH_TRANSFER_FLOW_M2M_DMA
XMC_DMA_CH_TRANSFER_FLOW_M2P_DMA
XMC_DMA_CH_TRANSFER_FLOW_P2M_DMA
XMC_DMA_CH_TRANSFER_FLOW_P2P_DMA
XMC_DMA_CH_TRANSFER_FLOW_P2M_PER
XMC_DMA_CH_TRANSFER_FLOW_P2P_SRCPER
XMC_DMA_CH_TRANSFER_FLOW_M2P_PER
XMC_DMA_CH_TRANSFER_FLOW_P2P_DSTPER
XMC_DMA_CH_TRANSFER_TYPE_t
XMC_DMA_CH_TRANSFER_TYPE_SINGLE_BLOCK
XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_CONTIGUOUS_DSTADR_RELOAD
XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_RELOAD_DSTADR_CONTIGUOUS
XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_RELOAD_DSTADR_RELOAD
XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_CONTIGUOUS_DSTADR_LINKED
XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_RELOAD_DSTADR_LINKED
XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_LINKED_DSTADR_CONTIGUOUS
XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_LINKED_DSTADR_RELOAD
XMC_DMA_CH_TRANSFER_TYPE_MULTI_BLOCK_SRCADR_LINKED_DSTADR_LINKED
XMC_DMA_CH_TRANSFER_WIDTH_t
XMC_DMA_CH_TRANSFER_WIDTH_8
XMC_DMA_CH_TRANSFER_WIDTH_16
XMC_DMA_CH_TRANSFER_WIDTH_32
XMC_DMA_CH_ClearDestinationPeripheralRequest
XMC_DMA_CH_ClearEventStatus
XMC_DMA_CH_ClearSourcePeripheralRequest
XMC_DMA_CH_Disable
XMC_DMA_CH_DisableDestinationAddressReload
XMC_DMA_CH_DisableDestinationScatter
XMC_DMA_CH_DisableEvent
XMC_DMA_CH_DisableSourceAddressReload
XMC_DMA_CH_DisableSourceGather
XMC_DMA_CH_Enable
XMC_DMA_CH_EnableDestinationAddressReload
XMC_DMA_CH_EnableDestinationScatter
XMC_DMA_CH_EnableEvent
XMC_DMA_CH_EnableSourceAddressReload
XMC_DMA_CH_EnableSourceGather
XMC_DMA_CH_GetEventStatus
XMC_DMA_CH_Init
XMC_DMA_CH_IsEnabled
XMC_DMA_CH_IsSuspended
XMC_DMA_CH_RequestLastMultiblockTransfer
XMC_DMA_CH_Resume
XMC_DMA_CH_SetBlockSize
XMC_DMA_CH_SetDestinationAddress
XMC_DMA_CH_SetEventHandler
XMC_DMA_CH_SetLinkedListPointer
XMC_DMA_CH_SetSourceAddress
XMC_DMA_CH_Suspend
XMC_DMA_CH_TriggerDestinationRequest
XMC_DMA_CH_TriggerSourceRequest
XMC_DMA_ClearOverrunStatus
XMC_DMA_ClearRequestLine
XMC_DMA_Disable
XMC_DMA_DisableRequestLine
XMC_DMA_Enable
XMC_DMA_EnableRequestLine
XMC_DMA_GetChannelsBlockCompleteStatus
XMC_DMA_GetChannelsDestinationTransactionCompleteStatus
XMC_DMA_GetChannelsErrorStatus
XMC_DMA_GetChannelsSourceTransactionCompleteStatus
XMC_DMA_GetChannelsTransferCompleteStatus
XMC_DMA_GetEventStatus
XMC_DMA_GetOverrunStatus
XMC_DMA_Init
XMC_DMA_IRQHandler
XMC_DMA_IsEnabled
xmc_dsd.h
XMC_DSD_CH_t
XMC_DSD_t
XMC_DSD_CH_AUX_EVENT_t
XMC_DSD_CH_AUX_EVENT_DISABLED
XMC_DSD_CH_AUX_EVENT_EVERY_NEW_RESULT
XMC_DSD_CH_AUX_EVENT_CAPTURE_SIGN_DELAY
XMC_DSD_CH_AUX_EVENT_INSIDE_BOUNDARY
XMC_DSD_CH_AUX_EVENT_OUTSIDE_BOUNDARY
XMC_DSD_CH_CLK_t
XMC_DSD_CH_CLK_DIV_2
XMC_DSD_CH_CLK_DIV_4
XMC_DSD_CH_CLK_DIV_6
XMC_DSD_CH_CLK_DIV_8
XMC_DSD_CH_CLK_DIV_10
XMC_DSD_CH_CLK_DIV_12
XMC_DSD_CH_CLK_DIV_14
XMC_DSD_CH_CLK_DIV_16
XMC_DSD_CH_CLK_DIV_18
XMC_DSD_CH_CLK_DIV_20
XMC_DSD_CH_CLK_DIV_22
XMC_DSD_CH_CLK_DIV_24
XMC_DSD_CH_CLK_DIV_26
XMC_DSD_CH_CLK_DIV_28
XMC_DSD_CH_CLK_DIV_30
XMC_DSD_CH_CLK_DIV_32
XMC_DSD_CH_CLOCK_SOURCE_t
XMC_DSD_CH_CLOCK_SOURCE_A
XMC_DSD_CH_CLOCK_SOURCE_B
XMC_DSD_CH_CLOCK_SOURCE_C
XMC_DSD_CH_CLOCK_SOURCE_D
XMC_DSD_CH_CLOCK_SOURCE_INTERN
XMC_DSD_CH_DATA_SOURCE_t
XMC_DSD_CH_DATA_SOURCE_DISCONNECT
XMC_DSD_CH_DATA_SOURCE_A_DIRECT
XMC_DSD_CH_DATA_SOURCE_A_INVERTED
XMC_DSD_CH_DATA_SOURCE_B_DIRECT
XMC_DSD_CH_DATA_SOURCE_B_INVERTED
XMC_DSD_CH_FILTER_TYPE_t
XMC_DSD_CH_FILTER_TYPE_CIC1
XMC_DSD_CH_FILTER_TYPE_CIC2
XMC_DSD_CH_FILTER_TYPE_CIC3
XMC_DSD_CH_FILTER_TYPE_CICF
XMC_DSD_CH_ID_t
XMC_DSD_CH_ID_0
XMC_DSD_CH_ID_1
XMC_DSD_CH_ID_2
XMC_DSD_CH_ID_3
XMC_DSD_CH_INTEGRATOR_START_t
XMC_DSD_CH_INTEGRATOR_START_OFF
XMC_DSD_CH_INTEGRATOR_START_TRIGGER_FALL
XMC_DSD_CH_INTEGRATOR_START_TRIGGER_RISE
XMC_DSD_CH_INTEGRATOR_START_ALLWAYS_ON
XMC_DSD_CH_INTEGRATOR_STOP_t
XMC_DSD_CH_INTEGRATOR_STOP_END_OF_LOOPS
XMC_DSD_CH_INTEGRATOR_STOP_ENDLESS_OR_INVERSE_TRIGGER
XMC_DSD_CH_RESULT_EVENT_t
XMC_DSD_CH_RESULT_EVENT_DISABLE
XMC_DSD_CH_RESULT_EVENT_ENABLE
XMC_DSD_CH_SIGN_SOURCE_t
XMC_DSD_CH_SIGN_SOURCE_ON_CHIP_GENERATOR
XMC_DSD_CH_SIGN_SOURCE_NEXT_CHANNEL
XMC_DSD_CH_SIGN_SOURCE_EXTERNAL_A
XMC_DSD_CH_SIGN_SOURCE_EXTERNAL_B
XMC_DSD_CH_STROBE_t
XMC_DSD_CH_TIMESTAMP_TRIGGER_t
XMC_DSD_CH_TIMESTAMP_TRIGGER_DISABLE
XMC_DSD_CH_TIMESTAMP_TRIGGER_FALL
XMC_DSD_CH_TIMESTAMP_TRIGGER_RISE
XMC_DSD_CH_TIMESTAMP_TRIGGER_BOTH_EDGES
XMC_DSD_CH_TRIGGER_SOURCE_t
XMC_DSD_CH_TRIGGER_SOURCE_A
XMC_DSD_CH_TRIGGER_SOURCE_B
XMC_DSD_CH_TRIGGER_SOURCE_C
XMC_DSD_CH_TRIGGER_SOURCE_D
XMC_DSD_CH_TRIGGER_SOURCE_E
XMC_DSD_CH_TRIGGER_SOURCE_F
XMC_DSD_CH_TRIGGER_SOURCE_G
XMC_DSD_CH_TRIGGER_SOURCE_H
XMC_DSD_GENERATOR_CLKDIV_t
XMC_DSD_GENERATOR_CLKDIV_2048
XMC_DSD_GENERATOR_CLKDIV_4096
XMC_DSD_GENERATOR_CLKDIV_6144
XMC_DSD_GENERATOR_CLKDIV_8192
XMC_DSD_GENERATOR_CLKDIV_10240
XMC_DSD_GENERATOR_CLKDIV_12288
XMC_DSD_GENERATOR_CLKDIV_14336
XMC_DSD_GENERATOR_CLKDIV_16384
XMC_DSD_GENERATOR_CLKDIV_18432
XMC_DSD_GENERATOR_CLKDIV_20480
XMC_DSD_GENERATOR_CLKDIV_22528
XMC_DSD_GENERATOR_CLKDIV_24576
XMC_DSD_GENERATOR_CLKDIV_26624
XMC_DSD_GENERATOR_CLKDIV_28672
XMC_DSD_GENERATOR_CLKDIV_30720
XMC_DSD_GENERATOR_CLKDIV_32768
XMC_DSD_GENERATOR_MODE_t
XMC_DSD_GENERATOR_MODE_STOPPED
XMC_DSD_GENERATOR_MODE_RECTANGLE
XMC_DSD_GENERATOR_MODE_TRIANGLE
XMC_DSD_GENERATOR_MODE_SINE
XMC_DSD_STATUS_t
XMC_DSD_STATUS_OK
XMC_DSD_STATUS_ERROR
XMC_DSD_CH_AuxFilter_DisableEvent
XMC_DSD_CH_AuxFilter_EnableEvent
XMC_DSD_CH_AuxFilter_Init
XMC_DSD_CH_AuxFilter_SetBoundary
XMC_DSD_CH_GetRectifyDelay
XMC_DSD_CH_GetResult
XMC_DSD_CH_GetResult_AUX
XMC_DSD_CH_GetResult_TS
XMC_DSD_CH_GetResult_TS_Time
XMC_DSD_CH_Init
XMC_DSD_CH_Integrator_Init
XMC_DSD_CH_MainFilter_DisableEvent
XMC_DSD_CH_MainFilter_EnableEvent
XMC_DSD_CH_MainFilter_Init
XMC_DSD_CH_MainFilter_SetOffset
XMC_DSD_CH_Rectify_Init
XMC_DSD_CH_Timestamp_Init
XMC_DSD_ClearAlarmEventFlag
XMC_DSD_ClearResultEventFlag
XMC_DSD_Disable
XMC_DSD_DisableClock
XMC_DSD_Enable
XMC_DSD_EnableClock
XMC_DSD_Generator_Init
XMC_DSD_Generator_Start
XMC_DSD_Generator_Stop
XMC_DSD_Init
XMC_DSD_IsChannelStarted
XMC_DSD_IsEnabled
XMC_DSD_SetAlarmEventFlag
XMC_DSD_SetResultEventFlag
XMC_DSD_Start
XMC_DSD_Stop
xmc_ebu.h
XMC_EBU
XMC_EBU_ADDRESS_SELECT_t
XMC_EBU_ADDRESS_SELECT_MEMORY_REGION_ENABLE
XMC_EBU_ADDRESS_SELECT_ALTERNATE_REGION_ENABLE
XMC_EBU_ADDRESS_SELECT_MEMORY_REGION_WRITE_PROTECT
XMC_EBU_ALE_MODE_t
XMC_EBU_ALE_OUTPUT_IS_INV_ADV
XMC_EBU_ALE_OUTPUT_IS_ALE
XMC_EBU_ARB_MODE_t
XMC_EBU_ARB_MODE_NOT_SELECTED
XMC_EBU_ARB_MODE_ARBITER_MODE
XMC_EBU_ARB_MODE_PARTICIPANT_MODE
XMC_EBU_ARB_MODE_SOLE_MASTER_MODE
XMC_EBU_ASYNCHRONOUS_ADDRESS_PHASE_t
XMC_EBU_ASYNCHRONOUS_ADDRESS_PHASE_CLOCK_ENABLED_AT_BEGINNING_OF_ACCESS
XMC_EBU_ASYNCHRONOUS_ADDRESS_PHASE_CLOCK_ENABLED_AFTER_ADDRESS_PHASE
XMC_EBU_BURST_ADDRESS_WRAPPING_t
XMC_EBU_BURST_ADDRESS_WRAPPING_DISABLED
XMC_EBU_BURST_ADDRESS_WRAPPING_ENABLED
XMC_EBU_BURST_BUFFER_SYNC_MODE_t
XMC_EBU_BURST_BUFFER_SYNC_LENGTH_SYNC_ENABLE
XMC_EBU_BURST_BUFFER_SYNC_SINGLE_MODE
XMC_EBU_BURST_FLASH_CLOCK_FEEDBACK_t
XMC_EBU_BURST_FLASH_CLOCK_FEEDBACK_DISABLE
XMC_EBU_BURST_FLASH_CLOCK_FEEDBACK_ENABLE
XMC_EBU_BURST_FLASH_CLOCK_MODE_t
XMC_EBU_BURST_FLASH_CLOCK_MODE_RUN_CONTINUOSLY
XMC_EBU_BURST_FLASH_CLOCK_MODE_DISABLED_BETWEEN_ACCESSES
XMC_EBU_BURST_LENGTH_SYNC_t
XMC_EBU_BURST_LENGTH_SYNC_1_DATA_ACCESS
XMC_EBU_BURST_LENGTH_SYNC_2_DATA_ACCESSES
XMC_EBU_BURST_LENGTH_SYNC_4_DATA_ACCESSES
XMC_EBU_BURST_LENGTH_SYNC_8_DATA_ACCESSES
XMC_EBU_BURST_SIGNAL_SYNC_BURST_t
XMC_EBU_BURST_SIGNAL_SYNC_BURST_ADV_DELAYED
XMC_EBU_BURST_SIGNAL_SYNC_BURST_ADV_NOT_DELAYED
XMC_EBU_BUSWCON_SELECT_t
XMC_EBU_BUSWCON_SELECT_NAN_WORKAROUND
XMC_EBU_BUSWCON_SELECT_DEVICE_ADDRESSING_MODE
XMC_EBU_BYTE_CONTROL_t
XMC_EBU_BYTE_CONTROL_FOLLOWS_CHIP_SELECT_TIMMING
XMC_EBU_BYTE_CONTROL_FOLLOWS_CONTROL_SIGNAL_TIMMING
XMC_EBU_BYTE_CONTROL_FOLLOWS_WRITE_ENABLE_SIGNAL_TIMMING
XMC_EBU_CLK_MODE_t
XMC_EBU_CLK_MODE_ASYNCHRONOUS_TO_AHB
XMC_EBU_CLK_MODE_SYNCHRONOUS_TO_CPU
XMC_EBU_CLK_STATUS_t
XMC_EBU_CLK_STATUS_DISABLE_BIT
XMC_EBU_CLK_STATUS_MODE
XMC_EBU_CLK_STATUS_DIV2_MODE
XMC_EBU_CLK_STATUS_DIV_RATIO
XMC_EBU_CLOCK_DIVIDE_RATIO_t
XMC_EBU_CLOCK_DIVIDED_BY_1
XMC_EBU_CLOCK_DIVIDED_BY_2
XMC_EBU_CLOCK_DIVIDED_BY_3
XMC_EBU_CLOCK_DIVIDED_BY_4
XMC_EBU_DEVICE_ADDRESSING_MODE_t
XMC_EBU_DEVICE_ADDRESSING_MODE_16_BITS
XMC_EBU_DEVICE_ADDRESSING_MODE_TWIN_16_BITS_MULTIPLEXED
XMC_EBU_DEVICE_ADDRESSING_MODE_32_BITS_MULTIPLEXED
XMC_EBU_DEVICE_TYPE_t
XMC_EBU_DEVICE_TYPE_MUXED_ASYNCHRONOUS_TYPE
XMC_EBU_DEVICE_TYPE_MUXED_BURST_TYPE
XMC_EBU_DEVICE_TYPE_NAND_FLASH
XMC_EBU_DEVICE_TYPE_MUXED_CELLULAR_RAM
XMC_EBU_DEVICE_TYPE_DEMUXED_ASYNCHRONOUS_TYPE
XMC_EBU_DEVICE_TYPE_DEMUXED_BURST_TYPE
XMC_EBU_DEVICE_TYPE_DEMUXED_PAGE_MODE
XMC_EBU_DEVICE_TYPE_DEMUXED_CELLULAR_RAM
XMC_EBU_DEVICE_TYPE_SDRAM
XMC_EBU_DIV2_CLK_MODE_t
XMC_EBU_DIV2_CLK_MODE_OFF
XMC_EBU_DIV2_CLK_MODE_ON
XMC_EBU_EARLY_CHIP_SELECT_SYNC_BURST_t
XMC_EBU_EARLY_CHIP_SELECT_DELAYED
XMC_EBU_EARLY_CHIP_SELECT_NOT_DELAYED
XMC_EBU_EXT_DATA_t
XMC_EBU_EXT_DATA_OUTPUT_EVERY_1_BFCLK_CYCLES
XMC_EBU_EXT_DATA_OUTPUT_EVERY_2_BFCLK_CYCLES
XMC_EBU_EXT_DATA_OUTPUT_EVERY_4_BFCLK_CYCLES
XMC_EBU_EXT_DATA_OUTPUT_EVERY_8_BFCLK_CYCLES
XMC_EBU_FLASH_NON_ARRAY_ACCESS_t
XMC_EBU_FLASH_NON_ARRAY_ACCESS_DISNABLE
XMC_EBU_FLASH_NON_ARRAY_ACCESS_ENABLE
XMC_EBU_FREQ_EXT_CLK_PIN_t
XMC_EBU_FREQ_EXT_CLK_PIN_EQUAL_TO_INT_CLK
XMC_EBU_FREQ_EXT_CLK_PIN_HALF_OF_INT_CLK
XMC_EBU_FREQ_EXT_CLK_PIN_THIRD_OF_INT_CLK
XMC_EBU_FREQ_EXT_CLK_PIN_QUARTER_OF_INT_CLK
XMC_EBU_LOCK_CHIP_SELECT_t
XMC_EBU_LOCK_CHIP_SELECT_DISABLED
XMC_EBU_LOCK_CHIP_SELECT_ENABLED
XMC_EBU_READ_STAGES_SYNC_t
XMC_EBU_READ_STAGES_SYNC_TWO
XMC_EBU_READ_STAGES_SYNC_ONE
XMC_EBU_SDRAM_BURST_LENGTH_t
XMC_EBU_SDRAM_BURST_LENGTH_1_LOCATION
XMC_EBU_SDRAM_BURST_LENGTH_2_LOCATION
XMC_EBU_SDRAM_BURST_LENGTH_4_LOCATION
XMC_EBU_SDRAM_BURST_LENGTH_8_LOCATION
XMC_EBU_SDRAM_BURST_LENGTH_16_LOCATION
XMC_EBU_SDRAM_CAS_LATENCY_t
XMC_EBU_SDRAM_CAS_LATENCY_2_CLKS
XMC_EBU_SDRAM_CAS_LATENCY_3_CLKS
XMC_EBU_SDRAM_CLK_MODE_t
XMC_EBU_SDRAM_CLK_MODE_CONTINUOUSLY_RUNS
XMC_EBU_SDRAM_CLK_MODE_DISABLED_BETWEEN_ACCESSES
XMC_EBU_SDRAM_CLK_OUTPUT_t
XMC_EBU_SDRAM_CLK_OUTPUT_ENABLED
XMC_EBU_SDRAM_CLK_OUTPUT_DISABLED
XMC_EBU_SDRAM_MASK_FOR_BANK_TAG_t
XMC_EBU_SDRAM_MASK_FOR_BANK_TAG_ADDRESS_21_to_20
XMC_EBU_SDRAM_MASK_FOR_BANK_TAG_ADDRESS_22_to_21
XMC_EBU_SDRAM_MASK_FOR_BANK_TAG_ADDRESS_23_to_22
XMC_EBU_SDRAM_MASK_FOR_BANK_TAG_ADDRESS_24_to_23
XMC_EBU_SDRAM_MASK_FOR_BANK_TAG_ADDRESS_25_to_24
XMC_EBU_SDRAM_MASK_FOR_BANK_TAG_ADDRESS_26_to_25
XMC_EBU_SDRAM_MASK_FOR_BANK_TAG_ADDRESS_26
XMC_EBU_SDRAM_MASK_FOR_ROW_TAG_t
XMC_EBU_SDRAM_MASK_FOR_ROW_TAG_ADDRESS_26_to_9
XMC_EBU_SDRAM_MASK_FOR_ROW_TAG_ADDRESS_26_to_10
XMC_EBU_SDRAM_MASK_FOR_ROW_TAG_ADDRESS_26_to_11
XMC_EBU_SDRAM_MASK_FOR_ROW_TAG_ADDRESS_26_to_12
XMC_EBU_SDRAM_MASK_FOR_ROW_TAG_ADDRESS_26_to_13
XMC_EBU_SDRAM_PWR_MODE_t
XMC_EBU_SDRAM_PWR_MODE_PRECHARGE_BEFORE_CLK_STOP
XMC_EBU_SDRAM_PWR_MODE_AUTO_PRECHARGE_BEFORE_CLK_STOP
XMC_EBU_SDRAM_PWR_MODE_ACTIVE_PWR_DOWN
XMC_EBU_SDRAM_PWR_MODE_CLK_STOP_PWR_DOWN
XMC_EBU_SDRAM_RFRSH_STATUS_t
XMC_EBU_SDRAM_RFRSH_STATUS_SELF_REFRESH_ENTRY_STATUS
XMC_EBU_SDRAM_RFRSH_STATUS_SELF_REFRESH_EXIT_STATUS
XMC_EBU_SDRAM_STATUS_t
XMC_EBU_SDRAM_STATUS_RX_ERROR
XMC_EBU_SDRAM_STATUS_BUSY
XMC_EBU_SDRAM_STATUS_REFRESH_ERROR
XMC_EBU_SDRAM_WIDTH_OF_COLUMN_ADDRESS_t
XMC_EBU_SDRAM_WIDTH_OF_COLUMN_ADDRESS_8_to_0
XMC_EBU_SDRAM_WIDTH_OF_COLUMN_ADDRESS_9_to_0
XMC_EBU_SDRAM_WIDTH_OF_COLUMN_ADDRESS_10_to_0
XMC_EBU_STATUS_t
XMC_EBU_STATUS_OK
XMC_EBU_STATUS_BUSY
XMC_EBU_STATUS_ERROR
XMC_EBU_WAIT_CONTROL_t
XMC_EBU_WAIT_CONTROL_OFF
XMC_EBU_WAIT_CONTROL_SYNC_EARLY_WAIT_ASYNC_ASYNC_INPUT_AT_WAIT
XMC_EBU_WAIT_CONTROL_SYNC_WAIT_WITH_DATA_ASYNC_SYNC_INPUT_AT_WAIT
XMC_EBU_WAIT_CONTROL_SYNC_ABORT_AND_RETRY_ACCESS
XMC_EBU_WAIT_SIGNAL_POLARITY_t
XMC_EBU_WAIT_SIGNAL_POLARITY_PIN_ACTIVE_LOW
XMC_EBU_WAIT_SIGNAL_POLARITY_PIN_ACTIVE_HIGH
XMC_EBU_AddressSelectDisable
XMC_EBU_AddressSelectEnable
XMC_EBU_CLKDivideRatio
XMC_EBU_ConfigureRegion
XMC_EBU_ConfigureSdram
XMC_EBU_Disable
XMC_EBU_Enable
XMC_EBU_GetBusWriteConfStatus
XMC_EBU_GetCLKStatus
XMC_EBU_Init
XMC_EBU_IsBusAribitrationSelected
XMC_EBU_SdramDisableAutomaticSelfRefresh
XMC_EBU_SdramDisableAutoRefreshSelfRefreshExit
XMC_EBU_SdramEnableAutomaticSelfRefresh
XMC_EBU_SdramEnableAutoRefreshSelfRefreshExit
XMC_EBU_SdramGetRefreshStatus
XMC_EBU_SdramGetStatus
XMC_EBU_SdramResetSelfRefreshEntry
XMC_EBU_SdramResetSelfRefreshExit
XMC_EBU_SdramSetSelfRefreshEntry
XMC_EBU_SdramSetSelfRefreshExit
xmc_ecat.h
XMC_ECAT_EVENT_t
XMC_ECAT_EVENT_AL_CONTROL
XMC_ECAT_EVENT_DC_LATCH
XMC_ECAT_EVENT_DC_SYNC0
XMC_ECAT_EVENT_DC_SYNC1
XMC_ECAT_EVENT_SM_ACTIVATION_REGISTER
XMC_ECAT_EVENT_EEPROM
XMC_ECAT_EVENT_WATCHDOG
XMC_ECAT_EVENT_SM0
XMC_ECAT_EVENT_SM1
XMC_ECAT_EVENT_SM2
XMC_ECAT_EVENT_SM3
XMC_ECAT_EVENT_SM4
XMC_ECAT_EVENT_SM5
XMC_ECAT_EVENT_SM6
XMC_ECAT_EVENT_SM7
XMC_ECAT_STATUS_t
XMC_ECAT_STATUS_OK
XMC_ECAT_STATUS_BUSY
XMC_ECAT_STATUS_ERROR
XMC_ECAT_Disable
XMC_ECAT_DisableEvent
XMC_ECAT_DisableSyncManChannel
XMC_ECAT_Enable
XMC_ECAT_EnableEvent
XMC_ECAT_EnableSyncManChannel
XMC_ECAT_GetALEventMask
XMC_ECAT_GetALEventRegister
XMC_ECAT_GetEventStatus
XMC_ECAT_Init
XMC_ECAT_ReadPhy
XMC_ECAT_SetALEventMask
XMC_ECAT_SetPortControl
XMC_ECAT_WritePhy
xmc_eru.h
XMC_ERU_ETL_EDGE_DETECTION_t
XMC_ERU_ETL_EDGE_DETECTION_DISABLED
XMC_ERU_ETL_EDGE_DETECTION_RISING
XMC_ERU_ETL_EDGE_DETECTION_FALLING
XMC_ERU_ETL_EDGE_DETECTION_BOTH
XMC_ERU_ETL_INPUT_A_t
XMC_ERU_ETL_INPUT_A0
XMC_ERU_ETL_INPUT_A1
XMC_ERU_ETL_INPUT_A2
XMC_ERU_ETL_INPUT_A3
XMC_ERU_ETL_INPUT_B_t
XMC_ERU_ETL_INPUT_B0
XMC_ERU_ETL_INPUT_B1
XMC_ERU_ETL_INPUT_B2
XMC_ERU_ETL_INPUT_B3
XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL_t
XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL0
XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL1
XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL2
XMC_ERU_ETL_OUTPUT_TRIGGER_CHANNEL3
XMC_ERU_ETL_OUTPUT_TRIGGER_t
XMC_ERU_ETL_OUTPUT_TRIGGER_DISABLED
XMC_ERU_ETL_OUTPUT_TRIGGER_ENABLED
XMC_ERU_ETL_SOURCE_t
XMC_ERU_ETL_SOURCE_A
XMC_ERU_ETL_SOURCE_B
XMC_ERU_ETL_SOURCE_A_OR_B
XMC_ERU_ETL_SOURCE_A_AND_B
XMC_ERU_ETL_SOURCE_NOT_A
XMC_ERU_ETL_SOURCE_NOT_A_OR_B
XMC_ERU_ETL_SOURCE_NOT_A_AND_B
XMC_ERU_ETL_SOURCE_NOT_B
XMC_ERU_ETL_SOURCE_A_OR_NOT_B
XMC_ERU_ETL_SOURCE_A_AND_NOT_B
XMC_ERU_ETL_SOURCE_NOT_A_OR_NOT_B
XMC_ERU_ETL_SOURCE_NOT_A_AND_NOT_B
XMC_ERU_ETL_STATUS_FLAG_MODE_t
XMC_ERU_ETL_STATUS_FLAG_MODE_SWCTRL
XMC_ERU_ETL_STATUS_FLAG_MODE_HWCTRL
XMC_ERU_OGU_PATTERN_DETECTION_INPUT_t
XMC_ERU_OGU_PATTERN_DETECTION_INPUT0
XMC_ERU_OGU_PATTERN_DETECTION_INPUT1
XMC_ERU_OGU_PATTERN_DETECTION_INPUT2
XMC_ERU_OGU_PATTERN_DETECTION_INPUT3
XMC_ERU_OGU_PATTERN_DETECTION_t
XMC_ERU_OGU_PATTERN_DETECTION_DISABLED
XMC_ERU_OGU_PATTERN_DETECTION_ENABLED
XMC_ERU_OGU_PERIPHERAL_TRIGGER_t
XMC_ERU_OGU_PERIPHERAL_TRIGGER1
XMC_ERU_OGU_PERIPHERAL_TRIGGER2
XMC_ERU_OGU_PERIPHERAL_TRIGGER3
XMC_ERU_OGU_SERVICE_REQUEST_t
XMC_ERU_OGU_SERVICE_REQUEST_DISABLED
XMC_ERU_OGU_SERVICE_REQUEST_ON_TRIGGER
XMC_ERU_OGU_SERVICE_REQUEST_ON_TRIGGER_AND_PATTERN_MATCH
XMC_ERU_OGU_SERVICE_REQUEST_ON_TRIGGER_AND_PATTERN_MISMATCH
XMC_ERU_Disable
XMC_ERU_Enable
XMC_ERU_ETL_ClearStatusFlag
XMC_ERU_ETL_DisableOutputTrigger
XMC_ERU_ETL_EnableOutputTrigger
XMC_ERU_ETL_GetEdgeDetection
XMC_ERU_ETL_GetStatusFlag
XMC_ERU_ETL_Init
XMC_ERU_ETL_SetEdgeDetection
XMC_ERU_ETL_SetInput
XMC_ERU_ETL_SetSource
XMC_ERU_ETL_SetStatusFlag
XMC_ERU_ETL_SetStatusFlagMode
XMC_ERU_OGU_DisablePatternDetection
XMC_ERU_OGU_DisablePeripheralTrigger
XMC_ERU_OGU_EnablePatternDetection
XMC_ERU_OGU_EnablePeripheralTrigger
XMC_ERU_OGU_GetPatternDetectionStatus
XMC_ERU_OGU_Init
XMC_ERU_OGU_SetServiceRequestMode
xmc_eth_mac.h
ETH_MAC_DMA_RDES0_AFM
ETH_MAC_DMA_RDES0_CE
ETH_MAC_DMA_RDES0_DBE
ETH_MAC_DMA_RDES0_DE
ETH_MAC_DMA_RDES0_ES
ETH_MAC_DMA_RDES0_ESA
ETH_MAC_DMA_RDES0_FL
ETH_MAC_DMA_RDES0_FS
ETH_MAC_DMA_RDES0_FT
ETH_MAC_DMA_RDES0_LC
ETH_MAC_DMA_RDES0_LE
ETH_MAC_DMA_RDES0_LS
ETH_MAC_DMA_RDES0_OE
ETH_MAC_DMA_RDES0_OWN
ETH_MAC_DMA_RDES0_RE
ETH_MAC_DMA_RDES0_RWT
ETH_MAC_DMA_RDES0_SAF
ETH_MAC_DMA_RDES0_TSA
ETH_MAC_DMA_RDES0_VLAN
ETH_MAC_DMA_TDES0_CC
ETH_MAC_DMA_TDES0_CIC
ETH_MAC_DMA_TDES0_DB
ETH_MAC_DMA_TDES0_DC
ETH_MAC_DMA_TDES0_DP
ETH_MAC_DMA_TDES0_EC
ETH_MAC_DMA_TDES0_ED
ETH_MAC_DMA_TDES0_ES
ETH_MAC_DMA_TDES0_FF
ETH_MAC_DMA_TDES0_FS
ETH_MAC_DMA_TDES0_IC
ETH_MAC_DMA_TDES0_IHE
ETH_MAC_DMA_TDES0_IPE
ETH_MAC_DMA_TDES0_JT
ETH_MAC_DMA_TDES0_LC
ETH_MAC_DMA_TDES0_LOC
ETH_MAC_DMA_TDES0_LS
ETH_MAC_DMA_TDES0_NC
ETH_MAC_DMA_TDES0_OWN
ETH_MAC_DMA_TDES0_TCH
ETH_MAC_DMA_TDES0_TER
ETH_MAC_DMA_TDES0_TTSE
ETH_MAC_DMA_TDES0_TTSS
ETH_MAC_DMA_TDES0_UF
ETH_MAC_DMA_TDES0_VF
XMC_ETH_MAC_BUF_SIZE
XMC_ETH_MAC_PHY_MAX_RETRIES
XMC_ETH_WAKEUP_REGISTER_LENGTH
XMC_ETH_LINK_DUPLEX_t
XMC_ETH_LINK_DUPLEX_HALF
XMC_ETH_LINK_DUPLEX_FULL
XMC_ETH_LINK_INTERFACE_t
XMC_ETH_LINK_INTERFACE_MII
XMC_ETH_LINK_INTERFACE_RMII
XMC_ETH_LINK_SPEED_t
XMC_ETH_LINK_SPEED_10M
XMC_ETH_LINK_SPEED_100M
XMC_ETH_LINK_STATUS_t
XMC_ETH_LINK_STATUS_DOWN
XMC_ETH_LINK_STATUS_UP
XMC_ETH_MAC_ADDR_FILTER_t
XMC_ETH_MAC_ADDR_FILTER_MASK_BYTE0
XMC_ETH_MAC_ADDR_FILTER_MASK_BYTE1
XMC_ETH_MAC_ADDR_FILTER_MASK_BYTE2
XMC_ETH_MAC_ADDR_FILTER_MASK_BYTE3
XMC_ETH_MAC_ADDR_FILTER_MASK_BYTE4
XMC_ETH_MAC_ADDR_FILTER_MASK_BYTE5
XMC_ETH_MAC_ADDR_FILTER_SA
XMC_ETH_MAC_EVENT_t
XMC_ETH_MAC_EVENT_PMT
XMC_ETH_MAC_EVENT_TIMESTAMP
XMC_ETH_MAC_EVENT_EARLY_RECEIVE
XMC_ETH_MAC_EVENT_BUS_ERROR
XMC_ETH_MAC_EVENT_EARLY_TRANSMIT
XMC_ETH_MAC_EVENT_RECEIVE_WATCHDOG_TIMEOUT
XMC_ETH_MAC_EVENT_RECEIVE_PROCESS_STOPPED
XMC_ETH_MAC_EVENT_RECEIVE_BUFFER_UNAVAILABLE
XMC_ETH_MAC_EVENT_RECEIVE
XMC_ETH_MAC_EVENT_TRANSMIT_UNDERFLOW
XMC_ETH_MAC_EVENT_RECEIVE_OVERFLOW
XMC_ETH_MAC_EVENT_TRANSMIT_JABBER_TIMEOUT
XMC_ETH_MAC_EVENT_TRANSMIT_BUFFER_UNAVAILABLE
XMC_ETH_MAC_EVENT_TRANSMIT_PROCESS_STOPPED
XMC_ETH_MAC_EVENT_TRANSMIT
XMC_ETH_MAC_PMT_EVENT_t
XMC_ETH_MAC_PMT_EVENT_ON_WAKEUP_FRAME
XMC_ETH_MAC_PMT_EVENT_ON_MAGIC_PACKET
XMC_ETH_MAC_PMT_EVENT_ON_UNICAST_FRAME_FILTER
XMC_ETH_MAC_STATUS_t
XMC_ETH_MAC_STATUS_OK
XMC_ETH_MAC_STATUS_BUSY
XMC_ETH_MAC_STATUS_ERROR
XMC_ETH_MAC_TIMESTAMP_CONFIG_t
XMC_ETH_MAC_TIMESTAMP_CONFIG_FINE_UPDATE
XMC_ETH_MAC_TIMESTAMP_CONFIG_ENABLE_TS_INTERRUPT
XMC_ETH_MAC_TIMESTAMP_CONFIG_ENABLE_ALL_FRAMES
XMC_ETH_MAC_TIMESTAMP_CONFIG_ENABLE_PTPV2
XMC_ETH_MAC_TIMESTAMP_CONFIG_ENABLE_PTP_OVER_ETHERNET
XMC_ETH_MAC_TIMESTAMP_CONFIG_ENABLE_PTP_OVER_IPV6
XMC_ETH_MAC_TIMESTAMP_CONFIG_ENABLE_PTP_OVER_IPV4
XMC_ETH_MAC_TIMESTAMP_CONFIG_ENABLE_MAC_ADDRESS_FILTER
XMC_ETH_MAC_TIMESTAMP_STATUS_t
XMC_ETH_MAC_TIMESTAMP_STATUS_SECONDS_OVERFLOW
XMC_ETH_MAC_TIMESTAMP_STATUS_TARGET_TIME_REACHED
XMC_ETH_MAC_TIMESTAMP_STATUS_TARGET_TIMER_ERROR
XMC_ETH_MAC_TX_FRAME_t
XMC_ETH_MAC_TX_FRAME_FRAGMENT
XMC_ETH_MAC_TX_FRAME_EVENT
XMC_ETH_MAC_TX_FRAME_TIMESTAMP
XMC_ETH_MAC_AdjustPTPClock
XMC_ETH_MAC_ClearEventStatus
XMC_ETH_MAC_Disable
XMC_ETH_MAC_DisableDestinationAddressInverseFilter
XMC_ETH_MAC_DisableEvent
XMC_ETH_MAC_DisableFrameBurst
XMC_ETH_MAC_DisableFrameFilter
XMC_ETH_MAC_DisableJumboFrame
XMC_ETH_MAC_DisableLoopback
XMC_ETH_MAC_DisableMulticastHashFilter
XMC_ETH_MAC_DisablePowerDownMode
XMC_ETH_MAC_DisablePowerManagmentEvent
XMC_ETH_MAC_DisablePromiscuousMode
XMC_ETH_MAC_DisablePTPAlarm
XMC_ETH_MAC_DisableReceptionBroadcastFrames
XMC_ETH_MAC_DisableReceptionMulticastFrames
XMC_ETH_MAC_DisableRx
XMC_ETH_MAC_DisableRxOwn
XMC_ETH_MAC_DisableRxWatchdog
XMC_ETH_MAC_DisableSourceAddressFilter
XMC_ETH_MAC_DisableSourceAddressInverseFilter
XMC_ETH_MAC_DisableTx
XMC_ETH_MAC_DisableTxJabber
XMC_ETH_MAC_DisableUnicastHashFilter
XMC_ETH_MAC_Enable
XMC_ETH_MAC_EnableDestinationAddressInverseFilter
XMC_ETH_MAC_EnableEvent
XMC_ETH_MAC_EnableFrameBurst
XMC_ETH_MAC_EnableFrameFilter
XMC_ETH_MAC_EnableHashPerfectFilter
XMC_ETH_MAC_EnableJumboFrame
XMC_ETH_MAC_EnableLoopback
XMC_ETH_MAC_EnableMulticastHashFilter
XMC_ETH_MAC_EnablePerfectFilter
XMC_ETH_MAC_EnablePowerDownMode
XMC_ETH_MAC_EnablePowerManagmentEvent
XMC_ETH_MAC_EnablePromiscuousMode
XMC_ETH_MAC_EnablePTPAlarm
XMC_ETH_MAC_EnableReceptionBroadcastFrames
XMC_ETH_MAC_EnableReceptionMulticastFrames
XMC_ETH_MAC_EnableRx
XMC_ETH_MAC_EnableRxOwn
XMC_ETH_MAC_EnableRxWatchdog
XMC_ETH_MAC_EnableSourceAddressFilter
XMC_ETH_MAC_EnableSourceAddressInverseFilter
XMC_ETH_MAC_EnableTx
XMC_ETH_MAC_EnableTxJabber
XMC_ETH_MAC_EnableUnicastHashFilter
XMC_ETH_MAC_FlushRx
XMC_ETH_MAC_FlushTx
XMC_ETH_MAC_GetAddress
XMC_ETH_MAC_GetEventStatus
XMC_ETH_MAC_GetPTPStatus
XMC_ETH_MAC_GetPTPTime
XMC_ETH_MAC_GetRxBuffer
XMC_ETH_MAC_GetRxFrameSize
XMC_ETH_MAC_GetRxTimeStamp
XMC_ETH_MAC_GetTxBuffer
XMC_ETH_MAC_GetTxTimeStamp
XMC_ETH_MAC_Init
XMC_ETH_MAC_InitPTP
XMC_ETH_MAC_InitPTPEx
XMC_ETH_MAC_InitRxDescriptors
XMC_ETH_MAC_InitTxDescriptors
XMC_ETH_MAC_IsEnabled
XMC_ETH_MAC_IsMagicPacketReceived
XMC_ETH_MAC_IsRxDescriptorOwnedByDma
XMC_ETH_MAC_IsTxDescriptorOwnedByDma
XMC_ETH_MAC_IsWakeupFrameReceived
XMC_ETH_MAC_ReadFrame
XMC_ETH_MAC_ReadPhy
XMC_ETH_MAC_Reset
XMC_ETH_MAC_ResumeRx
XMC_ETH_MAC_ResumeTx
XMC_ETH_MAC_ReturnRxDescriptor
XMC_ETH_MAC_ReturnTxDescriptor
XMC_ETH_MAC_SendFrame
XMC_ETH_MAC_SetAddress
XMC_ETH_MAC_SetAddressHashFilter
XMC_ETH_MAC_SetAddressPerfectFilter
XMC_ETH_MAC_SetLink
XMC_ETH_MAC_SetManagmentClockDivider
XMC_ETH_MAC_SetPortControl
XMC_ETH_MAC_SetPTPAlarm
XMC_ETH_MAC_SetPTPTime
XMC_ETH_MAC_SetTxBufferSize
XMC_ETH_MAC_SetVLANTag
XMC_ETH_MAC_SetWakeUpFrameFilter
XMC_ETH_MAC_UpdateAddend
XMC_ETH_MAC_UpdatePTPTime
XMC_ETH_MAC_WritePhy
xmc_eth_mac_map.h
XMC_ETH_MAC_PORT_CTRL_CLK_RMII_t
XMC_ETH_MAC_PORT_CTRL_CLK_RMII_P2_1
XMC_ETH_MAC_PORT_CTRL_CLK_RMII_P0_0
XMC_ETH_MAC_PORT_CTRL_CLK_RMII_P15_8
XMC_ETH_MAC_PORT_CTRL_CLK_RMII_P6_5
XMC_ETH_MAC_PORT_CTRL_CLK_TX_t
XMC_ETH_MAC_PORT_CTRL_CLK_TX_P5_10
XMC_ETH_MAC_PORT_CTRL_CLK_TX_P6_6
XMC_ETH_MAC_PORT_CTRL_COL_t
XMC_ETH_MAC_PORT_CTRL_COL_P2_15
XMC_ETH_MAC_PORT_CTRL_COL_P5_5
XMC_ETH_MAC_PORT_CTRL_CRS_DV_t
XMC_ETH_MAC_PORT_CTRL_CRS_DV_P2_5
XMC_ETH_MAC_PORT_CTRL_CRS_DV_P0_1
XMC_ETH_MAC_PORT_CTRL_CRS_DV_P15_9
XMC_ETH_MAC_PORT_CTRL_CRS_DV_P5_2
XMC_ETH_MAC_PORT_CTRL_CRS_t
XMC_ETH_MAC_PORT_CTRL_CRS_P5_11
XMC_ETH_MAC_PORT_CTRL_CRS_P5_4
XMC_ETH_MAC_PORT_CTRL_MDIO_t
XMC_ETH_MAC_PORT_CTRL_MDIO_P0_9
XMC_ETH_MAC_PORT_CTRL_MDIO_P2_0
XMC_ETH_MAC_PORT_CTRL_MDIO_P1_11
XMC_ETH_MAC_PORT_CTRL_MODE_t
XMC_ETH_MAC_PORT_CTRL_MODE_MII
XMC_ETH_MAC_PORT_CTRL_MODE_RMII
XMC_ETH_MAC_PORT_CTRL_RXD0_t
XMC_ETH_MAC_PORT_CTRL_RXD0_P2_2
XMC_ETH_MAC_PORT_CTRL_RXD0_P0_2
XMC_ETH_MAC_PORT_CTRL_RXD0_P14_8
XMC_ETH_MAC_PORT_CTRL_RXD0_P5_0
XMC_ETH_MAC_PORT_CTRL_RXD1_t
XMC_ETH_MAC_PORT_CTRL_RXD1_P2_3
XMC_ETH_MAC_PORT_CTRL_RXD1_P0_3
XMC_ETH_MAC_PORT_CTRL_RXD1_P14_9
XMC_ETH_MAC_PORT_CTRL_RXD1_P5_1
XMC_ETH_MAC_PORT_CTRL_RXD2_t
XMC_ETH_MAC_PORT_CTRL_RXD2_P5_8
XMC_ETH_MAC_PORT_CTRL_RXD2_P6_4
XMC_ETH_MAC_PORT_CTRL_RXD3_t
XMC_ETH_MAC_PORT_CTRL_RXD3_P5_9
XMC_ETH_MAC_PORT_CTRL_RXD3_P6_3
XMC_ETH_MAC_PORT_CTRL_RXER_t
XMC_ETH_MAC_PORT_CTRL_RXER_P2_4
XMC_ETH_MAC_PORT_CTRL_RXER_P0_11
XMC_ETH_MAC_PORT_CTRL_RXER_P5_3
xmc_eth_phy.h
XMC_ETH_PHY_STATUS_t
XMC_ETH_PHY_STATUS_OK
XMC_ETH_PHY_STATUS_BUSY
XMC_ETH_PHY_STATUS_ERROR
XMC_ETH_PHY_STATUS_ERROR_DEVICE_ID
XMC_ETH_PHY_STATUS_ERROR_TIMEOUT
XMC_ETH_PHY_ExitPowerDown
XMC_ETH_PHY_GetLinkDuplex
XMC_ETH_PHY_GetLinkSpeed
XMC_ETH_PHY_GetLinkStatus
XMC_ETH_PHY_Init
XMC_ETH_PHY_IsAutonegotiationCompleted
XMC_ETH_PHY_PowerDown
XMC_ETH_PHY_Reset
xmc_fce.h
XMC_FCE_CRC16
XMC_FCE_CRC32_0
XMC_FCE_CRC32_1
XMC_FCE_CRC8
XMC_FCE_INVSEL_RESET
XMC_FCE_INVSEL_SET
XMC_FCE_REFIN_RESET
XMC_FCE_REFIN_SET
XMC_FCE_REFOUT_RESET
XMC_FCE_REFOUT_SET
XMC_FCE_Kernel_t
XMC_FCE_CONFIG_ALGO_t
XMC_FCE_CFG_CONFIG_REFIN
XMC_FCE_CFG_CONFIG_REFOUT
XMC_FCE_CFG_CONFIG_XSEL
XMC_FCE_CONFIG_INTERRUPT_t
XMC_FCE_CFG_CONFIG_CMI
XMC_FCE_CFG_CONFIG_CEI
XMC_FCE_CFG_CONFIG_LEI
XMC_FCE_CFG_CONFIG_BEI
XMC_FCE_CONFIG_OPERATION_t
XMC_FCE_CFG_CONFIG_CCE
XMC_FCE_CFG_CONFIG_ALR
XMC_FCE_CTR_TEST_t
XMC_FCE_CTR_MISMATCH_CRC
XMC_FCE_CTR_MISMATCH_CFG
XMC_FCE_CTR_MISMATCH_CHECK
XMC_FCE_STATUS_t
XMC_FCE_STATUS_OK
XMC_FCE_STATUS_BUSY
XMC_FCE_STATUS_ERROR
XMC_FCE_STS_FLAG_t
XMC_FCE_STS_MISMATCH_CRC
XMC_FCE_STS_CONFIG_ERROR
XMC_FCE_STS_LENGTH_ERROR
XMC_FCE_STS_BUS_ERROR
XMC_FCE_CalculateCRC16
XMC_FCE_CalculateCRC32
XMC_FCE_CalculateCRC8
XMC_FCE_ClearEvent
XMC_FCE_Disable
XMC_FCE_DisableCRCAlgorithm
XMC_FCE_DisableEvent
XMC_FCE_DisableOperation
XMC_FCE_Enable
XMC_FCE_EnableCRCAlgorithm
XMC_FCE_EnableEvent
XMC_FCE_EnableOperation
XMC_FCE_Get_DisableStatus
XMC_FCE_GetCRCResult
XMC_FCE_GetEventStatus
XMC_FCE_Init
XMC_FCE_InitializeSeedValue
XMC_FCE_LittleEndian16bit
XMC_FCE_LittleEndian32bit
XMC_FCE_ReadModuleNumber
XMC_FCE_ReadModuleRev
XMC_FCE_ReadModuleType
XMC_FCE_TriggerMismatch
XMC_FCE_UpdateCRCCheck
XMC_FCE_UpdateLength
xmc_flash.h
XMC_FLASH_ClearStatus
XMC_FLASH_DisableEvent
XMC_FLASH_EnableEvent
XMC_FLASH_EraseSector
XMC_FLASH_GetStatus
XMC_FLASH_IsBusy
XMC_FLASH_ProgramPage
xmc_gpio.h
XMC_GPIO_HWCTRL_t
XMC_GPIO_HWCTRL_DISABLED
XMC_GPIO_HWCTRL_PERIPHERAL1
XMC_GPIO_HWCTRL_PERIPHERAL2
XMC_GPIO_OUTPUT_LEVEL_t
XMC_GPIO_OUTPUT_LEVEL_LOW
XMC_GPIO_OUTPUT_LEVEL_HIGH
XMC_GPIO_DisableDigitalInput
XMC_GPIO_DisablePowerSaveMode
XMC_GPIO_EnableDigitalInput
XMC_GPIO_EnablePowerSaveMode
XMC_GPIO_GetInput
XMC_GPIO_Init
XMC_GPIO_SetHardwareControl
XMC_GPIO_SetMode
XMC_GPIO_SetOutputHigh
XMC_GPIO_SetOutputLevel
XMC_GPIO_SetOutputLow
XMC_GPIO_ToggleOutput
xmc_hrpwm.h
XMC_HRPWM_CSG_t
XMC_HRPWM_HRC_t
XMC_HRPWM_t
XMC_HRPWM_CLK_FREQ_t
XMC_HRPWM_CLK_FREQ_NONE
XMC_HRPWM_CLK_FREQ_180MHZ
XMC_HRPWM_CLK_FREQ_120MHZ
XMC_HRPWM_CLK_FREQ_80MHZ
XMC_HRPWM_CSG_CLK_INPUT_t
XMC_HRPWM_CSG_CLK_INPUT_MCLK
XMC_HRPWM_CSG_CLK_INPUT_ECLKA
XMC_HRPWM_CSG_CLK_INPUT_ECLKB
XMC_HRPWM_CSG_CLK_INPUT_ECLKC
XMC_HRPWM_CSG_CLK_t
XMC_HRPWM_CSG_CLK_CSG0
XMC_HRPWM_CSG_CLK_CSG1
XMC_HRPWM_CSG_CLK_CSG2
XMC_HRPWM_CSG_CMP_FILTER_WINDOW_t
XMC_HRPWM_CSG_CMP_FILTER_WINDOW_2_CLK_CYCLES
XMC_HRPWM_CSG_CMP_FILTER_WINDOW_3_CLK_CYCLES
XMC_HRPWM_CSG_CMP_FILTER_WINDOW_4_CLK_CYCLES
XMC_HRPWM_CSG_CMP_FILTER_WINDOW_5_CLK_CYCLES
XMC_HRPWM_CSG_CMP_FILTER_WINDOW_6_CLK_CYCLES
XMC_HRPWM_CSG_CMP_FILTER_WINDOW_7_CLK_CYCLES
XMC_HRPWM_CSG_CMP_FILTER_WINDOW_8_CLK_CYCLES
XMC_HRPWM_CSG_CMP_FILTER_WINDOW_9_CLK_CYCLES
XMC_HRPWM_CSG_CMP_FILTER_WINDOW_10_CLK_CYCLES
XMC_HRPWM_CSG_CMP_FILTER_WINDOW_11_CLK_CYCLES
XMC_HRPWM_CSG_CMP_FILTER_WINDOW_12_CLK_CYCLES
XMC_HRPWM_CSG_CMP_FILTER_WINDOW_13_CLK_CYCLES
XMC_HRPWM_CSG_CMP_FILTER_WINDOW_14_CLK_CYCLES
XMC_HRPWM_CSG_CMP_FILTER_WINDOW_15_CLK_CYCLES
XMC_HRPWM_CSG_CMP_FILTER_WINDOW_16_CLK_CYCLES
XMC_HRPWM_CSG_CMP_FILTER_WINDOW_32_CLK_CYCLES
XMC_HRPWM_CSG_CMP_INPUT_t
XMC_HRPWM_CSG_CMP_INPUT_CINA
XMC_HRPWM_CSG_CMP_INPUT_CINB
XMC_HRPWM_CSG_CMP_INVERTING_INPUT_t
XMC_HRPWM_CSG_CMP_INVERTING_INPUT_CMP0
XMC_HRPWM_CSG_CMP_INVERTING_INPUT_CMP1
XMC_HRPWM_CSG_CMP_INVERTING_INPUT_CMP2
XMC_HRPWM_CSG_EDGE_SEL_t
XMC_HRPWM_CSG_EDGE_SEL_DISABLED
XMC_HRPWM_CSG_EDGE_SEL_RISING_EDGE
XMC_HRPWM_CSG_EDGE_SEL_FALLING_EDGE
XMC_HRPWM_CSG_EDGE_SEL_BOTH_EDGE
XMC_HRPWM_CSG_INPUT_SEL_t
XMC_HRPWM_CSG_INPUT_SEL_IA
XMC_HRPWM_CSG_INPUT_SEL_IB
XMC_HRPWM_CSG_INPUT_SEL_IC
XMC_HRPWM_CSG_INPUT_SEL_ID
XMC_HRPWM_CSG_INPUT_SEL_IE
XMC_HRPWM_CSG_INPUT_SEL_IF
XMC_HRPWM_CSG_INPUT_SEL_IG
XMC_HRPWM_CSG_INPUT_SEL_IH
XMC_HRPWM_CSG_INPUT_SEL_II
XMC_HRPWM_CSG_INPUT_SEL_IJ
XMC_HRPWM_CSG_INPUT_SEL_IK
XMC_HRPWM_CSG_INPUT_SEL_IL
XMC_HRPWM_CSG_INPUT_SEL_IM
XMC_HRPWM_CSG_INPUT_SEL_IN
XMC_HRPWM_CSG_INPUT_SEL_IO
XMC_HRPWM_CSG_INPUT_SEL_IP
XMC_HRPWM_CSG_IRQ_ID_t
XMC_HRPWM_CSG_IRQ_ID_VLS1
XMC_HRPWM_CSG_IRQ_ID_VLS2
XMC_HRPWM_CSG_IRQ_ID_TRGS
XMC_HRPWM_CSG_IRQ_ID_STRS
XMC_HRPWM_CSG_IRQ_ID_STPS
XMC_HRPWM_CSG_IRQ_ID_STD
XMC_HRPWM_CSG_IRQ_ID_CRSE
XMC_HRPWM_CSG_IRQ_ID_CFSE
XMC_HRPWM_CSG_IRQ_ID_CSEE
XMC_HRPWM_CSG_IRQ_SR_LINE_t
XMC_HRPWM_CSG_IRQ_SR_LINE_0
XMC_HRPWM_CSG_IRQ_SR_LINE_1
XMC_HRPWM_CSG_IRQ_SR_LINE_2
XMC_HRPWM_CSG_IRQ_SR_LINE_3
XMC_HRPWM_CSG_LVL_SEL_t
XMC_HRPWM_CSG_LVL_SEL_DISABLED
XMC_HRPWM_CSG_LVL_SEL_HIGH
XMC_HRPWM_CSG_LVL_SEL_LOW
XMC_HRPWM_CSG_POWER_MODE_t
XMC_HRPWM_CSG_POWER_MODE_OFF
XMC_HRPWM_CSG_POWER_MODE_LOW_SPEED
XMC_HRPWM_CSG_POWER_MODE_HI_SPEED
XMC_HRPWM_CSG_PRESCALER_CLR_t
XMC_HRPWM_CSG_PRESCALER_CLR_CSG0
XMC_HRPWM_CSG_PRESCALER_CLR_CSG1
XMC_HRPWM_CSG_PRESCALER_CLR_CSG2
XMC_HRPWM_CSG_PRESCALER_DIVISION_t
XMC_HRPWM_CSG_PRESCALER_DIVISION_BY_1
XMC_HRPWM_CSG_PRESCALER_DIVISION_BY_2
XMC_HRPWM_CSG_PRESCALER_DIVISION_BY_4
XMC_HRPWM_CSG_PRESCALER_DIVISION_BY_8
XMC_HRPWM_CSG_PRESCALER_EXT_START_t
XMC_HRPWM_CSG_PRESCALER_EXT_START_IGNORE
XMC_HRPWM_CSG_PRESCALER_EXT_START_STRT
XMC_HRPWM_CSG_PRESCALER_EXT_START_CLR
XMC_HRPWM_CSG_PRESCALER_EXT_START_CLR_N_STRT
XMC_HRPWM_CSG_PRESCALER_EXT_STOP_t
XMC_HRPWM_CSG_PRESCALER_EXT_STOP_IGNORE
XMC_HRPWM_CSG_PRESCALER_EXT_STOP_STP
XMC_HRPWM_CSG_PRESCALER_EXT_STOP_CLR
XMC_HRPWM_CSG_PRESCALER_EXT_STOP_CLR_N_STOP
XMC_HRPWM_CSG_PRESCALER_START_t
XMC_HRPWM_CSG_PRESCALER_START_CSG0
XMC_HRPWM_CSG_PRESCALER_START_CSG1
XMC_HRPWM_CSG_PRESCALER_START_CSG2
XMC_HRPWM_CSG_PRESCALER_STATUS_t
XMC_HRPWM_CSG_PRESCALER_STATUS_CSG0
XMC_HRPWM_CSG_PRESCALER_STATUS_CSG1
XMC_HRPWM_CSG_PRESCALER_STATUS_CSG2
XMC_HRPWM_CSG_PRESCALER_STOP_t
XMC_HRPWM_CSG_PRESCALER_STOP_CSG0
XMC_HRPWM_CSG_PRESCALER_STOP_CSG1
XMC_HRPWM_CSG_PRESCALER_STOP_CSG2
XMC_HRPWM_CSG_RUN_BIT_t
XMC_HRPWM_CSG_RUN_BIT_DAC0
XMC_HRPWM_CSG_RUN_BIT_CMP0
XMC_HRPWM_CSG_RUN_BIT_CMP0_PSL
XMC_HRPWM_CSG_RUN_BIT_DAC1
XMC_HRPWM_CSG_RUN_BIT_CMP1
XMC_HRPWM_CSG_RUN_BIT_CMP1_PSL
XMC_HRPWM_CSG_RUN_BIT_DAC2
XMC_HRPWM_CSG_RUN_BIT_CMP2
XMC_HRPWM_CSG_RUN_BIT_CMP2_PSL
XMC_HRPWM_CSG_SLICE_t
XMC_HRPWM_CSG_SLICE_0
XMC_HRPWM_CSG_SLICE_1
XMC_HRPWM_CSG_SLICE_2
XMC_HRPWM_CSG_SLOPE_CTRL_MODE_t
XMC_HRPWM_CSG_SLOPE_CTRL_MODE_STATIC
XMC_HRPWM_CSG_SLOPE_CTRL_MODE_DEC_GEN
XMC_HRPWM_CSG_SLOPE_CTRL_MODE_INC_GEN
XMC_HRPWM_CSG_SLOPE_CTRL_MODE_TRIANGULAR
XMC_HRPWM_CSG_SLOPE_EXT_START_t
XMC_HRPWM_CSG_SLOPE_EXT_START_IGNORE
XMC_HRPWM_CSG_SLOPE_EXT_START_STRT
XMC_HRPWM_CSG_SLOPE_EXT_START_RESUME
XMC_HRPWM_CSG_SLOPE_EXT_STOP_t
XMC_HRPWM_CSG_SLOPE_EXT_STOP_IGNORE
XMC_HRPWM_CSG_SLOPE_EXT_STOP_STP
XMC_HRPWM_CSG_SLOPE_EXT_STOP_FREEZE
XMC_HRPWM_CSG_SLOPE_START_t
XMC_HRPWM_CSG_SLOPE_START_DAC0
XMC_HRPWM_CSG_SLOPE_START_DAC1
XMC_HRPWM_CSG_SLOPE_START_DAC2
XMC_HRPWM_CSG_SLOPE_STEP_GAIN_t
XMC_HRPWM_CSG_SLOPE_STEP_GAIN_INC_DEC_BY_1
XMC_HRPWM_CSG_SLOPE_STEP_GAIN_INC_DEC_BY_2
XMC_HRPWM_CSG_SLOPE_STEP_GAIN_INC_DEC_BY_4
XMC_HRPWM_CSG_SLOPE_STEP_GAIN_INC_DEC_BY_8
XMC_HRPWM_CSG_SLOPE_STOP_t
XMC_HRPWM_CSG_SLOPE_STOP_DAC0
XMC_HRPWM_CSG_SLOPE_STOP_DAC1
XMC_HRPWM_CSG_SLOPE_STOP_DAC2
XMC_HRPWM_CSG_SWITCH_CMP_INPUT_t
XMC_HRPWM_CSG_SWITCH_CMP_INPUT_CMP0
XMC_HRPWM_CSG_SWITCH_CMP_INPUT_CMP1
XMC_HRPWM_CSG_SWITCH_CMP_INPUT_CMP2
XMC_HRPWM_CSG_SWSM_t
XMC_HRPWM_CSG_SWSM_DSV2_W_TRIGGER
XMC_HRPWM_CSG_SWSM_DSV1_W_TRIGGER
XMC_HRPWM_CSG_SWSM_DSV2_NO_TRIGGER
XMC_HRPWM_CSG_SWSM_DSV1_NO_TRIGGER
XMC_HRPWM_DAC_SLOPE_GEN_STATUS_t
XMC_HRPWM_DAC_SLOPE_GEN_STATUS_DAC0
XMC_HRPWM_DAC_SLOPE_GEN_STATUS_DAC1
XMC_HRPWM_DAC_SLOPE_GEN_STATUS_DAC2
XMC_HRPWM_FUNC_STATUS_t
XMC_HRPWM_FUNC_STATUS_DISABLE
XMC_HRPWM_FUNC_STATUS_ENABLE
XMC_HRPWM_HR_LOGIC_t
XMC_HRPWM_HR_LOGIC_NOT_WORKING
XMC_HRPWM_HR_LOGIC_WORKING
XMC_HRPWM_HR_PATH_t
XMC_HRPWM_HR_PATH_HRC0
XMC_HRPWM_HR_PATH_HRC1
XMC_HRPWM_HR_PATH_HRC2
XMC_HRPWM_HR_PATH_HRC3
XMC_HRPWM_HRC_CMP_SEL_t
XMC_HRPWM_HRC_CMP_SEL_CSG0
XMC_HRPWM_HRC_CMP_SEL_CSG1
XMC_HRPWM_HRC_CMP_SEL_CSG2
XMC_HRPWM_HRC_DT_TR_SEL_t
XMC_HRPWM_HRC_DT_TR_SEL_TIMER
XMC_HRPWM_HRC_DT_TR_SEL_OVERFLOW
XMC_HRPWM_HRC_HR_EDGE_t
XMC_HRPWM_HRC_HR_EDGE_SEL_RISING
XMC_HRPWM_HRC_HR_EDGE_SEL_FALLING
XMC_HRPWM_HRC_HR_EDGE_SEL_BOTH
XMC_HRPWM_HRC_HR_EDGE_SEL_NONE
XMC_HRPWM_HRC_OUT_PASSIVE_LVL_t
XMC_HRPWM_HRC_OUT_PASSIVE_LVL_LOW
XMC_HRPWM_HRC_OUT_PASSIVE_LVL_HIGH
XMC_HRPWM_HRC_SHADOW_TX_t
XMC_HRPWM_HRC_SHADOW_TX_HRC0_VALUE
XMC_HRPWM_HRC_SHADOW_TX_HRC0_DT_VALUE
XMC_HRPWM_HRC_SHADOW_TX_HRC1_VALUE
XMC_HRPWM_HRC_SHADOW_TX_HRC1_DT_VALUE
XMC_HRPWM_HRC_SHADOW_TX_HRC2_VALUE
XMC_HRPWM_HRC_SHADOW_TX_HRC2_DT_VALUE
XMC_HRPWM_HRC_SHADOW_TX_HRC3_VALUE
XMC_HRPWM_HRC_SHADOW_TX_HRC3_DT_VALUE
XMC_HRPWM_HRC_SOURCE_t
XMC_HRPWM_HRC_SOURCE_0
XMC_HRPWM_HRC_SOURCE_1
XMC_HRPWM_HRC_SRC_EDGE_SEL_t
XMC_HRPWM_HRC_SRC_EDGE_SEL_DISABLED
XMC_HRPWM_HRC_SRC_EDGE_SEL_RISING
XMC_HRPWM_HRC_SRC_EDGE_SEL_FALLING
XMC_HRPWM_HRC_SRC_EDGE_SEL_BOTH
XMC_HRPWM_HRC_SRC_INPUT_t
XMC_HRPWM_HRC_SRC_INPUT_CCU
XMC_HRPWM_HRC_SRC_INPUT_CSG
XMC_HRPWM_HRC_TIMER_SEL_t
XMC_HRPWM_HRC_TIMER_SEL_CCU_CC0
XMC_HRPWM_HRC_TIMER_SEL_CCU_CC1
XMC_HRPWM_HRC_TIMER_SEL_CCU_CC2
XMC_HRPWM_HRC_TIMER_SEL_CCU_CC3
XMC_HRPWM_LR_PATH_t
XMC_HRPWM_LR_PATH_HRC0
XMC_HRPWM_LR_PATH_HRC1
XMC_HRPWM_LR_PATH_HRC2
XMC_HRPWM_LR_PATH_HRC3
XMC_HRPWM_SHADOW_TX_DAC_t
XMC_HRPWM_SHADOW_TX_DAC0
XMC_HRPWM_SHADOW_TX_DAC1
XMC_HRPWM_SHADOW_TX_DAC2
XMC_HRPWM_STATUS_t
XMC_HRPWM_STATUS_OK
XMC_HRPWM_STATUS_BUSY
XMC_HRPWM_STATUS_ERROR
XMC_HRPWM_ClampComparatorOutput
XMC_HRPWM_ClearPreScaler
XMC_HRPWM_CSG_ClrEventSW
XMC_HRPWM_CSG_DACRefValSwitchingConfig
XMC_HRPWM_CSG_DisableEvent
XMC_HRPWM_CSG_EnableEvent
XMC_HRPWM_CSG_GetEventStatus
XMC_HRPWM_CSG_Init
XMC_HRPWM_CSG_SelBlankingInput
XMC_HRPWM_CSG_SelClampingInput
XMC_HRPWM_CSG_SelSlopeGenClkInput
XMC_HRPWM_CSG_SetCMPInput
XMC_HRPWM_CSG_SetEventSW
XMC_HRPWM_CSG_SetSRNode
XMC_HRPWM_CSG_StartSlopeGenConfig
XMC_HRPWM_CSG_StopSlopeGenConfig
XMC_HRPWM_CSG_TriggerDACConvConfig
XMC_HRPWM_CSG_TriggerShadowXferConfig
XMC_HRPWM_CSG_UpdateBlankingValue
XMC_HRPWM_CSG_UpdateDACPrescaler
XMC_HRPWM_CSG_UpdateDACRefDSV1
XMC_HRPWM_CSG_UpdateDACRefDSV2
XMC_HRPWM_CSG_UpdateDACStepGain
XMC_HRPWM_CSG_UpdateFilterWindow
XMC_HRPWM_CSG_UpdatePulseClk
XMC_HRPWM_DisableBias
XMC_HRPWM_DisableComparatorShadowTransfer
XMC_HRPWM_DisableCsgClock
XMC_HRPWM_DisableGlobalHR
XMC_HRPWM_DisableHighResolutionPath
XMC_HRPWM_DisableHighResolutionShadowTransfer
XMC_HRPWM_DisableHRPowerMode
XMC_HRPWM_DisableLowResolutionPath
XMC_HRPWM_EnableBias
XMC_HRPWM_EnableComparatorShadowTransfer
XMC_HRPWM_EnableGlobalHR
XMC_HRPWM_EnableHighResolutionPath
XMC_HRPWM_EnableHighResolutionShadowTransfer
XMC_HRPWM_EnableHRPowerMode
XMC_HRPWM_EnableLowResolutionPath
XMC_HRPWM_GetCMPInput
XMC_HRPWM_GetComparatorShadowTransferStatus
XMC_HRPWM_GetHighResolutionShadowTransferStatus
XMC_HRPWM_GetHRGenReadyStatus
XMC_HRPWM_GetRunBitStatus
XMC_HRPWM_HRC_ConfigSourceSelect0
XMC_HRPWM_HRC_ConfigSourceSelect1
XMC_HRPWM_HRC_Init
XMC_HRPWM_HRC_Set_HR_Source
XMC_HRPWM_HRC_SetCompare1
XMC_HRPWM_HRC_SetCompare2
XMC_HRPWM_HRC_SetDeadTimeFalling
XMC_HRPWM_HRC_SetDeadTimeRising
XMC_HRPWM_Init
XMC_HRPWM_IsComparatorClamped
XMC_HRPWM_IsComparatorRunning
XMC_HRPWM_IsDacRunning
XMC_HRPWM_IsPrescalerRunning
XMC_HRPWM_IsSlopeGenerationRunning
XMC_HRPWM_ModuleClkFreq
XMC_HRPWM_SetCsgPowerMode
XMC_HRPWM_StartComparator
XMC_HRPWM_StartDac
XMC_HRPWM_StartSlopeGeneration
XMC_HRPWM_StopComparator
XMC_HRPWM_StopDac
XMC_HRPWM_StopSlopeGeneration
XMC_HRPWM_UnClampComparatorOutput
xmc_i2c.h
XMC_I2C0_CH0
XMC_I2C0_CH1
XMC_I2C1_CH0
XMC_I2C1_CH1
XMC_I2C2_CH0
XMC_I2C2_CH1
XMC_I2C_10BIT_ADDR_GROUP
XMC_I2C_CH_CMD_t
XMC_I2C_CH_CMD_WRITE
XMC_I2C_CH_CMD_READ
XMC_I2C_CH_EVENT_t
XMC_I2C_CH_EVENT_RECEIVE_START
XMC_I2C_CH_EVENT_DATA_LOST
XMC_I2C_CH_EVENT_TRANSMIT_SHIFT
XMC_I2C_CH_EVENT_TRANSMIT_BUFFER
XMC_I2C_CH_EVENT_STANDARD_RECEIVE
XMC_I2C_CH_EVENT_ALTERNATIVE_RECEIVE
XMC_I2C_CH_EVENT_BAUD_RATE_GENERATOR
XMC_I2C_CH_EVENT_START_CONDITION_RECEIVED
XMC_I2C_CH_EVENT_REPEATED_START_CONDITION_RECEIVED
XMC_I2C_CH_EVENT_STOP_CONDITION_RECEIVED
XMC_I2C_CH_EVENT_NACK
XMC_I2C_CH_EVENT_ARBITRATION_LOST
XMC_I2C_CH_EVENT_SLAVE_READ_REQUEST
XMC_I2C_CH_EVENT_ERROR
XMC_I2C_CH_EVENT_ACK
XMC_I2C_CH_INPUT_t
XMC_I2C_CH_INPUT_SDA
XMC_I2C_CH_INPUT_SCL
XMC_I2C_CH_INTERRUPT_NODE_POINTER_t
XMC_I2C_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT
XMC_I2C_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER
XMC_I2C_CH_INTERRUPT_NODE_POINTER_RECEIVE
XMC_I2C_CH_INTERRUPT_NODE_POINTER_ALTERNATE_RECEIVE
XMC_I2C_CH_INTERRUPT_NODE_POINTER_PROTOCOL
XMC_I2C_CH_RECEIVER_STATUS_FLAG_t
XMC_I2C_CH_RECEIVER_STATUS_FLAG_ACK
XMC_I2C_CH_RECEIVER_STATUS_FLAG_FIN
XMC_I2C_CH_RECEIVER_STATUS_FLAG_MODE
XMC_I2C_CH_RECEIVER_STATUS_FLAG_ERR
XMC_I2C_CH_RECEIVER_STATUS_FLAG_ADR
XMC_I2C_CH_STATUS_FLAG_t
XMC_I2C_CH_STATUS_FLAG_SLAVE_SELECT
XMC_I2C_CH_STATUS_FLAG_WRONG_TDF_CODE_FOUND
XMC_I2C_CH_STATUS_FLAG_START_CONDITION_RECEIVED
XMC_I2C_CH_STATUS_FLAG_REPEATED_START_CONDITION_RECEIVED
XMC_I2C_CH_STATUS_FLAG_STOP_CONDITION_RECEIVED
XMC_I2C_CH_STATUS_FLAG_NACK_RECEIVED
XMC_I2C_CH_STATUS_FLAG_ARBITRATION_LOST
XMC_I2C_CH_STATUS_FLAG_SLAVE_READ_REQUESTED
XMC_I2C_CH_STATUS_FLAG_ERROR
XMC_I2C_CH_STATUS_FLAG_ACK_RECEIVED
XMC_I2C_CH_STATUS_FLAG_RECEIVER_START_INDICATION
XMC_I2C_CH_STATUS_FLAG_DATA_LOST_INDICATION
XMC_I2C_CH_STATUS_FLAG_TRANSMIT_SHIFT_INDICATION
XMC_I2C_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION
XMC_I2C_CH_STATUS_FLAG_RECEIVE_INDICATION
XMC_I2C_CH_STATUS_FLAG_ALTERNATIVE_RECEIVE_INDICATION
XMC_I2C_CH_STATUS_FLAG_BAUD_RATE_GENERATOR_INDICATION
XMC_I2C_CH_STATUS_t
XMC_I2C_CH_STATUS_OK
XMC_I2C_CH_STATUS_ERROR
XMC_I2C_CH_STATUS_BUSY
XMC_I2C_CH_ClearStatusFlag
XMC_I2C_CH_ConfigExternalInputSignalToBRG
XMC_I2C_CH_DisableAcknowledgeAddress0
XMC_I2C_CH_DisableDataTransmission
XMC_I2C_CH_DisableEvent
XMC_I2C_CH_EnableAcknowledgeAddress0
XMC_I2C_CH_EnableDataTransmission
XMC_I2C_CH_EnableEvent
XMC_I2C_CH_GetReceivedData
XMC_I2C_CH_GetReceiverStatusFlag
XMC_I2C_CH_GetSlaveAddress
XMC_I2C_CH_GetStatusFlag
XMC_I2C_CH_Init
XMC_I2C_CH_MasterReceiveAck
XMC_I2C_CH_MasterReceiveNack
XMC_I2C_CH_MasterRepeatedStart
XMC_I2C_CH_MasterStart
XMC_I2C_CH_MasterStop
XMC_I2C_CH_MasterTransmit
XMC_I2C_CH_SelectInterruptNodePointer
XMC_I2C_CH_SetBaudrate
XMC_I2C_CH_SetInputSource
XMC_I2C_CH_SetInterruptNodePointer
XMC_I2C_CH_SetSlaveAddress
XMC_I2C_CH_SlaveTransmit
XMC_I2C_CH_Start
XMC_I2C_CH_Stop
XMC_I2C_CH_TriggerServiceRequest
xmc_i2s.h
XMC_I2S0_CH0
XMC_I2S0_CH1
XMC_I2S1_CH0
XMC_I2S1_CH1
XMC_I2S2_CH0
XMC_I2S2_CH1
XMC_I2S_CH_BRG_SHIFT_CLOCK_OUTPUT_t
XMC_I2S_CH_BRG_SHIFT_CLOCK_OUTPUT_SCLK
XMC_I2S_CH_BRG_SHIFT_CLOCK_OUTPUT_DX1
XMC_I2S_CH_BUS_MODE_t
XMC_I2S_CH_BUS_MODE_MASTER
XMC_I2S_CH_BUS_MODE_SLAVE
XMC_I2S_CH_CHANNEL_t
XMC_I2S_CH_CHANNEL_1_LEFT
XMC_I2S_CH_CHANNEL_2_RIGHT
XMC_I2S_CH_EVENT_t
XMC_I2S_CH_EVENT_RECEIVE_START
XMC_I2S_CH_EVENT_DATA_LOST
XMC_I2S_CH_EVENT_TRANSMIT_SHIFT
XMC_I2S_CH_EVENT_TRANSMIT_BUFFER
XMC_I2S_CH_EVENT_STANDARD_RECEIVE
XMC_I2S_CH_EVENT_ALTERNATIVE_RECEIVE
XMC_I2S_CH_EVENT_BAUD_RATE_GENERATOR
XMC_I2S_CH_EVENT_WA_FALLING_EDGE
XMC_I2S_CH_EVENT_WA_RISING_EDGE
XMC_I2S_CH_EVENT_WA_GENERATION_END
XMC_I2S_CH_EVENT_DX2TIEN_ACTIVATED
XMC_I2S_CH_INPUT_t
XMC_I2S_CH_INPUT_DIN0
XMC_I2S_CH_INPUT_SLAVE_SCLKIN
XMC_I2S_CH_INPUT_SLAVE_WA
XMC_I2S_CH_INPUT_DIN1
XMC_I2S_CH_INPUT_DIN2
XMC_I2S_CH_INPUT_DIN3
XMC_I2S_CH_INTERRUPT_NODE_POINTER_t
XMC_I2S_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT
XMC_I2S_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER
XMC_I2S_CH_INTERRUPT_NODE_POINTER_RECEIVE
XMC_I2S_CH_INTERRUPT_NODE_POINTER_ALTERNATE_RECEIVE
XMC_I2S_CH_INTERRUPT_NODE_POINTER_PROTOCOL
XMC_I2S_CH_STATUS_FLAG_t
XMC_I2S_CH_STATUS_FLAG_WORD_ADDRESS
XMC_I2S_CH_STATUS_FLAG_DX2S
XMC_I2S_CH_STATUS_FLAG_DX2T_EVENT_DETECTED
XMC_I2S_CH_STATUS_FLAG_WA_FALLING_EDGE_EVENT
XMC_I2S_CH_STATUS_FLAG_WA_RISING_EDGE_EVENT
XMC_I2S_CH_STATUS_FLAG_WA_GENERATION_END
XMC_I2S_CH_STATUS_FLAG_RECEIVER_START_INDICATION
XMC_I2S_CH_STATUS_FLAG_DATA_LOST_INDICATION
XMC_I2S_CH_STATUS_FLAG_TRANSMIT_SHIFT_INDICATION
XMC_I2S_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION
XMC_I2S_CH_STATUS_FLAG_RECEIVE_INDICATION
XMC_I2S_CH_STATUS_FLAG_ALTERNATIVE_RECEIVE_INDICATION
XMC_I2S_CH_STATUS_FLAG_BAUD_RATE_GENERATOR_INDICATION
XMC_I2S_CH_STATUS_t
XMC_I2S_CH_STATUS_OK
XMC_I2S_CH_STATUS_ERROR
XMC_I2S_CH_STATUS_BUSY
XMC_I2S_CH_WA_POLARITY_t
XMC_I2S_CH_WA_POLARITY_DIRECT
XMC_I2S_CH_WA_POLARITY_INVERTED
XMC_I2S_CH_ClearStatusFlag
XMC_I2S_CH_ConfigureShiftClockOutput
XMC_I2S_CH_DisableDataTransmission
XMC_I2S_CH_DisableDelayCompensation
XMC_I2S_CH_DisableEvent
XMC_I2S_CH_DisableInputInversion
XMC_I2S_CH_DisableMasterClock
XMC_I2S_CH_EnableDataTransmission
XMC_I2S_CH_EnableDelayCompensation
XMC_I2S_CH_EnableEvent
XMC_I2S_CH_EnableInputInversion
XMC_I2S_CH_EnableMasterClock
XMC_I2S_CH_GetReceivedData
XMC_I2S_CH_GetStatusFlag
XMC_I2S_CH_Init
XMC_I2S_CH_Receive
XMC_I2S_CH_SelectInterruptNodePointer
XMC_I2S_CH_SetBaudrate
XMC_I2S_CH_SetBitOrderLsbFirst
XMC_I2S_CH_SetBitOrderMsbFirst
XMC_I2S_CH_SetFrameLength
XMC_I2S_CH_SetInputSource
XMC_I2S_CH_SetInterruptNodePointer
XMC_I2S_CH_SetSystemWordLength
XMC_I2S_CH_SetWordLength
XMC_I2S_CH_Start
XMC_I2S_CH_Stop
XMC_I2S_CH_Transmit
XMC_I2S_CH_TriggerServiceRequest
XMC_I2S_CH_WordAddressSignalPolarity
xmc_ledts.h
XMC_LEDTS0
XMC_LEDTS0
XMC_LEDTS_t
XMC_LEDTS_ACCUMULATION_COUNT_t
XMC_LEDTS_ACCUMULATION_COUNT_1_TIME
XMC_LEDTS_ACCUMULATION_COUNT_2_TIMES
XMC_LEDTS_ACCUMULATION_COUNT_3_TIMES
XMC_LEDTS_ACCUMULATION_COUNT_4_TIMES
XMC_LEDTS_ACCUMULATION_COUNT_5_TIMES
XMC_LEDTS_ACCUMULATION_COUNT_6_TIMES
XMC_LEDTS_ACCUMULATION_COUNT_7_TIMES
XMC_LEDTS_ACCUMULATION_COUNT_8_TIMES
XMC_LEDTS_ACCUMULATION_COUNT_9_TIMES
XMC_LEDTS_ACCUMULATION_COUNT_10_TIMES
XMC_LEDTS_ACCUMULATION_COUNT_11_TIMES
XMC_LEDTS_ACCUMULATION_COUNT_12_TIMES
XMC_LEDTS_ACCUMULATION_COUNT_13_TIMES
XMC_LEDTS_ACCUMULATION_COUNT_14_TIMES
XMC_LEDTS_ACCUMULATION_COUNT_15_TIMES
XMC_LEDTS_ACCUMULATION_COUNT_16_TIMES
XMC_LEDTS_ACTIVE_LEVEL_LED_COL_t
XMC_LEDTS_ACTIVE_LEVEL_LED_COL_LOW
XMC_LEDTS_ACTIVE_LEVEL_LED_COL_HIGH
XMC_LEDTS_AUTOSCAN_INTERRUPT_FLAG_t
XMC_LEDTS_AUTOSCAN_INTERRUPT_FLAG_INACTIVE
XMC_LEDTS_AUTOSCAN_INTERRUPT_FLAG_ACTIVE
XMC_LEDTS_CLOCK_TYPE_t
XMC_LEDTS_CLOCK_TYPE_MASTER
XMC_LEDTS_CLOCK_TYPE_SLAVE
XMC_LEDTS_COMMON_COMPARE_t
XMC_LEDTS_COMMON_COMPARE_DISABLE
XMC_LEDTS_COMMON_COMPARE_ENABLE
XMC_LEDTS_EXT_PULLUP_COLA_t
XMC_LEDTS_EXT_PULLUP_COLA_DISABLE
XMC_LEDTS_EXT_PULLUP_COLA_ENABLE
XMC_LEDTS_EXTEND_TS_OUTPUT_t
XMC_LEDTS_EXTEND_TS_OUTPUT_BY_1_CLK
XMC_LEDTS_EXTEND_TS_OUTPUT_BY_4_CLK
XMC_LEDTS_EXTEND_TS_OUTPUT_BY_8_CLK
XMC_LEDTS_EXTEND_TS_OUTPUT_BY_16_CLK
XMC_LEDTS_FLAG_STATUS_t
XMC_LEDTS_FLAG_STATUS_NO
XMC_LEDTS_FLAG_STATUS_YES
XMC_LEDTS_INTERRUPT_t
XMC_LEDTS_INTERRUPT_TIMESLICE
XMC_LEDTS_INTERRUPT_TIMEFRAME
XMC_LEDTS_INTERRUPT_TIMEPERIOD
XMC_LEDTS_LED_COLUMN_t
XMC_LEDTS_LED_COLUMN_0
XMC_LEDTS_LED_COLUMN_1
XMC_LEDTS_LED_COLUMN_2
XMC_LEDTS_LED_COLUMN_3
XMC_LEDTS_LED_COLUMN_4
XMC_LEDTS_LED_COLUMN_5
XMC_LEDTS_LED_COLUMN_6
XMC_LEDTS_LED_COLUMN_A
XMC_LEDTS_LED_FUNC_t
XMC_LEDTS_LED_FUNC_DISABLE
XMC_LEDTS_LED_FUNC_ENABLE
XMC_LEDTS_NUMBER_LED_COLUMNS_t
XMC_LEDTS_NUMBER_LED_COLUMNS_1
XMC_LEDTS_NUMBER_LED_COLUMNS_2
XMC_LEDTS_NUMBER_LED_COLUMNS_3
XMC_LEDTS_NUMBER_LED_COLUMNS_4
XMC_LEDTS_NUMBER_LED_COLUMNS_5
XMC_LEDTS_NUMBER_LED_COLUMNS_6
XMC_LEDTS_NUMBER_LED_COLUMNS_7
XMC_LEDTS_NUMBER_LED_COLUMNS_8
XMC_LEDTS_NUMBER_TS_INPUT_t
XMC_LEDTS_NUMBER_TS_INPUT_1
XMC_LEDTS_NUMBER_TS_INPUT_2
XMC_LEDTS_NUMBER_TS_INPUT_3
XMC_LEDTS_NUMBER_TS_INPUT_4
XMC_LEDTS_NUMBER_TS_INPUT_5
XMC_LEDTS_NUMBER_TS_INPUT_6
XMC_LEDTS_NUMBER_TS_INPUT_7
XMC_LEDTS_NUMBER_TS_INPUT_8
XMC_LEDTS_PAD_TURN_SW_CONTROL_t
XMC_LEDTS_SW_CONTROL_DISABLE
XMC_LEDTS_SW_CONTROL_ENABLE
XMC_LEDTS_PAD_TURN_t
XMC_LEDTS_PAD_TURN_0
XMC_LEDTS_PAD_TURN_1
XMC_LEDTS_PAD_TURN_2
XMC_LEDTS_PAD_TURN_3
XMC_LEDTS_PAD_TURN_4
XMC_LEDTS_PAD_TURN_5
XMC_LEDTS_PAD_TURN_6
XMC_LEDTS_PAD_TURN_7
XMC_LEDTS_STATUS_t
XMC_LEDTS_STATUS_SUCCESS
XMC_LEDTS_STATUS_RUNNING
XMC_LEDTS_STATUS_ERROR
XMC_LEDTS_STATUS_IDLE
XMC_LEDTS_SUSPEND_t
XMC_LEDTS_SUSPEND_DISABLE
XMC_LEDTS_SUSPEND_ENABLE
XMC_LEDTS_TF_INTERRUPT_FLAG_t
XMC_LEDTS_TF_INTERRUPT_FLAG_INACTIVE
XMC_LEDTS_TF_INTERRUPT_FLAG_ACTIVE
XMC_LEDTS_TF_VALIDATION_t
XMC_LEDTS_TF_VALIDATION_DISABLE
XMC_LEDTS_TF_VALIDATION_ENABLE
XMC_LEDTS_TP_SYNC_t
XMC_LEDTS_TP_SYNC_DISABLE
XMC_LEDTS_TP_SYNC_ENABLE
XMC_LEDTS_TS_COUNTER_AUTO_RESET_t
XMC_LEDTS_TS_COUNTER_AUTO_RESET_DISABLE
XMC_LEDTS_TS_COUNTER_AUTO_RESET_ENABLE
XMC_LEDTS_TS_COUNTER_MASK_t
XMC_LEDTS_TS_COUNTER_MASK_1_LSB
XMC_LEDTS_TS_COUNTER_MASK_2_LSB
XMC_LEDTS_TS_COUNTER_MASK_3_LSB
XMC_LEDTS_TS_COUNTER_MASK_4_LSB
XMC_LEDTS_TS_COUNTER_MASK_5_LSB
XMC_LEDTS_TS_COUNTER_MASK_6_LSB
XMC_LEDTS_TS_COUNTER_MASK_7_LSB
XMC_LEDTS_TS_COUNTER_MASK_8_LSB
XMC_LEDTS_TS_COUNTER_OVERLOW_FLAG_t
XMC_LEDTS_TS_COUNTER_OVERLOW_FLAG_NO
XMC_LEDTS_TS_COUNTER_OVERLOW_FLAG_YES
XMC_LEDTS_TS_COUNTER_SATURATION_t
XMC_LEDTS_TS_COUNTER_SATURATION_DISABLE
XMC_LEDTS_TS_COUNTER_SATURATION_ENABLE
XMC_LEDTS_TS_FUNC_t
XMC_LEDTS_TS_FUNC_DISABLE
XMC_LEDTS_TS_FUNC_ENABLE
XMC_LEDTS_TS_INPUT_t
XMC_LEDTS_TS_INPUT_0
XMC_LEDTS_TS_INPUT_1
XMC_LEDTS_TS_INPUT_2
XMC_LEDTS_TS_INPUT_3
XMC_LEDTS_TS_INPUT_4
XMC_LEDTS_TS_INPUT_5
XMC_LEDTS_TS_INPUT_6
XMC_LEDTS_TS_INPUT_7
XMC_LEDTS_TS_INTERRUPT_FLAG_t
XMC_LEDTS_INTERRUPT_FLAG_TIMESLICE
XMC_LEDTS_INTERRUPT_FLAG_TIMEFRAME
XMC_LEDTS_INTERRUPT_FLAG_TIMEPERIOD
XMC_LEDTS_INTERRUPT_FLAG_TSCOUNTER_OVERFLOW
XMC_LEDTS_ClearInterruptFlag
XMC_LEDTS_DisableInterrupt
XMC_LEDTS_EnableInterrupt
XMC_LEDTS_InitGlobal
XMC_LEDTS_InitLED
XMC_LEDTS_InitTSAdvanced
XMC_LEDTS_InitTSBasic
XMC_LEDTS_ReadFNCOL
XMC_LEDTS_ReadInterruptFlag
XMC_LEDTS_ReadTSVAL
XMC_LEDTS_SetActivePADNo
XMC_LEDTS_SetColumnBrightness
XMC_LEDTS_SetCommonOscillationWindow
XMC_LEDTS_SetLEDLinePattern
XMC_LEDTS_SetNumOfLEDColumns
XMC_LEDTS_SetOscillationWindow
XMC_LEDTS_StartCounter
XMC_LEDTS_StopCounter
xmc_posif.h
XMC_POSIF_t
XMC_POSIF_FILTER_t
XMC_POSIF_FILTER_DISABLED
XMC_POSIF_FILTER_1_CLOCK_CYCLE
XMC_POSIF_FILTER_2_CLOCK_CYCLE
XMC_POSIF_FILTER_4_CLOCK_CYCLE
XMC_POSIF_FILTER_8_CLOCK_CYCLE
XMC_POSIF_FILTER_16_CLOCK_CYCLE
XMC_POSIF_FILTER_32_CLOCK_CYCLE
XMC_POSIF_FILTER_64_CLOCK_CYCLE
XMC_POSIF_HSC_TRIGGER_EDGE_t
XMC_POSIF_HSC_TRIGGER_EDGE_RISING
XMC_POSIF_HSC_TRIGGER_EDGE_FALLING
XMC_POSIF_INPUT_ACTIVE_LEVEL_t
XMC_POSIF_INPUT_ACTIVE_LEVEL_HIGH
XMC_POSIF_INPUT_ACTIVE_LEVEL_LOW
XMC_POSIF_INPUT_PORT_t
XMC_POSIF_INPUT_PORT_A
XMC_POSIF_INPUT_PORT_B
XMC_POSIF_INPUT_PORT_C
XMC_POSIF_INPUT_PORT_D
XMC_POSIF_INPUT_PORT_E
XMC_POSIF_INPUT_PORT_F
XMC_POSIF_INPUT_PORT_G
XMC_POSIF_INPUT_PORT_H
XMC_POSIF_IRQ_EVENT_t
XMC_POSIF_IRQ_EVENT_CHE
XMC_POSIF_IRQ_EVENT_WHE
XMC_POSIF_IRQ_EVENT_HALL_INPUT
XMC_POSIF_IRQ_EVENT_MCP_SHADOW_TRANSFER
XMC_POSIF_IRQ_EVENT_INDX
XMC_POSIF_IRQ_EVENT_ERR
XMC_POSIF_IRQ_EVENT_CNT
XMC_POSIF_IRQ_EVENT_DIR
XMC_POSIF_IRQ_EVENT_PCLK
XMC_POSIF_MODE_t
XMC_POSIF_MODE_HALL_SENSOR
XMC_POSIF_MODE_QD
XMC_POSIF_MODE_MCM
XMC_POSIF_MODE_MCM_QD
XMC_POSIF_QD_DIR_t
XMC_POSIF_QD_DIR_COUNTERCLOCKWISE
XMC_POSIF_QD_DIR_CLOCKWISE
XMC_POSIF_QD_INDEX_GENERATION_t
XMC_POSIF_QD_INDEX_GENERATION_NEVER
XMC_POSIF_QD_INDEX_GENERATION_ONCE
XMC_POSIF_QD_INDEX_GENERATION_ALWAYS
XMC_POSIF_QD_MODE_t
XMC_POSIF_QD_MODE_QUADRATURE
XMC_POSIF_QD_MODE_DIRECTION_COUNT
XMC_POSIF_SR_ID_t
XMC_POSIF_SR_ID_0
XMC_POSIF_SR_ID_1
XMC_POSIF_STATUS_t
XMC_POSIF_STATUS_OK
XMC_POSIF_STATUS_ERROR
XMC_POSIF_ClearEvent
XMC_POSIF_Disable
XMC_POSIF_DisableEvent
XMC_POSIF_Enable
XMC_POSIF_EnableEvent
XMC_POSIF_GetEventStatus
XMC_POSIF_HSC_GetCurrentPattern
XMC_POSIF_HSC_GetExpectedPattern
XMC_POSIF_HSC_GetLastSampledPattern
XMC_POSIF_HSC_Init
XMC_POSIF_HSC_SetCurrentPattern
XMC_POSIF_HSC_SetExpectedPattern
XMC_POSIF_HSC_SetHallPatterns
XMC_POSIF_HSC_UpdateHallPattern
XMC_POSIF_Init
XMC_POSIF_IsRunning
XMC_POSIF_MCM_EnableMultiChannelPatternUpdate
XMC_POSIF_MCM_GetMultiChannelPattern
XMC_POSIF_MCM_GetShadowMultiChannelPattern
XMC_POSIF_MCM_Init
XMC_POSIF_MCM_SetMultiChannelPattern
XMC_POSIF_MCM_UpdateMultiChannelPattern
XMC_POSIF_QD_GetCurrentIndexValue
XMC_POSIF_QD_GetCurrentState
XMC_POSIF_QD_GetDirection
XMC_POSIF_QD_GetPreviousState
XMC_POSIF_QD_Init
XMC_POSIF_SelectInputSource
XMC_POSIF_SetEvent
XMC_POSIF_SetInterruptNode
XMC_POSIF_SetMode
XMC_POSIF_Start
XMC_POSIF_Stop
xmc_rtc.h
XMC_RTC_EVENT_t
XMC_RTC_EVENT_PERIODIC_SECONDS
XMC_RTC_EVENT_PERIODIC_MINUTES
XMC_RTC_EVENT_PERIODIC_HOURS
XMC_RTC_EVENT_PERIODIC_DAYS
XMC_RTC_EVENT_PERIODIC_MONTHS
XMC_RTC_EVENT_PERIODIC_YEARS
XMC_RTC_EVENT_ALARM
XMC_RTC_MONTH_t
XMC_RTC_STATUS_t
XMC_RTC_STATUS_OK
XMC_RTC_STATUS_ERROR
XMC_RTC_STATUS_BUSY
XMC_RTC_WEEKDAY_t
XMC_RTC_ClearEvent
XMC_RTC_Disable
XMC_RTC_DisableEvent
XMC_RTC_Enable
XMC_RTC_EnableEvent
XMC_RTC_GetAlarm
XMC_RTC_GetAlarmStdFormat
XMC_RTC_GetEventStatus
XMC_RTC_GetPrescaler
XMC_RTC_GetTime
XMC_RTC_GetTimeStdFormat
XMC_RTC_Init
XMC_RTC_IsEnabled
XMC_RTC_IsRunning
XMC_RTC_SetAlarm
XMC_RTC_SetAlarmStdFormat
XMC_RTC_SetPrescaler
XMC_RTC_SetTime
XMC_RTC_SetTimeStdFormat
XMC_RTC_Start
XMC_RTC_Stop
xmc_scu.h
XMC_SCU_INTERRUPT_EVENT_HANDLER_t
XMC_SCU_STATUS_t
XMC_SCU_STATUS_OK
XMC_SCU_STATUS_ERROR
XMC_SCU_STATUS_BUSY
XMC_SCU_CLOCK_GatePeripheralClock
XMC_SCU_CLOCK_GetCpuClockFrequency
XMC_SCU_CLOCK_GetPeripheralClockFrequency
XMC_SCU_CLOCK_Init
XMC_SCU_CLOCK_IsPeripheralClockGated
XMC_SCU_CLOCK_UngatePeripheralClock
XMC_SCU_GetMirrorStatus
XMC_SCU_INTERRUPT_ClearEventStatus
XMC_SCU_INTERRUPT_DisableEvent
XMC_SCU_INTERRUPT_EnableEvent
XMC_SCU_INTERRUPT_SetEventHandler
XMC_SCU_INTERRUPT_TriggerEvent
XMC_SCU_INTERUPT_GetEventStatus
XMC_SCU_IRQHandler
XMC_SCU_RESET_ClearDeviceResetReason
XMC_SCU_RESET_GetDeviceResetReason
XMC_SCU_SetCcuTriggerHigh
XMC_SCU_SetCcuTriggerLow
xmc_sdmmc.h
XMC_SDMMC
XMC_SDMMC_ACMD_ERR_t
XMC_SDMMC_ACMD12_NOT_EXEC_ERR
XMC_SDMMC_ACMD_TIMEOUT_ERR
XMC_SDMMC_ACMD_CRC_ERR
XMC_SDMMC_ACMD_END_BIT_ERR
XMC_SDMMC_ACMD_IND_ERR
XMC_SDMMC_CMD_NOT_ISSUED_BY_ACMD12_ERR
XMC_SDMMC_BUS_VOLTAGE_t
XMC_SDMMC_CD_SOURCE_t
XMC_SDMMC_CD_STATUS_t
XMC_SDMMC_COMMAND_RESPONSE_t
XMC_SDMMC_COMMAND_RESPONSE_NONE
XMC_SDMMC_COMMAND_RESPONSE_LONG
XMC_SDMMC_COMMAND_RESPONSE_SHORT
XMC_SDMMC_COMMAND_RESPONSE_SHORT_BUSY
XMC_SDMMC_COMMAND_TYPE_t
XMC_SDMMC_COMMAND_TYPE_NORMAL
XMC_SDMMC_COMMAND_TYPE_SUSPEND
XMC_SDMMC_COMMAND_TYPE_RESUME
XMC_SDMMC_COMMAND_TYPE_ABORT
XMC_SDMMC_DAT_TIMEOUT_COUNTER_t
XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_14
XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_15
XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_16
XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_17
XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_18
XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_19
XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_20
XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_21
XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_22
XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_23
XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_24
XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_25
XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_26
XMC_SDMMC_DAT_TIMEOUT_COUNTER_2_POW_27
XMC_SDMMC_DATA_LINES_t
XMC_SDMMC_DATA_LINES_1
XMC_SDMMC_DATA_LINES_4
XMC_SDMMC_DATA_LINES_8
XMC_SDMMC_DATA_TRANSFER_DIR_t
XMC_SDMMC_DATA_TRANSFER_CARD_TO_HOST
XMC_SDMMC_EVENT_t
XMC_SDMMC_CMD_COMPLETE
XMC_SDMMC_TX_COMPLETE
XMC_SDMMC_BLOCK_GAP_EVENT
XMC_SDMMC_BUFFER_WRITE_READY
XMC_SDMMC_BUFFER_READ_READY
XMC_SDMMC_CARD_INS
XMC_SDMMC_CARD_REMOVAL
XMC_SDMMC_CARD_INT
XMC_SDMMC_CARD_ERR
XMC_SDMMC_CMD_TIMEOUT_ERR
XMC_SDMMC_CMD_CRC_ERR
XMC_SDMMC_CMD_END_BIT_ERR
XMC_SDMMC_CMD_IND_ERR
XMC_SDMMC_DATA_TIMEOUT_ERR
XMC_SDMMC_DATA_CRC_ERR
XMC_SDMMC_DATA_END_BIT_ERR
XMC_SDMMC_CURRENT_LIMIT_ERR
XMC_SDMMC_ACMD_ERR
XMC_SDMMC_TARGET_RESP_ERR
XMC_SDMMC_RESPONSE_TYPE_t
XMC_SDMMC_RESPONSE_TYPE_NO_RESPONSE
XMC_SDMMC_RESPONSE_TYPE_R1
XMC_SDMMC_RESPONSE_TYPE_R1b
XMC_SDMMC_RESPONSE_TYPE_R2
XMC_SDMMC_RESPONSE_TYPE_R3
XMC_SDMMC_RESPONSE_TYPE_R6
XMC_SDMMC_RESPONSE_TYPE_R7
XMC_SDMMC_SDCLK_FREQ_SEL_t
XMC_SDMMC_CLK_DIV_1
XMC_SDMMC_CLK_DIV_2
XMC_SDMMC_CLK_DIV_4
XMC_SDMMC_CLK_DIV_8
XMC_SDMMC_CLK_DIV_16
XMC_SDMMC_CLK_DIV_32
XMC_SDMMC_CLK_DIV_64
XMC_SDMMC_CLK_DIV_128
XMC_SDMMC_CLK_DIV_256
XMC_SDMMC_STATUS_t
XMC_SDMMC_STATUS_SUCCESS
XMC_SDMMC_STATUS_CMD_LINE_BUSY
XMC_SDMMC_STATUS_DAT_LINE_BUSY
XMC_SDMMC_SW_RESET_t
XMC_SDMMC_SW_RESET_ALL
XMC_SDMMC_SW_RST_CMD_LINE
XMC_SDMMC_SW_RST_DAT_LINE
XMC_SDMMC_TRANSFER_MODE_AUTO_CMD_t
XMC_SDMMC_TRANSFER_MODE_AUTO_CMD_DISABLED
XMC_SDMMC_TRANSFER_MODE_AUTO_CMD_12
XMC_SDMMC_TRANSFER_MODE_TYPE_t
XMC_SDMMC_TRANSFER_MODE_TYPE_SINGLE
XMC_SDMMC_TRANSFER_MODE_TYPE_INFINITE
XMC_SDMMC_TRANSFER_MODE_TYPE_MULTIPLE
XMC_SDMMC_TRANSFER_MODE_TYPE_STOP_MULTIPLE
XMC_SDMMC_WAKEUP_EVENT_t
XMC_SDMMC_WAKEUP_EN_CARD_INT
XMC_SDMMC_WAKEUP_EN_CARD_INS
XMC_SDMMC_WAKEUP_EN_CARD_REM
XMC_SDMMC_BusPowerOff
XMC_SDMMC_BusPowerOn
XMC_SDMMC_ClearEvent
XMC_SDMMC_Disable
XMC_SDMMC_DisableDelayCmdDatLines
XMC_SDMMC_DisableEvent
XMC_SDMMC_DisableEventStatus
XMC_SDMMC_DisableHighSpeed
XMC_SDMMC_DisableInterruptAtBlockGap
XMC_SDMMC_DisableWakeupEvent
XMC_SDMMC_Enable
XMC_SDMMC_EnableDelayCmdDatLines
XMC_SDMMC_EnableEvent
XMC_SDMMC_EnableEventStatus
XMC_SDMMC_EnableHighSpeed
XMC_SDMMC_EnableInterruptAtBlockGap
XMC_SDMMC_EnableWakeupEvent
XMC_SDMMC_GetACMDErrStatus
XMC_SDMMC_GetAutoCommandResponse
XMC_SDMMC_GetClockStability
XMC_SDMMC_GetCommandResponse
XMC_SDMMC_GetContinueRequest
XMC_SDMMC_GetEvent
XMC_SDMMC_GetPowerStatus
XMC_SDMMC_GetPresentState
XMC_SDMMC_GetR2Response
XMC_SDMMC_GetSWResetStatus
XMC_SDMMC_GetTransferBlocksNum
XMC_SDMMC_Init
XMC_SDMMC_IsAllDataLinesHigh
XMC_SDMMC_IsAnyErrorEvent
XMC_SDMMC_IsCommandLineBusy
XMC_SDMMC_IsDataLineBusy
XMC_SDMMC_ReadFIFO
XMC_SDMMC_SDClockDisable
XMC_SDMMC_SDClockEnable
XMC_SDMMC_SDClockFreqSelect
XMC_SDMMC_SendCommand
XMC_SDMMC_SetBusVoltage
XMC_SDMMC_SetCardDetectionSource
XMC_SDMMC_SetCardDetectionStatus
XMC_SDMMC_SetContinueRequest
XMC_SDMMC_SetDataLineTimeout
XMC_SDMMC_SetDataTransferDirection
XMC_SDMMC_SetDataTransferMode
XMC_SDMMC_SetDataTransferWidth
XMC_SDMMC_SetDelay
XMC_SDMMC_SetReadWaitControl
XMC_SDMMC_SetStopAtBlockGap
XMC_SDMMC_SetSWReset
XMC_SDMMC_Start
XMC_SDMMC_Stop
XMC_SDMMC_TriggerACMDErr
XMC_SDMMC_TriggerEvent
XMC_SDMMC_WriteFIFO
xmc_spi.h
XMC_SPI0_CH0
XMC_SPI0_CH1
XMC_SPI1_CH0
XMC_SPI1_CH1
XMC_SPI2_CH0
XMC_SPI2_CH1
XMC_SPI_CH_BRG_SHIFT_CLOCK_OUTPUT_t
XMC_SPI_CH_BRG_SHIFT_CLOCK_OUTPUT_SCLK
XMC_SPI_CH_BRG_SHIFT_CLOCK_OUTPUT_DX1
XMC_SPI_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_t
XMC_SPI_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_0_DELAY_DISABLED
XMC_SPI_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_1_DELAY_DISABLED
XMC_SPI_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_0_DELAY_ENABLED
XMC_SPI_CH_BUS_MODE_t
XMC_SPI_CH_BUS_MODE_MASTER
XMC_SPI_CH_BUS_MODE_SLAVE
XMC_SPI_CH_DATA_POLARITY_t
XMC_SPI_CH_DATA_POLARITY_DIRECT
XMC_SPI_CH_DATA_POLARITY_INVERT
XMC_SPI_CH_EVENT_t
XMC_SPI_CH_EVENT_RECEIVE_START
XMC_SPI_CH_EVENT_DATA_LOST
XMC_SPI_CH_EVENT_TRANSMIT_SHIFT
XMC_SPI_CH_EVENT_TRANSMIT_BUFFER
XMC_SPI_CH_EVENT_STANDARD_RECEIVE
XMC_SPI_CH_EVENT_ALTERNATIVE_RECEIVE
XMC_SPI_CH_EVENT_BAUD_RATE_GENERATOR
XMC_SPI_CH_EVENT_PARITY_ERROR
XMC_SPI_CH_EVENT_MSLS_CHANGE
XMC_SPI_CH_EVENT_DX2TIEN_ACTIVATED
XMC_SPI_CH_INPUT_FREQ_SLAVE_SELECT_DELAY_t
XMC_SPI_CH_INPUT_FREQ_SLAVE_SELECT_DELAY_FPDIV
XMC_SPI_CH_INPUT_FREQ_SLAVE_SELECT_DELAY_FPPP
XMC_SPI_CH_INPUT_FREQ_SLAVE_SELECT_DELAY_FSCLK
XMC_SPI_CH_INPUT_FREQ_SLAVE_SELECT_DELAY_FMCLK
XMC_SPI_CH_INPUT_t
XMC_SPI_CH_INPUT_DIN0
XMC_SPI_CH_INPUT_SLAVE_SCLKIN
XMC_SPI_CH_INPUT_SLAVE_SELIN
XMC_SPI_CH_INPUT_DIN1
XMC_SPI_CH_INPUT_DIN2
XMC_SPI_CH_INPUT_DIN3
XMC_SPI_CH_INTERRUPT_NODE_POINTER_t
XMC_SPI_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT
XMC_SPI_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER
XMC_SPI_CH_INTERRUPT_NODE_POINTER_RECEIVE
XMC_SPI_CH_INTERRUPT_NODE_POINTER_ALTERNATE_RECEIVE
XMC_SPI_CH_INTERRUPT_NODE_POINTER_PROTOCOL
XMC_SPI_CH_MODE_t
XMC_SPI_CH_MODE_STANDARD
XMC_SPI_CH_MODE_STANDARD_HALFDUPLEX
XMC_SPI_CH_MODE_DUAL
XMC_SPI_CH_MODE_QUAD
XMC_SPI_CH_SLAVE_SEL_MSLS_INV_t
XMC_SPI_CH_SLAVE_SEL_SAME_AS_MSLS
XMC_SPI_CH_SLAVE_SEL_INV_TO_MSLS
XMC_SPI_CH_SLAVE_SELECT_t
XMC_SPI_CH_SLAVE_SELECT_0
XMC_SPI_CH_SLAVE_SELECT_1
XMC_SPI_CH_SLAVE_SELECT_2
XMC_SPI_CH_SLAVE_SELECT_3
XMC_SPI_CH_SLAVE_SELECT_4
XMC_SPI_CH_SLAVE_SELECT_5
XMC_SPI_CH_SLAVE_SELECT_6
XMC_SPI_CH_SLAVE_SELECT_7
XMC_SPI_CH_STATUS_FLAG_t
XMC_SPI_CH_STATUS_FLAG_MSLS
XMC_SPI_CH_STATUS_FLAG_DX2S
XMC_SPI_CH_STATUS_FLAG_MSLS_EVENT_DETECTED
XMC_SPI_CH_STATUS_FLAG_DX2T_EVENT_DETECTED
XMC_SPI_CH_STATUS_FLAG_PARITY_ERROR_EVENT_DETECTED
XMC_SPI_CH_STATUS_FLAG_RECEIVER_START_INDICATION
XMC_SPI_CH_STATUS_FLAG_DATA_LOST_INDICATION
XMC_SPI_CH_STATUS_FLAG_TRANSMIT_SHIFT_INDICATION
XMC_SPI_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION
XMC_SPI_CH_STATUS_FLAG_RECEIVE_INDICATION
XMC_SPI_CH_STATUS_FLAG_ALTERNATIVE_RECEIVE_INDICATION
XMC_SPI_CH_STATUS_FLAG_BAUD_RATE_GENERATOR_INDICATION
XMC_SPI_CH_STATUS_t
XMC_SPI_CH_STATUS_OK
XMC_SPI_CH_STATUS_ERROR
XMC_SPI_CH_STATUS_BUSY
XMC_SPI_CH_ClearStatusFlag
XMC_SPI_CH_ConfigExternalInputSignalToBRG
XMC_SPI_CH_ConfigureShiftClockOutput
XMC_SPI_CH_DisableDataTransmission
XMC_SPI_CH_DisableDelayCompensation
XMC_SPI_CH_DisableEOF
XMC_SPI_CH_DisableEvent
XMC_SPI_CH_DisableFEM
XMC_SPI_CH_DisableInputInversion
XMC_SPI_CH_DisableInterwordDelay
XMC_SPI_CH_DisableMasterClock
XMC_SPI_CH_DisableSlaveSelect
XMC_SPI_CH_DisableSlaveSelectCodedMode
XMC_SPI_CH_DisableSOF
XMC_SPI_CH_EnableDataTransmission
XMC_SPI_CH_EnableDelayCompensation
XMC_SPI_CH_EnableEOF
XMC_SPI_CH_EnableEvent
XMC_SPI_CH_EnableFEM
XMC_SPI_CH_EnableInputInversion
XMC_SPI_CH_EnableInterwordDelay
XMC_SPI_CH_EnableMasterClock
XMC_SPI_CH_EnableSlaveSelect
XMC_SPI_CH_EnableSlaveSelectCodedMode
XMC_SPI_CH_EnableSOF
XMC_SPI_CH_GetReceivedData
XMC_SPI_CH_GetStatusFlag
XMC_SPI_CH_Init
XMC_SPI_CH_Receive
XMC_SPI_CH_SelectInterruptNodePointer
XMC_SPI_CH_SetBaudrate
XMC_SPI_CH_SetBitOrderLsbFirst
XMC_SPI_CH_SetBitOrderMsbFirst
XMC_SPI_CH_SetFrameLength
XMC_SPI_CH_SetInputSource
XMC_SPI_CH_SetInterruptNodePointer
XMC_SPI_CH_SetInterwordDelay
XMC_SPI_CH_SetInterwordDelaySCLK
XMC_SPI_CH_SetSlaveSelectDelay
XMC_SPI_CH_SetSlaveSelectPolarity
XMC_SPI_CH_SetTransmitMode
XMC_SPI_CH_SetWordLength
XMC_SPI_CH_Start
XMC_SPI_CH_Stop
XMC_SPI_CH_Transmit
XMC_SPI_CH_TriggerServiceRequest
xmc_uart.h
XMC_UART0_CH0
XMC_UART0_CH1
XMC_UART1_CH0
XMC_UART1_CH1
XMC_UART2_CH0
XMC_UART2_CH1
XMC_UART_CH_EVENT_t
XMC_UART_CH_EVENT_RECEIVE_START
XMC_UART_CH_EVENT_DATA_LOST
XMC_UART_CH_EVENT_TRANSMIT_SHIFT
XMC_UART_CH_EVENT_TRANSMIT_BUFFER
XMC_UART_CH_EVENT_STANDARD_RECEIVE
XMC_UART_CH_EVENT_ALTERNATIVE_RECEIVE
XMC_UART_CH_EVENT_BAUD_RATE_GENERATOR
XMC_UART_CH_EVENT_SYNCHRONIZATION_BREAK
XMC_UART_CH_EVENT_COLLISION
XMC_UART_CH_EVENT_RECEIVER_NOISE
XMC_UART_CH_EVENT_FORMAT_ERROR
XMC_UART_CH_EVENT_FRAME_FINISHED
XMC_UART_CH_INPUT_SAMPLING_FREQ_t
XMC_UART_CH_INPUT_SAMPLING_FREQ_FPERIPH
XMC_UART_CH_INPUT_SAMPLING_FREQ_FRACTIONAL_DIVIDER
XMC_UART_CH_INPUT_t
XMC_UART_CH_INPUT_RXD
XMC_UART_CH_INPUT_RXD1
XMC_UART_CH_INPUT_RXD2
XMC_UART_CH_INTERRUPT_NODE_POINTER_t
XMC_UART_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT
XMC_UART_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER
XMC_UART_CH_INTERRUPT_NODE_POINTER_RECEIVE
XMC_UART_CH_INTERRUPT_NODE_POINTER_ALTERNATE_RECEIVE
XMC_UART_CH_INTERRUPT_NODE_POINTER_PROTOCOL
XMC_UART_CH_STATUS_FLAG_t
XMC_UART_CH_STATUS_FLAG_TRANSMISSION_IDLE
XMC_UART_CH_STATUS_FLAG_RECEPTION_IDLE
XMC_UART_CH_STATUS_FLAG_SYNCHRONIZATION_BREAK_DETECTED
XMC_UART_CH_STATUS_FLAG_COLLISION_DETECTED
XMC_UART_CH_STATUS_FLAG_RECEIVER_NOISE_DETECTED
XMC_UART_CH_STATUS_FLAG_FORMAT_ERROR_IN_STOP_BIT_0
XMC_UART_CH_STATUS_FLAG_FORMAT_ERROR_IN_STOP_BIT_1
XMC_UART_CH_STATUS_FLAG_RECEIVE_FRAME_FINISHED
XMC_UART_CH_STATUS_FLAG_TRANSMITTER_FRAME_FINISHED
XMC_UART_CH_STATUS_FLAG_TRANSFER_STATUS_BUSY
XMC_UART_CH_STATUS_FLAG_RECEIVER_START_INDICATION
XMC_UART_CH_STATUS_FLAG_DATA_LOST_INDICATION
XMC_UART_CH_STATUS_FLAG_TRANSMIT_SHIFT_INDICATION
XMC_UART_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION
XMC_UART_CH_STATUS_FLAG_RECEIVE_INDICATION
XMC_UART_CH_STATUS_FLAG_ALTERNATIVE_RECEIVE_INDICATION
XMC_UART_CH_STATUS_FLAG_BAUD_RATE_GENERATOR_INDICATION
XMC_UART_CH_STATUS_t
XMC_UART_CH_STATUS_OK
XMC_UART_CH_STATUS_ERROR
XMC_UART_CH_STATUS_BUSY
XMC_UART_CH_ClearStatusFlag
XMC_UART_CH_DisableDataTransmission
XMC_UART_CH_DisableEvent
XMC_UART_CH_DisableInputDigitalFilter
XMC_UART_CH_DisableInputInversion
XMC_UART_CH_DisableInputSync
XMC_UART_CH_EnableDataTransmission
XMC_UART_CH_EnableEvent
XMC_UART_CH_EnableInputDigitalFilter
XMC_UART_CH_EnableInputInversion
XMC_UART_CH_EnableInputSync
XMC_UART_CH_GetReceivedData
XMC_UART_CH_GetStatusFlag
XMC_UART_CH_Init
XMC_UART_CH_SelectInterruptNodePointer
XMC_UART_CH_SetBaudrate
XMC_UART_CH_SetFrameLength
XMC_UART_CH_SetInputSamplingFreq
XMC_UART_CH_SetInputSource
XMC_UART_CH_SetInterruptNodePointer
XMC_UART_CH_SetPulseLength
XMC_UART_CH_SetSamplePoint
XMC_UART_CH_SetWordLength
XMC_UART_CH_Start
XMC_UART_CH_Stop
XMC_UART_CH_Transmit
XMC_UART_CH_TriggerServiceRequest
xmc_usbd.h
XMC_USBD_ENDPOINT_DIRECTION_MASK
XMC_USBD_ENDPOINT_MAX_PACKET_SIZE_MASK
XMC_USBD_ENDPOINT_NUMBER_MASK
XMC_USBD_EP_DIR_MASK
XMC_USBD_EP_NUM_MASK
XMC_USBD_MAX_FIFO_SIZE
XMC_USBD_MAX_PACKET_SIZE
XMC_USBD_MAX_TRANSFER_SIZE_EP0
XMC_USBD_NUM_EPS
XMC_USBD_NUM_TX_FIFOS
XMC_USBD_SETUP_COUNT
XMC_USBD_SETUP_SIZE
XMC_USBD_SPEED_FULL
XMC_USBD_SignalDeviceEvent_t
XMC_USBD_SignalEndpointEvent_t
XMC_USBD_ENDPOINT_TYPE_t
XMC_USBD_ENDPOINT_TYPE_CONTROL
XMC_USBD_ENDPOINT_TYPE_ISOCHRONOUS
XMC_USBD_ENDPOINT_TYPE_BULK
XMC_USBD_ENDPOINT_TYPE_INTERRUPT
XMC_USBD_EP_EVENT_t
XMC_USBD_EP_EVENT_SETUP
XMC_USBD_EP_EVENT_OUT
XMC_USBD_EP_EVENT_IN
XMC_USBD_EVENT_IN_EP_t
XMC_USBD_EVENT_IN_EP_TX_COMPLET
XMC_USBD_EVENT_IN_EP_DISABLED
XMC_USBD_EVENT_IN_EP_AHB_ERROR
XMC_USBD_EVENT_IN_EP_TIMEOUT
XMC_USBD_EVENT_OUT_EP_t
XMC_USBD_EVENT_OUT_EP_TX_COMPLET
XMC_USBD_EVENT_OUT_EP_DISABLED
XMC_USBD_EVENT_OUT_EP_AHB_ERROR
XMC_USBD_EVENT_OUT_EP_SETUP
XMC_USBD_EVENT_t
XMC_USBD_EVENT_POWER_ON
XMC_USBD_EVENT_POWER_OFF
XMC_USBD_EVENT_CONNECT
XMC_USBD_EVENT_DISCONNECT
XMC_USBD_EVENT_RESET
XMC_USBD_EVENT_HIGH_SPEED
XMC_USBD_EVENT_SUSPEND
XMC_USBD_EVENT_RESUME
XMC_USBD_EVENT_REMOTE_WAKEUP
XMC_USBD_EVENT_SOF
XMC_USBD_EVENT_EARLYSUSPEND
XMC_USBD_EVENT_ENUMDONE
XMC_USBD_EVENT_ENUMNOTDONE
XMC_USBD_EVENT_OUTEP
XMC_USBD_EVENT_INEP
XMC_USBD_GRXSTS_PKTSTS_t
XMC_USBD_GRXSTS_PKTSTS_GOUTNAK
XMC_USBD_GRXSTS_PKTSTS_OUTDATA
XMC_USBD_GRXSTS_PKTSTS_OUTCMPL
XMC_USBD_GRXSTS_PKTSTS_SETUPCMPL
XMC_USBD_GRXSTS_PKTSTS_SETUP
XMC_USBD_MAX_NUM_EPS_t
XMC_USBD_MAX_NUM_EPS_1
XMC_USBD_MAX_NUM_EPS_2
XMC_USBD_MAX_NUM_EPS_3
XMC_USBD_MAX_NUM_EPS_4
XMC_USBD_MAX_NUM_EPS_5
XMC_USBD_MAX_NUM_EPS_6
XMC_USBD_MAX_NUM_EPS_7
XMC_USBD_SET_ADDRESS_STAGE_t
XMC_USBD_SET_ADDRESS_STAGE_SETUP
XMC_USBD_SET_ADDRESS_STAGE_STATUS
XMC_USBD_STATUS_t
XMC_USBD_STATUS_OK
XMC_USBD_STATUS_BUSY
XMC_USBD_STATUS_ERROR
XMC_USBD_TRANSFER_MODE_t
XMC_USBD_USE_DMA
XMC_USBD_USE_FIFO
XMC_USBD_ClearEvent
XMC_USBD_ClearEventINEP
XMC_USBD_ClearEventOUTEP
XMC_USBD_DeviceConnect
XMC_USBD_DeviceDisconnect
XMC_USBD_DeviceGetState
XMC_USBD_DeviceSetAddress
XMC_USBD_Disable
XMC_USBD_Enable
XMC_USBD_EnableEventINEP
XMC_USBD_EnableEventOUTEP
XMC_USBD_EndpointAbort
XMC_USBD_EndpointConfigure
XMC_USBD_EndpointRead
XMC_USBD_EndpointReadStart
XMC_USBD_EndpointStall
XMC_USBD_EndpointUnconfigure
XMC_USBD_EndpointWrite
XMC_USBD_GetCapabilities
XMC_USBD_GetFrameNumber
XMC_USBD_Init
XMC_USBD_IRQHandler
XMC_USBD_IsEnumDone
XMC_USBD_Uninitialize
Driver_USBD0
xmc_device
xmc_usbh.h
USB_CH_HCCHARx_DEVADDR
USB_CH_HCCHARx_EPDIR
USB_CH_HCCHARx_EPNUM
USB_CH_HCCHARx_EPTYPE
USB_CH_HCCHARx_MCEC
USB_CH_HCCHARx_MPS
USB_CH_HCFG_FSLSPCS
USB_CH_HCFG_FSLSSUP
USB_CH_HCINTx_ALL
USB_CH_HCINTx_ERRORS
USB_CH_HCTSIZx_DPID
USB_CH_HCTSIZx_DPID_DATA0
USB_CH_HCTSIZx_DPID_DATA1
USB_CH_HCTSIZx_DPID_DATA2
USB_CH_HCTSIZx_DPID_MDATA
USB_CH_HCTSIZx_DPID_SETUP
USB_GRXSTSR_HOSTMODE_PktSts_IN_DATA_PKT
USB_GRXSTSR_HOSTMODE_PktSts_IN_TRSF_CPL
USBH0_MAX_PIPE_NUM
USBH_PIPE_GET_INDEX
XMC_USB_DRIVE_PORT1
XMC_USB_DRIVE_PORT2
XMC_USBH_API_VERSION
XMC_USBH_CLOCK_GATING_DISABLE
XMC_USBH_CLOCK_GATING_ENABLE
XMC_USBH_DRIVER_ERROR
XMC_USBH_DRIVER_ERROR_BUSY
XMC_USBH_DRIVER_ERROR_PARAMETER
XMC_USBH_DRIVER_ERROR_SPECIFIC
XMC_USBH_DRIVER_ERROR_TIMEOUT
XMC_USBH_DRIVER_ERROR_UNSUPPORTED
XMC_USBH_DRIVER_OK
XMC_USBH_ENDPOINT_BULK
XMC_USBH_ENDPOINT_CONTROL
XMC_USBH_ENDPOINT_INTERRUPT
XMC_USBH_ENDPOINT_ISOCHRONOUS
XMC_USBH_EP_HANDLE
XMC_USBH_EVENT_BUS_ERROR
XMC_USBH_EVENT_CONNECT
XMC_USBH_EVENT_DISCONNECT
XMC_USBH_EVENT_HANDSHAKE_ERR
XMC_USBH_EVENT_HANDSHAKE_MDATA
XMC_USBH_EVENT_HANDSHAKE_NAK
XMC_USBH_EVENT_HANDSHAKE_NYET
XMC_USBH_EVENT_HANDSHAKE_STALL
XMC_USBH_EVENT_OVERCURRENT
XMC_USBH_EVENT_REMOTE_WAKEUP
XMC_USBH_EVENT_RESET
XMC_USBH_EVENT_RESUME
XMC_USBH_EVENT_SUSPEND
XMC_USBH_EVENT_TRANSFER_COMPLETE
XMC_USBH_PACKET_CSPLIT
XMC_USBH_PACKET_DATA0
XMC_USBH_PACKET_DATA1
XMC_USBH_PACKET_DATA_Msk
XMC_USBH_PACKET_DATA_Pos
XMC_USBH_PACKET_IN
XMC_USBH_PACKET_OUT
XMC_USBH_PACKET_PING
XMC_USBH_PACKET_PRE
XMC_USBH_PACKET_SETUP
XMC_USBH_PACKET_SSPLIT
XMC_USBH_PACKET_SSPLIT_E
XMC_USBH_PACKET_SSPLIT_S
XMC_USBH_PACKET_SSPLIT_S_E
XMC_USBH_PACKET_TOKEN_Msk
XMC_USBH_PACKET_TOKEN_Pos
XMC_USBH_SignalEndpointEvent_t
XMC_USBH_SPEED_FULL
XMC_USBH_SPEED_HIGH
XMC_USBH_SPEED_LOW
XMC_USBH_PIPE_HANDLE
XMC_USBH_SignalPipeEvent_t
XMC_USBH_SignalPortEvent_t
XMC_USBH_POWER_STATE_t
XMC_USBH_POWER_OFF
XMC_USBH_POWER_LOW
XMC_USBH_POWER_FULL
XMC_USBH_GetInterruptStatus
XMC_USBH_HandleIrq
XMC_USBH_osDelay
XMC_USBH_Select_VBUS
XMC_USBH_TurnOffResumeBit
xmc_usic.h
USIC_CH_DXCR_CM_Msk
USIC_CH_DXCR_CM_Pos
USIC_CH_DXCR_DFEN_Msk
USIC_CH_DXCR_DPOL_Msk
USIC_CH_DXCR_DSEL_Msk
USIC_CH_DXCR_DSEL_Pos
USIC_CH_DXCR_DSEN_Msk
USIC_CH_DXCR_INSW_Msk
USIC_CH_DXCR_INSW_pos
USIC_CH_DXCR_SFSEL_Msk
USIC_CH_DXCR_SFSEL_Pos
XMC_USIC0
XMC_USIC0_CH0
XMC_USIC0_CH1
XMC_USIC1
XMC_USIC1_CH0
XMC_USIC1_CH1
XMC_USIC2
XMC_USIC2_CH0
XMC_USIC2_CH1
XMC_USIC_t
XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_t
XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_DISABLED
XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_NORMAL
XMC_USIC_CH_BRG_CLOCK_DIVIDER_MODE_FRACTIONAL
XMC_USIC_CH_BRG_CLOCK_SOURCE_t
XMC_USIC_CH_BRG_CLOCK_SOURCE_DIVIDER
XMC_USIC_CH_BRG_CLOCK_SOURCE_DX1T
XMC_USIC_CH_BRG_MASTER_CLOCK_PASSIVE_LEVEL_t
XMC_USIC_CH_BRG_MASTER_CLOCK_PASSIVE_LEVEL_0
XMC_USIC_CH_BRG_MASTER_CLOCK_PASSIVE_LEVEL_1
XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_t
XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_SCLK
XMC_USIC_CH_BRG_SHIFT_CLOCK_OUTPUT_DX1
XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_t
XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_0_DELAY_DISABLED
XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_1_DELAY_DISABLED
XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_0_DELAY_ENABLED
XMC_USIC_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_1_DELAY_ENABLED
XMC_USIC_CH_DATA_OUTPUT_MODE_t
XMC_USIC_CH_DATA_OUTPUT_MODE_NORMAL
XMC_USIC_CH_DATA_OUTPUT_MODE_INVERTED
XMC_USIC_CH_EVENT_t
XMC_USIC_CH_EVENT_RECEIVE_START
XMC_USIC_CH_EVENT_DATA_LOST
XMC_USIC_CH_EVENT_TRANSMIT_SHIFT
XMC_USIC_CH_EVENT_TRANSMIT_BUFFER
XMC_USIC_CH_EVENT_STANDARD_RECEIVE
XMC_USIC_CH_EVENT_ALTERNATIVE_RECEIVE
XMC_USIC_CH_EVENT_BAUD_RATE_GENERATOR
XMC_USIC_CH_FIFO_SIZE_t
XMC_USIC_CH_FIFO_DISABLED
XMC_USIC_CH_FIFO_SIZE_2WORDS
XMC_USIC_CH_FIFO_SIZE_4WORDS
XMC_USIC_CH_FIFO_SIZE_8WORDS
XMC_USIC_CH_FIFO_SIZE_16WORDS
XMC_USIC_CH_FIFO_SIZE_32WORDS
XMC_USIC_CH_FIFO_SIZE_64WORDS
XMC_USIC_CH_INPUT_COMBINATION_MODE_t
XMC_USIC_CH_INPUT_COMBINATION_MODE_TRIGGER_DISABLED
XMC_USIC_CH_INPUT_COMBINATION_MODE_RISING_EDGE
XMC_USIC_CH_INPUT_COMBINATION_MODE_FALLING_EDGE
XMC_USIC_CH_INPUT_COMBINATION_MODE_BOTH_EDGES
XMC_USIC_CH_INPUT_SAMPLING_FREQ_t
XMC_USIC_CH_INPUT_SAMPLING_FREQ_FPERIPH
XMC_USIC_CH_INPUT_SAMPLING_FREQ_FRACTIONAL_DIVIDER
XMC_USIC_CH_INPUT_t
XMC_USIC_CH_INPUT_DX0
XMC_USIC_CH_INPUT_DX1
XMC_USIC_CH_INPUT_DX2
XMC_USIC_CH_INPUT_DX3
XMC_USIC_CH_INPUT_DX4
XMC_USIC_CH_INPUT_DX5
XMC_USIC_CH_INTERRUPT_NODE_POINTER_t
XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT
XMC_USIC_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER
XMC_USIC_CH_INTERRUPT_NODE_POINTER_RECEIVE
XMC_USIC_CH_INTERRUPT_NODE_POINTER_ALTERNATE_RECEIVE
XMC_USIC_CH_INTERRUPT_NODE_POINTER_PROTOCOL
XMC_USIC_CH_KERNEL_MODE_t
XMC_USIC_CH_KERNEL_MODE_RUN_0
XMC_USIC_CH_KERNEL_MODE_RUN_1
XMC_USIC_CH_KERNEL_MODE_STOP_0
XMC_USIC_CH_KERNEL_MODE_STOP_1
XMC_USIC_CH_OPERATING_MODE_t
XMC_USIC_CH_OPERATING_MODE_IDLE
XMC_USIC_CH_OPERATING_MODE_SPI
XMC_USIC_CH_OPERATING_MODE_UART
XMC_USIC_CH_OPERATING_MODE_I2S
XMC_USIC_CH_OPERATING_MODE_I2C
XMC_USIC_CH_PARITY_MODE_t
XMC_USIC_CH_PARITY_MODE_NONE
XMC_USIC_CH_PARITY_MODE_EVEN
XMC_USIC_CH_PARITY_MODE_ODD
XMC_USIC_CH_PASSIVE_DATA_LEVEL_t
XMC_USIC_CH_PASSIVE_DATA_LEVEL0
XMC_USIC_CH_PASSIVE_DATA_LEVEL1
XMC_USIC_CH_RBUF_STATUS_t
XMC_USIC_CH_RBUF_STATUS_DATA_VALID0
XMC_USIC_CH_RBUF_STATUS_DATA_VALID1
XMC_USIC_CH_RXFIFO_EVENT_CONF_t
XMC_USIC_CH_RXFIFO_EVENT_CONF_STANDARD
XMC_USIC_CH_RXFIFO_EVENT_CONF_ERROR
XMC_USIC_CH_RXFIFO_EVENT_CONF_ALTERNATE
XMC_USIC_CH_RXFIFO_EVENT_t
XMC_USIC_CH_RXFIFO_EVENT_STANDARD
XMC_USIC_CH_RXFIFO_EVENT_ERROR
XMC_USIC_CH_RXFIFO_EVENT_ALTERNATE
XMC_USIC_CH_RXFIFO_INTERRUPT_NODE_POINTER_t
XMC_USIC_CH_RXFIFO_INTERRUPT_NODE_POINTER_STANDARD
XMC_USIC_CH_RXFIFO_INTERRUPT_NODE_POINTER_ALTERNATE
XMC_USIC_CH_SHIFT_DIRECTION_t
XMC_USIC_CH_SHIFT_DIRECTION_LSB_FIRST
XMC_USIC_CH_SHIFT_DIRECTION_MSB_FIRST
XMC_USIC_CH_START_TRANSMISION_MODE_t
XMC_USIC_CH_START_TRANSMISION_DISABLED
XMC_USIC_CH_START_TRANSMISION_ON_TDV
XMC_USIC_CH_START_TRANSMISION_ON_TDV_DX2S_0
XMC_USIC_CH_START_TRANSMISION_ON_TDV_DX2S_1
XMC_USIC_CH_STATUS_t
XMC_USIC_CH_STATUS_OK
XMC_USIC_CH_STATUS_ERROR
XMC_USIC_CH_STATUS_BUSY
XMC_USIC_CH_TBUF_STATUS_SET_t
XMC_USIC_CH_TBUF_STATUS_SET_BUSY
XMC_USIC_CH_TBUF_STATUS_SET_IDLE
XMC_USIC_CH_TBUF_STATUS_t
XMC_USIC_CH_TBUF_STATUS_IDLE
XMC_USIC_CH_TBUF_STATUS_BUSY
XMC_USIC_CH_TXFIFO_EVENT_CONF_t
XMC_USIC_CH_TXFIFO_EVENT_CONF_STANDARD
XMC_USIC_CH_TXFIFO_EVENT_CONF_ERROR
XMC_USIC_CH_TXFIFO_EVENT_t
XMC_USIC_CH_TXFIFO_EVENT_STANDARD
XMC_USIC_CH_TXFIFO_EVENT_ERROR
XMC_USIC_CH_TXFIFO_INTERRUPT_NODE_POINTER_t
XMC_USIC_CH_TXFIFO_INTERRUPT_NODE_POINTER_STANDARD
XMC_USIC_CH_TXFIFO_INTERRUPT_NODE_POINTER_ALTERNATE
XMC_USIC_CH_ConfigExternalInputSignalToBRG
XMC_USIC_CH_ConfigureShiftClockOutput
XMC_USIC_CH_ConnectInputDataShiftToDataInput
XMC_USIC_CH_ConnectInputDataShiftToPPP
XMC_USIC_CH_Disable
XMC_USIC_CH_DisableDelayCompensation
XMC_USIC_CH_DisableEvent
XMC_USIC_CH_DisableFrameLengthControl
XMC_USIC_CH_DisableInputDigitalFilter
XMC_USIC_CH_DisableInputInversion
XMC_USIC_CH_DisableInputSync
XMC_USIC_CH_DisableTBUFDataValidTrigger
XMC_USIC_CH_DisableTimeMeasurement
XMC_USIC_CH_Enable
XMC_USIC_CH_EnableDelayCompensation
XMC_USIC_CH_EnableEvent
XMC_USIC_CH_EnableFrameLengthControl
XMC_USIC_CH_EnableInputDigitalFilter
XMC_USIC_CH_EnableInputInversion
XMC_USIC_CH_EnableInputSync
XMC_USIC_CH_EnableTBUFDataValidTrigger
XMC_USIC_CH_EnableTimeMeasurement
XMC_USIC_CH_GetCaptureTimerValue
XMC_USIC_CH_GetReceiveBufferStatus
XMC_USIC_CH_GetTransmitBufferStatus
XMC_USIC_CH_RXFIFO_ClearEvent
XMC_USIC_CH_RXFIFO_Configure
XMC_USIC_CH_RXFIFO_DisableEvent
XMC_USIC_CH_RXFIFO_EnableEvent
XMC_USIC_CH_RXFIFO_Flush
XMC_USIC_CH_RXFIFO_GetData
XMC_USIC_CH_RXFIFO_GetEvent
XMC_USIC_CH_RXFIFO_GetLevel
XMC_USIC_CH_RXFIFO_IsEmpty
XMC_USIC_CH_RXFIFO_IsFull
XMC_USIC_CH_RXFIFO_SetInterruptNodePointer
XMC_USIC_CH_RXFIFO_SetSizeTriggerLimit
XMC_USIC_CH_SetBaudrate
XMC_USIC_CH_SetBRGInputClockSource
XMC_USIC_CH_SetDataOutputMode
XMC_USIC_CH_SetFractionalDivider
XMC_USIC_CH_SetFrameLength
XMC_USIC_CH_SetInputSamplingFreq
XMC_USIC_CH_SetInputSource
XMC_USIC_CH_SetInputTriggerCombinationMode
XMC_USIC_CH_SetInterruptNodePointer
XMC_USIC_CH_SetMclkOutputPassiveLevel
XMC_USIC_CH_SetMode
XMC_USIC_CH_SetPassiveDataLevel
XMC_USIC_CH_SetShiftDirection
XMC_USIC_CH_SetStartTransmisionMode
XMC_USIC_CH_SetTransmitBufferStatus
XMC_USIC_CH_SetWordLength
XMC_USIC_CH_TriggerServiceRequest
XMC_USIC_CH_TXFIFO_ClearEvent
XMC_USIC_CH_TXFIFO_Configure
XMC_USIC_CH_TXFIFO_DisableEvent
XMC_USIC_CH_TXFIFO_EnableEvent
XMC_USIC_CH_TXFIFO_Flush
XMC_USIC_CH_TXFIFO_GetEvent
XMC_USIC_CH_TXFIFO_GetLevel
XMC_USIC_CH_TXFIFO_IsEmpty
XMC_USIC_CH_TXFIFO_IsFull
XMC_USIC_CH_TXFIFO_PutData
XMC_USIC_CH_TXFIFO_PutDataFLEMode
XMC_USIC_CH_TXFIFO_PutDataHPCMode
XMC_USIC_CH_TXFIFO_SetInterruptNodePointer
XMC_USIC_CH_TXFIFO_SetSizeTriggerLimit
XMC_USIC_CH_WriteToTBUF
XMC_USIC_CH_WriteToTBUFTCI
XMC_USIC_Disable
XMC_USIC_Enable
XMC_USIC_IsChannelValid
XMC_USIC_IsModuleValid
xmc_vadc.h
XMC_VADC_NUM_CHANNELS_PER_GROUP
XMC_VADC_BACKGROUND_CONFIG_t
XMC_VADC_GLOBAL_t
XMC_VADC_GROUP_t
XMC_VADC_RESULT_SIZE_t
XMC_VADC_BOUNDARY_NODE_t
XMC_VADC_BOUNDARY_NODE_COMMON_BOUNDARY_FLAG_0
XMC_VADC_BOUNDARY_NODE_COMMON_BOUNDARY_FLAG_1
XMC_VADC_BOUNDARY_NODE_COMMON_BOUNDARY_FLAG_2
XMC_VADC_BOUNDARY_NODE_COMMON_BOUNDARY_FLAG_3
XMC_VADC_BOUNDARY_NODE_COMMON_SR_LINE_0
XMC_VADC_BOUNDARY_NODE_COMMON_SR_LINE_1
XMC_VADC_BOUNDARY_NODE_COMMON_SR_LINE_2
XMC_VADC_BOUNDARY_NODE_COMMON_SR_LINE_3
XMC_VADC_BOUNDARY_SELECT_t
XMC_VADC_BOUNDARY_SELECT_LOWER_BOUND
XMC_VADC_BOUNDARY_SELECT_UPPER_BOUND
XMC_VADC_CHANNEL_ALIAS_t
XMC_VADC_CHANNEL_BOUNDARY_CONDITION_t
XMC_VADC_CHANNEL_BOUNDARY_CONDITION_ABOVE_BAND
XMC_VADC_CHANNEL_BOUNDARY_CONDITION_BELOW_BAND
XMC_VADC_CHANNEL_BOUNDARY_t
XMC_VADC_CHANNEL_BOUNDARY_GROUP_BOUND0
XMC_VADC_CHANNEL_BOUNDARY_GROUP_BOUND1
XMC_VADC_CHANNEL_BOUNDARY_GLOBAL_BOUND0
XMC_VADC_CHANNEL_BOUNDARY_GLOBAL_BOUND1
XMC_VADC_CHANNEL_BWDCH_t
XMC_VADC_CHANNEL_BWDCH_VAGND
XMC_VADC_CHANNEL_BWDCH_VAREF
XMC_VADC_CHANNEL_CONV_t
XMC_VADC_CHANNEL_CONV_GROUP_CLASS0
XMC_VADC_CHANNEL_CONV_GROUP_CLASS1
XMC_VADC_CHANNEL_CONV_GLOBAL_CLASS0
XMC_VADC_CHANNEL_CONV_GLOBAL_CLASS1
XMC_VADC_CHANNEL_EVGEN_t
XMC_VADC_CHANNEL_EVGEN_NEVER
XMC_VADC_CHANNEL_EVGEN_INBOUND
XMC_VADC_CHANNEL_EVGEN_COMPHIGH
XMC_VADC_CHANNEL_EVGEN_OUTBOUND
XMC_VADC_CHANNEL_EVGEN_COMPLOW
XMC_VADC_CHANNEL_EVGEN_ALWAYS
XMC_VADC_CHANNEL_REF_t
XMC_VADC_CHANNEL_REF_INTREF
XMC_VADC_CHANNEL_REF_ALT_CH0
XMC_VADC_CONVMODE_t
XMC_VADC_CONVMODE_12BIT
XMC_VADC_CONVMODE_10BIT
XMC_VADC_CONVMODE_8BIT
XMC_VADC_CONVMODE_FASTCOMPARE
XMC_VADC_DMM_t
XMC_VADC_DMM_REDUCTION_MODE
XMC_VADC_DMM_FILTERING_MODE
XMC_VADC_DMM_DIFFERENCE_MODE
XMC_VADC_FAST_COMPARE_t
XMC_VADC_FAST_COMPARE_LOW
XMC_VADC_FAST_COMPARE_HIGH
XMC_VADC_FAST_COMPARE_UNKNOWN
XMC_VADC_GATE_INPUT_SELECT_t
XMC_VADC_REQ_GT_A
XMC_VADC_REQ_GT_B
XMC_VADC_REQ_GT_C
XMC_VADC_REQ_GT_D
XMC_VADC_REQ_GT_E
XMC_VADC_REQ_GT_F
XMC_VADC_REQ_GT_G
XMC_VADC_REQ_GT_H
XMC_VADC_REQ_GT_I
XMC_VADC_REQ_GT_J
XMC_VADC_REQ_GT_K
XMC_VADC_REQ_GT_L
XMC_VADC_REQ_GT_M
XMC_VADC_REQ_GT_N
XMC_VADC_REQ_GT_O
XMC_VADC_REQ_GT_P
XMC_VADC_GATEMODE_t
XMC_VADC_GATEMODE_BLOCK
XMC_VADC_GATEMODE_IGNORE
XMC_VADC_GATEMODE_ACTIVEHIGH
XMC_VADC_GATEMODE_ACTIVELOW
XMC_VADC_GLOBAL_EVENT_t
XMC_VADC_GLOBAL_EVENT_BKGNDSOURCE
XMC_VADC_GLOBAL_EVENT_RESULT
XMC_VADC_GROUP_ARBMODE_t
XMC_VADC_GROUP_ARBMODE_ALWAYS
XMC_VADC_GROUP_ARBMODE_ONDEMAND
XMC_VADC_GROUP_BOUNDARY_FLAG_MODE_t
XMC_VADC_GROUP_BOUNDARY_FLAG_MODE_DISABLED
XMC_VADC_GROUP_BOUNDARY_FLAG_MODE_ENABLED
XMC_VADC_GROUP_BOUNDARY_FLAG_MODE_ENABLED_ACTIVE_LOW
XMC_VADC_GROUP_BOUNDARY_FLAG_MODE_ENABLED_ACTIVE_HIGH
XMC_VADC_GROUP_CONV_t
XMC_VADC_GROUP_CONV_STD
XMC_VADC_GROUP_CONV_EMUX
XMC_VADC_GROUP_EMUXCODE_t
XMC_VADC_GROUP_EMUXCODE_BINARY
XMC_VADC_GROUP_EMUXCODE_GRAY
XMC_VADC_GROUP_EMUXMODE_t
XMC_VADC_GROUP_EMUXMODE_SWCTRL
XMC_VADC_GROUP_EMUXMODE_STEADYMODE
XMC_VADC_GROUP_EMUXMODE_SINGLEMODE
XMC_VADC_GROUP_EMUXMODE_SEQUENCEMODE
XMC_VADC_GROUP_INDEX_t
XMC_VADC_GROUP_IRQ_t
XMC_VADC_GROUP_IRQ_KERNEL
XMC_VADC_GROUP_IRQ_SHARED
XMC_VADC_GROUP_POWERMODE_t
XMC_VADC_GROUP_POWERMODE_OFF
XMC_VADC_GROUP_POWERMODE_RESERVED1
XMC_VADC_GROUP_POWERMODE_RESERVED2
XMC_VADC_GROUP_POWERMODE_NORMAL
XMC_VADC_GROUP_RS_PRIORITY_t
XMC_VADC_GROUP_RS_PRIORITY_0
XMC_VADC_GROUP_RS_PRIORITY_1
XMC_VADC_GROUP_RS_PRIORITY_2
XMC_VADC_GROUP_RS_PRIORITY_3
XMC_VADC_GROUP_STATE_t
XMC_VADC_GROUP_STATE_IDLE
XMC_VADC_GROUP_STATE_BUSY
XMC_VADC_RESULT_ALIGN_t
XMC_VADC_RESULT_ALIGN_LEFT
XMC_VADC_RESULT_ALIGN_RIGHT
XMC_VADC_RESULT_SUBTRATION_t
XMC_VADC_RESULT_SUBTRATION_12BIT_LEFT_ALIGN
XMC_VADC_RESULT_SUBTRATION_12BIT_RIGHT_ALIGN
XMC_VADC_RESULT_SUBTRATION_10BIT_LEFT_ALIGN
XMC_VADC_RESULT_SUBTRATION_10BIT_RIGHT_ALIGN
XMC_VADC_RESULT_SUBTRATION_8BIT_LEFT_ALIGN
XMC_VADC_RESULT_SUBTRATION_8BIT_RIGHT_ALIGN
XMC_VADC_SCAN_LOAD_t
XMC_VADC_SCAN_LOAD_OVERWRITE
XMC_VADC_SCAN_LOAD_COMBINE
XMC_VADC_SCAN_TYPE_t
XMC_VADC_SCAN_TYPE_GROUPSCAN
XMC_VADC_SCAN_TYPE_BACKGROUND
XMC_VADC_SR_t
XMC_VADC_SR_GROUP_SR0
XMC_VADC_SR_GROUP_SR1
XMC_VADC_SR_GROUP_SR2
XMC_VADC_SR_GROUP_SR3
XMC_VADC_SR_SHARED_SR0
XMC_VADC_SR_SHARED_SR1
XMC_VADC_SR_SHARED_SR2
XMC_VADC_SR_SHARED_SR3
XMC_VADC_STARTMODE_t
XMC_VADC_STARTMODE_WFS
XMC_VADC_STARTMODE_CIR
XMC_VADC_STARTMODE_CNR
XMC_VADC_STATUS_t
XMC_VADC_STATUS_SUCCESS
XMC_VADC_STATUS_ERROR
XMC_VADC_SYNCTR_EVAL_t
XMC_VADC_SYNCTR_EVAL_1
XMC_VADC_TRIGGER_EDGE_t
XMC_VADC_TRIGGER_EDGE_NONE
XMC_VADC_TRIGGER_EDGE_FALLING
XMC_VADC_TRIGGER_EDGE_RISING
XMC_VADC_TRIGGER_EDGE_ANY
XMC_VADC_TRIGGER_INPUT_SELECT_t
XMC_VADC_REQ_TR_A
XMC_VADC_REQ_TR_B
XMC_VADC_REQ_TR_C
XMC_VADC_REQ_TR_D
XMC_VADC_REQ_TR_E
XMC_VADC_REQ_TR_F
XMC_VADC_REQ_TR_G
XMC_VADC_REQ_TR_H
XMC_VADC_REQ_TR_I
XMC_VADC_REQ_TR_J
XMC_VADC_REQ_TR_K
XMC_VADC_REQ_TR_L
XMC_VADC_REQ_TR_M
XMC_VADC_REQ_TR_N
XMC_VADC_REQ_TR_O
XMC_VADC_REQ_TR_P
XMC_VADC_GLOBAL_BackgndAddMultipleChannels
XMC_VADC_GLOBAL_BackgndRemoveMultipleChannels
XMC_VADC_GLOBAL_BackgroundAbortSequence
XMC_VADC_GLOBAL_BackgroundAddChannelToSequence
XMC_VADC_GLOBAL_BackgroundClearReqSrcEvent
XMC_VADC_GLOBAL_BackgroundDisableContinuousMode
XMC_VADC_GLOBAL_BackgroundDisableEvent
XMC_VADC_GLOBAL_BackgroundDisableExternalTrigger
XMC_VADC_GLOBAL_BackgroundEnableContinuousMode
XMC_VADC_GLOBAL_BackgroundEnableEvent
XMC_VADC_GLOBAL_BackgroundEnableExternalTrigger
XMC_VADC_GLOBAL_BackgroundGetNumChannelsPending
XMC_VADC_GLOBAL_BackgroundGetReqSrcEventStatus
XMC_VADC_GLOBAL_BackgroundInit
XMC_VADC_GLOBAL_BackgroundIsChannelPending
XMC_VADC_GLOBAL_BackgroundRemoveChannelFromSequence
XMC_VADC_GLOBAL_BackgroundSelectGating
XMC_VADC_GLOBAL_BackgroundSelectTrigger
XMC_VADC_GLOBAL_BackgroundSelectTriggerEdge
XMC_VADC_GLOBAL_BackgroundSetGatingMode
XMC_VADC_GLOBAL_BackgroundSetReqSrcEventInterruptNode
XMC_VADC_GLOBAL_BackgroundTriggerConversion
XMC_VADC_GLOBAL_BackgroundTriggerReqSrcEvent
XMC_VADC_GLOBAL_BindGroupToEMux
XMC_VADC_GLOBAL_ClearEvent
XMC_VADC_GLOBAL_ClockInit
XMC_VADC_GLOBAL_DisableModule
XMC_VADC_GLOBAL_DisableModuleClock
XMC_VADC_GLOBAL_DisablePostCalibration
XMC_VADC_GLOBAL_DisableSleepMode
XMC_VADC_GLOBAL_DisableStartupCalibration
XMC_VADC_GLOBAL_EnableModule
XMC_VADC_GLOBAL_EnableModuleClock
XMC_VADC_GLOBAL_EnablePostCalibration
XMC_VADC_GLOBAL_EnableSleepMode
XMC_VADC_GLOBAL_GetCompareResult
XMC_VADC_GLOBAL_GetDetailedResult
XMC_VADC_GLOBAL_GetResult
XMC_VADC_GLOBAL_Init
XMC_VADC_GLOBAL_InputClassInit
XMC_VADC_GLOBAL_ResultInit
XMC_VADC_GLOBAL_SetBoundaries
XMC_VADC_GLOBAL_SetCompareValue
XMC_VADC_GLOBAL_SetIndividualBoundary
XMC_VADC_GLOBAL_SetResultEventInterruptNode
XMC_VADC_GLOBAL_StartupCalibration
XMC_VADC_GLOBAL_TriggerEvent
XMC_VADC_GROUP_AddResultToFifo
XMC_VADC_GROUP_BackgroundDisableArbitrationSlot
XMC_VADC_GROUP_BackgroundEnableArbitrationSlot
XMC_VADC_GROUP_ChannelClearEvent
XMC_VADC_GROUP_ChannelGetAssertedEvents
XMC_VADC_GROUP_ChannelGetInputClass
XMC_VADC_GROUP_ChannelGetResultAlignment
XMC_VADC_GROUP_ChannelGetResultRegister
XMC_VADC_GROUP_ChannelInit
XMC_VADC_GROUP_ChannelIsResultOutOfBounds
XMC_VADC_GROUP_ChannelSetBoundarySelection
XMC_VADC_GROUP_ChannelSetEventInterruptNode
XMC_VADC_GROUP_ChannelSetIclass
XMC_VADC_GROUP_ChannelSetInputReference
XMC_VADC_GROUP_ChannelSetResultRegister
XMC_VADC_GROUP_ChannelTriggerEvent
XMC_VADC_GROUP_ChannelTriggerEventGenCriteria
XMC_VADC_GROUP_CheckSlaveReadiness
XMC_VADC_GROUP_ClearResultEvent
XMC_VADC_GROUP_DisableChannelSyncRequest
XMC_VADC_GROUP_DisableResultEvent
XMC_VADC_GROUP_EnableChannelSyncRequest
XMC_VADC_GROUP_EnableResultEvent
XMC_VADC_GROUP_ExternalMuxControlInit
XMC_VADC_GROUP_GetAlias
XMC_VADC_GROUP_GetAssertedResultEvents
XMC_VADC_GROUP_GetDetailedResult
XMC_VADC_GROUP_GetFastCompareResult
XMC_VADC_GROUP_GetInputClass
XMC_VADC_GROUP_GetResult
XMC_VADC_GROUP_GetResultFifoHead
XMC_VADC_GROUP_GetResultFifoTail
XMC_VADC_GROUP_GetSyncReadySignal
XMC_VADC_GROUP_IgnoreSlaveReadiness
XMC_VADC_GROUP_Init
XMC_VADC_GROUP_InputClassInit
XMC_VADC_GROUP_IsConverterBusy
XMC_VADC_GROUP_IsResultRegisterFifoHead
XMC_VADC_GROUP_IsResultRegisterInFifo
XMC_VADC_GROUP_QueueAbortSequence
XMC_VADC_GROUP_QueueClearReqSrcEvent
XMC_VADC_GROUP_QueueDisableArbitrationSlot
XMC_VADC_GROUP_QueueDisableExternalTrigger
XMC_VADC_GROUP_QueueEnableArbitrationSlot
XMC_VADC_GROUP_QueueEnableExternalTrigger
XMC_VADC_GROUP_QueueFlushEntries
XMC_VADC_GROUP_QueueGetInterruptedChannel
XMC_VADC_GROUP_QueueGetLength
XMC_VADC_GROUP_QueueGetNextChannel
XMC_VADC_GROUP_QueueGetReqSrcEventStatus
XMC_VADC_GROUP_QueueInit
XMC_VADC_GROUP_QueueInsertChannel
XMC_VADC_GROUP_QueueIsArbitrationSlotEnabled
XMC_VADC_GROUP_QueueRemoveChannel
XMC_VADC_GROUP_QueueSelectGating
XMC_VADC_GROUP_QueueSelectTrigger
XMC_VADC_GROUP_QueueSelectTriggerEdge
XMC_VADC_GROUP_QueueSetGatingMode
XMC_VADC_GROUP_QueueSetReqSrcEventInterruptNode
XMC_VADC_GROUP_QueueTriggerConversion
XMC_VADC_GROUP_QueueTriggerReqSrcEvent
XMC_VADC_GROUP_ResultInit
XMC_VADC_GROUP_ScanAddChannelToSequence
XMC_VADC_GROUP_ScanAddMultipleChannels
XMC_VADC_GROUP_ScanClearReqSrcEvent
XMC_VADC_GROUP_ScanDisableArbitrationSlot
XMC_VADC_GROUP_ScanDisableContinuousMode
XMC_VADC_GROUP_ScanDisableEvent
XMC_VADC_GROUP_ScanDisableExternalTrigger
XMC_VADC_GROUP_ScanEnableArbitrationSlot
XMC_VADC_GROUP_ScanEnableContinuousMode
XMC_VADC_GROUP_ScanEnableEvent
XMC_VADC_GROUP_ScanEnableExternalTrigger
XMC_VADC_GROUP_ScanGetNumChannelsPending
XMC_VADC_GROUP_ScanGetReqSrcEventStatus
XMC_VADC_GROUP_ScanInit
XMC_VADC_GROUP_ScanIsArbitrationSlotEnabled
XMC_VADC_GROUP_ScanIsChannelPending
XMC_VADC_GROUP_ScanRemoveChannel
XMC_VADC_GROUP_ScanSelectGating
XMC_VADC_GROUP_ScanSelectTrigger
XMC_VADC_GROUP_ScanSelectTriggerEdge
XMC_VADC_GROUP_ScanSequenceAbort
XMC_VADC_GROUP_ScanSetGatingMode
XMC_VADC_GROUP_ScanSetReqSrcEventInterruptNode
XMC_VADC_GROUP_ScanTriggerConversion
XMC_VADC_GROUP_ScanTriggerReqSrcEvent
XMC_VADC_GROUP_SetBoundaries
XMC_VADC_GROUP_SetBoundaryEventInterruptNode
XMC_VADC_GROUP_SetChannelAlias
XMC_VADC_GROUP_SetIndividualBoundary
XMC_VADC_GROUP_SetPowerMode
XMC_VADC_GROUP_SetResultFastCompareValue
XMC_VADC_GROUP_SetResultInterruptNode
XMC_VADC_GROUP_SetResultSubtractionValue
XMC_VADC_GROUP_SetSyncMaster
XMC_VADC_GROUP_SetSyncReadySignal
XMC_VADC_GROUP_SetSyncSlave
XMC_VADC_GROUP_SetSyncSlaveReadySignal
XMC_VADC_GROUP_TriggerResultEvent
XMC_VADC_GROUP_TriggerServiceRequest
xmc_wdt.h
XMC_WDT_DEBUG_MODE_t
XMC_WDT_DEBUG_MODE_STOP
XMC_WDT_DEBUG_MODE_RUN
XMC_WDT_MODE_t
XMC_WDT_MODE_TIMEOUT
XMC_WDT_MODE_PREWARNING
XMC_WDT_ClearAlarm
XMC_WDT_Disable
XMC_WDT_Enable
XMC_WDT_GetCounter
XMC_WDT_Init
XMC_WDT_Service
XMC_WDT_SetDebugMode
XMC_WDT_SetMode
XMC_WDT_SetServicePulseWidth
XMC_WDT_SetWindowBounds
XMC_WDT_Start
XMC_WDT_Stop
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