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XMC Peripheral Library for XMC4000 Family
2.1.16
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#include <xmc_ebu.h>
Detailed Description
SDRAM configuration structure
The structure is a placeholder for setting (and obtaining) the SDRAM configuration, operation mode configuration and the right refresh parameters. The XMC_EBU_ConfigureSdram() can be used to populate the structure with the SDRAM operation mode and refresh parameters configuration.
Field Documentation
| uint32_t ebu_init_refresh_commands_counter |
(CRFSH) Number of refresh commands issued during powerup init sequence: Perform CRFSH + 1 refresh cycles
| uint32_t ebu_mode_register_set_up_time |
(CRSC) Number of NOP cycles after a mode register set command: Insert CRSC + 1 NOP cycles
| uint32_t ebu_row_precharge_delay_counter |
Number of clock cycles between row activate command and a precharge command
| uint32_t ebu_row_precharge_time_counter |
(CRP) Number of NOP cycles inserted after a precharge command: Insert CRP + 1 NOP cycles
| uint32_t ebu_sdram_auto_refresh |
If 1, an auto refresh cycle will be performed; If 0, no refresh will be performed
| uint32_t ebu_sdram_auto_self_refresh |
If 1, memory controller will automatically issue the "self refresh entry" command to all SDRAM devices when it gives up control of the external bus. It will also automatically issue "self refresh exit" when it regains control of the bus
| uint32_t ebu_sdram_burst_length |
Number of locations can be accessed with a single command
| uint32_t ebu_sdram_casclk_mode |
Number of clocks between a READ command and the availability of data
| uint32_t ebu_sdram_clk_mode |
SDRAM clock mode select
| uint32_t ebu_sdram_clk_output |
Disable SDRAM clock output
| uint32_t ebu_sdram_cold_start |
Cold start
| uint32_t ebu_sdram_delay_on_power_down_exit |
Number of NOPs after the SDRAM controller exits power down before an active command is permitted
| uint32_t ebu_sdram_extended_operation_bank_select |
Value to be written to the bank select pins of a mobile SDRAM device during an extended mode register write operation
| uint32_t ebu_sdram_extended_operation_mode |
Value to be written to the extended mode register of a mobile SDRAM device
| uint32_t ebu_sdram_extended_refresh_counter_period |
Extended number of refresh counter period
| uint32_t ebu_sdram_mask_for_bank_tag |
Mask for bank tag
| uint32_t ebu_sdram_mask_for_row_tag |
Mask for row tag
| uint32_t ebu_sdram_num_refresh_cmnds |
Number of refresh commands
| uint32_t ebu_sdram_num_refresh_counter_period |
Number of refresh counter period: Refresh period is 'num_refresh_counter_period' x 64 clock cycles
| uint32_t ebu_sdram_pwr_mode |
Power Save Mode used for gated clock mode
| uint32_t ebu_sdram_row_cycle_time_counter |
Row cycle time counter: Insert (CRCE * 8) + CRC + 1 NOP cycles
| uint32_t ebu_sdram_row_cycle_time_counter_extension |
Extension to the Row cycle time counter (CRCE)
| uint32_t ebu_sdram_row_to_column_delay_counter |
(CRCD) Number of NOP cycles between a row address and a column address: Insert CRCD + 1 NOP cycles
| uint32_t ebu_sdram_self_refresh_entry |
If "1", the self refresh entry command is issued to all SDRAM devices, regardless regardless of their attachment to type 0 or type 1
| uint32_t ebu_sdram_self_refresh_exit |
If 1, the self refresh exit command is issued to all SDRAM devices regardless of their attachment to type 0 or type 1
| uint32_t ebu_sdram_self_refresh_exit_delay |
Number of NOP cycles inserted after a self refresh exit before a command is permitted to the SDRAM/DDRAM
| uint32_t ebu_sdram_width_of_column_address |
Number of address bits from bit 0 to be used for column address
The documentation for this struct was generated from the following file:
Generated on Mon Aug 7 2017 11:33:58 for XMC Peripheral Library for XMC4000 Family by
1.8.11