XMC Peripheral Library for XMC4000 Family: XMC_EBU_BUS_WRITE_CONFIG_t Struct Reference

Address cycles:
This bit field determines the number of clock cycles of the address phase.
0000B: 1 clock cycle selected
0001B: 1 clock cycle selected
...
1110B: 14 clock cycles selected
1111B: 15 clock cycles selected

Address hold cycles:
This bit field determines the number of clock cycles of the address hold phase.
0000B: 0 clock cycle selected
0001B: 1 clock cycle selected
...
1110B: 14 clock cycles selected
1111B: 15 clock cycles selected

Command delay cycles:
This bit field determines the basic number of Command Delay phase clock cycles.
0000B: 0 clock cycle selected
0001B: 1 clock cycle selected
...
1110B: 14 clock cycles selected
1111B: 15 clock cycles selected

Asynchronous address phase (XMC_EBU_ASYNCHRONOUS_ADDRESS_PHASE_t)

Burst buffer mode (XMC_EBU_BURST_BUFFER_SYNC_MODE_t)

Burst length for synchronous burst (XMC_EBU_BURST_LENGTH_SYNC_t)

Early burst signal enable for synchronous burst (XMC_EBU_BURST_SIGNAL_SYNC_BURST_t)

Byte control signal control (XMC_EBU_BYTE_CONTROL_t)

Data Hold Cycles for Write Accesses This bit field determines the basic number of Data Hold phase clock cycles during write accesses.
0000B: No recovery phase clock cycles available
0001B: 1 clock cycle selected
...
1110B: 14 clock cycles selected
1111B: 15 clock cycles selected
Frequency of external clock at pin BFCLKO (XMC_EBU_FREQ_EXT_CLK_PIN_t)

Device addressing mode (XMC_EBU_DEVICE_ADDRESSING_MODE_t)

Device type for region (XMC_EBU_DEVICE_TYPE_t)

Early chip select for sync burst (XMC_EBU_EARLY_CHIP_SELECT_SYNC_BURST_t)

EBU extended data (XMC_EBU_EXT_DATA_t)

Lock chip select (XMC_EBU_LOCK_CHIP_SELECT_t)

Programmed wait states for write accesses:
Number of programmed wait states for write accesses. For synchronous accesses, this will always be adjusted so that the phase exits on a rising edge of the external clock.
00000B: 1 wait state
00001B: 1 wait state
00010B: 2 wait state
...
11110B: 30 wait states
11111B: 31 wait states

Recovery cycles after write accesses:
This bit field determines the basic number of clock cycles of the Recovery Phase at the end of write accesses.
000B: No recovery phase clock cycles available
001B: 1 clock cycle selected
...
110B: 6 clock cycles selected
111B: 7 clock cycles selected

Recovery cycles between different regions:
This bit field determines the number of clock cycles of the Recovery Phase between consecutive accesses directed to different regions or different types of access.
0000B: No recovery phase clock cycles available
0001B: 1 clock cycle selected
...
1110B: 14 clock cycles selected
1111B: 15 clock cycles selected

External wait control (XMC_EBU_WAIT_CONTROL_t)

Reversed polarity at WAIT (XMC_EBU_WAIT_SIGNAL_POLARITY_t)