Data Structures
struct	XMC_SPI_CH_CONFIG_t

Macros
#define	XMC_SPI0_CH0 XMC_USIC0_CH0

#define	XMC_SPI0_CH1 XMC_USIC0_CH1

#define	XMC_SPI1_CH0 XMC_USIC1_CH0

#define	XMC_SPI1_CH1 XMC_USIC1_CH1

#define	XMC_SPI2_CH0 XMC_USIC2_CH0

#define	XMC_SPI2_CH1 XMC_USIC2_CH1

Enumerations

Functions
void	XMC_SPI_CH_ClearStatusFlag (XMC_USIC_CH_t *const channel, const uint32_t flag)

void	XMC_SPI_CH_ConfigExternalInputSignalToBRG (XMC_USIC_CH_t *const channel, const uint16_t pdiv, const XMC_USIC_CH_INPUT_COMBINATION_MODE_t combination_mode)

void	XMC_SPI_CH_ConfigureShiftClockOutput (XMC_USIC_CH_t *const channel, const XMC_SPI_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_t passive_level, const XMC_SPI_CH_BRG_SHIFT_CLOCK_OUTPUT_t clock_output)

void	XMC_SPI_CH_DisableDataTransmission (XMC_USIC_CH_t *const channel)

void	XMC_SPI_CH_DisableDelayCompensation (XMC_USIC_CH_t *const channel)

void	XMC_SPI_CH_DisableEOF (XMC_USIC_CH_t *const channel)

void	XMC_SPI_CH_DisableEvent (XMC_USIC_CH_t *const channel, const uint32_t event)

void	XMC_SPI_CH_DisableFEM (XMC_USIC_CH_t *const channel)

void	XMC_SPI_CH_DisableInputInversion (XMC_USIC_CH_t *const channel, const XMC_SPI_CH_INPUT_t input)

void	XMC_SPI_CH_DisableInterwordDelay (XMC_USIC_CH_t *const channel)

void	XMC_SPI_CH_DisableMasterClock (XMC_USIC_CH_t *const channel)

void	XMC_SPI_CH_DisableSlaveSelect (XMC_USIC_CH_t *const channel)

void	XMC_SPI_CH_DisableSlaveSelectCodedMode (XMC_USIC_CH_t *const channel)

void	XMC_SPI_CH_DisableSOF (XMC_USIC_CH_t *const channel)

void	XMC_SPI_CH_EnableDataTransmission (XMC_USIC_CH_t *const channel)

void	XMC_SPI_CH_EnableDelayCompensation (XMC_USIC_CH_t *const channel)

void	XMC_SPI_CH_EnableEOF (XMC_USIC_CH_t *const channel)

void	XMC_SPI_CH_EnableEvent (XMC_USIC_CH_t *const channel, const uint32_t event)

void	XMC_SPI_CH_EnableFEM (XMC_USIC_CH_t *const channel)

void	XMC_SPI_CH_EnableInputInversion (XMC_USIC_CH_t *const channel, const XMC_SPI_CH_INPUT_t input)

void	XMC_SPI_CH_EnableInterwordDelay (XMC_USIC_CH_t *const channel)

void	XMC_SPI_CH_EnableMasterClock (XMC_USIC_CH_t *const channel)

void	XMC_SPI_CH_EnableSlaveSelect (XMC_USIC_CH_t *const channel, const XMC_SPI_CH_SLAVE_SELECT_t slave)

void	XMC_SPI_CH_EnableSlaveSelectCodedMode (XMC_USIC_CH_t *const channel)

void	XMC_SPI_CH_EnableSOF (XMC_USIC_CH_t *const channel)

uint16_t	XMC_SPI_CH_GetReceivedData (XMC_USIC_CH_t *const channel)

uint32_t	XMC_SPI_CH_GetStatusFlag (XMC_USIC_CH_t *const channel)

void	XMC_SPI_CH_Init (XMC_USIC_CH_t const channel, const XMC_SPI_CH_CONFIG_t const config)

void	XMC_SPI_CH_Receive (XMC_USIC_CH_t *const channel, const XMC_SPI_CH_MODE_t mode)

void	XMC_SPI_CH_SelectInterruptNodePointer (XMC_USIC_CH_t *const channel, const XMC_SPI_CH_INTERRUPT_NODE_POINTER_t interrupt_node, const uint32_t service_request)

XMC_SPI_CH_STATUS_t	XMC_SPI_CH_SetBaudrate (XMC_USIC_CH_t *const channel, const uint32_t rate)

void	XMC_SPI_CH_SetBitOrderLsbFirst (XMC_USIC_CH_t *const channel)

void	XMC_SPI_CH_SetBitOrderMsbFirst (XMC_USIC_CH_t *const channel)

void	XMC_SPI_CH_SetFrameLength (XMC_USIC_CH_t *const channel, const uint8_t frame_length)

void	XMC_SPI_CH_SetInputSource (XMC_USIC_CH_t *const channel, const XMC_SPI_CH_INPUT_t input, const uint8_t source)

void	XMC_SPI_CH_SetInterruptNodePointer (XMC_USIC_CH_t *const channel, const uint8_t service_request)

void	XMC_SPI_CH_SetInterwordDelay (XMC_USIC_CH_t *const channel, uint32_t tinterword_delay_ns)

void	XMC_SPI_CH_SetInterwordDelaySCLK (XMC_USIC_CH_t *const channel, uint32_t sclk_period)

void	XMC_SPI_CH_SetSlaveSelectDelay (XMC_USIC_CH_t *const channel, uint32_t sclk_period)

void	XMC_SPI_CH_SetSlaveSelectPolarity (XMC_USIC_CH_t *const channel, const XMC_SPI_CH_SLAVE_SEL_MSLS_INV_t selo_inversion)

void	XMC_SPI_CH_SetTransmitMode (XMC_USIC_CH_t *const channel, const XMC_SPI_CH_MODE_t mode)

void	XMC_SPI_CH_SetWordLength (XMC_USIC_CH_t *const channel, const uint8_t word_length)

void	XMC_SPI_CH_Start (XMC_USIC_CH_t *const channel)

XMC_SPI_CH_STATUS_t	XMC_SPI_CH_Stop (XMC_USIC_CH_t *const channel)

void	XMC_SPI_CH_Transmit (XMC_USIC_CH_t *const channel, const uint16_t data, const XMC_SPI_CH_MODE_t mode)

void	XMC_SPI_CH_TriggerServiceRequest (XMC_USIC_CH_t *const channel, const uint32_t service_request_line)

Detailed Description

The SPI driver uses Universal Serial Interface Channel(USIC) module. The USIC module supports multiple data lines for SPI communication.

Full duplex communication with 2 separate lines for transmission and reception.
Half duplex communication with 1 common line shared for transmission and reception.
Dual mode communication with 2 common lines shared for transmission and reception.
Quad mode communication with 4 common lines shared for transmission and reception.

SPI driver provides structures, enumerations and APIs for configuring the USIC channel for SPI communication and also for data transaction.
SPI driver features:

Configuration structure XMC_SPI_CH_CONFIG_t and SPI initialization function XMC_SPI_CH_Init()
Allows configuration of protocol word and frame length using XMC_SPI_CH_SetWordLength(), XMC_SPI_CH_SetFrameLength()
Allows manipulation of data frame at runtime using XMC_SPI_CH_EnableSOF(), XMC_SPI_CH_EnableEOF(), XMC_SPI_CH_EnableSlaveSelect(), XMC_SPI_CH_DisableSlaveSelect()
Provides APIs for transmitting data and receiving data using XMC_SPI_CH_Transmit(), XMC_SPI_CH_Receive(), XMC_SPI_CH_GetReceivedData()
Allows configuration of shift clock using XMC_SPI_CH_ConfigureShiftClockOutput()
Provides enumeration of SPI protocol events using XMC_SPI_CH_STATUS_FLAG_t

Macro Definition Documentation

#define XMC_SPI0_CH0 XMC_USIC0_CH0

SPI0 channel 0 base address

#define XMC_SPI0_CH1 XMC_USIC0_CH1

SPI0 channel 1 base address

#define XMC_SPI1_CH0 XMC_USIC1_CH0

SPI1 channel 0 base address

#define XMC_SPI1_CH1 XMC_USIC1_CH1

SPI1 channel 1 base address

#define XMC_SPI2_CH0 XMC_USIC2_CH0

SPI2 channel 0 base address

#define XMC_SPI2_CH1 XMC_USIC2_CH1

SPI2 channel 1 base address

Enumeration Type Documentation

enum XMC_SPI_CH_BRG_SHIFT_CLOCK_OUTPUT_t

SPI Baudrate Generator shift clock output

Enumerator
XMC_SPI_CH_BRG_SHIFT_CLOCK_OUTPUT_SCLK	Baudrate Generator shift clock output: SCLK
XMC_SPI_CH_BRG_SHIFT_CLOCK_OUTPUT_DX1	Clock obtained as input from master: DX1

enum XMC_SPI_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_t

SPI Baudrate Generator shift clock passive level

Enumerator
XMC_SPI_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_0_DELAY_DISABLED	Passive clock level 0, delay disabled Passive clock level 1, delay disabled
XMC_SPI_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_1_DELAY_DISABLED	Passive clock level 0, delay enabled
XMC_SPI_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_0_DELAY_ENABLED	Passive clock level 1, delay enabled

enum XMC_SPI_CH_BUS_MODE_t

Defines the SPI bus mode

Enumerator
XMC_SPI_CH_BUS_MODE_MASTER	SPI Master
XMC_SPI_CH_BUS_MODE_SLAVE	SPI Slave

enum XMC_SPI_CH_DATA_POLARITY_t

Defines the Polarity of the data inputs.

Enumerator
XMC_SPI_CH_DATA_POLARITY_DIRECT	The polarity of the data line is not inverted
XMC_SPI_CH_DATA_POLARITY_INVERT	The polarity of the data line is inverted

enum XMC_SPI_CH_EVENT_t

Defines SPI specific events

Enumerator
XMC_SPI_CH_EVENT_RECEIVE_START	Receive start event
XMC_SPI_CH_EVENT_DATA_LOST	Data lost event
XMC_SPI_CH_EVENT_TRANSMIT_SHIFT	Transmit shift event
XMC_SPI_CH_EVENT_TRANSMIT_BUFFER	Transmit buffer event
XMC_SPI_CH_EVENT_STANDARD_RECEIVE	Receive event
XMC_SPI_CH_EVENT_ALTERNATIVE_RECEIVE	Alternate receive event
XMC_SPI_CH_EVENT_BAUD_RATE_GENERATOR	Baudrate generator event
XMC_SPI_CH_EVENT_PARITY_ERROR	Parity error event
XMC_SPI_CH_EVENT_MSLS_CHANGE	Master slave select(MSLS) output transition event
XMC_SPI_CH_EVENT_DX2TIEN_ACTIVATED	Slave select input signal transition event

enum XMC_SPI_CH_INPUT_FREQ_SLAVE_SELECT_DELAY_t

Defines input frequency sources for slave select signal delay configuration.

Enumerator
XMC_SPI_CH_INPUT_FREQ_SLAVE_SELECT_DELAY_FPDIV	Output of PDIV divider: FPDIV
XMC_SPI_CH_INPUT_FREQ_SLAVE_SELECT_DELAY_FPPP	Peripheral clock: FPPP
XMC_SPI_CH_INPUT_FREQ_SLAVE_SELECT_DELAY_FSCLK	Shift clock: FSCLK
XMC_SPI_CH_INPUT_FREQ_SLAVE_SELECT_DELAY_FMCLK	Master clock: FMCLK

enum XMC_SPI_CH_INPUT_t

Define data and clock input stages

Enumerator
XMC_SPI_CH_INPUT_DIN0	Data input stage 0
XMC_SPI_CH_INPUT_SLAVE_SCLKIN	Clock input stage
XMC_SPI_CH_INPUT_SLAVE_SELIN	Slave select input stage
XMC_SPI_CH_INPUT_DIN1	Data input stage 1
XMC_SPI_CH_INPUT_DIN2	Data input stage 2
XMC_SPI_CH_INPUT_DIN3	Data input stage 3

enum XMC_SPI_CH_INTERRUPT_NODE_POINTER_t

SPI channel interrupt node pointers

Enumerator
XMC_SPI_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT	Node pointer for transmit shift interrupt
XMC_SPI_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER	Node pointer for transmit buffer interrupt
XMC_SPI_CH_INTERRUPT_NODE_POINTER_RECEIVE	Node pointer for receive interrupt
XMC_SPI_CH_INTERRUPT_NODE_POINTER_ALTERNATE_RECEIVE	Node pointer for alternate receive interrupt
XMC_SPI_CH_INTERRUPT_NODE_POINTER_PROTOCOL	Node pointer for protocol related interrupts

enum XMC_SPI_CH_MODE_t

Define SPI data transfer mode

Enumerator
XMC_SPI_CH_MODE_STANDARD	SPI standard full duplex mode
XMC_SPI_CH_MODE_STANDARD_HALFDUPLEX	SPI standard half duplex mode
XMC_SPI_CH_MODE_DUAL	SPI half duplex mode with dual data lines
XMC_SPI_CH_MODE_QUAD	SPI half duplex mode with quad data lines

enum XMC_SPI_CH_SLAVE_SEL_MSLS_INV_t

Defines the Polarity of the slave select signals SELO[7:0] in relation to the master slave select signal MSLS.

Enumerator
XMC_SPI_CH_SLAVE_SEL_SAME_AS_MSLS	The SELO outputs have the same polarity as the MSLS signal (active high)
XMC_SPI_CH_SLAVE_SEL_INV_TO_MSLS	The SELO outputs have the inverted polarity to the MSLS signal (active low)

enum XMC_SPI_CH_SLAVE_SELECT_t

Defines Slave Select lines

Enumerator
XMC_SPI_CH_SLAVE_SELECT_0	Slave Select line 0
XMC_SPI_CH_SLAVE_SELECT_1	Slave Select line 1
XMC_SPI_CH_SLAVE_SELECT_2	Slave Select line 2
XMC_SPI_CH_SLAVE_SELECT_3	Slave Select line 3
XMC_SPI_CH_SLAVE_SELECT_4	Slave Select line 4
XMC_SPI_CH_SLAVE_SELECT_5	Slave Select line 5
XMC_SPI_CH_SLAVE_SELECT_6	Slave Select line 6
XMC_SPI_CH_SLAVE_SELECT_7	Slave Select line 7

enum XMC_SPI_CH_STATUS_FLAG_t

Defines SPI event status

Enumerator
XMC_SPI_CH_STATUS_FLAG_MSLS	Status of Master slave select(MSLS) signal
XMC_SPI_CH_STATUS_FLAG_DX2S	Status of slave select input(DX2) signal
XMC_SPI_CH_STATUS_FLAG_MSLS_EVENT_DETECTED	Status for master slave select output signal transition
XMC_SPI_CH_STATUS_FLAG_DX2T_EVENT_DETECTED	Status for slave select input signal transition
XMC_SPI_CH_STATUS_FLAG_PARITY_ERROR_EVENT_DETECTED	Indicates status of the parity error
XMC_SPI_CH_STATUS_FLAG_RECEIVER_START_INDICATION	Status for receive start event
XMC_SPI_CH_STATUS_FLAG_DATA_LOST_INDICATION	Status for data lost event
XMC_SPI_CH_STATUS_FLAG_TRANSMIT_SHIFT_INDICATION	Status for transmit shift event
XMC_SPI_CH_STATUS_FLAG_TRANSMIT_BUFFER_INDICATION	Status for transmit buffer event
XMC_SPI_CH_STATUS_FLAG_RECEIVE_INDICATION	Status for receive event
XMC_SPI_CH_STATUS_FLAG_ALTERNATIVE_RECEIVE_INDICATION	Status for alternative receive event
XMC_SPI_CH_STATUS_FLAG_BAUD_RATE_GENERATOR_INDICATION	Status for baud rate generation error event

enum XMC_SPI_CH_STATUS_t

Defines return status of SPI driver APIs

Enumerator
XMC_SPI_CH_STATUS_OK	Status of the Module: OK
XMC_SPI_CH_STATUS_ERROR	Status of the Module: ERROR
XMC_SPI_CH_STATUS_BUSY	The Module is busy

Function Documentation

void XMC_SPI_CH_ClearStatusFlag	(	XMC_USIC_CH_t *const	channel,
		const uint32_t	flag
	)

Parameters

channel	A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
flag	Protocol event status to be cleared for detection of next occurence. Refer @ XMC_SPI_CH_STATUS_FLAG_t for valid values. OR combinations of these enum item can be used as input.

Returns: None

Description:: Clears the events specified, by setting PSCR register.

During communication the events occurred have to be cleared to detect their next occurence.
e.g: During transmission Transmit buffer event occurs to indicating data word transfer has started. This event has to be cleared after transmission of each data word. Otherwise next event cannot be recognized.

Related APIs:: XMC_SPI_CH_GetStatusFlag()

void XMC_SPI_CH_ConfigExternalInputSignalToBRG	(	XMC_USIC_CH_t *const	channel,
		const uint16_t	pdiv,
		const XMC_USIC_CH_INPUT_COMBINATION_MODE_t	combination_mode
	)

Parameters

channel Pointer to USIC channel handler of type XMC_USIC_CH_t
Range: XMC_SPI0_CH0, XMC_SPI0_CH1,XMC_SPI1_CH0,XMC_SPI1_CH1,XMC_SPI2_CH0,XMC_SPI2_CH1

Note: Availability of SPI1 and SPI2 depends on device selection

Parameters

pdiv	Desired divider for the external frequency input. Range: minimum value = 1, maximum value = 1024
combination_mode	USIC channel input combination mode

Returns: None

Description: Enables the external frequency input for the Baudrate Generator and configures the divider, oversampling and the combination mode of the USIC channel.

Related APIs:: XMC_USIC_CH_SetBRGInputClockSource(), XMC_USIC_CH_SetInputTriggerCombinationMode()

void XMC_SPI_CH_ConfigureShiftClockOutput	(	XMC_USIC_CH_t *const	channel,
		const XMC_SPI_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_t	passive_level,
		const XMC_SPI_CH_BRG_SHIFT_CLOCK_OUTPUT_t	clock_output
	)

Parameters

channel	A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
passive_level	polarity and delay of the selected shift clock. Refer XMC_SPI_CH_BRG_SHIFT_CLOCK_PASSIVE_LEVEL_t for valid inputs.
clock_output	shift clock source. Refer XMC_SPI_CH_BRG_SHIFT_CLOCK_OUTPUT_t for valid inputs.

Returns: None

Description:: Configures the shift clock source with the selected polarity and delay by setting BRG.SCLKOSEL and BRG.SCLKCFG.

In Master mode operation, shift clock is generated by the internal baud rate generator. This SCLK is made available for external slave devices by SCLKOUT signal.
In Slave mode, the signal is received from the external master. So the DX1(input) stage has to be connected to input.
The shift clock output(SCLKOUT) signal polarity can be set relative to SCLK, with the delay of half the shift clock period. These settings are applicable only in master mode.

void XMC_SPI_CH_DisableDataTransmission ( XMC_USIC_CH_t *const channel )

Parameters

channel Constant pointer to USIC channel handle of type XMC_USIC_CH_t
Range: XMC_SPI0_CH0, XMC_SPI0_CH1,XMC_SPI1_CH0,XMC_SPI1_CH1,XMC_SPI2_CH0,XMC_SPI2_CH1

Note: Availability of SPI1 and SPI2 depends on device selection

Returns: None

Description: Disable data transmission.

Use this function in combination with XMC_SPI_CH_EnableDataTransmission() to fill the FIFO and send the FIFO content without gaps in the transmission. FIFO is filled using XMC_USIC_CH_TXFIFO_PutData().

Related APIs:: XMC_SPI_CH_EnableDataTransmission()

void XMC_SPI_CH_DisableDelayCompensation ( XMC_USIC_CH_t *const channel )

Parameters

channel Pointer to USIC channel handler of type XMC_USIC_CH_t
Range: XMC_SPI0_CH0, XMC_SPI0_CH1,XMC_SPI1_CH0,XMC_SPI1_CH1,XMC_SPI2_CH0,XMC_SPI2_CH1

Note: Availability of SPI1 and SPI2 depends on device selection

Returns: None

Description: Disables delay compensation..

Related APIs:: XMC_SPI_CH_EnableDelayCompensation()

void XMC_SPI_CH_DisableEOF ( XMC_USIC_CH_t *const channel )

Parameters

channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.

Returns: None

Description: Configure the handling of end of frame through hardware, by clearing TCSR.EOF bit.

Typically this can be disabled, where the transmission control is done by the hardware.

Related APIs:: XMC_SPI_CH_EnableEOF()

void XMC_SPI_CH_DisableEvent	(	XMC_USIC_CH_t *const	channel,
		const uint32_t	event
	)

Parameters

channel	A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
event	Protocol events which have to be disabled. Refer @ XMC_SPI_CH_EVENT_t for valid values. OR combinations of these enum item can be used as input.

Returns: None

Description:: Disables the SPI protocol specific events, by configuring PCR register.

After disabling the events, XMC_SPI_CH_EnableEvent() has to be invoked to re-enable the events.

Related APIs:: XMC_SPI_CH_EnableEvent()

void XMC_SPI_CH_DisableFEM ( XMC_USIC_CH_t *const channel )

Parameters

channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.

Returns: None

Description:: Configure to disable the MSLS(Slave select signal) if the current data frame is considered as finished, by setting PCR.FEM bit.

When the last bit of a data word has been sent out and the transmit buffer TBUF does not contain new data, is considered as frame is ended and MSLS(Slave select signal) is disabled.

Related APIs:: XMC_SPI_CH_EnableFEM()

void XMC_SPI_CH_DisableInputInversion	(	XMC_USIC_CH_t *const	channel,
		const XMC_SPI_CH_INPUT_t	input
	)

Parameters

channel	A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
input	SPI channel input stage. Refer XMC_SPI_CH_INPUT_t for valid inputs.

Returns: None

Description: Disables the polarity inversion of input data signal, by clearing DXyCR.DPOL(where y = input).

Resets the input data polarity. Invoke XMC_SPI_CH_EnableInputInversion() to apply inversion.

Related APIs:: XMC_SPI_CH_EnableInputInversion()

void XMC_SPI_CH_DisableInterwordDelay ( XMC_USIC_CH_t *const channel )

Parameters

channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.

Returns: None

Description:: Disables the delay after after each word, by clearing PCR.TIWEN bit.

So the last data bit of a data word is directly followed by the first data bit of the next data word. If needed can be enabled by invoking XMC_SPI_CH_EnableInterwordDelay().

Related APIs:: XMC_SPI_CH_EnableInterwordDelay()

void XMC_SPI_CH_DisableMasterClock ( XMC_USIC_CH_t *const channel )

Parameters

channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.

Returns: None

Description:: Disables the generation of Master clock by clearing PCR.MCLK bit.

This clock can be enabled by invoking XMC_SPI_CH_EnableMasterClock() as needed in the program.

Related APIs:: XMC_SPI_CH_EnableMasterClock()

void XMC_SPI_CH_DisableSlaveSelect ( XMC_USIC_CH_t *const channel )

Parameters

channel A constant ponter to XMC_USIC_CH_t, pointing to the USIC channel base address.

Returns: None

Description:: Disable all the slave signals by clearing PCR.SELO bits.

XMC_SPI_CH_EnableSlaveSelect() has to be invoked to start the communication with the desired slave again.

Related APIs:: XMC_SPI_CH_EnableSlaveSelect()

void XMC_SPI_CH_DisableSlaveSelectCodedMode ( XMC_USIC_CH_t *const channel )

Parameters

channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.

Returns: None

Description: Each SELOx line (with x = 0-7) can be directly connected to an external slave device.

void XMC_SPI_CH_DisableSOF ( XMC_USIC_CH_t *const channel )

Parameters

channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.

Returns: None

Description: Set the control of the handling start of frame through hardware, by clearing TCSR.SOF bit.

Typically this can be disabled, where the transmission control is done by the hardware.

Related APIs:: XMC_SPI_CH_EnableSOF()

void XMC_SPI_CH_EnableDataTransmission ( XMC_USIC_CH_t *const channel )

Parameters

channel Constant pointer to USIC channel handle of type XMC_USIC_CH_t
Range: XMC_SPI0_CH0, XMC_SPI0_CH1,XMC_SPI1_CH0,XMC_SPI1_CH1,XMC_SPI2_CH0,XMC_SPI2_CH1

Note: Availability of SPI1 and SPI2 depends on device selection

Returns: None

Description: Enable data transmission.

Use this function in combination with XMC_SPI_CH_DisableDataTransmission() to fill the FIFO and send the FIFO content without gaps in the transmission. FIFO is filled using XMC_USIC_CH_TXFIFO_PutData().

Note: If you need more control over the start of transmission use XMC_USIC_CH_SetStartTransmisionMode()

Related APIs:: XMC_SPI_CH_DisableDataTransmission()

void XMC_SPI_CH_EnableDelayCompensation ( XMC_USIC_CH_t *const channel )

Parameters

channel Pointer to USIC channel handler of type XMC_USIC_CH_t
Range: XMC_SPI0_CH0, XMC_SPI0_CH1,XMC_SPI1_CH0,XMC_SPI1_CH1,XMC_SPI2_CH0,XMC_SPI2_CH1

Note: Availability of SPI1 and SPI2 depends on device selection

Returns: None

Description: Enables delay compensation.

Delay compensation can be applied to the receive path.

Related APIs:: XMC_SPI_CH_DisableDelayCompensation()

void XMC_SPI_CH_EnableEOF ( XMC_USIC_CH_t *const channel )

Parameters

channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.

Returns: None

Description: Configure the handling of end of frame through software, by setting TCSR.EOF bit.

This can be used if the software handles the TBUF data without FIFO. If EOF is set, a valid content of the TBUF is considered as last word of a frame. After transfer of the last word, MSLS signal becomes inactive. For software handling of EOF bit, it is recommended to configure TCSR.WLEMD as 0.
Note: The API should be called before putting the last data word of the frame to TBUF.

Related APIs:: XMC_SPI_CH_DisableEOF()

void XMC_SPI_CH_EnableEvent	(	XMC_USIC_CH_t *const	channel,
		const uint32_t	event
	)

Parameters

channel	A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
event	Protocol events which have to be enabled. Refer @ XMC_SPI_CH_EVENT_t for valid values. OR combinations of these enum items can be used as input.

Returns: None

Description:: Enables the SPI protocol specific events, by configuring PCR register.

Events can be enabled as needed using XMC_SPI_CH_EnableEvent(). XMC_SPI_CH_DisableEvent() can be used to disable the events.

Related APIs:: XMC_SPI_CH_DisableEvent()

void XMC_SPI_CH_EnableFEM ( XMC_USIC_CH_t *const channel )

Parameters

channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.

Returns: None

Description:

Configure to keep MSLS(Slave select signal) active even after finishing the current data frame, by setting PCR.FEM bit.

This is typically used during the transmission of multi-data word frames, where there is possibility of delay in delivering the data. Frame end mode is enabled in XMC_SPI_CH_Init() during initialization. To disable XMC_SPI_CH_DisableFEM() can be invoked as needed in the program.

Related APIs:: XMC_SPI_CH_DisableFEM()

void XMC_SPI_CH_EnableInputInversion	(	XMC_USIC_CH_t *const	channel,
		const XMC_SPI_CH_INPUT_t	input
	)

Parameters

channel	A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
input	SPI channel input stage. Refer XMC_SPI_CH_INPUT_t for valid inputs.

Returns: None

Description: Enables the polarity inversion of input data signal, by setting DXyCR.DPOL(where y = input).

This is not set in XMC_SPI_CH_Init(). Invoke XMC_SPI_CH_EnableInputInversion() as needed later in the program. To disable the inversion XMC_SPI_CH_DisableInputInversion() can be invoked.

Related APIs:: XMC_SPI_CH_DisableInputInversion()

void XMC_SPI_CH_EnableInterwordDelay ( XMC_USIC_CH_t *const channel )

Parameters

channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.

Returns: None

Description:: Enables the delay after each word, by setting PCR.TIWEN bit.

The inter word delay starts at the end of last SCLK cycle of data word. During this time no clock pulses are generated and MSLS signal stays active. If inter word delay is not enabled, last data bit of a data word is directly followed by the first data bit of the next data word. This is not enabled in XMC_SPI_CH_Init(). To enable XMC_SPI_CH_EnableInterwordDelay() has to be invoked as needed in the program. And can be disabled by invoking XMC_SPI_CH_DisableInterwordDelay().

Related APIs:: XMC_SPI_CH_DisableInterwordDelay()

void XMC_SPI_CH_EnableMasterClock ( XMC_USIC_CH_t *const channel )

Parameters

channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.

Returns: None

Description:: Enables the generation of Master clock by setting PCR.MCLK bit.

This clock can be used as a clock reference for external devices. This is not enabled during initialization in XMC_SPI_CH_Init(). Invoke XMC_SPI_CH_EnableMasterClock() to enable as needed in the program, or if it is disabled by XMC_SPI_CH_DisableMasterClock().

Related APIs:: XMC_SPI_CH_DisableMasterClock()

void XMC_SPI_CH_EnableSlaveSelect	(	XMC_USIC_CH_t *const	channel,
		const XMC_SPI_CH_SLAVE_SELECT_t	slave
	)

Parameters

channel	A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
slave	Slave select signal. Refer XMC_SPI_CH_SLAVE_SELECT_t for valid values.

Returns: None

Description:: Enable the selected slave signal by setting PCR.SELO bits.

Each slave is connected with one slave select signal. This is not configured in XMC_SPI_CH_Init(). Invoke XMC_SPI_CH_EnableSlaveSelect() with required slave to to start the communication. After finishing the communication XMC_SPI_CH_DisableSlaveSelect() can be invoked to disable the slaves.

Related APIs:: XMC_SPI_CH_DisableSlaveSelect()

void XMC_SPI_CH_EnableSlaveSelectCodedMode ( XMC_USIC_CH_t *const channel )

Parameters

channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.

Returns: None

Description: The SELOx lines (with x = 1-7) can be used as addresses for an external address decoder to increase the number of external slave devices.

void XMC_SPI_CH_EnableSOF ( XMC_USIC_CH_t *const channel )

Parameters

channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.

Returns: None

Description: Configure the handling of start of frame through software, by setting TCSR.SOF bit.

This can be used if the software handles the TBUF data without FIFO. If SOF is set, a valid content of the TBUF is considered as first word of a new frame by finishing the currently running frame. For software handling of SOF bit, it is recommended to configure TCSR.WLEMD as 0. This is not configured during initialization. XMC_SPI_CH_EnableSOF() can be called as needed in the program and can be disabled by XMC_SPI_CH_DisableSOF().

Related APIs:: XMC_SPI_CH_DisableSOF()

uint16_t XMC_SPI_CH_GetReceivedData ( XMC_USIC_CH_t *const channel )

Parameters

channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.

Returns: uint16_t Data read from the receive buffer.

Description:: Reads data from the receive buffer based on the FIFO selection.

Invocation of XMC_SPI_CH_Receive() receives the data and place it into receive buffer. After receiving the data XMC_SPI_CH_GetReceivedData() can be used to read the data from the buffer.

Related APIs:: XMC_SPI_CH_Receive()

uint32_t XMC_SPI_CH_GetStatusFlag ( XMC_USIC_CH_t *const channel )

Parameters

channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.

Returns: uint32_t Status of SPI protocol events.

Description:: Returns the status of the events, by reading PSR register.

This indicates the status of the all the events, for SPI communication.

Related APIs:: XMC_SPI_CH_ClearStatusFlag()

void XMC_SPI_CH_Init	(	XMC_USIC_CH_t *const	channel,
		const XMC_SPI_CH_CONFIG_t *const	config
	)

Parameters

channel	A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
config	pointer to constant SPI channel configuration data structure. Refer data structure XMC_SPI_CH_CONFIG_t for detail.

Returns: None

Description:

Initializes the selected SPI channel with the config structure.

Enable SPI channel by calling XMC_USIC_CH_Enable() and then configures

Baudrate,
Passive data level as active high,
Shift control signal as active high,
Frame length as 64U,
Word length as 8U,
Enable Hardware port control mode,
Enable transmission of data TDV(Transmit data valid) bit is set to 1,
Enable invalidation of data in TBUF once loaded into shift register,
Parity mode settings

And if master mode is selected,

Enables MSLS signal generation,
configures slave selection as normal mode,
Set polarity for the Slave signal,
Enable Frame end mode(MSLS signal is kept active after transmission of a frame)

void XMC_SPI_CH_Receive	(	XMC_USIC_CH_t *const	channel,
		const XMC_SPI_CH_MODE_t	mode
	)

Parameters

channel	A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
mode	Communication mode of the SPI, based on this mode TCI(Transmit control information)is updated. Refer XMC_SPI_CH_MODE_t for valid values.

Returns: None

Description:: Transmits a dummy data(FFFFH) to provide clock for slave and receives the data from the slave.

XMC_SPI_CH_Receive() receives the data and places it into buffer based on the FIFO selection. After reception of data XMC_SPI_CH_GetReceivedData() can be invoked to read the data from the buffers.

Related APIs:: XMC_SPI_CH_GetReceivedDaa()

void XMC_SPI_CH_SelectInterruptNodePointer	(	XMC_USIC_CH_t *const	channel,
		const XMC_SPI_CH_INTERRUPT_NODE_POINTER_t	interrupt_node,
		const uint32_t	service_request
	)

Parameters

channel Pointer to USIC channel handler of type XMC_USIC_CH_t
Range: XMC_SPI0_CH0, XMC_SPI0_CH1,XMC_SPI1_CH0,XMC_SPI1_CH1,XMC_SPI2_CH0,XMC_SPI2_CH1

Note: Availability of SPI1 and SPI2 depends on device selection

Parameters

interrupt_node	Interrupt node pointer to be configured. Range: XMC_SPI_CH_INTERRUPT_NODE_POINTER_TRANSMIT_SHIFT, XMC_SPI_CH_INTERRUPT_NODE_POINTER_TRANSMIT_BUFFER etc.
service_request	Service request number. Range: 0 to 5.

Returns: None

Description: Sets the interrupt node for USIC channel events.

For an event to generate interrupt, node pointer should be configured with service request(SR0, SR1..SR5). The NVIC node gets linked to the interrupt event by doing so.
Note: NVIC node should be separately enabled to generate the interrupt.

Related APIs:: XMC_SPI_CH_EnableEvent()

XMC_SPI_CH_STATUS_t XMC_SPI_CH_SetBaudrate	(	XMC_USIC_CH_t *const	channel,
		const uint32_t	rate
	)

Parameters

channel	A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
rate	Bus speed in bits per second

Returns: XMC_SPI_CH_STATUS_t Status of the SPI driver after the request for setting baudrate is processed.
XMC_SPI_CH_STATUS_OK- If the baudrate is successfully changed.
XMC_SPI_CH_STATUS_ERROR- If the new baudrate value is out of range.

Description:: Sets the bus speed in bits per second

Related APIs:: XMC_SPI_CH_Init(), XMC_SPI_CH_Stop()

void XMC_SPI_CH_SetBitOrderLsbFirst ( XMC_USIC_CH_t *const channel )

Parameters

channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.

Returns: None

Description:: Set the order of data transfer from LSB to MSB, by clearing SCTR.SDIR bit.

This is typically based on the slave settings. Invoke XMC_SPI_CH_SetBitOrderLsbFirst() to set direction as needed in the program.

Related APIs:: XMC_SPI_CH_SetBitOrderMsbFirst()

void XMC_SPI_CH_SetBitOrderMsbFirst ( XMC_USIC_CH_t *const channel )

Parameters

channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.

Returns: None

Description:: Set the order of data transfer from MSB to LSB, by setting SCTR.SDIR bit.

This is typically based on the slave settings. This is not set during XMC_SPI_CH_Init(). Invoke XMC_SPI_CH_SetBitOrderMsbFirst() to set direction as needed in the program.

Related APIs:: XMC_SPI_CH_SetBitOrderLsbFirst()

void XMC_SPI_CH_SetFrameLength	(	XMC_USIC_CH_t *const	channel,
		const uint8_t	frame_length
	)

Parameters

channel	A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
frame_length	Number of bits in a frame. Range: 1 to 64. If the value 64 is configured, then the frame does not automatically end. User should explicitly end the frame.

Returns: None

Description: Define the data frame length.

Set the number of bits to be serially transmitted in a frame. The frame length should be multiples of word length. If the value is set to 64, the frame does not automatically end. Use XMC_SPI_CH_DisableSlaveSelect() to end the frame after all the data is transmitted.

Related APIs:: XMC_USIC_CH_SetWordLength(), XMC_USIC_CH_EnableFrameLengthControl(), XMC_SPI_CH_DisableSlaveSelect()

void XMC_SPI_CH_SetInputSource	(	XMC_USIC_CH_t *const	channel,
		const XMC_SPI_CH_INPUT_t	input,
		const uint8_t	source
	)

Parameters

channel	A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
input	SPI channel input stage. Refer XMC_SPI_CH_INPUT_t for valid values
source	Input source select for the input stage. Range : [0 to 7]

Returns: None

Description: Selects the data source for SPI input stage, by configuring DXCR.DSEL bits.

Selects the input data signal source among DXnA, DXnB.. DXnG for the input stage. The API can be used for all the input stages like DX0CR, DX1CR etc. This is not done during initialization. This has to be configured before starting the SPI communication.

void XMC_SPI_CH_SetInterruptNodePointer	(	XMC_USIC_CH_t *const	channel,
		const uint8_t	service_request
	)

Parameters

channel	A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
service_request	Service request number. Range: [0 to 5]

Returns: None

Description: Sets the interrupt node for SPI channel events.

For an event to generate interrupt, node pointer should be configured with service request(SR0, SR1..SR5). The NVIC node gets linked to the interrupt event by doing so. This is not configured in XMC_SPI_CH_Init() during initialization.

Note::

NVIC node should be separately enabled to generate the interrupt.

Related APIs:: XMC_USIC_CH_EnableEvent()

void XMC_SPI_CH_SetInterwordDelay	(	XMC_USIC_CH_t *const	channel,
		uint32_t	tinterword_delay_ns
	)

Parameters

channel	A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
tinterword_delay_ns	delay in terms of nano seconds.

Returns: None

Description:: Configures the inter word delay by setting PCR.PCTQ1, PCR.DCTQ1 bit fields.

The inter word delay is dependent on the peripheral clock. The maximum possible value is calculated by using the below formula
Maximum inter word delay = ((1 + PCTQ1_max)(1 + DCTQ1_max)) / peripheral clock
where PCTQ1_max = 3 and DCTQ1_max = 31
After configuring the inter word delay, this has to be enabled by invoking XMC_SPI_CH_EnableInterwordDelay().

Related APIs:: XMC_SPI_CH_EnableInterwordDelay(),XMC_SPI_CH_SetInterwordDelaySCLK()

void XMC_SPI_CH_SetInterwordDelaySCLK	(	XMC_USIC_CH_t *const	channel,
		uint32_t	sclk_period
	)

Parameters

channel	A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
sclk_period	in terms of clk cycles.

Returns: None

Description:: Configures the inter word delay by setting PCR.DCTQ1 bit fields.

This delay is dependent on the peripheral clock. The maximum possible value supported by this API is 32 clock cycles. After configuring the inter word delay, this has to be enabled by invoking XMC_SPI_CH_EnableInterwordDelay().

Related APIs:: XMC_SPI_CH_EnableInterwordDelay(),XMC_SPI_CH_EnableInterwordDelay()

void XMC_SPI_CH_SetSlaveSelectDelay	(	XMC_USIC_CH_t *const	channel,
		uint32_t	sclk_period
	)

Parameters

channel	A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
sclk_period	delay in terms of sclk clock cycles.

Returns: None

Description:: Configures the leading/trailing delay by setting BRG.DCTQ bit field.

This delay is dependent on the peripheral clock. The maximum possible value supported by this API is 30 clock cycles.

void XMC_SPI_CH_SetSlaveSelectPolarity	(	XMC_USIC_CH_t *const	channel,
		const XMC_SPI_CH_SLAVE_SEL_MSLS_INV_t	selo_inversion
	)

Parameters

channel	A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
selo_inversion	Polarity of the slave select signal relative to the MSLS signal. Refer XMC_SPI_CH_SLAVE_SEL_MSLS_INV_t for valid values

Returns: None

Description: Set the polarity of the slave select signal, by configuring PCR.SELINV bit.

Normally MSLS signal is active low level signal. SO based on the slave inversion has to be applied. This is configured in XMC_SPI_CH_Init() during initialization. Invoke XMC_SPI_CH_SetSlaveSelectPolarity() with desired settings as needed later in the program.

void XMC_SPI_CH_SetTransmitMode	(	XMC_USIC_CH_t *const	channel,
		const XMC_SPI_CH_MODE_t	mode
	)

Parameters

channel	A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
mode	Communication mode of the SPI, based on this mode TCI(Transmit control information)is updated. Refer XMC_SPI_CH_MODE_t for valid values.

Returns: None

Description:: In Dual and Quad modes, hardware port control(CCR.HPCEN) mode is enabled.

By enabling this the direction of the data pin is updated by hardware itself. Before transmitting the data set the mode to ensure the proper communication.

Related APIs:: XMC_SPI_CH_Transmit()

void XMC_SPI_CH_SetWordLength	(	XMC_USIC_CH_t *const	channel,
		const uint8_t	word_length
	)

Parameters

channel	A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
word_length	Number of bits to be configured for a data word. Range: 1 to 16.

Returns: None

Description: Defines the data word length.

Sets the number of bits to represent a data word. Frame length should be a multiple of word length.

Related APIs:: XMC_SPI_CH_SetFrameLength()

void XMC_SPI_CH_Start ( XMC_USIC_CH_t *const channel )

Parameters

channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.

Returns: None

Description:: Set the selected USIC channel to operate in SPI mode, by setting CCR.MODE bits.

It should be executed after XMC_SPI_CH_Init() during initialization. By invoking XMC_SPI_CH_Stop(), the MODE is set to IDLE state. Call XMC_SPI_CH_Start() to set the SPI mode again, as needed later in the program.

Related APIs:: XMC_SPI_CH_Init(), XMC_SPI_CH_Stop()

XMC_SPI_CH_STATUS_t XMC_SPI_CH_Stop ( XMC_USIC_CH_t *const channel )

Parameters

channel A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.

Returns: XMC_SPI_CH_STATUS_t Status of the SPI driver after the request for stopping is processed.
XMC_SPI_CH_STATUS_OK- If the USIC channel is successfully put to IDLE mode.
XMC_SPI_CH_STATUS_BUSY- If the USIC channel is busy transmitting data.

Description:: Set the selected SPI channel to IDLE mode, by clearing CCR.MODE bits.

After calling XMC_SPI_CH_Stop, channel is IDLE mode. So no communication is supported. XMC_SPI_CH_Start() has to be invoked to start the communication again.

Related APIs:: XMC_SPI_CH_Start()

void XMC_SPI_CH_Transmit	(	XMC_USIC_CH_t *const	channel,
		const uint16_t	data,
		const XMC_SPI_CH_MODE_t	mode
	)

Parameters

channel	A constant pointer to XMC_USIC_CH_t, pointing to the USIC channel base address.
data	Data to be transmitted
mode	Communication mode of the SPI, based on this mode TCI(Transmit control information)is updated. Refer XMC_SPI_CH_MODE_t for valid values.

Returns: None

Description:: Puts the data into FIFO, if FIFO mode is enabled or else into standard buffer, by setting the proper mode.

In Dual and Quad modes, hardware port control(CCR.HPCEN) mode is enabled. By enabling this the direction of the data pin is updated by hardware itself. TCI(Transmit Control Information) allows dynamic control of both the data shift mode and pin direction during data transfers by writing to SCTR.DSM and SCTR.HPCDIR bit fields. To support this auto update, TCSR.HPCMD(Hardware Port control) will be enabled during the initialization using XMC_SPI_CH_Init() for all modes.

Related APIs:: XMC_SPI_CH_Receive()

void XMC_SPI_CH_TriggerServiceRequest	(	XMC_USIC_CH_t *const	channel,
		const uint32_t	service_request_line
	)

Parameters

channel Pointer to USIC channel handler of type XMC_USIC_CH_t
Range: XMC_SPI0_CH0, XMC_SPI0_CH1,XMC_SPI1_CH0,XMC_SPI1_CH1,XMC_SPI2_CH0,XMC_SPI2_CH1

Note: Availability of SPI1 and SPI2 depends on device selection

Parameters

service_request_line service request number of the event to be triggered.
Range: 0 to 5.

Returns: None

Description: Trigger a SPI interrupt service request.

When the SPI service request is triggered, the NVIC interrupt associated with it will be generated if enabled.

Related APIs:: XMC_SPI_CH_SelectInterruptNodePointer()

XMC Peripheral Library for XMC4000 Family: SPI

XMC Peripheral Library for XMC4000 Family

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