IO Registers
[Memory Map]
IWRAM 'registers' | |
| #define | REG_IFBIOS *(vu16*)(REG_BASE-0x0008) |
| IRQ ack for IntrWait functions. | |
| #define | REG_RESET_DST *(vu16*)(REG_BASE-0x0006) |
| Destination for after SoftReset. | |
| #define | REG_ISR_MAIN *(fnptr*)(REG_BASE-0x0004) |
| IRQ handler address. | |
Display registers | |
| #define | REG_DISPCNT *(vu32*)(REG_BASE+0x0000) |
| Display control. | |
| #define | REG_DISPSTAT *(vu16*)(REG_BASE+0x0004) |
| Display status. | |
| #define | REG_VCOUNT *(vu16*)(REG_BASE+0x0006) |
| Scanline count. | |
Background control registers | |
| #define | REG_BGCNT ((vu16*)(REG_BASE+0x0008)) |
| Bg control array. | |
| #define | REG_BG0CNT *(vu16*)(REG_BASE+0x0008) |
| Bg0 control. | |
| #define | REG_BG1CNT *(vu16*)(REG_BASE+0x000A) |
| Bg1 control. | |
| #define | REG_BG2CNT *(vu16*)(REG_BASE+0x000C) |
| Bg2 control. | |
| #define | REG_BG3CNT *(vu16*)(REG_BASE+0x000E) |
| Bg3 control. | |
Regular background scroll registers. (write only!) | |
| #define | REG_BG_OFS ((BG_POINT*)(REG_BASE+0x0010)) |
| Bg scroll array. | |
| #define | REG_BG0HOFS *(vu16*)(REG_BASE+0x0010) |
| Bg0 horizontal scroll. | |
| #define | REG_BG0VOFS *(vu16*)(REG_BASE+0x0012) |
| Bg0 vertical scroll. | |
| #define | REG_BG1HOFS *(vu16*)(REG_BASE+0x0014) |
| Bg1 horizontal scroll. | |
| #define | REG_BG1VOFS *(vu16*)(REG_BASE+0x0016) |
| Bg1 vertical scroll. | |
| #define | REG_BG2HOFS *(vu16*)(REG_BASE+0x0018) |
| Bg2 horizontal scroll. | |
| #define | REG_BG2VOFS *(vu16*)(REG_BASE+0x001A) |
| Bg2 vertical scroll. | |
| #define | REG_BG3HOFS *(vu16*)(REG_BASE+0x001C) |
| Bg3 horizontal scroll. | |
| #define | REG_BG3VOFS *(vu16*)(REG_BASE+0x001E) |
| Bg3 vertical scroll. | |
Affine background parameters. (write only!) | |
| #define | REG_BG_AFFINE ((BG_AFFINE*)(REG_BASE+0x0000)) |
| Bg affine array. | |
| #define | REG_BG2PA *(vs16*)(REG_BASE+0x0020) |
| Bg2 matrix.pa. | |
| #define | REG_BG2PB *(vs16*)(REG_BASE+0x0022) |
| Bg2 matrix.pb. | |
| #define | REG_BG2PC *(vs16*)(REG_BASE+0x0024) |
| Bg2 matrix.pc. | |
| #define | REG_BG2PD *(vs16*)(REG_BASE+0x0026) |
| Bg2 matrix.pd. | |
| #define | REG_BG2X *(vs32*)(REG_BASE+0x0028) |
| Bg2 x scroll. | |
| #define | REG_BG2Y *(vs32*)(REG_BASE+0x002C) |
| Bg2 y scroll. | |
| #define | REG_BG3PA *(vs16*)(REG_BASE+0x0030) |
| Bg3 matrix.pa. | |
| #define | REG_BG3PB *(vs16*)(REG_BASE+0x0032) |
| Bg3 matrix.pb. | |
| #define | REG_BG3PC *(vs16*)(REG_BASE+0x0034) |
| Bg3 matrix.pc. | |
| #define | REG_BG3PD *(vs16*)(REG_BASE+0x0036) |
| Bg3 matrix.pd. | |
| #define | REG_BG3X *(vs32*)(REG_BASE+0x0038) |
| Bg3 x scroll. | |
| #define | REG_BG3Y *(vs32*)(REG_BASE+0x003C) |
| Bg3 y scroll. | |
Windowing registers | |
| #define | REG_WIN0H *(vu16*)(REG_BASE+0x0040) |
| win0 right, left (0xLLRR) | |
| #define | REG_WIN1H *(vu16*)(REG_BASE+0x0042) |
| win1 right, left (0xLLRR) | |
| #define | REG_WIN0V *(vu16*)(REG_BASE+0x0044) |
| win0 bottom, top (0xTTBB) | |
| #define | REG_WIN1V *(vu16*)(REG_BASE+0x0046) |
| win1 bottom, top (0xTTBB) | |
| #define | REG_WININ *(vu16*)(REG_BASE+0x0048) |
| win0, win1 control | |
| #define | REG_WINOUT *(vu16*)(REG_BASE+0x004A) |
| winOut, winObj control | |
Alternate Windowing registers | |
| #define | REG_WIN0R *(vu8*)(REG_BASE+0x0040) |
| Win 0 right. | |
| #define | REG_WIN0L *(vu8*)(REG_BASE+0x0041) |
| Win 0 left. | |
| #define | REG_WIN1R *(vu8*)(REG_BASE+0x0042) |
| Win 1 right. | |
| #define | REG_WIN1L *(vu8*)(REG_BASE+0x0043) |
| Win 1 left. | |
| #define | REG_WIN0B *(vu8*)(REG_BASE+0x0044) |
| Win 0 bottom. | |
| #define | REG_WIN0T *(vu8*)(REG_BASE+0x0045) |
| Win 0 top. | |
| #define | REG_WIN1B *(vu8*)(REG_BASE+0x0046) |
| Win 1 bottom. | |
| #define | REG_WIN1T *(vu8*)(REG_BASE+0x0047) |
| Win 1 top. | |
| #define | REG_WIN0CNT *(vu8*)(REG_BASE+0x0048) |
| window 0 control | |
| #define | REG_WIN1CNT *(vu8*)(REG_BASE+0x0049) |
| window 1 control | |
| #define | REG_WINOUTCNT *(vu8*)(REG_BASE+0x004A) |
| Out window control. | |
| #define | REG_WINOBJCNT *(vu8*)(REG_BASE+0x004B) |
| Obj window control. | |
Graphic effects | |
| #define | REG_MOSAIC *(vu32*)(REG_BASE+0x004C) |
| Mosaic control. | |
| #define | REG_BLDCNT *(vu16*)(REG_BASE+0x0050) |
| Alpha control. | |
| #define | REG_BLDALPHA *(vu16*)(REG_BASE+0x0052) |
| Fade level. | |
| #define | REG_BLDY *(vu16*)(REG_BASE+0x0054) |
| Blend levels. | |
Channel 1: Square wave with sweep | |
| #define | REG_SND1SWEEP *(vu16*)(REG_BASE+0x0060) |
| Channel 1 Sweep. | |
| #define | REG_SND1CNT *(vu16*)(REG_BASE+0x0062) |
| Channel 1 Control. | |
| #define | REG_SND1FREQ *(vu16*)(REG_BASE+0x0064) |
| Channel 1 frequency. | |
Channel 2: Simple square wave | |
| #define | REG_SND2CNT *(vu16*)(REG_BASE+0x0068) |
| Channel 2 control. | |
| #define | REG_SND2FREQ *(vu16*)(REG_BASE+0x006C) |
| Channel 2 frequency. | |
Channel 3: Wave player | |
| #define | REG_SND3SEL *(vu16*)(REG_BASE+0x0070) |
| Channel 3 wave select. | |
| #define | REG_SND3CNT *(vu16*)(REG_BASE+0x0072) |
| Channel 3 control. | |
| #define | REG_SND3FREQ *(vu16*)(REG_BASE+0x0074) |
| Channel 3 frequency. | |
Channel 4: Noise generator | |
| #define | REG_SND4CNT *(vu16*)(REG_BASE+0x0078) |
| Channel 4 control. | |
| #define | REG_SND4FREQ *(vu16*)(REG_BASE+0x007C) |
| Channel 4 frequency. | |
Sound control | |
| #define | REG_SNDCNT *(vu32*)(REG_BASE+0x0080) |
| Main sound control. | |
| #define | REG_SNDDMGCNT *(vu16*)(REG_BASE+0x0080) |
| DMG channel control. | |
| #define | REG_SNDDSCNT *(vu16*)(REG_BASE+0x0082) |
| Direct Sound control. | |
| #define | REG_SNDSTAT *(vu16*)(REG_BASE+0x0084) |
| Sound status. | |
| #define | REG_SNDBIAS *(vu16*)(REG_BASE+0x0088) |
| Sound bias. | |
Sound buffers | |
| #define | REG_WAVE_RAM (vu32*)(REG_BASE+0x0090) |
| Channel 3 wave buffer. | |
| #define | REG_WAVE_RAM0 *(vu32*)(REG_BASE+0x0090) |
| Channel 3 wave buffer. | |
| #define | REG_WAVE_RAM1 *(vu32*)(REG_BASE+0x0094) |
| Channel 3 wave buffer. | |
| #define | REG_WAVE_RAM2 *(vu32*)(REG_BASE+0x0098) |
| Channel 3 wave buffer. | |
| #define | REG_WAVE_RAM3 *(vu32*)(REG_BASE+0x009C) |
| Channel 3 wave buffer. | |
| #define | REG_FIFO_A *(vu32*)(REG_BASE+0x00A0) |
| DSound A FIFO. | |
| #define | REG_FIFO_B *(vu32*)(REG_BASE+0x00A4) |
| DSound B FIFO. | |
DMA registers | |
| #define | REG_DMA ((volatile DMA_REC*)(REG_BASE+0x00B0)) |
| DMA as DMA_REC array. | |
| #define | REG_DMA0SAD *(vu32*)(REG_BASE+0x00B0) |
| DMA 0 Source address. | |
| #define | REG_DMA0DAD *(vu32*)(REG_BASE+0x00B4) |
| DMA 0 Destination address. | |
| #define | REG_DMA0CNT *(vu32*)(REG_BASE+0x00B8) |
| DMA 0 Control. | |
| #define | REG_DMA1SAD *(vu32*)(REG_BASE+0x00BC) |
| DMA 1 Source address. | |
| #define | REG_DMA1DAD *(vu32*)(REG_BASE+0x00C0) |
| DMA 1 Destination address. | |
| #define | REG_DMA1CNT *(vu32*)(REG_BASE+0x00C4) |
| DMA 1 Control. | |
| #define | REG_DMA2SAD *(vu32*)(REG_BASE+0x00C8) |
| DMA 2 Source address. | |
| #define | REG_DMA2DAD *(vu32*)(REG_BASE+0x00CC) |
| DMA 2 Destination address. | |
| #define | REG_DMA2CNT *(vu32*)(REG_BASE+0x00D0) |
| DMA 2 Control. | |
| #define | REG_DMA3SAD *(vu32*)(REG_BASE+0x00D4) |
| DMA 3 Source address. | |
| #define | REG_DMA3DAD *(vu32*)(REG_BASE+0x00D8) |
| DMA 3 Destination address. | |
| #define | REG_DMA3CNT *(vu32*)(REG_BASE+0x00DC) |
| DMA 3 Control. | |
Timer registers | |
| #define | REG_TM ((volatile TMR_REC*)(REG_BASE+0x0100)) |
| Timers as TMR_REC array. | |
| #define | REG_TM0D *(vu16*)(REG_BASE+0x0100) |
| Timer 0 data. | |
| #define | REG_TM0CNT *(vu16*)(REG_BASE+0x0102) |
| Timer 0 control. | |
| #define | REG_TM1D *(vu16*)(REG_BASE+0x0104) |
| Timer 1 data. | |
| #define | REG_TM1CNT *(vu16*)(REG_BASE+0x0106) |
| Timer 1 control. | |
| #define | REG_TM2D *(vu16*)(REG_BASE+0x0108) |
| Timer 2 data. | |
| #define | REG_TM2CNT *(vu16*)(REG_BASE+0x010A) |
| Timer 2 control. | |
| #define | REG_TM3D *(vu16*)(REG_BASE+0x010C) |
| Timer 3 data. | |
| #define | REG_TM3CNT *(vu16*)(REG_BASE+0x010E) |
| Timer 3 control. | |
Serial communication | |
| #define | REG_SIOCNT *(vu16*)(REG_BASE+0x0128) |
| Serial IO control (Normal/MP/UART). | |
| #define | REG_SIODATA ((vu32*)(REG_BASE+0x0120)) |
| Serial IO control (Normal/MP/UART). | |
| #define | REG_SIODATA32 *(vu32*)(REG_BASE+0x0120) |
| Normal/UART 32bit data. | |
| #define | REG_SIODATA8 *(vu16*)(REG_BASE+0x012A) |
| Normal/UART 8bit data. | |
| #define | REG_SIOMULTI ((vu16*)(REG_BASE+0x0120)) |
| Multiplayer data array. | |
| #define | REG_SIOMULTI0 *(vu16*)(REG_BASE+0x0120) |
| MP master data. | |
| #define | REG_SIOMULTI1 *(vu16*)(REG_BASE+0x0122) |
| MP Slave 1 data. | |
| #define | REG_SIOMULTI2 *(vu16*)(REG_BASE+0x0124) |
| MP Slave 2 data. | |
| #define | REG_SIOMULTI3 *(vu16*)(REG_BASE+0x0126) |
| MP Slave 3 data. | |
| #define | REG_SIOMLT_RECV *(vu16*)(REG_BASE+0x0120) |
| MP data receiver. | |
| #define | REG_SIOMLT_SEND *(vu16*)(REG_BASE+0x012A) |
| MP data sender. | |
Keypad registers | |
| #define | REG_KEYINPUT *(vu16*)(REG_BASE+0x0130) |
| Key status (read only??). | |
| #define | REG_KEYCNT *(vu16*)(REG_BASE+0x0132) |
| Key IRQ control. | |
Joybus communication | |
| #define | REG_RCNT *(vu16*)(REG_BASE+0x0134) |
| SIO Mode Select/General Purpose Data. | |
| #define | REG_JOYCNT *(vu16*)(REG_BASE+0x0140) |
| JOY bus control. | |
| #define | REG_JOY_RECV *(vu32*)(REG_BASE+0x0150) |
| JOY bus receiever. | |
| #define | REG_JOY_TRANS *(vu32*)(REG_BASE+0x0154) |
| JOY bus transmitter. | |
| #define | REG_JOYSTAT *(vu16*)(REG_BASE+0x0158) |
| JOY bus status. | |
Interrupt / System registers | |
| #define | REG_IE *(vu16*)(REG_BASE+0x0200) |
| IRQ enable. | |
| #define | REG_IF *(vu16*)(REG_BASE+0x0202) |
| IRQ status/acknowledge. | |
| #define | REG_WAITCNT *(vu16*)(REG_BASE+0x0204) |
| Waitstate control. | |
| #define | REG_IME *(vu16*)(REG_BASE+0x0208) |
| IRQ master enable. | |
| #define | REG_PAUSE *(vu16*)(REG_BASE+0x0300) |
| Pause system (?). | |
Detailed Description
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