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STM8S/A Standard Peripherals Firmware Library
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STM8S_StdPeriph_Examples/TIM1/TIM1_6Steps/stm8s_it.c
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00001 /** 00002 ****************************************************************************** 00003 * @file stm8s_it.c 00004 * @author MCD Application Team 00005 * @version V2.2.0 00006 * @date 30-September-2014 00007 * @brief This file contains all the interrupt routines. 00008 ****************************************************************************** 00009 * @attention 00010 * 00011 * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> 00012 * 00013 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 00014 * You may not use this file except in compliance with the License. 00015 * You may obtain a copy of the License at: 00016 * 00017 * http://www.st.com/software_license_agreement_liberty_v2 00018 * 00019 * Unless required by applicable law or agreed to in writing, software 00020 * distributed under the License is distributed on an "AS IS" BASIS, 00021 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 00022 * See the License for the specific language governing permissions and 00023 * limitations under the License. 00024 * 00025 ****************************************************************************** 00026 */ 00027 00028 /* Includes ------------------------------------------------------------------*/ 00029 #include "stm8s_it.h" 00030 00031 /* Private typedef -----------------------------------------------------------*/ 00032 /* Private define ------------------------------------------------------------*/ 00033 /* Private macro -------------------------------------------------------------*/ 00034 /* Private variables ---------------------------------------------------------*/ 00035 uint8_t TimeCounter = 0; 00036 uint8_t step = 1; 00037 00038 /* Private function prototypes -----------------------------------------------*/ 00039 /* Private functions ---------------------------------------------------------*/ 00040 00041 /* Public functions ----------------------------------------------------------*/ 00042 00043 /** @addtogroup TIM1_6Steps 00044 * @{ 00045 */ 00046 #ifdef _COSMIC_ 00047 /** 00048 * @brief Dummy interrupt routine 00049 * @param None 00050 * @retval None 00051 */ 00052 INTERRUPT_HANDLER(NonHandledInterrupt, 25) 00053 { 00054 /* In order to detect unexpected events during development, 00055 it is recommended to set a breakpoint on the following instruction. 00056 */ 00057 } 00058 #endif /*_COSMIC_*/ 00059 00060 /** 00061 * @brief TRAP interrupt routine 00062 * @param None 00063 * @retval None 00064 */ 00065 INTERRUPT_HANDLER_TRAP(TRAP_IRQHandler) 00066 { 00067 /* In order to detect unexpected events during development, 00068 it is recommended to set a breakpoint on the following instruction. 00069 */ 00070 } 00071 /** 00072 * @brief Top Level Interrupt routine 00073 * @param None 00074 * @retval None 00075 */ 00076 INTERRUPT_HANDLER(TLI_IRQHandler, 0) 00077 { 00078 /* In order to detect unexpected events during development, 00079 it is recommended to set a breakpoint on the following instruction. 00080 */ 00081 } 00082 00083 /** 00084 * @brief Auto Wake Up Interrupt routine 00085 * @param None 00086 * @retval None 00087 */ 00088 INTERRUPT_HANDLER(AWU_IRQHandler, 1) 00089 { 00090 /* In order to detect unexpected events during development, 00091 it is recommended to set a breakpoint on the following instruction. 00092 */ 00093 } 00094 00095 /** 00096 * @brief Clock Controller Interrupt routine 00097 * @param None 00098 * @retval None 00099 */ 00100 INTERRUPT_HANDLER(CLK_IRQHandler, 2) 00101 { 00102 /* In order to detect unexpected events during development, 00103 it is recommended to set a breakpoint on the following instruction. 00104 */ 00105 } 00106 00107 /** 00108 * @brief External Interrupt PORTA Interrupt routine 00109 * @param None 00110 * @retval None 00111 */ 00112 INTERRUPT_HANDLER(EXTI_PORTA_IRQHandler, 3) 00113 { 00114 /* In order to detect unexpected events during development, 00115 it is recommended to set a breakpoint on the following instruction. 00116 */ 00117 } 00118 00119 /** 00120 * @brief External Interrupt PORTB Interrupt routine 00121 * @param None 00122 * @retval None 00123 */ 00124 INTERRUPT_HANDLER(EXTI_PORTB_IRQHandler, 4) 00125 { 00126 /* In order to detect unexpected events during development, 00127 it is recommended to set a breakpoint on the following instruction. 00128 */ 00129 } 00130 00131 /** 00132 * @brief External Interrupt PORTC Interrupt routine 00133 * @param None 00134 * @retval None 00135 */ 00136 INTERRUPT_HANDLER(EXTI_PORTC_IRQHandler, 5) 00137 { 00138 /* In order to detect unexpected events during development, 00139 it is recommended to set a breakpoint on the following instruction. 00140 */ 00141 } 00142 00143 /** 00144 * @brief External Interrupt PORTD Interrupt routine 00145 * @param None 00146 * @retval None 00147 */ 00148 INTERRUPT_HANDLER(EXTI_PORTD_IRQHandler, 6) 00149 { 00150 /* In order to detect unexpected events during development, 00151 it is recommended to set a breakpoint on the following instruction. 00152 */ 00153 } 00154 00155 /** 00156 * @brief External Interrupt PORTE Interrupt routine 00157 * @param None 00158 * @retval None 00159 */ 00160 INTERRUPT_HANDLER(EXTI_PORTE_IRQHandler, 7) 00161 { 00162 /* In order to detect unexpected events during development, 00163 it is recommended to set a breakpoint on the following instruction. 00164 */ 00165 } 00166 #ifdef STM8S903 00167 /** 00168 * @brief External Interrupt PORTF Interrupt routine 00169 * @param None 00170 * @retval None 00171 */ 00172 INTERRUPT_HANDLER(EXTI_PORTF_IRQHandler, 8) 00173 { 00174 /* In order to detect unexpected events during development, 00175 it is recommended to set a breakpoint on the following instruction. 00176 */ 00177 } 00178 #endif /*STM8S903*/ 00179 00180 #if defined (STM8S208) || defined (STM8AF52Ax) 00181 /** 00182 * @brief CAN RX Interrupt routine. 00183 * @param None 00184 * @retval None 00185 */ 00186 INTERRUPT_HANDLER(CAN_RX_IRQHandler, 8) 00187 { 00188 /* In order to detect unexpected events during development, 00189 it is recommended to set a breakpoint on the following instruction. 00190 */ 00191 } 00192 00193 /** 00194 * @brief CAN TX Interrupt routine 00195 * @param None 00196 * @retval None 00197 */ 00198 INTERRUPT_HANDLER(CAN_TX_IRQHandler, 9) 00199 { 00200 /* In order to detect unexpected events during development, 00201 it is recommended to set a breakpoint on the following instruction. 00202 */ 00203 } 00204 #endif /*STM8S208 || STM8AF52Ax */ 00205 00206 /** 00207 * @brief SPI Interrupt routine 00208 * @param None 00209 * @retval None 00210 */ 00211 INTERRUPT_HANDLER(SPI_IRQHandler, 10) 00212 { 00213 /* In order to detect unexpected events during development, 00214 it is recommended to set a breakpoint on the following instruction. 00215 */ 00216 } 00217 00218 /** 00219 * @brief Timer1 Update/Overflow/Trigger/Break Interrupt routine 00220 * @param None 00221 * @retval None 00222 */ 00223 INTERRUPT_HANDLER(TIM1_UPD_OVF_TRG_BRK_IRQHandler, 11) 00224 { 00225 /* In order to detect unexpected events during development, 00226 it is recommended to set a breakpoint on the following instruction. 00227 */ 00228 } 00229 00230 /** 00231 * @brief Timer1 Capture/Compare Interrupt routine 00232 * @param None 00233 * @retval None 00234 */ 00235 INTERRUPT_HANDLER(TIM1_CAP_COM_IRQHandler, 12) 00236 { 00237 /* Clear TIM1 COM pending bit */ 00238 TIM1_ClearITPendingBit(TIM1_IT_COM); 00239 00240 if(step == 1) 00241 { 00242 /* Next step: Step 2 Configuration ---------------------------- */ 00243 /* Channel3 configuration */ 00244 TIM1_CCxCmd(TIM1_CHANNEL_3, DISABLE); 00245 TIM1_CCxNCmd(TIM1_CHANNEL_3, DISABLE); 00246 00247 /* Channel1 configuration */ 00248 TIM1_SelectOCxM(TIM1_CHANNEL_1,(TIM1_OCMode_TypeDef)TIM1_FORCEDACTION_ACTIVE); 00249 TIM1_CCxCmd(TIM1_CHANNEL_1, ENABLE); 00250 TIM1_CCxNCmd(TIM1_CHANNEL_1, ENABLE); 00251 00252 /* Channel2 configuration */ 00253 TIM1_SelectOCxM(TIM1_CHANNEL_2, (TIM1_OCMode_TypeDef)TIM1_FORCEDACTION_INACTIVE); 00254 TIM1_CCxCmd(TIM1_CHANNEL_2, ENABLE); 00255 TIM1_CCxNCmd(TIM1_CHANNEL_2, ENABLE); 00256 step++; 00257 } 00258 else if(step == 2) 00259 { 00260 /* Next step: Step 3 Configuration ---------------------------- */ 00261 /* Channel2 configuration */ 00262 TIM1_SelectOCxM(TIM1_CHANNEL_2, (TIM1_OCMode_TypeDef)TIM1_FORCEDACTION_INACTIVE); 00263 TIM1_CCxCmd(TIM1_CHANNEL_2, ENABLE); 00264 TIM1_CCxNCmd(TIM1_CHANNEL_2, ENABLE); 00265 00266 /* Channel3 configuration */ 00267 TIM1_SelectOCxM(TIM1_CHANNEL_3, (TIM1_OCMode_TypeDef)TIM1_FORCEDACTION_ACTIVE); 00268 TIM1_CCxCmd(TIM1_CHANNEL_3, ENABLE); 00269 TIM1_CCxNCmd(TIM1_CHANNEL_3, ENABLE); 00270 00271 /* Channel1 configuration */ 00272 TIM1_CCxCmd(TIM1_CHANNEL_1, DISABLE); 00273 TIM1_CCxNCmd(TIM1_CHANNEL_1, DISABLE); 00274 step++; 00275 } 00276 else if(step == 3) 00277 { 00278 /* Next step: Step 4 Configuration ---------------------------- */ 00279 /* Channel3 configuration */ 00280 TIM1_SelectOCxM(TIM1_CHANNEL_3, (TIM1_OCMode_TypeDef)TIM1_FORCEDACTION_ACTIVE); 00281 TIM1_CCxCmd(TIM1_CHANNEL_3, ENABLE); 00282 TIM1_CCxNCmd(TIM1_CHANNEL_3, ENABLE); 00283 00284 /* Channel2 configuration */ 00285 TIM1_CCxCmd(TIM1_CHANNEL_2, DISABLE); 00286 TIM1_CCxNCmd(TIM1_CHANNEL_2, DISABLE); 00287 00288 /* Channel1 configuration */ 00289 TIM1_SelectOCxM(TIM1_CHANNEL_1, (TIM1_OCMode_TypeDef)TIM1_FORCEDACTION_INACTIVE); 00290 TIM1_CCxCmd(TIM1_CHANNEL_1, ENABLE); 00291 TIM1_CCxNCmd(TIM1_CHANNEL_1, ENABLE); 00292 step++; 00293 } 00294 else if(step == 4) 00295 { 00296 /* Next step: Step 5 Configuration ---------------------------- */ 00297 /* Channel3 configuration */ 00298 TIM1_CCxCmd(TIM1_CHANNEL_3, DISABLE); 00299 TIM1_CCxNCmd(TIM1_CHANNEL_3, DISABLE); 00300 00301 /* Channel1 configuration */ 00302 TIM1_SelectOCxM(TIM1_CHANNEL_1, (TIM1_OCMode_TypeDef)TIM1_FORCEDACTION_INACTIVE); 00303 TIM1_CCxCmd(TIM1_CHANNEL_1, ENABLE); 00304 TIM1_CCxNCmd(TIM1_CHANNEL_1, ENABLE); 00305 00306 /* Channel2 configuration */ 00307 TIM1_SelectOCxM(TIM1_CHANNEL_2, (TIM1_OCMode_TypeDef)TIM1_FORCEDACTION_ACTIVE); 00308 TIM1_CCxCmd(TIM1_CHANNEL_2, ENABLE); 00309 TIM1_CCxNCmd(TIM1_CHANNEL_2, ENABLE); 00310 step++; 00311 } 00312 else if (step == 5) 00313 { 00314 /* Next step: Step 6 Configuration ---------------------------- */ 00315 /* Channel3 configuration */ 00316 TIM1_SelectOCxM(TIM1_CHANNEL_3, (TIM1_OCMode_TypeDef)TIM1_FORCEDACTION_INACTIVE); 00317 TIM1_CCxCmd(TIM1_CHANNEL_3, ENABLE); 00318 TIM1_CCxNCmd(TIM1_CHANNEL_3, ENABLE); 00319 00320 /* Channel1 configuration */ 00321 TIM1_CCxCmd(TIM1_CHANNEL_1, DISABLE); 00322 TIM1_CCxNCmd(TIM1_CHANNEL_1, DISABLE); 00323 00324 /* Channel2 configuration */ 00325 TIM1_SelectOCxM(TIM1_CHANNEL_2, (TIM1_OCMode_TypeDef)TIM1_FORCEDACTION_ACTIVE); 00326 TIM1_CCxCmd(TIM1_CHANNEL_2, ENABLE); 00327 TIM1_CCxNCmd(TIM1_CHANNEL_2, ENABLE); 00328 step++; 00329 } 00330 else 00331 { 00332 /* Next step: Step 1 Configuration ---------------------------- */ 00333 /* Channel1 configuration */ 00334 TIM1_SelectOCxM(TIM1_CHANNEL_1, (TIM1_OCMode_TypeDef)TIM1_FORCEDACTION_ACTIVE); 00335 TIM1_CCxCmd(TIM1_CHANNEL_1, ENABLE); 00336 TIM1_CCxNCmd(TIM1_CHANNEL_1, ENABLE); 00337 00338 /* Channel3 configuration */ 00339 TIM1_SelectOCxM(TIM1_CHANNEL_3, (TIM1_OCMode_TypeDef)TIM1_FORCEDACTION_INACTIVE); 00340 TIM1_CCxCmd(TIM1_CHANNEL_3, ENABLE); 00341 TIM1_CCxNCmd(TIM1_CHANNEL_3, ENABLE); 00342 00343 /* Channel2 configuration */ 00344 TIM1_CCxCmd(TIM1_CHANNEL_2, DISABLE); 00345 TIM1_CCxNCmd(TIM1_CHANNEL_2, DISABLE); 00346 step = 1; 00347 } 00348 } 00349 00350 #ifdef STM8S903 00351 /** 00352 * @brief Timer5 Update/Overflow/Break/Trigger Interrupt routine 00353 * @param None 00354 * @retval None 00355 */ 00356 INTERRUPT_HANDLER(TIM5_UPD_OVF_BRK_TRG_IRQHandler, 13) 00357 { 00358 /* In order to detect unexpected events during development, 00359 it is recommended to set a breakpoint on the following instruction. 00360 */ 00361 } 00362 /** 00363 * @brief Timer5 Capture/Compare Interrupt routine 00364 * @param None 00365 * @retval None 00366 */ 00367 INTERRUPT_HANDLER(TIM5_CAP_COM_IRQHandler, 14) 00368 { 00369 /* In order to detect unexpected events during development, 00370 it is recommended to set a breakpoint on the following instruction. 00371 */ 00372 } 00373 00374 #else /*STM8S208, STM8S207, STM8S105 or STM8S103 or STM8AF62Ax or STM8AF52Ax or STM8AF626x */ 00375 /** 00376 * @brief Timer2 Update/Overflow/Break Interrupt routine 00377 * @param None 00378 * @retval None 00379 */ 00380 INTERRUPT_HANDLER(TIM2_UPD_OVF_BRK_IRQHandler, 13) 00381 { 00382 /* In order to detect unexpected events during development, 00383 it is recommended to set a breakpoint on the following instruction. 00384 */ 00385 } 00386 00387 /** 00388 * @brief Timer2 Capture/Compare Interrupt routine 00389 * @param None 00390 * @retval None 00391 */ 00392 INTERRUPT_HANDLER(TIM2_CAP_COM_IRQHandler, 14) 00393 { 00394 /* In order to detect unexpected events during development, 00395 it is recommended to set a breakpoint on the following instruction. 00396 */ 00397 } 00398 #endif /*STM8S903*/ 00399 00400 #if defined (STM8S208) || defined(STM8S207) || defined(STM8S007) || defined(STM8S105) || \ 00401 defined(STM8S005) || defined (STM8AF62Ax) || defined (STM8AF52Ax) || defined (STM8AF626x) 00402 /** 00403 * @brief Timer3 Update/Overflow/Break Interrupt routine. 00404 * @param None 00405 * @retval None 00406 */ 00407 INTERRUPT_HANDLER(TIM3_UPD_OVF_BRK_IRQHandler, 15) 00408 { 00409 /* In order to detect unexpected events during development, 00410 it is recommended to set a breakpoint on the following instruction. 00411 */ 00412 } 00413 00414 /** 00415 * @brief Timer3 Capture/Compare Interrupt routine 00416 * @param None 00417 * @retval None 00418 */ 00419 INTERRUPT_HANDLER(TIM3_CAP_COM_IRQHandler, 16) 00420 { 00421 /* In order to detect unexpected events during development, 00422 it is recommended to set a breakpoint on the following instruction. 00423 */ 00424 } 00425 #endif /*STM8S208, STM8S207 or STM8S105 or STM8AF62Ax or STM8AF52Ax or STM8AF626x */ 00426 00427 #if defined (STM8S208) || defined(STM8S207) || defined(STM8S007) || defined(STM8S103) || \ 00428 defined(STM8S003) || defined (STM8AF62Ax) || defined (STM8AF52Ax) || defined (STM8S903) 00429 /** 00430 * @brief UART1 TX Interrupt routine 00431 * @param None 00432 * @retval None 00433 */ 00434 INTERRUPT_HANDLER(UART1_TX_IRQHandler, 17) 00435 { 00436 /* In order to detect unexpected events during development, 00437 it is recommended to set a breakpoint on the following instruction. 00438 */ 00439 } 00440 00441 /** 00442 * @brief UART1 RX Interrupt routine 00443 * @param None 00444 * @retval None 00445 */ 00446 INTERRUPT_HANDLER(UART1_RX_IRQHandler, 18) 00447 { 00448 /* In order to detect unexpected events during development, 00449 it is recommended to set a breakpoint on the following instruction. 00450 */ 00451 } 00452 #endif /*STM8S105*/ 00453 00454 /** 00455 * @brief I2C Interrupt routine 00456 * @param None 00457 * @retval None 00458 */ 00459 INTERRUPT_HANDLER(I2C_IRQHandler, 19) 00460 { 00461 /* In order to detect unexpected events during development, 00462 it is recommended to set a breakpoint on the following instruction. 00463 */ 00464 } 00465 00466 #if defined(STM8S105) || defined(STM8S005) || defined (STM8AF626x) 00467 /** 00468 * @brief UART2 TX interrupt routine. 00469 * @param None 00470 * @retval None 00471 */ 00472 INTERRUPT_HANDLER(UART2_TX_IRQHandler, 20) 00473 { 00474 /* In order to detect unexpected events during development, 00475 it is recommended to set a breakpoint on the following instruction. 00476 */ 00477 } 00478 00479 /** 00480 * @brief UART2 RX interrupt routine. 00481 * @param None 00482 * @retval None 00483 */ 00484 INTERRUPT_HANDLER(UART2_RX_IRQHandler, 21) 00485 { 00486 /* In order to detect unexpected events during development, 00487 it is recommended to set a breakpoint on the following instruction. 00488 */ 00489 } 00490 #endif /* STM8S105*/ 00491 00492 #if defined(STM8S207) || defined(STM8S007) || defined(STM8S208) || defined (STM8AF52Ax) || defined (STM8AF62Ax) 00493 /** 00494 * @brief UART3 TX interrupt routine. 00495 * @param None 00496 * @retval None 00497 */ 00498 INTERRUPT_HANDLER(UART3_TX_IRQHandler, 20) 00499 { 00500 /* In order to detect unexpected events during development, 00501 it is recommended to set a breakpoint on the following instruction. 00502 */ 00503 } 00504 00505 /** 00506 * @brief UART3 RX interrupt routine. 00507 * @param None 00508 * @retval None 00509 */ 00510 INTERRUPT_HANDLER(UART3_RX_IRQHandler, 21) 00511 { 00512 /* In order to detect unexpected events during development, 00513 it is recommended to set a breakpoint on the following instruction. 00514 */ 00515 } 00516 #endif /*STM8S208 or STM8S207 or STM8AF52Ax or STM8AF62Ax */ 00517 00518 #if defined(STM8S207) || defined(STM8S007) || defined(STM8S208) || defined (STM8AF52Ax) || defined (STM8AF62Ax) 00519 /** 00520 * @brief ADC2 interrupt routine. 00521 * @param None 00522 * @retval None 00523 */ 00524 INTERRUPT_HANDLER(ADC2_IRQHandler, 22) 00525 { 00526 00527 /* In order to detect unexpected events during development, 00528 it is recommended to set a breakpoint on the following instruction. 00529 */ 00530 return; 00531 00532 } 00533 #else /*STM8S105, STM8S103 or STM8S903 or STM8AF626x */ 00534 /** 00535 * @brief ADC1 interrupt routine. 00536 * @param None 00537 * @retval None 00538 */ 00539 INTERRUPT_HANDLER(ADC1_IRQHandler, 22) 00540 { 00541 00542 /* In order to detect unexpected events during development, 00543 it is recommended to set a breakpoint on the following instruction. 00544 */ 00545 return; 00546 00547 } 00548 #endif /*STM8S208 or STM8S207 or STM8AF52Ax or STM8AF62Ax */ 00549 00550 #ifdef STM8S903 00551 /** 00552 * @brief Timer6 Update/Overflow/Trigger Interrupt routine 00553 * @param None 00554 * @retval None 00555 */ 00556 INTERRUPT_HANDLER(TIM6_UPD_OVF_TRG_IRQHandler, 23) 00557 { 00558 /* In order to detect unexpected events during development, 00559 it is recommended to set a breakpoint on the following instruction. 00560 */ 00561 } 00562 #else /*STM8S208, STM8S207, STM8S105 or STM8S103 or STM8AF62Ax or STM8AF52Ax or STM8AF626x */ 00563 /** 00564 * @brief Timer4 Update/Overflow Interrupt routine 00565 * @param None 00566 * @retval None 00567 */ 00568 INTERRUPT_HANDLER(TIM4_UPD_OVF_IRQHandler, 23) 00569 { 00570 TIM4_ClearITPendingBit(TIM4_IT_UPDATE); 00571 00572 if (TimeCounter == 11) 00573 { 00574 /* Generate TIM1 COM event by software */ 00575 TIM1_GenerateEvent(TIM1_EVENTSOURCE_COM); 00576 TimeCounter = 1; 00577 /* 00578 the TIM4 Update Interrupt occurs each 0.064ms ( Tui=(Period * Prescaler)/Fmaster = (256*128)/2Mhz = 16,384 ms ) 00579 so after 11 TIM4 Update Interrupts, 180ms have been spent (T= 11 * 16,384 = 180.2 ms) 00580 */ 00581 00582 } 00583 else 00584 { 00585 TimeCounter++; 00586 } 00587 } 00588 #endif /*STM8S903*/ 00589 00590 /** 00591 * @brief Eeprom EEC Interrupt routine 00592 * @param None 00593 * @retval None 00594 */ 00595 INTERRUPT_HANDLER(EEPROM_EEC_IRQHandler, 24) 00596 { 00597 /* In order to detect unexpected events during development, 00598 it is recommended to set a breakpoint on the following instruction. 00599 */ 00600 } 00601 00602 /** 00603 * @} 00604 */ 00605 00606 00607 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/