Socket APIs: Ethernet/wizchip_conf.c Source File

Wiznet Socket API

wizchip_conf.c
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1 //****************************************************************************/
14 // Issued by Mathias ClauBen.
49 //
50 //*****************************************************************************/
51 //A20140501 : for use the type - ptrdiff_t
52 #include <stddef.h>
53 //
54 
55 #include "wizchip_conf.h"
56 
58 //M20150401 : Remove ; in the default callback function such as wizchip_cris_enter(), wizchip_cs_select() and etc.
60 
66 //void wizchip_cris_enter(void) {};
67 void wizchip_cris_enter(void) {}
68 
74 //void wizchip_cris_exit(void) {};
75 void wizchip_cris_exit(void) {}
76 
82 //void wizchip_cs_select(void) {};
83 void wizchip_cs_select(void) {}
84 
90 //void wizchip_cs_deselect(void) {};
91 void wizchip_cs_deselect(void) {}
92 
98  //M20150601 : Rename the function for integrating with W5300
99 //uint8_t wizchip_bus_readbyte(uint32_t AddrSel) { return * ((volatile uint8_t *)((ptrdiff_t) AddrSel)); }
100 iodata_t wizchip_bus_readdata(uint32_t AddrSel) { return * ((volatile iodata_t *)((ptrdiff_t) AddrSel)); }
101 
107 //M20150601 : Rename the function for integrating with W5300
108 //void wizchip_bus_writebyte(uint32_t AddrSel, uint8_t wb) { *((volatile uint8_t*)((ptrdiff_t)AddrSel)) = wb; }
109 void wizchip_bus_writedata(uint32_t AddrSel, iodata_t wb) { *((volatile iodata_t*)((ptrdiff_t)AddrSel)) = wb; }
110 
116 //uint8_t wizchip_spi_readbyte(void) {return 0;};
117 uint8_t wizchip_spi_readbyte(void) {return 0;}
118 
124 //void wizchip_spi_writebyte(uint8_t wb) {};
125 void wizchip_spi_writebyte(uint8_t wb) {}
126 
132 //void wizchip_spi_readburst(uint8_t* pBuf, uint16_t len) {};
133 void wizchip_spi_readburst(uint8_t* pBuf, uint16_t len) {}
134 
140 //void wizchip_spi_writeburst(uint8_t* pBuf, uint16_t len) {};
141 void wizchip_spi_writeburst(uint8_t* pBuf, uint16_t len) {}
142 
146 //
147 //M20150401 : For a compiler didnot support a member of structure
148 // Replace the assignment of struct members with the assingment of array
149 //
150 /*
151 _WIZCHIP WIZCHIP =
152  {
153  .id = _WIZCHIP_ID_,
154  .if_mode = _WIZCHIP_IO_MODE_,
155  .CRIS._enter = wizchip_cris_enter,
156  .CRIS._exit = wizchip_cris_exit,
157  .CS._select = wizchip_cs_select,
158  .CS._deselect = wizchip_cs_deselect,
159  .IF.BUS._read_byte = wizchip_bus_readbyte,
160  .IF.BUS._write_byte = wizchip_bus_writebyte
161 // .IF.SPI._read_byte = wizchip_spi_readbyte,
162 // .IF.SPI._write_byte = wizchip_spi_writebyte
163  };
164 */
166  {
168  _WIZCHIP_ID_ ,
173  //M20150601 : Rename the function
174  //wizchip_bus_readbyte,
175  //wizchip_bus_writebyte
178 // wizchip_spi_readbyte,
179 // wizchip_spi_writebyte
180  };
181 
182 
183 static uint8_t _DNS_[4]; // DNS server ip address
184 static dhcp_mode _DHCP_; // DHCP mode
185 
186 void reg_wizchip_cris_cbfunc(void(*cris_en)(void), void(*cris_ex)(void))
187 {
188  if(!cris_en || !cris_ex)
189  {
190  WIZCHIP.CRIS._enter = wizchip_cris_enter;
191  WIZCHIP.CRIS._exit = wizchip_cris_exit;
192  }
193  else
194  {
195  WIZCHIP.CRIS._enter = cris_en;
196  WIZCHIP.CRIS._exit = cris_ex;
197  }
198 }
199 
200 void reg_wizchip_cs_cbfunc(void(*cs_sel)(void), void(*cs_desel)(void))
201 {
202  if(!cs_sel || !cs_desel)
203  {
204  WIZCHIP.CS._select = wizchip_cs_select;
205  WIZCHIP.CS._deselect = wizchip_cs_deselect;
206  }
207  else
208  {
209  WIZCHIP.CS._select = cs_sel;
210  WIZCHIP.CS._deselect = cs_desel;
211  }
212 }
213 
214 //M20150515 : For integrating with W5300
215 //void reg_wizchip_bus_cbfunc(uint8_t(*bus_rb)(uint32_t addr), void (*bus_wb)(uint32_t addr, uint8_t wb))
216 void reg_wizchip_bus_cbfunc(iodata_t(*bus_rb)(uint32_t addr), void (*bus_wb)(uint32_t addr, iodata_t wb))
217 {
218  while(!(WIZCHIP.if_mode & _WIZCHIP_IO_MODE_BUS_));
219  //M20150601 : Rename call back function for integrating with W5300
220  /*
221  if(!bus_rb || !bus_wb)
222  {
223  WIZCHIP.IF.BUS._read_byte = wizchip_bus_readbyte;
224  WIZCHIP.IF.BUS._write_byte = wizchip_bus_writebyte;
225  }
226  else
227  {
228  WIZCHIP.IF.BUS._read_byte = bus_rb;
229  WIZCHIP.IF.BUS._write_byte = bus_wb;
230  }
231  */
232  if(!bus_rb || !bus_wb)
233  {
236  }
237  else
238  {
239  WIZCHIP.IF.BUS._read_data = bus_rb;
240  WIZCHIP.IF.BUS._write_data = bus_wb;
241  }
242 }
243 
244 void reg_wizchip_spi_cbfunc(uint8_t (*spi_rb)(void), void (*spi_wb)(uint8_t wb))
245 {
246  while(!(WIZCHIP.if_mode & _WIZCHIP_IO_MODE_SPI_));
247 
248  if(!spi_rb || !spi_wb)
249  {
252  }
253  else
254  {
255  WIZCHIP.IF.SPI._read_byte = spi_rb;
256  WIZCHIP.IF.SPI._write_byte = spi_wb;
257  }
258 }
259 
260 // 20140626 Eric Added for SPI burst operations
261 void reg_wizchip_spiburst_cbfunc(void (*spi_rb)(uint8_t* pBuf, uint16_t len), void (*spi_wb)(uint8_t* pBuf, uint16_t len))
262 {
263  while(!(WIZCHIP.if_mode & _WIZCHIP_IO_MODE_SPI_));
264 
265  if(!spi_rb || !spi_wb)
266  {
269  }
270  else
271  {
272  WIZCHIP.IF.SPI._read_burst = spi_rb;
273  WIZCHIP.IF.SPI._write_burst = spi_wb;
274  }
275 }
276 
277 int8_t ctlwizchip(ctlwizchip_type cwtype, void* arg)
278 {
279 #if _WIZCHIP_ == 5200 || _WIZCHIP_ == 5500
280  uint8_t tmp = 0;
281 #endif
282  uint8_t* ptmp[2] = {0,0};
283  switch(cwtype)
284  {
285  case CW_RESET_WIZCHIP:
287  break;
288  case CW_INIT_WIZCHIP:
289  if(arg != 0)
290  {
291  ptmp[0] = (uint8_t*)arg;
292  ptmp[1] = ptmp[0] + _WIZCHIP_SOCK_NUM_;
293  }
294  return wizchip_init(ptmp[0], ptmp[1]);
295  case CW_CLR_INTERRUPT:
297  break;
298  case CW_GET_INTERRUPT:
299  *((intr_kind*)arg) = wizchip_getinterrupt();
300  break;
301  case CW_SET_INTRMASK:
303  break;
304  case CW_GET_INTRMASK:
305  *((intr_kind*)arg) = wizchip_getinterruptmask();
306  break;
307  //M20150601 : This can be supported by W5200, W5500
308  //#if _WIZCHIP_ > 5100
309  #if (_WIZCHIP_ == 5200 || _WIZCHIP_ == 5500)
310  case CW_SET_INTRTIME:
311  setINTLEVEL(*(uint16_t*)arg);
312  break;
313  case CW_GET_INTRTIME:
314  *(uint16_t*)arg = getINTLEVEL();
315  break;
316  #endif
317  case CW_GET_ID:
318  ((uint8_t*)arg)[0] = WIZCHIP.id[0];
319  ((uint8_t*)arg)[1] = WIZCHIP.id[1];
320  ((uint8_t*)arg)[2] = WIZCHIP.id[2];
321  ((uint8_t*)arg)[3] = WIZCHIP.id[3];
322  ((uint8_t*)arg)[4] = WIZCHIP.id[4];
323  ((uint8_t*)arg)[5] = 0;
324  break;
325  #if _WIZCHIP_ == 5500
326  case CW_RESET_PHY:
327  wizphy_reset();
328  break;
329  case CW_SET_PHYCONF:
331  break;
332  case CW_GET_PHYCONF:
334  break;
335  case CW_GET_PHYSTATUS:
336  break;
337  case CW_SET_PHYPOWMODE:
338  return wizphy_setphypmode(*(uint8_t*)arg);
339  #endif
340  #if _WIZCHIP_ == 5200 || _WIZCHIP_ == 5500
341  case CW_GET_PHYPOWMODE:
342  tmp = wizphy_getphypmode();
343  if((int8_t)tmp == -1) return -1;
344  *(uint8_t*)arg = tmp;
345  break;
346  case CW_GET_PHYLINK:
347  tmp = wizphy_getphylink();
348  if((int8_t)tmp == -1) return -1;
349  *(uint8_t*)arg = tmp;
350  break;
351  #endif
352  default:
353  return -1;
354  }
355  return 0;
356 }
357 
358 
359 int8_t ctlnetwork(ctlnetwork_type cntype, void* arg)
360 {
361 
362  switch(cntype)
363  {
364  case CN_SET_NETINFO:
366  break;
367  case CN_GET_NETINFO:
369  break;
370  case CN_SET_NETMODE:
371  return wizchip_setnetmode(*(netmode_type*)arg);
372  case CN_GET_NETMODE:
373  *(netmode_type*)arg = wizchip_getnetmode();
374  break;
375  case CN_SET_TIMEOUT:
377  break;
378  case CN_GET_TIMEOUT:
380  break;
381  default:
382  return -1;
383  }
384  return 0;
385 }
386 
388 {
389  uint8_t gw[4], sn[4], sip[4];
390  uint8_t mac[6];
391 //A20150601
392 #if _WIZCHIP_IO_MODE_ == _WIZCHIP_IO_MODE_BUS_INDIR_
393  uint16_t mr = (uint16_t)getMR();
394  setMR(mr | MR_IND);
395 #endif
396 //
397  getSHAR(mac);
398  getGAR(gw); getSUBR(sn); getSIPR(sip);
399  setMR(MR_RST);
400  getMR(); // for delay
401 //A2015051 : For indirect bus mode
402 #if _WIZCHIP_IO_MODE_ == _WIZCHIP_IO_MODE_BUS_INDIR_
403  setMR(mr | MR_IND);
404 #endif
405 //
406  setSHAR(mac);
407  setGAR(gw);
408  setSUBR(sn);
409  setSIPR(sip);
410 }
411 
412 int8_t wizchip_init(uint8_t* txsize, uint8_t* rxsize)
413 {
414  int8_t i;
415  int8_t tmp = 0;
417  if(txsize)
418  {
419  tmp = 0;
420  //M20150601 : For integrating with W5300
421  #if _WIZCHIP_ == 5300
422  for(i = 0 ; i < _WIZCHIP_SOCK_NUM_; i++)
423  {
424  if(txsize[i] >= 64) return -1; //No use 64KB even if W5300 support max 64KB memory allocation
425  tmp += txsize[i];
426  if(tmp > 128) return -1;
427  }
428  if(tmp % 8) return -1;
429  #else
430  for(i = 0 ; i < _WIZCHIP_SOCK_NUM_; i++)
431  {
432  tmp += txsize[i];
433  if(tmp > 16) return -1;
434  }
435  #endif
436  for(i = 0 ; i < _WIZCHIP_SOCK_NUM_; i++)
437  setSn_TXBUF_SIZE(i, txsize[i]);
438  }
439  if(rxsize)
440  {
441  tmp = 0;
442  #if _WIZCHIP_ == 5300
443  for(i = 0 ; i < _WIZCHIP_SOCK_NUM_; i++)
444  {
445  if(rxsize[i] >= 64) return -1; //No use 64KB even if W5300 support max 64KB memory allocation
446  tmp += rxsize[i];
447  if(tmp > 128) return -1;
448  }
449  if(tmp % 8) return -1;
450  #else
451  for(i = 0 ; i < _WIZCHIP_SOCK_NUM_; i++)
452  {
453  tmp += rxsize[i];
454  if(tmp > 16) return -1;
455  }
456  #endif
457 
458  for(i = 0 ; i < _WIZCHIP_SOCK_NUM_; i++)
459  setSn_RXBUF_SIZE(i, rxsize[i]);
460  }
461  return 0;
462 }
463 
465 {
466  uint8_t ir = (uint8_t)intr;
467  uint8_t sir = (uint8_t)((uint16_t)intr >> 8);
468 #if _WIZCHIP_ < 5500
469  ir |= (1<<4); // IK_WOL
470 #endif
471 #if _WIZCHIP_ == 5200
472  ir |= (1 << 6);
473 #endif
474 
475 #if _WIZCHIP_ < 5200
476  sir &= 0x0F;
477 #endif
478 
479 #if _WIZCHIP_ == 5100
480  ir |= sir;
481  setIR(ir);
482 //A20150601 : For integrating with W5300
483 #elif _WIZCHIP_ == 5300
484  setIR( ((((uint16_t)ir) << 8) | (((uint16_t)sir) & 0x00FF)) );
485 #else
486  setIR(ir);
487  setSIR(sir);
488 #endif
489 }
490 
492 {
493  uint8_t ir = 0;
494  uint8_t sir = 0;
495  uint16_t ret = 0;
496 #if _WIZCHIP_ == 5100
497  ir = getIR();
498  sir = ir & 0x0F;
499 //A20150601 : For integrating with W5300
500 #elif _WIZCHIP_ == 5300
501  ret = getIR();
502  ir = (uint8_t)(ret >> 8);
503  sir = (uint8_t)ret;
504 #else
505  ir = getIR();
506  sir = getSIR();
507 #endif
508 
509 //M20150601 : For Integrating with W5300
510 //#if _WIZCHIP_ < 5500
511 #if _WIZCHIP_ < 5200
512  ir &= ~(1<<4); // IK_WOL
513 #endif
514 #if _WIZCHIP_ == 5200
515  ir &= ~(1 << 6);
516 #endif
517  ret = sir;
518  ret = (ret << 8) + ir;
519  return (intr_kind)ret;
520 }
521 
523 {
524  uint8_t imr = (uint8_t)intr;
525  uint8_t simr = (uint8_t)((uint16_t)intr >> 8);
526 #if _WIZCHIP_ < 5500
527  imr &= ~(1<<4); // IK_WOL
528 #endif
529 #if _WIZCHIP_ == 5200
530  imr &= ~(1 << 6);
531 #endif
532 
533 #if _WIZCHIP_ == 5100
534  simr &= 0x0F;
535  imr |= simr;
536  setIMR(imr);
537 //A20150601 : For integrating with W5300
538 #elif _WIZCHIP_ == 5300
539  setIMR( ((((uint16_t)imr) << 8) | (((uint16_t)simr) & 0x00FF)) );
540 #else
541  setIMR(imr);
542  setSIMR(simr);
543 #endif
544 }
545 
547 {
548  uint8_t imr = 0;
549  uint8_t simr = 0;
550  uint16_t ret = 0;
551 #if _WIZCHIP_ == 5100
552  imr = getIMR();
553  simr = imr & 0x0F;
554 //A20150601 : For integrating with W5300
555 #elif _WIZCHIP_ == 5300
556  ret = getIMR();
557  imr = (uint8_t)(ret >> 8);
558  simr = (uint8_t)ret;
559 #else
560  imr = getIMR();
561  simr = getSIMR();
562 #endif
563 
564 #if _WIZCHIP_ < 5500
565  imr &= ~(1<<4); // IK_WOL
566 #endif
567 #if _WIZCHIP_ == 5200
568  imr &= ~(1 << 6); // IK_DEST_UNREACH
569 #endif
570  ret = simr;
571  ret = (ret << 8) + imr;
572  return (intr_kind)ret;
573 }
574 
575 int8_t wizphy_getphylink(void)
576 {
577  int8_t tmp;
578 #if _WIZCHIP_ == 5200
580  tmp = PHY_LINK_ON;
581  else
582  tmp = PHY_LINK_OFF;
583 #elif _WIZCHIP_ == 5500
584  if(getPHYCFGR() & PHYCFGR_LNK_ON)
585  tmp = PHY_LINK_ON;
586  else
587  tmp = PHY_LINK_OFF;
588 #else
589  tmp = -1;
590 #endif
591  return tmp;
592 }
593 
594 #if _WIZCHIP_ > 5100
595 
596 int8_t wizphy_getphypmode(void)
597 {
598  int8_t tmp = 0;
599  #if _WIZCHIP_ == 5200
601  tmp = PHY_POWER_DOWN;
602  else
603  tmp = PHY_POWER_NORM;
604  #elif _WIZCHIP_ == 5500
606  tmp = PHY_POWER_DOWN;
607  else
608  tmp = PHY_POWER_NORM;
609  #else
610  tmp = -1;
611  #endif
612  return tmp;
613 }
614 #endif
615 
616 #if _WIZCHIP_ == 5500
617 void wizphy_reset(void)
618 {
619  uint8_t tmp = getPHYCFGR();
620  tmp &= PHYCFGR_RST;
621  setPHYCFGR(tmp);
622  tmp = getPHYCFGR();
623  tmp |= ~PHYCFGR_RST;
624  setPHYCFGR(tmp);
625 }
626 
628 {
629  uint8_t tmp = 0;
630  if(phyconf->by == PHY_CONFBY_SW)
631  tmp |= PHYCFGR_OPMD;
632  else
633  tmp &= ~PHYCFGR_OPMD;
634  if(phyconf->mode == PHY_MODE_AUTONEGO)
635  tmp |= PHYCFGR_OPMDC_ALLA;
636  else
637  {
638  if(phyconf->duplex == PHY_DUPLEX_FULL)
639  {
640  if(phyconf->speed == PHY_SPEED_100)
641  tmp |= PHYCFGR_OPMDC_100F;
642  else
643  tmp |= PHYCFGR_OPMDC_10F;
644  }
645  else
646  {
647  if(phyconf->speed == PHY_SPEED_100)
648  tmp |= PHYCFGR_OPMDC_100H;
649  else
650  tmp |= PHYCFGR_OPMDC_10H;
651  }
652  }
653  setPHYCFGR(tmp);
654  wizphy_reset();
655 }
656 
658 {
659  uint8_t tmp = 0;
660  tmp = getPHYCFGR();
661  phyconf->by = (tmp & PHYCFGR_OPMD) ? PHY_CONFBY_SW : PHY_CONFBY_HW;
662  switch(tmp & PHYCFGR_OPMDC_ALLA)
663  {
664  case PHYCFGR_OPMDC_ALLA:
665  case PHYCFGR_OPMDC_100FA:
666  phyconf->mode = PHY_MODE_AUTONEGO;
667  break;
668  default:
669  phyconf->mode = PHY_MODE_MANUAL;
670  break;
671  }
672  switch(tmp & PHYCFGR_OPMDC_ALLA)
673  {
674  case PHYCFGR_OPMDC_100FA:
675  case PHYCFGR_OPMDC_100F:
676  case PHYCFGR_OPMDC_100H:
677  phyconf->speed = PHY_SPEED_100;
678  break;
679  default:
680  phyconf->speed = PHY_SPEED_10;
681  break;
682  }
683  switch(tmp & PHYCFGR_OPMDC_ALLA)
684  {
685  case PHYCFGR_OPMDC_100FA:
686  case PHYCFGR_OPMDC_100F:
687  case PHYCFGR_OPMDC_10F:
688  phyconf->duplex = PHY_DUPLEX_FULL;
689  break;
690  default:
691  phyconf->duplex = PHY_DUPLEX_HALF;
692  break;
693  }
694 }
695 
697 {
698  uint8_t tmp = getPHYCFGR();
700  phyconf->speed = (tmp & PHYCFGR_SPD_100) ? PHY_SPEED_100 : PHY_SPEED_10;
701 }
702 
703 int8_t wizphy_setphypmode(uint8_t pmode)
704 {
705  uint8_t tmp = 0;
706  tmp = getPHYCFGR();
707  if((tmp & PHYCFGR_OPMD)== 0) return -1;
708  tmp &= ~PHYCFGR_OPMDC_ALLA;
709  if( pmode == PHY_POWER_DOWN)
710  tmp |= PHYCFGR_OPMDC_PDOWN;
711  else
712  tmp |= PHYCFGR_OPMDC_ALLA;
713  setPHYCFGR(tmp);
714  wizphy_reset();
715  tmp = getPHYCFGR();
716  if( pmode == PHY_POWER_DOWN)
717  {
718  if(tmp & PHYCFGR_OPMDC_PDOWN) return 0;
719  }
720  else
721  {
722  if(tmp & PHYCFGR_OPMDC_ALLA) return 0;
723  }
724  return -1;
725 }
726 #endif
727 
728 
730 {
731  setSHAR(pnetinfo->mac);
732  setGAR(pnetinfo->gw);
733  setSUBR(pnetinfo->sn);
734  setSIPR(pnetinfo->ip);
735  _DNS_[0] = pnetinfo->dns[0];
736  _DNS_[1] = pnetinfo->dns[1];
737  _DNS_[2] = pnetinfo->dns[2];
738  _DNS_[3] = pnetinfo->dns[3];
739  _DHCP_ = pnetinfo->dhcp;
740 }
741 
743 {
744  getSHAR(pnetinfo->mac);
745  getGAR(pnetinfo->gw);
746  getSUBR(pnetinfo->sn);
747  getSIPR(pnetinfo->ip);
748  pnetinfo->dns[0]= _DNS_[0];
749  pnetinfo->dns[1]= _DNS_[1];
750  pnetinfo->dns[2]= _DNS_[2];
751  pnetinfo->dns[3]= _DNS_[3];
752  pnetinfo->dhcp = _DHCP_;
753 }
754 
756 {
757  uint8_t tmp = 0;
758 #if _WIZCHIP_ != 5500
759  if(netmode & ~(NM_WAKEONLAN | NM_PPPOE | NM_PINGBLOCK)) return -1;
760 #else
761  if(netmode & ~(NM_WAKEONLAN | NM_PPPOE | NM_PINGBLOCK | NM_FORCEARP)) return -1;
762 #endif
763  tmp = getMR();
764  tmp |= (uint8_t)netmode;
765  setMR(tmp);
766  return 0;
767 }
768 
770 {
771  return (netmode_type) getMR();
772 }
773 
775 {
776  setRCR(nettime->retry_cnt);
777  setRTR(nettime->time_100us);
778 }
779 
781 {
782  nettime->retry_cnt = getRCR();
783  nettime->time_100us = getRTR();
784 }
netmode_type wizchip_getnetmode(void)
Get the network mode such WOL, PPPoE, Ping Block, and etc.
Definition: wizchip_conf.c:769
uint8_t(* _read_byte)(void)
Definition: wizchip_conf.h:246
void wizchip_gettimeout(wiz_NetTimeout *nettime)
Get retry time value(RTR) and retry count(RCR).
Definition: wizchip_conf.c:780
_WIZCHIP WIZCHIP
Definition: wizchip_conf.c:165
#define getSIMR()
Definition: w5200.h:1548
#define getSIR()
Definition: w5200.h:1509
Get Network with wiz_NetInfo.
Definition: wizchip_conf.h:296
void wizphy_setphyconf(wiz_PhyConf *phyconf)
Set the phy information for WIZCHIP without power mode.
Definition: wizchip_conf.c:627
union __WIZCHIP::_IF IF
uint8_t retry_cnt
retry count
Definition: wizchip_conf.h:419
void(* _write_data)(uint32_t AddrSel, iodata_t wb)
Definition: wizchip_conf.h:238
void wizchip_cs_select(void)
Default function to select chip.
Definition: wizchip_conf.c:83
#define getSIPR(sipr)
Get SIPR.
Definition: w5100.h:1195
void wizchip_clrinterrupt(intr_kind intr)
Clear Interrupt of WIZCHIP.
Definition: wizchip_conf.c:464
Get network mode as WOL, PPPoE, Ping Block, and Force ARP mode.
Definition: wizchip_conf.h:298
void(* _select)(void)
_WIZCHIP_ selected
Definition: wizchip_conf.h:218
void wizchip_cs_deselect(void)
Default function to deselect chip.
Definition: wizchip_conf.c:91
void wizchip_spi_writeburst(uint8_t *pBuf, uint16_t len)
Default function to burst write in SPI interface.
Definition: wizchip_conf.c:141
#define PHY_DUPLEX_FULL
Link Full-Duplex.
Definition: wizchip_conf.h:350
#define setSIPR(sipr)
Set SIPR.
Definition: w5100.h:1186
void wizphy_getphyconf(wiz_PhyConf *phyconf)
Get phy configuration information.
Definition: wizchip_conf.c:657
void wizchip_spi_readburst(uint8_t *pBuf, uint16_t len)
Default function to burst read in SPI interface.
Definition: wizchip_conf.c:133
Get PHY operation mode in internal register. Valid Only W5500.
Definition: wizchip_conf.h:278
void reg_wizchip_bus_cbfunc(iodata_t(*bus_rb)(uint32_t addr), void(*bus_wb)(uint32_t addr, iodata_t wb))
Registers call back function for bus interface.
Definition: wizchip_conf.c:216
#define _WIZCHIP_IO_MODE_SPI_
Definition: wizchip_conf.h:69
#define _WIZCHIP_ID_
Definition: wizchip_conf.h:111
#define PHY_CONFBY_SW
Configured PHY operation mode by SW register.
Definition: wizchip_conf.h:344
#define PHYCFGR_OPMDC_ALLA
Definition: w5500.h:764
Get interrupt mask.
Definition: wizchip_conf.h:269
#define MR_IND
Indirect Bus Interface mode.
Definition: w5100.h:611
#define PHY_MODE_MANUAL
Configured PHY operation mode with user setting.
Definition: wizchip_conf.h:345
Set Network with wiz_NetInfo.
Definition: wizchip_conf.h:295
Get network timeout as retry count and time.
Definition: wizchip_conf.h:300
void wizphy_reset(void)
Reset phy. Vailid only in W5500.
Definition: wizchip_conf.c:617
uint8_t mac[6]
Source Mac Address.
Definition: wizchip_conf.h:391
#define PHYCFGR_LNK_ON
Definition: w5500.h:776
Get Interrupt status of WIZCHIP.
Definition: wizchip_conf.h:266
#define getINTLEVEL()
Get INTLEVEL register.
Definition: w5200.h:1488
Get PHY Power mode as down or normal, Valid Only W5100, W5200.
Definition: wizchip_conf.h:284
#define PHYCFGR_OPMDC_100H
Definition: w5500.h:769
Set network mode as WOL, PPPoE, Ping Block, and Force ARP mode.
Definition: wizchip_conf.h:297
void(* _exit)(void)
critial section exit
Definition: wizchip_conf.h:211
#define setGAR(gar)
Set GAR.
Definition: w5100.h:1129
uint16_t if_mode
host interface mode
Definition: wizchip_conf.h:203
void(* _read_burst)(uint8_t *pBuf, uint16_t len)
Definition: wizchip_conf.h:248
#define PHYCFGR_OPMDC_100FA
Definition: w5500.h:767
Gets WIZCHIP name.
Definition: wizchip_conf.h:272
#define PHYCFGR_OPMDC_100F
Definition: w5500.h:768
#define PHY_SPEED_100
Link Speed 100.
Definition: wizchip_conf.h:348
#define PHY_CONFBY_HW
Configured PHY operation mode by HW pin.
Definition: wizchip_conf.h:343
#define PHYSTATUS_LINK
Link Status [Read Only].
Definition: w5200.h:757
void(* _deselect)(void)
_WIZCHIP_ deselected
Definition: wizchip_conf.h:219
#define PHYCFGR_OPMDC_PDOWN
Definition: w5500.h:765
void(* _write_byte)(uint8_t wb)
Definition: wizchip_conf.h:247
Clears interrupt.
Definition: wizchip_conf.h:267
void reg_wizchip_cs_cbfunc(void(*cs_sel)(void), void(*cs_desel)(void))
Registers call back function for WIZCHIP select & deselect.
Definition: wizchip_conf.c:200
void wizchip_getnetinfo(wiz_NetInfo *pnetinfo)
Get the network information for WIZCHIP.
Definition: wizchip_conf.c:742
#define setIR(ir)
Set IR register.
Definition: w5100.h:1204
uint8_t wizchip_spi_readbyte(void)
Default function to read in SPI interface.
Definition: wizchip_conf.c:117
#define setSIR(ir2)
Definition: w5200.h:1499
iodata_t(* _read_data)(uint32_t AddrSel)
Definition: wizchip_conf.h:237
#define PHYCFGR_OPMDC_10F
Definition: w5500.h:770
struct __WIZCHIP::_IF::@1 SPI
#define PHYCFGR_OPMD
Definition: w5500.h:763
#define setMR(mr)
Set Mode Register.
Definition: w5100.h:1108
#define getIR()
Get IR register.
Definition: w5100.h:1212
intr_kind wizchip_getinterruptmask(void)
Get Interrupt mask of WIZCHIP.
Definition: wizchip_conf.c:546
uint8_t id[6]
WIZCHIP ID such as 5100, 5200, 5500, and so on.
Definition: wizchip_conf.h:204
#define PHY_DUPLEX_HALF
Link Half-Duplex.
Definition: wizchip_conf.h:349
Get real PHY status on operating. Valid Only W5500.
Definition: wizchip_conf.h:279
#define PHYSTATUS_POWERDOWN
Power down mode of PHY.
Definition: w5200.h:769
#define PHY_POWER_DOWN
PHY power down mode.
Definition: wizchip_conf.h:354
#define getGAR(gar)
Get GAR.
Definition: w5100.h:1138
uint8_t dns[4]
DNS server IP Address.
Definition: wizchip_conf.h:395
uint8_t speed
set by PHY_SPEED_10 or PHY_SPEED_100
Definition: wizchip_conf.h:368
int8_t ctlnetwork(ctlnetwork_type cntype, void *arg)
Controls to network.
Definition: wizchip_conf.c:359
uint8_t gw[4]
Gateway IP Address.
Definition: wizchip_conf.h:394
Wake On Lan.
Definition: wizchip_conf.h:408
struct __WIZCHIP::_CRIS CRIS
#define setSUBR(subr)
Set SUBR.
Definition: w5100.h:1150
#define PHY_MODE_AUTONEGO
Configured PHY operation mode with auto-negotiation.
Definition: wizchip_conf.h:346
Set interval time between the current and next interrupt.
Definition: wizchip_conf.h:271
uint8_t duplex
set by PHY_DUPLEX_HALF PHY_DUPLEX_FULL
Definition: wizchip_conf.h:369
#define PHY_POWER_NORM
PHY power normal mode.
Definition: wizchip_conf.h:353
iodata_t wizchip_bus_readdata(uint32_t AddrSel)
Default function to read in direct or indirect interface.
Definition: wizchip_conf.c:100
int8_t wizphy_getphypmode(void)
get the power mode of PHY in WIZCHIP. No use in W5100
Definition: wizchip_conf.c:596
#define getMR()
Get MR.
Definition: w5100.h:1120
Force to APP send whenever udp data is sent. Valid only in W5500.
Definition: wizchip_conf.h:406
#define setPHYCFGR(phycfgr)
Set PHYCFGR register.
Definition: w5500.h:1612
#define getPHYSTATUS()
Get PHYSTATUS register.
Definition: w5200.h:1516
dhcp_mode dhcp
1 - Static, 2 - DHCP
Definition: wizchip_conf.h:396
#define getSHAR(shar)
Get SHAR.
Definition: w5100.h:1177
void reg_wizchip_cris_cbfunc(void(*cris_en)(void), void(*cris_ex)(void))
Registers call back function for critical section of I/O functions such as WIZCHIP_READ, WIZCHIP_WRITE, WIZCHIP_READ_BUF and WIZCHIP_WRITE_BUF.
Definition: wizchip_conf.c:186
#define setRCR(rcr)
Set RCR register.
Definition: w5100.h:1259
#define _WIZCHIP_IO_MODE_
Define interface mode. .
Definition: wizchip_conf.h:128
#define PHY_LINK_ON
Link On.
Definition: wizchip_conf.h:352
Initializes to WIZCHIP with SOCKET buffer size 2 or 1 dimension array typed uint8_t.
Definition: wizchip_conf.h:265
Resets WIZCHIP by softly.
Definition: wizchip_conf.h:264
uint16_t time_100us
time unit 100us
Definition: wizchip_conf.h:420
#define _WIZCHIP_IO_MODE_BUS_
Definition: wizchip_conf.h:68
void wizchip_setinterruptmask(intr_kind intr)
Mask or Unmask Interrupt of WIZCHIP.
Definition: wizchip_conf.c:522
intr_kind wizchip_getinterrupt(void)
Get Interrupt of WIZCHIP.
Definition: wizchip_conf.c:491
The set of callback functions for W5500:WIZCHIP I/O functions W5200:WIZCHIP I/O functions.
Definition: wizchip_conf.h:201
void wizchip_cris_enter(void)
Default function to enable interrupt.
Definition: wizchip_conf.c:67
#define setSHAR(shar)
Set SHAR.
Definition: w5100.h:1168
#define PHYCFGR_DPX_FULL
Definition: w5500.h:772
Set PHY power mode as normal and down when PHYSTATUS.OPMD == 1. Valid Only W5500. ...
Definition: wizchip_conf.h:280
#define getSUBR(subr)
Get SUBR.
Definition: w5100.h:1159
ctlnetwork_type
Definition: wizchip_conf.h:293
int8_t wizphy_setphypmode(uint8_t pmode)
set the power mode of phy inside WIZCHIP. Refer to PHYCFGR in W5500, PHYSTATUS in W5200 ...
Definition: wizchip_conf.c:703
#define getRCR()
Get RCR register.
Definition: w5100.h:1268
#define setRTR(rtr)
Set RTR register.
Definition: w5100.h:1239
Resets internal PHY. Valid Only W5500.
Definition: wizchip_conf.h:276
uint8_t ip[4]
Source IP Address.
Definition: wizchip_conf.h:392
Masks interrupt.
Definition: wizchip_conf.h:268
int8_t wizchip_init(uint8_t *txsize, uint8_t *rxsize)
Initializes WIZCHIP with socket buffer size.
Definition: wizchip_conf.c:412
void wizchip_settimeout(wiz_NetTimeout *nettime)
Set retry time value(RTR) and retry count(RCR).
Definition: wizchip_conf.c:774
#define setSn_RXBUF_SIZE(sn, rxmemsize)
Definition: w5100.h:1604
void wizchip_sw_reset(void)
Reset WIZCHIP by softly.
Definition: wizchip_conf.c:387
#define _WIZCHIP_SOCK_NUM_
The count of independant socket of WIZCHIP.
Definition: wizchip_conf.h:188
#define PHYCFGR_OPMDC_10H
Definition: w5500.h:771
#define getRTR()
Get RTR register.
Definition: w5100.h:1250
void wizchip_setnetinfo(wiz_NetInfo *pnetinfo)
Set the network information for WIZCHIP.
Definition: wizchip_conf.c:729
void(* _write_burst)(uint8_t *pBuf, uint16_t len)
Definition: wizchip_conf.h:249
void wizchip_spi_writebyte(uint8_t wb)
Default function to write in SPI interface.
Definition: wizchip_conf.c:125
Set interval time between the current and next interrupt.
Definition: wizchip_conf.h:270
int8_t ctlwizchip(ctlwizchip_type cwtype, void *arg)
Controls to the WIZCHIP.
Definition: wizchip_conf.c:277
struct __WIZCHIP::_CS CS
uint8_t iodata_t
Definition: wizchip_conf.h:131
uint8_t by
set by PHY_CONFBY_HW or PHY_CONFBY_SW
Definition: wizchip_conf.h:366
intr_kind
Definition: wizchip_conf.h:309
Set network timeout as retry count and time.
Definition: wizchip_conf.h:299
#define getIMR()
Get IMR register.
Definition: w5100.h:1230
void wizchip_cris_exit(void)
Default function to disable interrupt.
Definition: wizchip_conf.c:75
void wizphy_getphystat(wiz_PhyConf *phyconf)
Get phy status.
Definition: wizchip_conf.c:696
int8_t wizchip_setnetmode(netmode_type netmode)
Set the network mode such WOL, PPPoE, Ping Block, and etc.
Definition: wizchip_conf.c:755
#define setIMR(imr)
Set IMR register.
Definition: w5100.h:1221
#define PHYCFGR_SPD_100
Definition: w5500.h:774
uint8_t sn[4]
Subnet Mask.
Definition: wizchip_conf.h:393
#define getPHYCFGR()
Get PHYCFGR register.
Definition: w5500.h:1621
struct __WIZCHIP::_IF::@0 BUS
void reg_wizchip_spiburst_cbfunc(void(*spi_rb)(uint8_t *pBuf, uint16_t len), void(*spi_wb)(uint8_t *pBuf, uint16_t len))
Registers call back function for SPI interface.
Definition: wizchip_conf.c:261
uint8_t mode
set by PHY_MODE_MANUAL or PHY_MODE_AUTONEGO
Definition: wizchip_conf.h:367
When PHY configured by internal register, PHY operation mode (Manual/Auto, 10/100, Half/Full). Valid Only W5000.
Definition: wizchip_conf.h:277
netmode_type
Definition: wizchip_conf.h:403
void reg_wizchip_spi_cbfunc(uint8_t(*spi_rb)(void), void(*spi_wb)(uint8_t wb))
Registers call back function for SPI interface.
Definition: wizchip_conf.c:244
WIZCHIP Config Header File.
dhcp_mode
Definition: wizchip_conf.h:379
#define PHYCFGR_RST
Definition: w5500.h:762
Get PHY Link status, Valid Only W5100, W5200.
Definition: wizchip_conf.h:285
#define setINTLEVEL(intlevel)
Set INTLEVEL register.
Definition: w5200.h:1478
int8_t wizphy_getphylink(void)
get the link status of phy in WIZCHIP. No use in W5100
Definition: wizchip_conf.c:575
ctlwizchip_type
Definition: wizchip_conf.h:262
#define MR_RST
Reset.
Definition: w5100.h:577
void wizchip_bus_writedata(uint32_t AddrSel, iodata_t wb)
Default function to write in direct or indirect interface.
Definition: wizchip_conf.c:109
PPPoE mode.
Definition: wizchip_conf.h:410
#define PHY_LINK_OFF
Link Off.
Definition: wizchip_conf.h:351
#define setSIMR(imr2)
Definition: w5200.h:1533
Block ping-request.
Definition: wizchip_conf.h:409
void(* _enter)(void)
crtical section enter
Definition: wizchip_conf.h:210
#define PHY_SPEED_10
Link Speed 10.
Definition: wizchip_conf.h:347
#define setSn_TXBUF_SIZE(sn, txmemsize)
Definition: w5100.h:1626
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