|
| #define | _WIZCHIP_SN_BASE_ (0x0200) |
| |
| #define | _WIZCHIP_SN_SIZE_ (0x0040) |
| |
| #define | WIZCHIP_CREG_BLOCK 0x00 |
| | Common register block. More...
|
| |
| #define | WIZCHIP_SREG_BLOCK(N) (_WIZCHIP_SN_BASE_+ _WIZCHIP_SN_SIZE_*N) |
| | Socket N register block. More...
|
| |
| #define | WIZCHIP_OFFSET_INC(ADDR, N) (ADDR + N) |
| | Increase offset address. More...
|
| |
| #define | _W5300_IO_BASE_ _WIZCHIP_IO_BASE_ |
| |
| #define | IINCHIP_READ(ADDR) WIZCHIP_READ(ADDR) |
| | The defined for legacy chip driver. More...
|
| |
| #define | IINCHIP_WRITE(ADDR, VAL) WIZCHIP_WRITE(ADDR,VAL) |
| | The defined for legacy chip driver. More...
|
| |
| #define | MR (_WIZCHIP_IO_BASE_) |
| | Mode Register address(R/W)
MR is used for S/W reset, ping block mode, PPPoE mode and etc. More...
|
| |
| #define | IR (_W5300_IO_BASE_ + 0x02) |
| | Interrupt Register(R/W) More...
|
| |
| #define | _IMR_ (_W5300_IO_BASE_ + 0x04) |
| | Socket Interrupt Mask Register(R/W) More...
|
| |
| #define | SHAR (_W5300_IO_BASE_ + 0x08) |
| | Source MAC Register address(R/W) More...
|
| |
| #define | GAR (_W5300_IO_BASE_ + 0x10) |
| | Gateway IP Register address(R/W) More...
|
| |
| #define | SUBR (_W5300_IO_BASE_ + 0x14) |
| | Subnet mask Register address(R/W) More...
|
| |
| #define | SIPR (_W5300_IO_BASE_ + 0x18) |
| | Source IP Register address(R/W) More...
|
| |
| #define | _RTR_ (_W5300_IO_BASE_ + 0x1C) |
| | Timeout register address( 1 is 100us )(R/W) More...
|
| |
| #define | _RCR_ (_W5300_IO_BASE_ + 0x1E) |
| | Retry count register(R/W) More...
|
| |
| #define | TMS01R (_W5300_IO_BASE_ + 0x20) |
| | TX memory size of SOCKET 0 & 1. More...
|
| |
| #define | TMS23R (TMS01R + 2) |
| | TX memory size of SOCKET 2 & 3. More...
|
| |
| #define | TMS45R (TMS01R + 4) |
| | TX memory size of SOCKET 4 & 5. More...
|
| |
| #define | TMS67R (TMS01R + 6) |
| | TX memory size of SOCKET 6 & 7. More...
|
| |
| #define | TMSR0 TMS01R |
| | TX memory size of SOCKET 0. More...
|
| |
| #define | TMSR1 (TMSR0 + 1) |
| | TX memory size of SOCKET 1. More...
|
| |
| #define | TMSR2 (TMSR0 + 2) |
| | TX memory size of SOCKET 2. More...
|
| |
| #define | TMSR3 (TMSR0 + 3) |
| | TX memory size of SOCKET 3. More...
|
| |
| #define | TMSR4 (TMSR0 + 4) |
| | TX memory size of SOCKET 4. More...
|
| |
| #define | TMSR5 (TMSR0 + 5) |
| | TX memory size of SOCKET 5. More...
|
| |
| #define | TMSR6 (TMSR0 + 6) |
| | TX memory size of SOCKET 6. More...
|
| |
| #define | TMSR7 (TMSR0 + 7) |
| | TX memory size of SOCKET 7. More...
|
| |
| #define | RMS01R (_W5300_IO_BASE_ + 0x28) |
| | RX memory size of SOCKET 0 & 1. More...
|
| |
| #define | RMS23R (RMS01R + 2) |
| | RX memory size of SOCKET 2 & 3. More...
|
| |
| #define | RMS45R (RMS01R + 4) |
| | RX memory size of SOCKET 4 & 5. More...
|
| |
| #define | RMS67R (RMS01R + 6) |
| | RX memory size of SOCKET 6 & 7. More...
|
| |
| #define | RMSR0 RMS01R |
| | RX memory size of SOCKET 0. More...
|
| |
| #define | RMSR1 (RMSR0 + 1) |
| | RX memory size of SOCKET 1. More...
|
| |
| #define | RMSR2 (RMSR0 + 2) |
| | RX memory size of SOCKET 2. More...
|
| |
| #define | RMSR3 (RMSR0 + 3) |
| | RX memory size of SOCKET 3. More...
|
| |
| #define | RMSR4 (RMSR0 + 4) |
| | RX memory size of SOCKET 4. More...
|
| |
| #define | RMSR5 (RMSR0 + 5) |
| | RX memory size of SOCKET 5. More...
|
| |
| #define | RMSR6 (RMSR0 + 6) |
| | RX memory size of SOCKET 6. More...
|
| |
| #define | RMSR7 (RMSR0 + 7) |
| | RX memory size of SOCKET 7. More...
|
| |
| #define | MTYPER (_W5300_IO_BASE_ + 0x30) |
| | Memory Type Register. More...
|
| |
| #define | PATR (_W5300_IO_BASE_ + 0x32) |
| | PPPoE Authentication Type register. More...
|
| |
| #define | PTIMER (_W5300_IO_BASE_ + 0x36) |
| | PPP Link Control Protocol Request Timer Register. More...
|
| |
| #define | PMAGICR (_W5300_IO_BASE_ + 0x38) |
| | PPP LCP magic number register. More...
|
| |
| #define | PSIDR (_W5300_IO_BASE_ + 0x3C) |
| | PPPoE session ID register. More...
|
| |
| #define | PDHAR (_W5300_IO_BASE_ + 0x40) |
| | PPPoE destination hardware address register. More...
|
| |
| #define | UIPR (_W5300_IO_BASE_ + 0x48) |
| | Unreachable IP address register. More...
|
| |
| #define | UPORTR (_W5300_IO_BASE_ + 0x4C) |
| | Unreachable port number register. More...
|
| |
| #define | FMTUR (_W5300_IO_BASE_ + 0x4E) |
| | Fragment MTU register. More...
|
| |
| #define | Pn_BRDYR(n) (_W5300_IO_BASE_ + 0x60 + n*4) |
| | PIN 'BRDYn' configure register. More...
|
| |
| #define | Pn_BDPTHR(n) (_W5300_IO_BASE_ + 0x60 + n*4 + 2) |
| | PIN 'BRDYn' buffer depth Register. More...
|
| |
| #define | IDR (_W5300_IO_BASE_ + 0xFE) |
| | W5300 identification register. More...
|
| |
| #define | VERSIONR IDR |
| |
| #define | Sn_MR(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x00) |
| | Socket Mode register(R/W) More...
|
| |
| #define | Sn_CR(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x02) |
| | Socket command register(R/W) More...
|
| |
| #define | Sn_IMR(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x04) |
| | socket interrupt mask register(R) More...
|
| |
| #define | Sn_IR(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x06) |
| | Socket interrupt register(R) More...
|
| |
| #define | Sn_SSR(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x08) |
| | Socket status register(R) More...
|
| |
| #define | Sn_SR(n) Sn_SSR(n) |
| | For Compatible ioLibrary. Refer to Sn_SSR(n) More...
|
| |
| #define | Sn_PORTR(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x0A) |
| | source port register(R/W) More...
|
| |
| #define | Sn_PORT(n) Sn_PORTR(n) |
| | For compatible ioLibrary. Refer to Sn_PORTR(n). More...
|
| |
| #define | Sn_DHAR(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x0C) |
| | Peer MAC register address(R/W) More...
|
| |
| #define | Sn_DPORTR(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x12) |
| | Peer port register address(R/W) More...
|
| |
| #define | Sn_DPORT(n) Sn_DPORTR(n) |
| | For compatible ioLibrary. Refer to Sn_DPORTR. More...
|
| |
| #define | Sn_DIPR(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x14) |
| | Peer IP register address(R/W) More...
|
| |
| #define | Sn_MSSR(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x18) |
| | Maximum Segment Size(Sn_MSSR0) register address(R/W) More...
|
| |
| #define | Sn_KPALVTR(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x1A) |
| | Keep Alive Timer register(R/W) More...
|
| |
| #define | Sn_PROTOR(n) Sn_KPALVTR(n) |
| | IP Protocol(PROTO) Register(R/W) More...
|
| |
| #define | Sn_TOSR(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x1C) |
| | IP Type of Service(TOS) Register(R/W) More...
|
| |
| #define | Sn_TOS(n) Sn_TOSR(n) |
| | For compatible ioLibrary. Refer to Sn_TOSR. More...
|
| |
| #define | Sn_TTLR(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x1E) |
| | IP Time to live(TTL) Register(R/W) More...
|
| |
| #define | Sn_TTL(n) Sn_TTLR(n) |
| | For compatible ioLibrary. Refer to Sn_TTLR. More...
|
| |
| #define | Sn_TX_WRSR(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x20) |
| | SOCKETn TX write size register(R/W) More...
|
| |
| #define | Sn_TX_FSR(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x0024) |
| | Transmit free memory size register(R) More...
|
| |
| #define | Sn_RX_RSR(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x0028) |
| | Received data size register(R) More...
|
| |
| #define | Sn_FRAGR(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x002C) |
| | Fragment field value in IP header register(R/W) More...
|
| |
| #define | Sn_FRAG(n) Sn_FRAGR(n) |
| |
| #define | Sn_TX_FIFOR(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x2E) |
| | SOCKET n TX FIFO regsiter. More...
|
| |
| #define | Sn_RX_FIFOR(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x30) |
| | SOCKET n RX FIFO register. More...
|
| |
| #define | MR_DBW (1 << 15) |
| |
| #define | MR_MPF (1 << 14) |
| |
| #define | MR_WDF(X) ((X & 0x07) << 11) |
| |
| #define | MR_RDH (1 << 10) |
| |
| #define | MR_FS (1 << 8) |
| |
| #define | MR_RST (1 << 7) |
| |
| #define | MR_MT (1 << 5) |
| |
| #define | MR_PB (1 << 4) |
| |
| #define | MR_PPPoE (1 << 3) |
| |
| #define | MR_DBS (1 << 2) |
| |
| #define | MR_IND (1 << 0) |
| |
| #define | IR_IPCF (1 << 15) |
| |
| #define | IR_DPUR (1 << 14) |
| |
| #define | IR_PPPT (1 << 13) |
| |
| #define | IR_FMTU (1 << 12) |
| |
| #define | IR_SnINT(n) (0x01 << n) |
| |
| #define | Pn_PEN (1 << 7) |
| |
| #define | Pn_MT (1 << 6) |
| |
| #define | Pn_PPL (1 << 5) |
| |
| #define | Pn_SN(n) ((n & 0x07) << 0) |
| |
| #define | Sn_MR_ALIGN (1 << 8) |
| | Alignment bit of Sn_MR. More...
|
| |
| #define | Sn_MR_MULTI (1 << 7) |
| | Multicasting bit of Sn_MR. More...
|
| |
| #define | Sn_MR_MF (1 << 6) |
| | MAC filter bit of Sn_MR. More...
|
| |
| #define | Sn_MR_IGMPv (1 << 5) |
| | IGMP version bit of Sn_MR details It is valid in case of Sn_MR_MULTI='1' and UDP(Sn_MR_UDP). It configures IGMP version to send IGMP message such as Join/Leave/Report to multicast-group.
0 : IGMPv2, 1 : IGMPv1. More...
|
| |
| #define | Sn_MR_MC Sn_MR_IGMPv |
| | For compatible ioLibrary. More...
|
| |
| #define | Sn_MR_ND (1 << 5) |
| | No delayed ack bit of Sn_MR. More...
|
| |
| #define | Sn_MR_CLOSE 0x00 |
| | No mode. More...
|
| |
| #define | Sn_MR_TCP 0x01 |
| | TCP mode. More...
|
| |
| #define | Sn_MR_UDP 0x02 |
| | UDP mode. More...
|
| |
| #define | Sn_MR_IPRAW 0x03 |
| | IP LAYER RAW mode. More...
|
| |
| #define | Sn_MR_MACRAW 0x04 |
| | MAC LAYER RAW mode. More...
|
| |
| #define | Sn_MR_PPPoE 0x05 |
| | PPPoE mode. More...
|
| |
| #define | SOCK_STREAM Sn_MR_TCP |
| |
| #define | SOCK_DGRAM Sn_MR_UDP |
| |
| #define | Sn_CR_OPEN 0x01 |
| | Initialize or open a socket. More...
|
| |
| #define | Sn_CR_LISTEN 0x02 |
| | Wait connection request in TCP mode(Server mode) More...
|
| |
| #define | Sn_CR_CONNECT 0x04 |
| | Send connection request in TCP mode(Client mode) More...
|
| |
| #define | Sn_CR_DISCON 0x08 |
| | Send closing request in TCP mode. More...
|
| |
| #define | Sn_CR_CLOSE 0x10 |
| | Close socket. More...
|
| |
| #define | Sn_CR_SEND 0x20 |
| | Update TX buffer pointer and send data. More...
|
| |
| #define | Sn_CR_SEND_MAC 0x21 |
| | Send data with MAC address, so without ARP process. More...
|
| |
| #define | Sn_CR_SEND_KEEP 0x22 |
| | Send keep alive message. More...
|
| |
| #define | Sn_CR_RECV 0x40 |
| | Update RX buffer pointer and receive data. More...
|
| |
| #define | Sn_CR_PCON 0x23 |
| |
| #define | Sn_CR_PDISCON 0x24 |
| |
| #define | Sn_CR_PCR 0x25 |
| |
| #define | Sn_CR_PCN 0x26 |
| |
| #define | Sn_CR_PCJ 0x27 |
| |
| #define | Sn_IR_PRECV 0x80 |
| |
| #define | Sn_IR_PFAIL 0x40 |
| |
| #define | Sn_IR_PNEXT 0x20 |
| |
| #define | Sn_IR_SENDOK 0x10 |
| |
| #define | Sn_IR_TIMEOUT 0x08 |
| |
| #define | Sn_IR_RECV 0x04 |
| |
| #define | Sn_IR_DISCON 0x02 |
| |
| #define | Sn_IR_CON 0x01 |
| |
| #define | SOCK_CLOSED 0x00 |
| | The state of SOCKET intialized or closed. More...
|
| |
| #define | SOCK_ARP 0x01 |
| | The state of ARP process. More...
|
| |
| #define | SOCK_INIT 0x13 |
| | Initiate state in TCP. More...
|
| |
| #define | SOCK_LISTEN 0x14 |
| | Listen state. More...
|
| |
| #define | SOCK_SYNSENT 0x15 |
| | Connection state. More...
|
| |
| #define | SOCK_SYNRECV 0x16 |
| | Connection state. More...
|
| |
| #define | SOCK_ESTABLISHED 0x17 |
| | Success to connect. More...
|
| |
| #define | SOCK_FIN_WAIT 0x18 |
| | Closing state. More...
|
| |
| #define | SOCK_CLOSING 0x1A |
| | Closing state. More...
|
| |
| #define | SOCK_TIME_WAIT 0x1B |
| | Closing state. More...
|
| |
| #define | SOCK_CLOSE_WAIT 0x1C |
| | Closing state. More...
|
| |
| #define | SOCK_LAST_ACK 0x1D |
| | Closing state. More...
|
| |
| #define | SOCK_UDP 0x22 |
| | UDP socket. More...
|
| |
| #define | SOCK_IPRAW 0x32 |
| | IP raw mode socket. More...
|
| |
| #define | SOCK_MACRAW 0x42 |
| | MAC raw mode socket. More...
|
| |
| #define | SOCK_PPPoE 0x5F |
| | PPPoE mode socket. More...
|
| |
| #define | IPPROTO_IP 0 |
| |
| #define | IPPROTO_ICMP 1 |
| |
| #define | IPPROTO_IGMP 2 |
| |
| #define | IPPROTO_GGP 3 |
| |
| #define | IPPROTO_TCP 6 |
| |
| #define | IPPROTO_PUP 12 |
| |
| #define | IPPROTO_UDP 17 |
| |
| #define | IPPROTO_IDP 22 |
| |
| #define | IPPROTO_ND 77 |
| |
| #define | IPPROTO_RAW 255 |
| |
| #define | WIZCHIP_CRITICAL_ENTER() WIZCHIP.CRIS._enter() |
| | Enter a critical section. More...
|
| |
| #define | WIZCHIP_CRITICAL_EXIT() WIZCHIP.CRIS._exit() |
| | Exit a critical section. More...
|
| |
| #define | setIR(ir) WIZCHIP_WRITE(IR, ir & 0xF0FF) |
| | Set Mode Register. More...
|
| |
| #define | getIR() (WIZCHIP_READ(IR) & 0xF0FF) |
| | Get IR register. More...
|
| |
| #define | setIMR(imr) WIZCHIP_WRITE(_IMR_, imr & 0xF0FF) |
| | Set IMR register. More...
|
| |
| #define | getIMR() (WIZCHIP_READ(_IMR_) & 0xF0FF) |
| | Get IMR register. More...
|
| |
| #define | setSHAR(shar) |
| | Set local MAC address. More...
|
| |
| #define | getSHAR(shar) |
| | Get local MAC address. More...
|
| |
| #define | setGAR(gar) |
| | Set gateway IP address. More...
|
| |
| #define | getGAR(gar) |
| | Get gateway IP address. More...
|
| |
| #define | setSUBR(subr) |
| | Set subnet mask address. More...
|
| |
| #define | getSUBR(subr) |
| | Get subnet mask address. More...
|
| |
| #define | setSIPR(sipr) |
| | Set local IP address. More...
|
| |
| #define | getSIPR(sipr) |
| | Get local IP address. More...
|
| |
| #define | setRTR(rtr) WIZCHIP_WRITE(_RTR_, rtr) |
| | Set RTR register. More...
|
| |
| #define | getRTR() WIZCHIP_READ(_RTR_) |
| | Get RTR register. More...
|
| |
| #define | setRCR(rcr) WIZCHIP_WRITE(_RCR_, ((uint16_t)rcr)&0x00FF) |
| | Set RCR register. More...
|
| |
| #define | getRCR() ((uint8_t)(WIZCHIP_READ(_RCR_) & 0x00FF)) |
| | Get RCR register. More...
|
| |
| #define | setTMS01R(tms01r) WIZCHIP_WRITE(TMS01R,tms01r) |
| | Set TMS01R register. More...
|
| |
| #define | getTMS01R() WIZCHIP_READ(TMS01R) |
| | Get TMS01R register. More...
|
| |
| #define | setTMS23R(tms23r) WIZCHIP_WRITE(TMS23R,tms23r) |
| | Set TMS23R register. More...
|
| |
| #define | getTMS23R() WIZCHIP_READ(TMS23R) |
| | Get TMS23R register. More...
|
| |
| #define | setTMS45R(tms45r) WIZCHIP_WRITE(TMS45R,tms45r) |
| | Set TMS45R register. More...
|
| |
| #define | getTMS45R() WIZCHIP_READ(TMS45R) |
| | Get TMS45R register. More...
|
| |
| #define | setTMS67R(tms67r) WIZCHIP_WRITE(TMS67R,tms67r) |
| | Set TMS67R register. More...
|
| |
| #define | getTMS67R() WIZCHIP_READ(TMS67R) |
| | Get TMS67R register. More...
|
| |
| #define | setSn_TXBUF_SIZE(sn, tmsr) setTMSR(sn, tmsr) |
| | For compatible ioLibrary. More...
|
| |
| #define | getSn_TXBUF_SIZE(sn) getTMSR(sn) |
| | For compatible ioLibrary. More...
|
| |
| #define | setRMS01R(rms01r) WIZCHIP_WRITE(RMS01R,rms01r) |
| | Set RMS01R register. More...
|
| |
| #define | getRMS01R() WIZCHIP_READ(RMS01R) |
| | Get RMS01R register. More...
|
| |
| #define | setRMS23R(rms23r) WIZCHIP_WRITE(RMS23R,rms23r) |
| | Set RMS23R register. More...
|
| |
| #define | getRMS23R() WIZCHIP_READ(RMS23R) |
| | Get RMS23R register. More...
|
| |
| #define | setRMS45R(rms45r) WIZCHIP_WRITE(RMS45R,rms45r) |
| | Set RMS45R register. More...
|
| |
| #define | getRMS45R() WIZCHIP_READ(RMS45R) |
| | Get RMS45R register. More...
|
| |
| #define | setRMS67R(rms67r) WIZCHIP_WRITE(RMS67R,rms67r) |
| | Set RMS67R register. More...
|
| |
| #define | getRMS67R() WIZCHIP_READ(RMS67R) |
| | Get RMS67R register. More...
|
| |
| #define | setSn_RXBUF_SIZE(sn, rmsr) setRMSR(sn, rmsr) |
| | For compatible ioLibrary. More...
|
| |
| #define | getSn_RXBUF_SIZE(sn) getRMSR(sn) |
| | For compatible ioLibrary. More...
|
| |
| #define | setMTYPER(mtype) WIZCHIP_WRITE(MTYPER, mtype) |
| | Set MTYPER register. More...
|
| |
| #define | getMTYPER() WIZCHIP_READ(MTYPER) |
| | Get MTYPER register. More...
|
| |
| #define | getPATR() WIZCHIP_READ(PATR) |
| | Get RATR register. More...
|
| |
| #define | setPTIMER(ptimer) WIZCHIP_WRITE(PTIMER, ((uint16_t)ptimer) & 0x00FF) |
| | Set PTIMER register. More...
|
| |
| #define | getPTIMER() ((uint8_t)(WIZCHIP_READ(PTIMER) & 0x00FF)) |
| | Get PTIMER register. More...
|
| |
| #define | setPMAGIC(pmagic) WIZCHIP_WRITE(PMAGIC, ((uint16_t)pmagic) & 0x00FF) |
| | Set PMAGIC register. More...
|
| |
| #define | getPMAGIC() ((uint8_t)(WIZCHIP_READ(PMAGIC) & 0x00FF)) |
| | Get PMAGIC register. More...
|
| |
| #define | getPSIDR() WIZCHIP_READ(PSIDR) |
| | Get PSID register. More...
|
| |
| #define | getPDHAR(pdhar) |
| | Get PDHAR register. More...
|
| |
| #define | getUIPR(uipr) |
| | Get unreachable IP address. UIPR. More...
|
| |
| #define | getUPORTR() WIZCHIP_READ(UPORTR) |
| | Get UPORTR register. More...
|
| |
| #define | getFMTUR() WIZCHIP_READ(FMTUR) |
| | Get FMTUR register. More...
|
| |
| #define | getPn_BRDYR(p) ((uint8_t)(WIZCHIP_READ(Pn_BRDYR(p)) & 0x00FF)) |
| | Get Pn_BRDYR register. More...
|
| |
| #define | setPn_BRDYR(p, brdyr) WIZCHIP_WRITE(Pn_BRDYR(p), brdyr & 0x00E7) |
| | Set Pn_BRDYR register. More...
|
| |
| #define | getPn_BDPTHR(p) WIZCHIP_READ(Pn_BDPTHR(p)) |
| | Get Pn_BDPTHR register. More...
|
| |
| #define | setPn_BDPTHR(p, bdpthr) WIZCHIP_WRITE(Pn_BDPTHR(p),bdpthr) |
| | Set Pn_BDPTHR register. More...
|
| |
| #define | getIDR() WIZCHIP_READ(IDR) |
| | Get IDR register. More...
|
| |
| #define | setSn_MR(sn, mr) WIZCHIP_WRITE(Sn_MR(sn),mr) |
| | Set Sn_MR register. More...
|
| |
| #define | getSn_MR(sn) WIZCHIP_READ(Sn_MR(sn)) |
| | Get Sn_MR register. More...
|
| |
| #define | setSn_CR(sn, cr) WIZCHIP_WRITE(Sn_CR(sn), ((uint16_t)cr) & 0x00FF) |
| | Set Sn_CR register. More...
|
| |
| #define | getSn_CR(sn) ((uint8_t)WIZCHIP_READ(Sn_CR(sn))) |
| | Get Sn_CR register. More...
|
| |
| #define | setSn_IMR(sn, imr) WIZCHIP_WRITE(Sn_IMR(sn), ((uint16_t)imr) & 0x00FF) |
| | Set Sn_IMR register. More...
|
| |
| #define | getSn_IMR(sn) ((uint8_t)WIZCHIP_READ(Sn_IMR(sn))) |
| | Get Sn_IMR register. More...
|
| |
| #define | setSn_IR(sn, ir) WIZCHIP_WRITE(Sn_IR(sn), ((uint16_t)ir) & 0x00FF) |
| | Set Sn_IR register. More...
|
| |
| #define | getSn_IR(sn) ((uint8_t)WIZCHIP_READ(Sn_IR(sn))) |
| | Get Sn_IR register. More...
|
| |
| #define | getSn_SSR(sn) ((uint8_t)WIZCHIP_READ(Sn_SR(sn))) |
| | Get Sn_SR register. More...
|
| |
| #define | getSn_SR(sn) getSn_SSR(sn) |
| | For compatible ioLibrary. Refer to getSn_SSR(). More...
|
| |
| #define | setSn_PORTR(sn, port) WIZCHIP_WRITE(Sn_PORTR(sn), port) |
| | Set Sn_PORTR register. More...
|
| |
| #define | setSn_PORT(sn, port) setSn_PORTR(sn, port) |
| | For compatible ioLibrary. More...
|
| |
| #define | getSn_PORTR(sn, port) WIZCHIP_READ(Sn_PORTR(sn)) |
| | Get Sn_PORTR register. More...
|
| |
| #define | getSn_PORT(sn) getSn_PORTR(sn) |
| | For compatible ioLibrary. More...
|
| |
| #define | setSn_DHAR(sn, dhar) |
| | Set Sn_DHAR register. More...
|
| |
| #define | getSn_DHAR(sn, dhar) |
| | Get Sn_MR register. More...
|
| |
| #define | setSn_DPORTR(sn, dport) WIZCHIP_WRITE(Sn_DPORTR(sn),dport) |
| | Set Sn_DPORT register. More...
|
| |
| #define | setSn_DPORT(sn, dport) setSn_DPORTR(sn,dport) |
| | For compatible ioLibrary. Refer to Sn_DPORTR. More...
|
| |
| #define | getSn_DPORTR(sn) WIZCHIP_READ(Sn_DPORTR(sn)) |
| | Get Sn_DPORT register. More...
|
| |
| #define | getSn_DPORT(sn) getSn_DPORTR(sn) |
| | For compatible ioLibrary. Refer to Sn_DPORTR. More...
|
| |
| #define | setSn_DIPR(sn, dipr) |
| | Set Sn_DIPR register. More...
|
| |
| #define | getSn_DIPR(sn, dipr) |
| | Get Sn_DIPR register. More...
|
| |
| #define | setSn_MSSR(sn, mss) WIZCHIP_WRITE(Sn_MSSR(sn), mss) |
| | Set Sn_MSSR register. More...
|
| |
| #define | getSn_MSSR(sn) WIZCHIP_READ(Sn_MSSR(sn)) |
| | Get Sn_MSSR register. More...
|
| |
| #define | setSn_KPALVTR(sn, kpalvt) WIZCHIP_WRITE(Sn_KPALVTR(sn), (WIZCHIP_READ(Sn_KPALVTR(sn)) & 0x00FF) | (((uint16_t)kpalvt)<<8)) |
| | Set Sn_KPALVTR register. More...
|
| |
| #define | getSn_KPALVTR(sn) ((uint8_t)(WIZCHIP_READ(Sn_KPALVTR(sn)) >> 8)) |
| | Get Sn_KPALVTR register. More...
|
| |
| #define | setSn_PROTOR(sn, proto) WIZCHIP_WRITE(Sn_PROTOR(sn),(WIZCHIP_READ(Sn_PROTOR(sn) & 0xFF00) | (((uint16_t)proto) & 0x00FF)) |
| | Set Sn_PROTOR register. More...
|
| |
| #define | setSn_PROTO(sn, proto) setSn_PROTOR(sn,proto) |
| | For compatible ioLibrary. More...
|
| |
| #define | getSn_PROTOR(sn) ((uint8_t)WIZCHIP_READ(Sn_PROTOR(sn))) |
| | Get Sn_PROTOR register. More...
|
| |
| #define | getSn_PROTO(sn) getSn_PROTOR(sn) |
| | For compatible ioLibrary. More...
|
| |
| #define | setSn_TX_WRSR(sn, txwrs) |
| | Set Sn_TX_WRSR register. More...
|
| |
| #define | getSn_TX_WRSR(sn) ( (((uint32_t)WIZCHIP_READ(Sn_TX_WRSR(sn))) << 16) + (((uint32_t)WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_WRSR(sn),1))) & 0x0000FFFF) ) |
| | Get Sn_TX_WRSR register. More...
|
| |
| #define | setSn_TX_FIFOR(sn, txfifo) WIZCHIP_WRITE(Sn_TX_FIFOR(sn), txfifo); |
| | Set Sn_TX_FIFOR register. More...
|
| |
| #define | getSn_RX_FIFOR(sn) WIZCHIP_READ(Sn_RX_FIFOR(sn)); |
| | Get Sn_RX_FIFOR register. More...
|
| |
| #define | setSn_TOSR(sn, tos) WIZCHIP_WRITE(Sn_TOS(sn), ((uint16_t)tos) & 0x00FF) |
| | Set Sn_TOSR register. More...
|
| |
| #define | setSn_TOS(sn, tos) setSn_TOSR(sn,tos) |
| | For compatible ioLibrar. More...
|
| |
| #define | getSn_TOSR(sn) ((uint8_t)WIZCHIP_READ(Sn_TOSR(sn))) |
| | Get Sn_TOSR register. More...
|
| |
| #define | getSn_TOS(sn) getSn_TOSR(sn) |
| | For compatible ioLibrar. More...
|
| |
| #define | setSn_TTLR(sn, ttl) WIZCHIP_WRITE(Sn_TTLR(sn), ((uint16_t)ttl) & 0x00FF) |
| | Set Sn_TTLR register. More...
|
| |
| #define | setSn_TTL(sn, ttl) setSn_TTLR(sn,ttl) |
| | For compatible ioLibrary. More...
|
| |
| #define | getSn_TTLR(sn) ((uint8_t)WIZCHIP_READ(Sn_TTL(sn))) |
| | Get Sn_TTLR register. More...
|
| |
| #define | getSn_TTL(sn) getSn_TTLR(sn) |
| | For compatible ioLibrary. More...
|
| |
| #define | setSn_FRAGR(sn, frag) WIZCHIP_WRITE(Sn_FRAGR(sn), (uint16_t)(frag >>8)) |
| | Set Sn_FRAGR register. More...
|
| |
| #define | setSn_FRAG(sn, frag) setSn_FRAGR(sn,flag) |
| |
| #define | getSn_FRAGR(sn) (WIZCHIP_READ(Sn_FRAG(sn)) << 8) |
| | Get Sn_FRAGR register. More...
|
| |
| #define | getSn_FRAG(sn) getSn_FRAGR(sn) |
| |
| #define | getSn_RxMAX(sn) (((uint32_t)getSn_RXBUF_SIZE(sn)) << 10) |
| | Socket_register_access_function_W5300. More...
|
| |
| #define | getSn_TxMAX(sn) (((uint32_t)getSn_TXBUF_SIZE(sn)) << 10) |
| | Socket_register_access_function_W5300. More...
|
| |