Socket APIs: Ethernet/W5500/w5500.h File Reference

Wiznet Socket API

w5500.h File Reference

W5500 HAL Header File. More...

#include <stdint.h> #include "wizchip_conf.h"

Go to the source code of this file.

Macros

#define _W5500_IO_BASE_   0x00000000
 
#define _W5500_SPI_READ_   (0x00 << 2)
 
#define _W5500_SPI_WRITE_   (0x01 << 2)
 
#define WIZCHIP_CREG_BLOCK   0x00
 
#define WIZCHIP_SREG_BLOCK(N)   (1+4*N)
 
#define WIZCHIP_TXBUF_BLOCK(N)   (2+4*N)
 
#define WIZCHIP_RXBUF_BLOCK(N)   (3+4*N)
 
#define WIZCHIP_OFFSET_INC(ADDR, N)   (ADDR + (N<<8))
 
#define IINCHIP_READ(ADDR)   WIZCHIP_READ(ADDR)
 The defined for legacy chip driver. More...
 
#define IINCHIP_WRITE(ADDR, VAL)   WIZCHIP_WRITE(ADDR,VAL)
 The defined for legacy chip driver. More...
 
#define IINCHIP_READ_BUF(ADDR, BUF, LEN)   WIZCHIP_READ_BUF(ADDR,BUF,LEN)
 The defined for legacy chip driver. More...
 
#define IINCHIP_WRITE_BUF(ADDR, BUF, LEN)   WIZCHIP_WRITE(ADDR,BUF,LEN)
 The defined for legacy chip driver. More...
 
#define MR   (_W5500_IO_BASE_ + (0x0000 << 8) + (WIZCHIP_CREG_BLOCK << 3))
 Mode Register address(R/W)
MR is used for S/W reset, ping block mode, PPPoE mode and etc. More...
 
#define GAR   (_W5500_IO_BASE_ + (0x0001 << 8) + (WIZCHIP_CREG_BLOCK << 3))
 Gateway IP Register address(R/W) More...
 
#define SUBR   (_W5500_IO_BASE_ + (0x0005 << 8) + (WIZCHIP_CREG_BLOCK << 3))
 Subnet mask Register address(R/W) More...
 
#define SHAR   (_W5500_IO_BASE_ + (0x0009 << 8) + (WIZCHIP_CREG_BLOCK << 3))
 Source MAC Register address(R/W) More...
 
#define SIPR   (_W5500_IO_BASE_ + (0x000F << 8) + (WIZCHIP_CREG_BLOCK << 3))
 Source IP Register address(R/W) More...
 
#define INTLEVEL   (_W5500_IO_BASE_ + (0x0013 << 8) + (WIZCHIP_CREG_BLOCK << 3))
 Set Interrupt low level timer register address(R/W) More...
 
#define IR   (_W5500_IO_BASE_ + (0x0015 << 8) + (WIZCHIP_CREG_BLOCK << 3))
 Interrupt Register(R/W) More...
 
#define _IMR_   (_W5500_IO_BASE_ + (0x0016 << 8) + (WIZCHIP_CREG_BLOCK << 3))
 Interrupt mask register(R/W) More...
 
#define SIR   (_W5500_IO_BASE_ + (0x0017 << 8) + (WIZCHIP_CREG_BLOCK << 3))
 Socket Interrupt Register(R/W) More...
 
#define SIMR   (_W5500_IO_BASE_ + (0x0018 << 8) + (WIZCHIP_CREG_BLOCK << 3))
 Socket Interrupt Mask Register(R/W) More...
 
#define _RTR_   (_W5500_IO_BASE_ + (0x0019 << 8) + (WIZCHIP_CREG_BLOCK << 3))
 Timeout register address( 1 is 100us )(R/W) More...
 
#define _RCR_   (_W5500_IO_BASE_ + (0x001B << 8) + (WIZCHIP_CREG_BLOCK << 3))
 Retry count register(R/W) More...
 
#define PTIMER   (_W5500_IO_BASE_ + (0x001C << 8) + (WIZCHIP_CREG_BLOCK << 3))
 PPP LCP Request Timer register in PPPoE mode(R/W) More...
 
#define PMAGIC   (_W5500_IO_BASE_ + (0x001D << 8) + (WIZCHIP_CREG_BLOCK << 3))
 PPP LCP Magic number register in PPPoE mode(R/W) More...
 
#define PHAR   (_W5500_IO_BASE_ + (0x001E << 8) + (WIZCHIP_CREG_BLOCK << 3))
 PPP Destination MAC Register address(R/W) More...
 
#define PSID   (_W5500_IO_BASE_ + (0x0024 << 8) + (WIZCHIP_CREG_BLOCK << 3))
 PPP Session Identification Register(R/W) More...
 
#define PMRU   (_W5500_IO_BASE_ + (0x0026 << 8) + (WIZCHIP_CREG_BLOCK << 3))
 PPP Maximum Segment Size(MSS) register(R/W) More...
 
#define UIPR   (_W5500_IO_BASE_ + (0x0028 << 8) + (WIZCHIP_CREG_BLOCK << 3))
 Unreachable IP register address in UDP mode(R) More...
 
#define UPORTR   (_W5500_IO_BASE_ + (0x002C << 8) + (WIZCHIP_CREG_BLOCK << 3))
 Unreachable Port register address in UDP mode(R) More...
 
#define PHYCFGR   (_W5500_IO_BASE_ + (0x002E << 8) + (WIZCHIP_CREG_BLOCK << 3))
 PHY Status Register(R/W) More...
 
#define VERSIONR   (_W5500_IO_BASE_ + (0x0039 << 8) + (WIZCHIP_CREG_BLOCK << 3))
 chip version register address(R) More...
 
#define Sn_MR(N)   (_W5500_IO_BASE_ + (0x0000 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
 socket Mode register(R/W) More...
 
#define Sn_CR(N)   (_W5500_IO_BASE_ + (0x0001 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
 Socket command register(R/W) More...
 
#define Sn_IR(N)   (_W5500_IO_BASE_ + (0x0002 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
 Socket interrupt register(R) More...
 
#define Sn_SR(N)   (_W5500_IO_BASE_ + (0x0003 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
 Socket status register(R) More...
 
#define Sn_PORT(N)   (_W5500_IO_BASE_ + (0x0004 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
 source port register(R/W) More...
 
#define Sn_DHAR(N)   (_W5500_IO_BASE_ + (0x0006 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
 Peer MAC register address(R/W) More...
 
#define Sn_DIPR(N)   (_W5500_IO_BASE_ + (0x000C << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
 Peer IP register address(R/W) More...
 
#define Sn_DPORT(N)   (_W5500_IO_BASE_ + (0x0010 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
 Peer port register address(R/W) More...
 
#define Sn_MSSR(N)   (_W5500_IO_BASE_ + (0x0012 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
 Maximum Segment Size(Sn_MSSR0) register address(R/W) More...
 
#define Sn_TOS(N)   (_W5500_IO_BASE_ + (0x0015 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
 IP Type of Service(TOS) Register(R/W) More...
 
#define Sn_TTL(N)   (_W5500_IO_BASE_ + (0x0016 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
 IP Time to live(TTL) Register(R/W) More...
 
#define Sn_RXBUF_SIZE(N)   (_W5500_IO_BASE_ + (0x001E << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
 Receive memory size register(R/W) More...
 
#define Sn_TXBUF_SIZE(N)   (_W5500_IO_BASE_ + (0x001F << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
 Transmit memory size register(R/W) More...
 
#define Sn_TX_FSR(N)   (_W5500_IO_BASE_ + (0x0020 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
 Transmit free memory size register(R) More...
 
#define Sn_TX_RD(N)   (_W5500_IO_BASE_ + (0x0022 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
 Transmit memory read pointer register address(R) More...
 
#define Sn_TX_WR(N)   (_W5500_IO_BASE_ + (0x0024 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
 Transmit memory write pointer register address(R/W) More...
 
#define Sn_RX_RSR(N)   (_W5500_IO_BASE_ + (0x0026 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
 Received data size register(R) More...
 
#define Sn_RX_RD(N)   (_W5500_IO_BASE_ + (0x0028 << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
 Read point of Receive memory(R/W) More...
 
#define Sn_RX_WR(N)   (_W5500_IO_BASE_ + (0x002A << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
 Write point of Receive memory(R) More...
 
#define Sn_IMR(N)   (_W5500_IO_BASE_ + (0x002C << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
 socket interrupt mask register(R) More...
 
#define Sn_FRAG(N)   (_W5500_IO_BASE_ + (0x002D << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
 Fragment field value in IP header register(R/W) More...
 
#define Sn_KPALVTR(N)   (_W5500_IO_BASE_ + (0x002F << 8) + (WIZCHIP_SREG_BLOCK(N) << 3))
 Keep Alive Timer register(R/W) More...
 
#define MR_RST   0x80
 Reset. More...
 
#define MR_WOL   0x20
 Wake on LAN. More...
 
#define MR_PB   0x10
 Ping block. More...
 
#define MR_PPPOE   0x08
 Enable PPPoE. More...
 
#define MR_FARP   0x02
 Enable UDP_FORCE_ARP CHECHK. More...
 
#define IR_CONFLICT   0x80
 Check IP conflict. More...
 
#define IR_UNREACH   0x40
 Get the destination unreachable message in UDP sending. More...
 
#define IR_PPPoE   0x20
 Get the PPPoE close message. More...
 
#define IR_MP   0x10
 Get the magic packet interrupt. More...
 
#define PHYCFGR_RST   ~(1<<7)
 
#define PHYCFGR_OPMD   (1<<6)
 
#define PHYCFGR_OPMDC_ALLA   (7<<3)
 
#define PHYCFGR_OPMDC_PDOWN   (6<<3)
 
#define PHYCFGR_OPMDC_NA   (5<<3)
 
#define PHYCFGR_OPMDC_100FA   (4<<3)
 
#define PHYCFGR_OPMDC_100F   (3<<3)
 
#define PHYCFGR_OPMDC_100H   (2<<3)
 
#define PHYCFGR_OPMDC_10F   (1<<3)
 
#define PHYCFGR_OPMDC_10H   (0<<3)
 
#define PHYCFGR_DPX_FULL   (1<<2)
 
#define PHYCFGR_DPX_HALF   (0<<2)
 
#define PHYCFGR_SPD_100   (1<<1)
 
#define PHYCFGR_SPD_10   (0<<1)
 
#define PHYCFGR_LNK_ON   (1<<0)
 
#define PHYCFGR_LNK_OFF   (0<<0)
 
#define IM_IR7   0x80
 IP Conflict Interrupt Mask. More...
 
#define IM_IR6   0x40
 Destination unreachable Interrupt Mask. More...
 
#define IM_IR5   0x20
 PPPoE Close Interrupt Mask. More...
 
#define IM_IR4   0x10
 Magic Packet Interrupt Mask. More...
 
#define Sn_MR_MULTI   0x80
 Support UDP Multicasting. More...
 
#define Sn_MR_BCASTB   0x40
 Broadcast block in UDP Multicasting. More...
 
#define Sn_MR_ND   0x20
 No Delayed Ack(TCP), Multicast flag. More...
 
#define Sn_MR_UCASTB   0x10
 Unicast Block in UDP Multicasting. More...
 
#define Sn_MR_MACRAW   0x04
 MAC LAYER RAW SOCK. More...
 
#define Sn_MR_UDP   0x02
 UDP. More...
 
#define Sn_MR_TCP   0x01
 TCP. More...
 
#define Sn_MR_CLOSE   0x00
 Unused socket. More...
 
#define Sn_MR_MFEN   Sn_MR_MULTI
 MAC filter enable in Sn_MR_MACRAW mode. More...
 
#define Sn_MR_MMB   Sn_MR_ND
 Multicast Blocking in Sn_MR_MACRAW mode. More...
 
#define Sn_MR_MIP6B   Sn_MR_UCASTB
 IPv6 packet Blocking in Sn_MR_MACRAW mode. More...
 
#define Sn_MR_MC   Sn_MR_ND
 IGMP version used in UDP mulitcasting. More...
 
#define SOCK_STREAM   Sn_MR_TCP
 For Berkeley Socket API. More...
 
#define SOCK_DGRAM   Sn_MR_UDP
 For Berkeley Socket API. More...
 
#define Sn_CR_OPEN   0x01
 Initialize or open socket. More...
 
#define Sn_CR_LISTEN   0x02
 Wait connection request in TCP mode(Server mode) More...
 
#define Sn_CR_CONNECT   0x04
 Send connection request in TCP mode(Client mode) More...
 
#define Sn_CR_DISCON   0x08
 Send closing request in TCP mode. More...
 
#define Sn_CR_CLOSE   0x10
 Close socket. More...
 
#define Sn_CR_SEND   0x20
 Update TX buffer pointer and send data. More...
 
#define Sn_CR_SEND_MAC   0x21
 Send data with MAC address, so without ARP process. More...
 
#define Sn_CR_SEND_KEEP   0x22
 Send keep alive message. More...
 
#define Sn_CR_RECV   0x40
 Update RX buffer pointer and receive data. More...
 
#define Sn_IR_SENDOK   0x10
 SEND_OK Interrupt. More...
 
#define Sn_IR_TIMEOUT   0x08
 TIMEOUT Interrupt. More...
 
#define Sn_IR_RECV   0x04
 RECV Interrupt. More...
 
#define Sn_IR_DISCON   0x02
 DISCON Interrupt. More...
 
#define Sn_IR_CON   0x01
 CON Interrupt. More...
 
#define SOCK_CLOSED   0x00
 Closed. More...
 
#define SOCK_INIT   0x13
 Initiate state. More...
 
#define SOCK_LISTEN   0x14
 Listen state. More...
 
#define SOCK_SYNSENT   0x15
 Connection state. More...
 
#define SOCK_SYNRECV   0x16
 Connection state. More...
 
#define SOCK_ESTABLISHED   0x17
 Success to connect. More...
 
#define SOCK_FIN_WAIT   0x18
 Closing state. More...
 
#define SOCK_CLOSING   0x1A
 Closing state. More...
 
#define SOCK_TIME_WAIT   0x1B
 Closing state. More...
 
#define SOCK_CLOSE_WAIT   0x1C
 Closing state. More...
 
#define SOCK_LAST_ACK   0x1D
 Closing state. More...
 
#define SOCK_UDP   0x22
 UDP socket. More...
 
#define SOCK_MACRAW   0x42
 MAC raw mode socket. More...
 
#define IPPROTO_IP   0
 
#define IPPROTO_ICMP   1
 
#define IPPROTO_IGMP   2
 
#define IPPROTO_GGP   3
 
#define IPPROTO_TCP   6
 
#define IPPROTO_PUP   12
 
#define IPPROTO_UDP   17
 
#define IPPROTO_IDP   22
 
#define IPPROTO_ND   77
 
#define IPPROTO_RAW   255
 
#define WIZCHIP_CRITICAL_ENTER()   WIZCHIP.CRIS._enter()
 Enter a critical section. More...
 
#define WIZCHIP_CRITICAL_EXIT()   WIZCHIP.CRIS._exit()
 Exit a critical section. More...
 
#define setMR(mr)   WIZCHIP_WRITE(MR,mr)
 Set Mode Register. More...
 
#define getMR()   WIZCHIP_READ(MR)
 Get Mode Register. More...
 
#define setGAR(gar)   WIZCHIP_WRITE_BUF(GAR,gar,4)
 Set gateway IP address. More...
 
#define getGAR(gar)   WIZCHIP_READ_BUF(GAR,gar,4)
 Get gateway IP address. More...
 
#define setSUBR(subr)   WIZCHIP_WRITE_BUF(SUBR, subr,4)
 Set subnet mask address. More...
 
#define getSUBR(subr)   WIZCHIP_READ_BUF(SUBR, subr, 4)
 Get subnet mask address. More...
 
#define setSHAR(shar)   WIZCHIP_WRITE_BUF(SHAR, shar, 6)
 Set local MAC address. More...
 
#define getSHAR(shar)   WIZCHIP_READ_BUF(SHAR, shar, 6)
 Get local MAC address. More...
 
#define setSIPR(sipr)   WIZCHIP_WRITE_BUF(SIPR, sipr, 4)
 Set local IP address. More...
 
#define getSIPR(sipr)   WIZCHIP_READ_BUF(SIPR, sipr, 4)
 Get local IP address. More...
 
#define setINTLEVEL(intlevel)
 Set INTLEVEL register. More...
 
#define getINTLEVEL()   (((uint16_t)WIZCHIP_READ(INTLEVEL) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(INTLEVEL,1)))
 Get INTLEVEL register. More...
 
#define setIR(ir)   WIZCHIP_WRITE(IR, (ir & 0xF0))
 Set IR register. More...
 
#define getIR()   (WIZCHIP_READ(IR) & 0xF0)
 Get IR register. More...
 
#define setIMR(imr)   WIZCHIP_WRITE(_IMR_, imr)
 Set IMR register. More...
 
#define getIMR()   WIZCHIP_READ(_IMR_)
 Get IMR register. More...
 
#define setSIR(sir)   WIZCHIP_WRITE(SIR, sir)
 Set SIR register. More...
 
#define getSIR()   WIZCHIP_READ(SIR)
 Get SIR register. More...
 
#define setSIMR(simr)   WIZCHIP_WRITE(SIMR, simr)
 Set SIMR register. More...
 
#define getSIMR()   WIZCHIP_READ(SIMR)
 Get SIMR register. More...
 
#define setRTR(rtr)
 Set RTR register. More...
 
#define getRTR()   (((uint16_t)WIZCHIP_READ(_RTR_) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_RTR_,1)))
 Get RTR register. More...
 
#define setRCR(rcr)   WIZCHIP_WRITE(_RCR_, rcr)
 Set RCR register. More...
 
#define getRCR()   WIZCHIP_READ(_RCR_)
 Get RCR register. More...
 
#define setPTIMER(ptimer)   WIZCHIP_WRITE(PTIMER, ptimer)
 Set PTIMER register. More...
 
#define getPTIMER()   WIZCHIP_READ(PTIMER)
 Get PTIMER register. More...
 
#define setPMAGIC(pmagic)   WIZCHIP_WRITE(PMAGIC, pmagic)
 Set PMAGIC register. More...
 
#define getPMAGIC()   WIZCHIP_READ(PMAGIC)
 Get PMAGIC register. More...
 
#define setPHAR(phar)   WIZCHIP_WRITE_BUF(PHAR, phar, 6)
 Set PHAR address. More...
 
#define getPHAR(phar)   WIZCHIP_READ_BUF(PHAR, phar, 6)
 Get PHAR address. More...
 
#define setPSID(psid)
 Set PSID register. More...
 
#define getPSID()   (((uint16_t)WIZCHIP_READ(PSID) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(PSID,1)))
 Get PSID register. More...
 
#define setPMRU(pmru)
 Set PMRU register. More...
 
#define getPMRU()   (((uint16_t)WIZCHIP_READ(PMRU) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(PMRU,1)))
 Get PMRU register. More...
 
#define getUIPR(uipr)   WIZCHIP_READ_BUF(UIPR,uipr,4)
 Get unreachable IP address. More...
 
#define getUPORTR()   (((uint16_t)WIZCHIP_READ(UPORTR) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(UPORTR,1)))
 Get UPORTR register. More...
 
#define setPHYCFGR(phycfgr)   WIZCHIP_WRITE(PHYCFGR, phycfgr)
 Set PHYCFGR register. More...
 
#define getPHYCFGR()   WIZCHIP_READ(PHYCFGR)
 Get PHYCFGR register. More...
 
#define getVERSIONR()   WIZCHIP_READ(VERSIONR)
 Get VERSIONR register. More...
 
#define setSn_MR(sn, mr)   WIZCHIP_WRITE(Sn_MR(sn),mr)
 Set Sn_MR register. More...
 
#define getSn_MR(sn)   WIZCHIP_READ(Sn_MR(sn))
 Get Sn_MR register. More...
 
#define setSn_CR(sn, cr)   WIZCHIP_WRITE(Sn_CR(sn), cr)
 Set Sn_CR register. More...
 
#define getSn_CR(sn)   WIZCHIP_READ(Sn_CR(sn))
 Get Sn_CR register. More...
 
#define setSn_IR(sn, ir)   WIZCHIP_WRITE(Sn_IR(sn), (ir & 0x1F))
 Set Sn_IR register. More...
 
#define getSn_IR(sn)   (WIZCHIP_READ(Sn_IR(sn)) & 0x1F)
 Get Sn_IR register. More...
 
#define setSn_IMR(sn, imr)   WIZCHIP_WRITE(Sn_IMR(sn), (imr & 0x1F))
 Set Sn_IMR register. More...
 
#define getSn_IMR(sn)   (WIZCHIP_READ(Sn_IMR(sn)) & 0x1F)
 Get Sn_IMR register. More...
 
#define getSn_SR(sn)   WIZCHIP_READ(Sn_SR(sn))
 Get Sn_SR register. More...
 
#define setSn_PORT(sn, port)
 Set Sn_PORT register. More...
 
#define getSn_PORT(sn)   (((uint16_t)WIZCHIP_READ(Sn_PORT(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_PORT(sn),1)))
 Get Sn_PORT register. More...
 
#define setSn_DHAR(sn, dhar)   WIZCHIP_WRITE_BUF(Sn_DHAR(sn), dhar, 6)
 Set Sn_DHAR register. More...
 
#define getSn_DHAR(sn, dhar)   WIZCHIP_READ_BUF(Sn_DHAR(sn), dhar, 6)
 Get Sn_MR register. More...
 
#define setSn_DIPR(sn, dipr)   WIZCHIP_WRITE_BUF(Sn_DIPR(sn), dipr, 4)
 Set Sn_DIPR register. More...
 
#define getSn_DIPR(sn, dipr)   WIZCHIP_READ_BUF(Sn_DIPR(sn), dipr, 4)
 Get Sn_DIPR register. More...
 
#define setSn_DPORT(sn, dport)
 Set Sn_DPORT register. More...
 
#define getSn_DPORT(sn)   (((uint16_t)WIZCHIP_READ(Sn_DPORT(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_DPORT(sn),1)))
 Get Sn_DPORT register. More...
 
#define setSn_MSSR(sn, mss)
 Set Sn_MSSR register. More...
 
#define getSn_MSSR(sn)   (((uint16_t)WIZCHIP_READ(Sn_MSSR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_MSSR(sn),1)))
 Get Sn_MSSR register. More...
 
#define setSn_TOS(sn, tos)   WIZCHIP_WRITE(Sn_TOS(sn), tos)
 Set Sn_TOS register. More...
 
#define getSn_TOS(sn)   WIZCHIP_READ(Sn_TOS(sn))
 Get Sn_TOS register. More...
 
#define setSn_TTL(sn, ttl)   WIZCHIP_WRITE(Sn_TTL(sn), ttl)
 Set Sn_TTL register. More...
 
#define getSn_TTL(sn)   WIZCHIP_READ(Sn_TTL(sn))
 Get Sn_TTL register. More...
 
#define setSn_RXBUF_SIZE(sn, rxbufsize)   WIZCHIP_WRITE(Sn_RXBUF_SIZE(sn),rxbufsize)
 Set Sn_RXBUF_SIZE register. More...
 
#define getSn_RXBUF_SIZE(sn)   WIZCHIP_READ(Sn_RXBUF_SIZE(sn))
 Get Sn_RXBUF_SIZE register. More...
 
#define setSn_TXBUF_SIZE(sn, txbufsize)   WIZCHIP_WRITE(Sn_TXBUF_SIZE(sn), txbufsize)
 Set Sn_TXBUF_SIZE register. More...
 
#define getSn_TXBUF_SIZE(sn)   WIZCHIP_READ(Sn_TXBUF_SIZE(sn))
 Get Sn_TXBUF_SIZE register. More...
 
#define getSn_TX_RD(sn)   (((uint16_t)WIZCHIP_READ(Sn_TX_RD(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_RD(sn),1)))
 Get Sn_TX_RD register. More...
 
#define setSn_TX_WR(sn, txwr)
 Set Sn_TX_WR register. More...
 
#define getSn_TX_WR(sn)   (((uint16_t)WIZCHIP_READ(Sn_TX_WR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_WR(sn),1)))
 Get Sn_TX_WR register. More...
 
#define setSn_RX_RD(sn, rxrd)
 Set Sn_RX_RD register. More...
 
#define getSn_RX_RD(sn)   (((uint16_t)WIZCHIP_READ(Sn_RX_RD(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RX_RD(sn),1)))
 Get Sn_RX_RD register. More...
 
#define getSn_RX_WR(sn)   (((uint16_t)WIZCHIP_READ(Sn_RX_WR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RX_WR(sn),1)))
 Get Sn_RX_WR register. More...
 
#define setSn_FRAG(sn, frag)
 Set Sn_FRAG register. More...
 
#define getSn_FRAG(sn)   (((uint16_t)WIZCHIP_READ(Sn_FRAG(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_FRAG(sn),1)))
 Get Sn_FRAG register. More...
 
#define setSn_KPALVTR(sn, kpalvt)   WIZCHIP_WRITE(Sn_KPALVTR(sn), kpalvt)
 Set Sn_KPALVTR register. More...
 
#define getSn_KPALVTR(sn)   WIZCHIP_READ(Sn_KPALVTR(sn))
 Get Sn_KPALVTR register. More...
 
#define getSn_RxMAX(sn)   (((uint16_t)getSn_RXBUF_SIZE(sn)) << 10)
 Socket_register_access_function. More...
 
#define getSn_TxMAX(sn)   (((uint16_t)getSn_TXBUF_SIZE(sn)) << 10)
 Socket_register_access_function. More...
 

Functions

uint8_t WIZCHIP_READ (uint32_t AddrSel)
 It reads 1 byte value from a register. More...
 
void WIZCHIP_WRITE (uint32_t AddrSel, uint8_t wb)
 It writes 1 byte value to a register. More...
 
void WIZCHIP_READ_BUF (uint32_t AddrSel, uint8_t *pBuf, uint16_t len)
 It reads sequence data from registers. More...
 
void WIZCHIP_WRITE_BUF (uint32_t AddrSel, uint8_t *pBuf, uint16_t len)
 It writes sequence data to registers. More...
 
uint16_t getSn_TX_FSR (uint8_t sn)
 Get Sn_TX_FSR register. More...
 
uint16_t getSn_RX_RSR (uint8_t sn)
 Get Sn_RX_RSR register. More...
 
void wiz_send_data (uint8_t sn, uint8_t *wizdata, uint16_t len)
 It copies data to internal TX memory. More...
 
void wiz_recv_data (uint8_t sn, uint8_t *wizdata, uint16_t len)
 It copies data to your buffer from internal RX memory. More...
 
void wiz_recv_ignore (uint8_t sn, uint16_t len)
 It discard the received data in RX memory. More...
 

Detailed Description

W5500 HAL Header File.

Version
1.0.0
Date
2013/10/21
Revision history
<2015/02/05> Notice The version history is not updated after this point. Download the latest version directly from GitHub. Please visit the our GitHub repository for ioLibrary. >> https://github.com/Wiznet/ioLibrary_Driver <2013/10/21> 1st Release
Author
MidnightCow
Copyright

Copyright (c) 2013, WIZnet Co., LTD. All rights reserved.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

* Redistributions of source code must retain the above copyright 

notice, this list of conditions and the following disclaimer.

  • Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
  • Neither the name of the <ORGANIZATION> nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Definition in file w5500.h.

Macro Definition Documentation

#define _W5500_IO_BASE_   0x00000000

Definition at line 58 of file w5500.h.

#define _W5500_SPI_READ_   (0x00 << 2)

Definition at line 60 of file w5500.h.

#define _W5500_SPI_WRITE_   (0x01 << 2)

Definition at line 61 of file w5500.h.

#define WIZCHIP_CREG_BLOCK   0x00

Definition at line 63 of file w5500.h.

#define WIZCHIP_SREG_BLOCK (   N)    (1+4*N)

Definition at line 64 of file w5500.h.

#define WIZCHIP_TXBUF_BLOCK (   N)    (2+4*N)

Definition at line 65 of file w5500.h.

#define WIZCHIP_RXBUF_BLOCK (   N)    (3+4*N)

Definition at line 66 of file w5500.h.

#define WIZCHIP_OFFSET_INC (   ADDR,
 
)    (ADDR + (N<<8))

Definition at line 68 of file w5500.h.

#define IINCHIP_READ (   ADDR)    WIZCHIP_READ(ADDR)

The defined for legacy chip driver.

Definition at line 74 of file w5500.h.

#define IINCHIP_WRITE (   ADDR,
  VAL 
)    WIZCHIP_WRITE(ADDR,VAL)

The defined for legacy chip driver.

Definition at line 75 of file w5500.h.

#define IINCHIP_READ_BUF (   ADDR,
  BUF,
  LEN 
)    WIZCHIP_READ_BUF(ADDR,BUF,LEN)

The defined for legacy chip driver.

Definition at line 76 of file w5500.h.

#define IINCHIP_WRITE_BUF (   ADDR,
  BUF,
  LEN 
)    WIZCHIP_WRITE(ADDR,BUF,LEN)

The defined for legacy chip driver.

Definition at line 77 of file w5500.h.

#define MR_RST   0x80

Reset.

If this bit is All internal registers will be initialized. It will be automatically cleared as after S/W reset.

Definition at line 697 of file w5500.h.

#define MR_WOL   0x20

Wake on LAN.

0 : Disable WOL mode
1 : Enable WOL mode
If WOL mode is enabled and the received magic packet over UDP has been normally processed, the Interrupt PIN (INTn) asserts to low. When using WOL mode, the UDP Socket should be opened with any source port number. (Refer to Socket n Mode Register (Sn_MR) for opening Socket.)

Note
The magic packet over UDP supported by W5500 consists of 6 bytes synchronization stream (xFFFFFFFFFFFF and 16 times Target MAC address stream in UDP payload. The options such like password are ignored. You can use any UDP source port number for WOL mode.

Definition at line 708 of file w5500.h.

#define MR_PB   0x10

Ping block.

0 : Disable Ping block
1 : Enable Ping block
If the bit is it blocks the response to a ping request.

Definition at line 716 of file w5500.h.

#define MR_PPPOE   0x08

Enable PPPoE.

0 : DisablePPPoE mode
1 : EnablePPPoE mode
If you use ADSL, this bit should be

Definition at line 724 of file w5500.h.

#define MR_FARP   0x02

Enable UDP_FORCE_ARP CHECHK.

0 : Disable Force ARP mode
1 : Enable Force ARP mode
In Force ARP mode, It forces on sending ARP Request whenever data is sent.

Definition at line 732 of file w5500.h.

#define IR_CONFLICT   0x80

Check IP conflict.

Bit is set as when own source IP address is same with the sender IP address in the received ARP request.

Definition at line 739 of file w5500.h.

#define IR_UNREACH   0x40

Get the destination unreachable message in UDP sending.

When receiving the ICMP (Destination port unreachable) packet, this bit is set as When this bit is Destination Information such as IP address and Port number may be checked with the corresponding UIPR & UPORTR.

Definition at line 746 of file w5500.h.

#define IR_PPPoE   0x20

Get the PPPoE close message.

When PPPoE is disconnected during PPPoE mode, this bit is set.

Definition at line 752 of file w5500.h.

#define IR_MP   0x10

Get the magic packet interrupt.

When WOL mode is enabled and receives the magic packet over UDP, this bit is set.

Definition at line 758 of file w5500.h.

#define PHYCFGR_RST   ~(1<<7)

Definition at line 762 of file w5500.h.

Referenced by wizphy_reset().

#define PHYCFGR_OPMD   (1<<6)

Definition at line 763 of file w5500.h.

Referenced by wizphy_getphyconf(), wizphy_setphyconf(), and wizphy_setphypmode().

#define PHYCFGR_OPMDC_ALLA   (7<<3)

Definition at line 764 of file w5500.h.

Referenced by wizphy_getphyconf(), wizphy_setphyconf(), and wizphy_setphypmode().

#define PHYCFGR_OPMDC_PDOWN   (6<<3)

Definition at line 765 of file w5500.h.

Referenced by wizphy_getphypmode(), and wizphy_setphypmode().

#define PHYCFGR_OPMDC_NA   (5<<3)

Definition at line 766 of file w5500.h.

#define PHYCFGR_OPMDC_100FA   (4<<3)

Definition at line 767 of file w5500.h.

Referenced by wizphy_getphyconf().

#define PHYCFGR_OPMDC_100F   (3<<3)

Definition at line 768 of file w5500.h.

Referenced by wizphy_getphyconf(), and wizphy_setphyconf().

#define PHYCFGR_OPMDC_100H   (2<<3)

Definition at line 769 of file w5500.h.

Referenced by wizphy_getphyconf(), and wizphy_setphyconf().

#define PHYCFGR_OPMDC_10F   (1<<3)

Definition at line 770 of file w5500.h.

Referenced by wizphy_getphyconf(), and wizphy_setphyconf().

#define PHYCFGR_OPMDC_10H   (0<<3)

Definition at line 771 of file w5500.h.

Referenced by wizphy_setphyconf().

#define PHYCFGR_DPX_FULL   (1<<2)

Definition at line 772 of file w5500.h.

Referenced by wizphy_getphystat().

#define PHYCFGR_DPX_HALF   (0<<2)

Definition at line 773 of file w5500.h.

#define PHYCFGR_SPD_100   (1<<1)

Definition at line 774 of file w5500.h.

Referenced by wizphy_getphystat().

#define PHYCFGR_SPD_10   (0<<1)

Definition at line 775 of file w5500.h.

#define PHYCFGR_LNK_ON   (1<<0)

Definition at line 776 of file w5500.h.

Referenced by wizphy_getphylink().

#define PHYCFGR_LNK_OFF   (0<<0)

Definition at line 777 of file w5500.h.

#define IM_IR7   0x80

IP Conflict Interrupt Mask.

0: Disable IP Conflict Interrupt
1: Enable IP Conflict Interrupt

Definition at line 785 of file w5500.h.

#define IM_IR6   0x40

Destination unreachable Interrupt Mask.

0: Disable Destination unreachable Interrupt
1: Enable Destination unreachable Interrupt

Definition at line 792 of file w5500.h.

#define IM_IR5   0x20

PPPoE Close Interrupt Mask.

0: Disable PPPoE Close Interrupt
1: Enable PPPoE Close Interrupt

Definition at line 799 of file w5500.h.

#define IM_IR4   0x10

Magic Packet Interrupt Mask.

0: Disable Magic Packet Interrupt
1: Enable Magic Packet Interrupt

Definition at line 806 of file w5500.h.

#define Sn_MR_MULTI   0x80

Support UDP Multicasting.

0 : disable Multicasting
1 : enable Multicasting
This bit is applied only during UDP mode(P[3:0] = 010.
To use multicasting, Sn_DIPR & Sn_DPORT should be respectively configured with the multicast group IP address & port number before Socket n is opened by OPEN command of Sn_CR.

Definition at line 817 of file w5500.h.

#define Sn_MR_BCASTB   0x40

Broadcast block in UDP Multicasting.

0 : disable Broadcast Blocking
1 : enable Broadcast Blocking
This bit blocks to receive broadcasting packet during UDP mode(P[3:0] = 010. In addition, This bit does when MACRAW mode(P[3:0] = 100

Definition at line 826 of file w5500.h.

#define Sn_MR_ND   0x20

No Delayed Ack(TCP), Multicast flag.

0 : Disable No Delayed ACK option
1 : Enable No Delayed ACK option
This bit is applied only during TCP mode (P[3:0] = 001.
When this bit is It sends the ACK packet without delay as soon as a Data packet is received from a peer.
When this bit is It sends the ACK packet after waiting for the timeout time configured by RTR.

Definition at line 836 of file w5500.h.

#define Sn_MR_UCASTB   0x10

Unicast Block in UDP Multicasting.

0 : disable Unicast Blocking
1 : enable Unicast Blocking
This bit blocks receiving the unicast packet during UDP mode(P[3:0] = 010 and MULTI =

Definition at line 844 of file w5500.h.

#define Sn_MR_MACRAW   0x04

MAC LAYER RAW SOCK.

This configures the protocol mode of Socket n.

Note
MACRAW mode should be only used in Socket 0.

Definition at line 851 of file w5500.h.

#define Sn_MR_UDP   0x02

UDP.

This configures the protocol mode of Socket n.

Definition at line 859 of file w5500.h.

#define Sn_MR_TCP   0x01

TCP.

This configures the protocol mode of Socket n.

Definition at line 865 of file w5500.h.

#define Sn_MR_CLOSE   0x00

Unused socket.

This configures the protocol mode of Socket n.

Definition at line 871 of file w5500.h.

#define Sn_MR_MFEN   Sn_MR_MULTI

MAC filter enable in Sn_MR_MACRAW mode.

0 : disable MAC Filtering
1 : enable MAC Filtering
This bit is applied only during MACRAW mode(P[3:0] = 100.
When set as W5500 can only receive broadcasting packet or packet sent to itself. When this bit is W5500 can receive all packets on Ethernet. If user wants to implement Hybrid TCP/IP stack, it is recommended that this bit is set as for reducing host overhead to process the all received packets.

Definition at line 884 of file w5500.h.

#define Sn_MR_MMB   Sn_MR_ND

Multicast Blocking in Sn_MR_MACRAW mode.

0 : using IGMP version 2
1 : using IGMP version 1
This bit is applied only during UDP mode(P[3:0] = 010 and MULTI = It configures the version for IGMP messages (Join/Leave/Report).

Definition at line 893 of file w5500.h.

#define Sn_MR_MIP6B   Sn_MR_UCASTB

IPv6 packet Blocking in Sn_MR_MACRAW mode.

0 : disable IPv6 Blocking
1 : enable IPv6 Blocking
This bit is applied only during MACRAW mode (P[3:0] = 100. It blocks to receiving the IPv6 packet.

Definition at line 901 of file w5500.h.

#define Sn_MR_MC   Sn_MR_ND

IGMP version used in UDP mulitcasting.

0 : disable Multicast Blocking
1 : enable Multicast Blocking
This bit is applied only when MACRAW mode(P[3:0] = 100. It blocks to receive the packet with multicast MAC address.

Definition at line 910 of file w5500.h.

#define SOCK_STREAM   Sn_MR_TCP

For Berkeley Socket API.

Definition at line 916 of file w5500.h.

#define SOCK_DGRAM   Sn_MR_UDP

For Berkeley Socket API.

Definition at line 921 of file w5500.h.

#define Sn_CR_OPEN   0x01

Initialize or open socket.

Socket n is initialized and opened according to the protocol selected in Sn_MR(P3:P0). The table below shows the value of Sn_SR corresponding to Sn_MR.

Sn_MR (P[3:0]) Sn_SR
Sn_MR_CLOSE (000)
Sn_MR_TCP (001) SOCK_INIT (0x13)
Sn_MR_UDP (010) SOCK_UDP (0x22)
S0_MR_MACRAW (100) SOCK_MACRAW (0x02)

Definition at line 937 of file w5500.h.

#define Sn_CR_LISTEN   0x02

Wait connection request in TCP mode(Server mode)

This is valid only in TCP mode (Sn_MR(P3:P0) = Sn_MR_TCP). In this mode, Socket n operates as a TCP serverand waits for connection-request (SYN packet) from any TCP client The Sn_SR changes the state from SOCK_INIT to SOCKET_LISTEN. When a TCP clientconnection request is successfully established, the Sn_SR changes from SOCK_LISTEN to SOCK_ESTABLISHED and the Sn_IR(0) becomes But when a TCP clientconnection request is failed, Sn_IR(3) becomes and the status of Sn_SR changes to SOCK_CLOSED.

Definition at line 948 of file w5500.h.

#define Sn_CR_CONNECT   0x04

Send connection request in TCP mode(Client mode)

To connect, a connect-request (SYN packet) is sent to TCP serverconfigured by Sn_DIPR & Sn_DPORT(destination address & port). If the connect-request is successful, the Sn_SR is changed to SOCK_ESTABLISHED and the Sn_IR(0) becomes

The connect-request fails in the following three cases.

  1. When a ARPTO occurs (Sn_IR[3] = ) because destination hardware address is not acquired through the ARP-process.
  2. When a SYN/ACK packet is not received and TCPTO (Sn_IR(3) = )
  3. When a RST packet is received instead of a SYN/ACK packet. In these cases, Sn_SR is changed to SOCK_CLOSED.
    Note
    This is valid only in TCP mode and operates when Socket n acts as TCP client

Definition at line 960 of file w5500.h.

#define Sn_CR_DISCON   0x08

Send closing request in TCP mode.

Regardless of TCP serveror TCP client the DISCON command processes the disconnect-process (b>Active closeor Passive close.

Active close
it transmits disconnect-request(FIN packet) to the connected peer
Passive close
When FIN packet is received from peer, a FIN packet is replied back to the peer.

When the disconnect-process is successful (that is, FIN/ACK packet is received successfully), Sn_SR is changed to SOCK_CLOSED.
Otherwise, TCPTO occurs (Sn_IR(3)='1') and then Sn_SR is changed to SOCK_CLOSED.

Note
Valid only in TCP mode.

Definition at line 973 of file w5500.h.

#define Sn_CR_CLOSE   0x10

Close socket.

Sn_SR is changed to SOCK_CLOSED.

Definition at line 979 of file w5500.h.

#define Sn_CR_SEND   0x20

Update TX buffer pointer and send data.

SEND transmits all the data in the Socket n TX buffer.
For more details, please refer to Socket n TX Free Size Register (Sn_TX_FSR), Socket n, TX Write Pointer Register(Sn_TX_WR), and Socket n TX Read Pointer Register(Sn_TX_RD).

Definition at line 987 of file w5500.h.

#define Sn_CR_SEND_MAC   0x21

Send data with MAC address, so without ARP process.

The basic operation is same as SEND.
Normally SEND transmits data after destination hardware address is acquired by the automatic ARP-process(Address Resolution Protocol).
But SEND_MAC transmits data without the automatic ARP-process.
In this case, the destination hardware address is acquired from Sn_DHAR configured by host, instead of APR-process.

Note
Valid only in UDP mode.

Definition at line 997 of file w5500.h.

#define Sn_CR_SEND_KEEP   0x22

Send keep alive message.

It checks the connection status by sending 1byte keep-alive packet.
If the peer can not respond to the keep-alive packet during timeout time, the connection is terminated and the timeout interrupt will occur.

Note
Valid only in TCP mode.

Definition at line 1005 of file w5500.h.

#define Sn_CR_RECV   0x40

Update RX buffer pointer and receive data.

RECV completes the processing of the received data in Socket n RX Buffer by using a RX read pointer register (Sn_RX_RD).
For more details, refer to Socket n RX Received Size Register (Sn_RX_RSR), Socket n RX Write Pointer Register (Sn_RX_WR), and Socket n RX Read Pointer Register (Sn_RX_RD).

Definition at line 1013 of file w5500.h.

#define Sn_IR_SENDOK   0x10

SEND_OK Interrupt.

This is issued when SEND command is completed.

Definition at line 1020 of file w5500.h.

#define Sn_IR_TIMEOUT   0x08

TIMEOUT Interrupt.

This is issued when ARPTO or TCPTO occurs.

Definition at line 1026 of file w5500.h.

#define Sn_IR_RECV   0x04

RECV Interrupt.

This is issued whenever data is received from a peer.

Definition at line 1032 of file w5500.h.

#define Sn_IR_DISCON   0x02

DISCON Interrupt.

This is issued when FIN or FIN/ACK packet is received from a peer.

Definition at line 1038 of file w5500.h.

#define Sn_IR_CON   0x01

CON Interrupt.

This is issued one time when the connection with peer is successful and then Sn_SR is changed to SOCK_ESTABLISHED.

Definition at line 1044 of file w5500.h.

#define SOCK_CLOSED   0x00

Closed.

This indicates that Socket n is released.
When DICON, CLOSE command is ordered, or when a timeout occurs, it is changed to SOCK_CLOSED regardless of previous status.

Definition at line 1052 of file w5500.h.

#define SOCK_INIT   0x13

Initiate state.

This indicates Socket n is opened with TCP mode.
It is changed to SOCK_INIT when Sn_MR(P[3:0]) = 001 and OPEN command is ordered.
After SOCK_INIT, user can use LISTEN /CONNECT command.

Definition at line 1060 of file w5500.h.

#define SOCK_LISTEN   0x14

Listen state.

This indicates Socket n is operating as TCP servermode and waiting for connection-request (SYN packet) from a peer TCP client.
It will change to SOCK_ESTALBLISHED when the connection-request is successfully accepted.
Otherwise it will change to SOCK_CLOSED after TCPTO Sn_IR(TIMEOUT) = '1') is occurred.

Definition at line 1068 of file w5500.h.

#define SOCK_SYNSENT   0x15

Connection state.

This indicates Socket n sent the connect-request packet (SYN packet) to a peer.
It is temporarily shown when Sn_SR is changed from SOCK_INIT to SOCK_ESTABLISHED by CONNECT command.
If connect-accept(SYN/ACK packet) is received from the peer at SOCK_SYNSENT, it changes to SOCK_ESTABLISHED.
Otherwise, it changes to SOCK_CLOSED after TCPTO (Sn_IR[TIMEOUT] = '1') is occurred.

Definition at line 1077 of file w5500.h.

#define SOCK_SYNRECV   0x16

Connection state.

It indicates Socket n successfully received the connect-request packet (SYN packet) from a peer.
If socket n sends the response (SYN/ACK packet) to the peer successfully, it changes to SOCK_ESTABLISHED.
If not, it changes to SOCK_CLOSED after timeout (Sn_IR[TIMEOUT] = '1') is occurred.

Definition at line 1085 of file w5500.h.

#define SOCK_ESTABLISHED   0x17

Success to connect.

This indicates the status of the connection of Socket n.
It changes to SOCK_ESTABLISHED when the TCP SERVERprocessed the SYN packet from the TCP CLIENTduring SOCK_LISTEN, or when the CONNECT command is successful.
During SOCK_ESTABLISHED, DATA packet can be transferred using SEND or RECV command.

Definition at line 1094 of file w5500.h.

#define SOCK_FIN_WAIT   0x18

Closing state.

These indicate Socket n is closing.
These are shown in disconnect-process such as active-close and passive-close.
When Disconnect-process is successfully completed, or when timeout occurs, these change to SOCK_CLOSED.

Definition at line 1102 of file w5500.h.

#define SOCK_CLOSING   0x1A

Closing state.

These indicate Socket n is closing.
These are shown in disconnect-process such as active-close and passive-close.
When Disconnect-process is successfully completed, or when timeout occurs, these change to SOCK_CLOSED.

Definition at line 1110 of file w5500.h.

#define SOCK_TIME_WAIT   0x1B

Closing state.

These indicate Socket n is closing.
These are shown in disconnect-process such as active-close and passive-close.
When Disconnect-process is successfully completed, or when timeout occurs, these change to SOCK_CLOSED.

Definition at line 1118 of file w5500.h.

#define SOCK_CLOSE_WAIT   0x1C

Closing state.

This indicates Socket n received the disconnect-request (FIN packet) from the connected peer.
This is half-closing status, and data can be transferred.
For full-closing, DISCON command is used. But For just-closing, CLOSE command is used.

Definition at line 1126 of file w5500.h.

#define SOCK_LAST_ACK   0x1D

Closing state.

This indicates Socket n is waiting for the response (FIN/ACK packet) to the disconnect-request (FIN packet) by passive-close.
It changes to SOCK_CLOSED when Socket n received the response successfully, or when timeout(Sn_IR[TIMEOUT] = '1') is occurred.

Definition at line 1133 of file w5500.h.

#define SOCK_UDP   0x22

UDP socket.

This indicates Socket n is opened in UDP mode(Sn_MR(P[3:0]) = '010').
It changes to SOCK_UDP when Sn_MR(P[3:0]) = '010' and Sn_CR_OPEN command is ordered.
Unlike TCP mode, data can be transfered without the connection-process.

Definition at line 1141 of file w5500.h.

#define SOCK_MACRAW   0x42

MAC raw mode socket.

This indicates Socket 0 is opened in MACRAW mode (S0_MR(P[3:0]) = 100and is valid only in Socket 0.
It changes to SOCK_MACRAW when S0_MR(P[3:0] = 100and OPEN command is ordered.
Like UDP mode socket, MACRAW mode Socket 0 can transfer a MAC packet (Ethernet frame) without the connection-process.

Definition at line 1151 of file w5500.h.

#define IPPROTO_IP   0

Definition at line 1156 of file w5500.h.

#define IPPROTO_ICMP   1

Definition at line 1157 of file w5500.h.

#define IPPROTO_IGMP   2

Definition at line 1158 of file w5500.h.

#define IPPROTO_GGP   3

Definition at line 1159 of file w5500.h.

#define IPPROTO_TCP   6

Definition at line 1160 of file w5500.h.

#define IPPROTO_PUP   12

Definition at line 1161 of file w5500.h.

#define IPPROTO_UDP   17

Definition at line 1162 of file w5500.h.

#define IPPROTO_IDP   22

Definition at line 1163 of file w5500.h.

#define IPPROTO_ND   77

Definition at line 1164 of file w5500.h.

#define IPPROTO_RAW   255

Definition at line 1165 of file w5500.h.

#define WIZCHIP_CRITICAL_ENTER ( )    WIZCHIP.CRIS._enter()

Enter a critical section.

It is provided to protect your shared code which are executed without distribution.

In non-OS environment, It can be just implemented by disabling whole interrupt.
In OS environment, You can replace it to critical section api supported by OS.

See also
WIZCHIP_READ(), WIZCHIP_WRITE(), WIZCHIP_READ_BUF(), WIZCHIP_WRITE_BUF()
WIZCHIP_CRITICAL_EXIT()

Definition at line 1179 of file w5500.h.

#define WIZCHIP_CRITICAL_EXIT ( )    WIZCHIP.CRIS._exit()

Exit a critical section.

It is provided to protect your shared code which are executed without distribution.

In non-OS environment, It can be just implemented by disabling whole interrupt.
In OS environment, You can replace it to critical section api supported by OS.

See also
WIZCHIP_READ(), WIZCHIP_WRITE(), WIZCHIP_READ_BUF(), WIZCHIP_WRITE_BUF()
WIZCHIP_CRITICAL_ENTER()

Definition at line 1196 of file w5500.h.

#define getSn_RxMAX (   sn)    (((uint16_t)getSn_RXBUF_SIZE(sn)) << 10)

Socket_register_access_function.

Gets the max buffer size of socket sn passed as parameter.

Parameters
(uint8_t)snSocket number. It should be 0 ~ 7.
Returns
uint16_t. Value of Socket n RX max buffer size.

Definition at line 2093 of file w5500.h.

#define getSn_TxMAX (   sn)    (((uint16_t)getSn_TXBUF_SIZE(sn)) << 10)

Socket_register_access_function.

Gets the max buffer size of socket sn passed as parameters.

Parameters
(uint8_t)snSocket number. It should be 0 ~ 7.
Returns
uint16_t. Value of Socket n TX max buffer size.

Definition at line 2107 of file w5500.h.

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