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Socket APIs
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Common register group
It set the basic for the networking
It set the configuration such as interrupt, network information, ICMP, etc.
More...
Macros | |
| #define | MR (_WIZCHIP_IO_BASE_) |
| Mode Register address(R/W) MR is used for S/W reset, ping block mode, PPPoE mode and etc. More... | |
| #define | IR (_W5300_IO_BASE_ + 0x02) |
| Interrupt Register(R/W) More... | |
| #define | _IMR_ (_W5300_IO_BASE_ + 0x04) |
| Socket Interrupt Mask Register(R/W) More... | |
| #define | SHAR (_W5300_IO_BASE_ + 0x08) |
| Source MAC Register address(R/W) More... | |
| #define | GAR (_W5300_IO_BASE_ + 0x10) |
| Gateway IP Register address(R/W) More... | |
| #define | SUBR (_W5300_IO_BASE_ + 0x14) |
| Subnet mask Register address(R/W) More... | |
| #define | SIPR (_W5300_IO_BASE_ + 0x18) |
| Source IP Register address(R/W) More... | |
| #define | _RTR_ (_W5300_IO_BASE_ + 0x1C) |
| Timeout register address( 1 is 100us )(R/W) More... | |
| #define | _RCR_ (_W5300_IO_BASE_ + 0x1E) |
| Retry count register(R/W) More... | |
| #define | TMS01R (_W5300_IO_BASE_ + 0x20) |
TX memory size of SOCKET 0 & 1. More... | |
| #define | TMS23R (TMS01R + 2) |
TX memory size of SOCKET 2 & 3. More... | |
| #define | TMS45R (TMS01R + 4) |
TX memory size of SOCKET 4 & 5. More... | |
| #define | TMS67R (TMS01R + 6) |
TX memory size of SOCKET 6 & 7. More... | |
| #define | TMSR0 TMS01R |
TX memory size of SOCKET 0. More... | |
| #define | TMSR1 (TMSR0 + 1) |
TX memory size of SOCKET 1. More... | |
| #define | TMSR2 (TMSR0 + 2) |
TX memory size of SOCKET 2. More... | |
| #define | TMSR3 (TMSR0 + 3) |
TX memory size of SOCKET 3. More... | |
| #define | TMSR4 (TMSR0 + 4) |
TX memory size of SOCKET 4. More... | |
| #define | TMSR5 (TMSR0 + 5) |
TX memory size of SOCKET 5. More... | |
| #define | TMSR6 (TMSR0 + 6) |
TX memory size of SOCKET 6. More... | |
| #define | TMSR7 (TMSR0 + 7) |
TX memory size of SOCKET 7. More... | |
| #define | RMS01R (_W5300_IO_BASE_ + 0x28) |
RX memory size of SOCKET 0 & 1. More... | |
| #define | RMS23R (RMS01R + 2) |
RX memory size of SOCKET 2 & 3. More... | |
| #define | RMS45R (RMS01R + 4) |
RX memory size of SOCKET 4 & 5. More... | |
| #define | RMS67R (RMS01R + 6) |
RX memory size of SOCKET 6 & 7. More... | |
| #define | RMSR0 RMS01R |
RX memory size of SOCKET 0. More... | |
| #define | RMSR1 (RMSR0 + 1) |
RX memory size of SOCKET 1. More... | |
| #define | RMSR3 (RMSR0 + 3) |
RX memory size of SOCKET 3. More... | |
| #define | RMSR4 (RMSR0 + 4) |
RX memory size of SOCKET 4. More... | |
| #define | RMSR5 (RMSR0 + 5) |
RX memory size of SOCKET 5. More... | |
| #define | RMSR6 (RMSR0 + 6) |
RX memory size of SOCKET 6. More... | |
| #define | RMSR7 (RMSR0 + 7) |
RX memory size of SOCKET 7. More... | |
| #define | MTYPER (_W5300_IO_BASE_ + 0x30) |
| Memory Type Register. More... | |
| #define | PATR (_W5300_IO_BASE_ + 0x32) |
| PPPoE Authentication Type register. More... | |
| #define | PTIMER (_W5300_IO_BASE_ + 0x36) |
| PPP Link Control Protocol Request Timer Register. More... | |
| #define | PMAGICR (_W5300_IO_BASE_ + 0x38) |
| PPP LCP magic number register. More... | |
| #define | PSIDR (_W5300_IO_BASE_ + 0x3C) |
| PPPoE session ID register. More... | |
| #define | PDHAR (_W5300_IO_BASE_ + 0x40) |
| PPPoE destination hardware address register. More... | |
| #define | UIPR (_W5300_IO_BASE_ + 0x48) |
| Unreachable IP address register. More... | |
| #define | UPORTR (_W5300_IO_BASE_ + 0x4C) |
| Unreachable port number register. More... | |
| #define | FMTUR (_W5300_IO_BASE_ + 0x4E) |
| Fragment MTU register. More... | |
| #define | Pn_BRDYR(n) (_W5300_IO_BASE_ + 0x60 + n*4) |
| PIN 'BRDYn' configure register. More... | |
| #define | Pn_BDPTHR(n) (_W5300_IO_BASE_ + 0x60 + n*4 + 2) |
| PIN 'BRDYn' buffer depth Register. More... | |
| #define | IDR (_W5300_IO_BASE_ + 0xFE) |
| W5300 identification register. More... | |
Detailed Description
Common register group
It set the basic for the networking
It set the configuration such as interrupt, network information, ICMP, etc.
- See also
- MR : Mode register.
- GAR, SUBR, SHAR, SIPR : Network Configuration
- IR, IMR : Interrupt.
- MTYPER, TMS01R,TMS23R, TMS45R, TMS67R,RMS01R,RMS23R, RMS45R, RMS67R : Socket TX/RX memory
- RTR, RCR : Data retransmission.
- PTIMER, PMAGIC, PSID, PDHAR : PPPoE.
- UIPR, UPORTR, FMTUR : ICMP message.
- Pn_BRDYR, Pn_BDPTHR, IDR : etc.
Macro Definition Documentation
| #define MR (_WIZCHIP_IO_BASE_) |
Mode Register address(R/W)
MR is used for S/W reset, ping block mode, PPPoE mode and etc.
Each bit of MR defined as follows.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| DBW | MPF | WDF | RDF | Reserved | FS | ||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RST | Reserved | WOL | PB | PPPoE | Reserved | FARP | Reserved |
- MR_DBW : Data bus width (0 : 8 Bit, 1 : 16 Bit), Read Only
- MR_MPF : Received a Pause Frame from MAC layer (0 : Normal Frame, 1 : Pause Frame), Read Only
- MR_WDF : Write Data Fetch time (When CS signal is low, W5300 Fetch a written data by Host after PLL_CLK * MR_WDF)
- MR_RDH : Read Data Hold time (0 : No use data hold time, 1 : Use data hold time, 2 PLL_CLK)
- MR_FS : FIFO Swap (0 : Disable Swap, 1 : Enable Swap)
- MR_RST : Reset
- MR_WOL : Wake on LAN
- MR_PB : Ping block
- MR_PPPOE : PPPoE mode
- MR_FARP : Force ARP mode
| #define IR (_W5300_IO_BASE_ + 0x02) |
Interrupt Register(R/W)
IR indicates the interrupt status. Each bit of IR will be still until the bit will be written to by the host. If IR is not equal to 0x0000 INTn PIN is asserted to low until it is 0x0000
Each bit of IR defined as follows.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| IPCF | DPUR | PPPT | FMTU | Reserved | Reserved | Reserved | Reserved |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| S7_INT | S6_INT | S5_INT | S4_INT | S3_INT | S2_INT | S1_INT | S0_INT |
- IR_IPCF : IP conflict
- IR_DPUR : Destination Port Unreachable
- IR_PPPT : PPPoE Termination
- IR_FMTU : Fragmented MTU
- IR_SnINT(n) : Interrupted from SOCKETn
- Note
- : In W5300, IR is operated same as IR and SIR in other WIZCHIP(5100,5200,W5500)
| #define _IMR_ (_W5300_IO_BASE_ + 0x04) |
Socket Interrupt Mask Register(R/W)
Each bit of IMR corresponds to each bit of IR. When a bit of IMR is and the corresponding bit of IR is Interrupt will be issued. In other words, if a bit of IMR, an interrupt will be not issued even if the corresponding bit of IR is set
- Note
- : In W5300, IMR is operated same as IMR and SIMR in other WIZCHIP(5100,5200,W5500)
| #define SHAR (_W5300_IO_BASE_ + 0x08) |
| #define GAR (_W5300_IO_BASE_ + 0x10) |
| #define SUBR (_W5300_IO_BASE_ + 0x14) |
| #define SIPR (_W5300_IO_BASE_ + 0x18) |
| #define _RTR_ (_W5300_IO_BASE_ + 0x1C) |
Timeout register address( 1 is 100us )(R/W)
RTR configures the retransmission timeout period. The unit of timeout period is 100us and the default of RTR is x07D0. And so the default timeout period is 200ms(100us X 2000). During the time configured by RTR, W5300 waits for the peer response to the packet that is transmitted by Sn_CR (CONNECT, DISCON, CLOSE, SEND, SEND_MAC, SEND_KEEP command). If the peer does not respond within the RTR time, W5300 retransmits the packet or issues timeout.
| #define _RCR_ (_W5300_IO_BASE_ + 0x1E) |
Retry count register(R/W)
RCR configures the number of time of retransmission. When retransmission occurs as many as ref RCR+1 Timeout interrupt is issued (Sn_IR_TIMEOUT = '1').
| #define TMS01R (_W5300_IO_BASE_ + 0x20) |
TX memory size of SOCKET 0 & 1.
TMS01R configures the TX buffer block size of SOCKET 0 & 1. The default value is configured with 8KB and can be configure from 0 to 64KB with unit 1KB. But the sum of all SOCKET TX buffer size should be multiple of 8 and the sum of all SOCKET TX and RX memory size can't exceed 128KB. When exceeded nor multiple of 8, the data transmittion is invalid.
| #define TMS23R (TMS01R + 2) |
| #define TMS45R (TMS01R + 4) |
| #define TMS67R (TMS01R + 6) |
| #define TMSR0 TMS01R |
| #define TMSR1 (TMSR0 + 1) |
| #define TMSR2 (TMSR0 + 2) |
| #define TMSR3 (TMSR0 + 3) |
| #define TMSR4 (TMSR0 + 4) |
| #define TMSR5 (TMSR0 + 5) |
| #define TMSR6 (TMSR0 + 6) |
| #define TMSR7 (TMSR0 + 7) |
| #define RMS01R (_W5300_IO_BASE_ + 0x28) |
RX memory size of SOCKET 0 & 1.
RMS01R configures the RX buffer block size of SOCKET 0 & 1. The default value is configured with 8KB and can be configure from 0 to 64KB with unit 1KB. But the sum of all SOCKET RX buffer size should be multiple of 8 and the sum of all SOCKET RX and TX memory size can't exceed 128KB. When exceeded nor multiple of 8, the data reception is invalid.
| #define RMS23R (RMS01R + 2) |
| #define RMS45R (RMS01R + 4) |
| #define RMS67R (RMS01R + 6) |
| #define RMSR0 RMS01R |
| #define RMSR1 (RMSR0 + 1) |
| #define RMSR3 (RMSR0 + 3) |
| #define RMSR4 (RMSR0 + 4) |
| #define RMSR5 (RMSR0 + 5) |
| #define RMSR6 (RMSR0 + 6) |
| #define RMSR7 (RMSR0 + 7) |
| #define MTYPER (_W5300_IO_BASE_ + 0x30) |
Memory Type Register.
W5300’s 128Kbytes data memory (Internal TX/RX memory) is composed of 16 memory blocks of 8Kbytes. MTYPER configures type of each 8KB memory block in order to select RX or TX memory. The type of 8KB memory block corresponds to each bit of MTYPER. When the bit is ‘1’, it is used as TX memory, and the bit is ‘0’, it is used as RX memory. MTYPER is configured as TX memory type from the lower bit. The rest of the bits not configured as TX memory, should be set as ‘0’.
| #define PATR (_W5300_IO_BASE_ + 0x32) |
| #define PTIMER (_W5300_IO_BASE_ + 0x36) |
| #define PMAGICR (_W5300_IO_BASE_ + 0x38) |
| #define PSIDR (_W5300_IO_BASE_ + 0x3C) |
| #define PDHAR (_W5300_IO_BASE_ + 0x40) |
| #define UIPR (_W5300_IO_BASE_ + 0x48) |
Unreachable IP address register.
When trying to transmit UDP data to destination port number which is not open, W5300 can receive ICMP (Destination port unreachable) packet.
In this case, IR_DPUR bit of IR becomes '1'. And destination IP address and unreachable port number of ICMP packet can be acquired through UIPR and UPORTR.
| #define UPORTR (_W5300_IO_BASE_ + 0x4C) |
| #define FMTUR (_W5300_IO_BASE_ + 0x4E) |
Fragment MTU register.
When communicating with the peer having a different MTU, W5300 can receive an ICMP(Fragment MTU) packet. At this case, IR(FMTU) becomes ‘1’ and destination IP address and fragment MTU value of ICMP packet can be acquired through UIPR and FMTUR. In order to keep communicating with the peer having Fragment MTU, set the FMTUR first in Sn_MSSR of the SOCKETn, and try the next communication.
| #define Pn_BRDYR | ( | n | ) | (_W5300_IO_BASE_ + 0x60 + n*4) |
PIN 'BRDYn' configure register.
It configures the PIN "BRDYn" which is monitoring TX/RX memory status of the specified SOCKET. If the free buffer size of TX memory is same or bigger than the buffer depth of Pn_BDPTHR, or received buffer size of RX memory is same or bigger than the Pn_BDPTHR, PIN "BRDYn" is signaled.
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| Reserved, Read as 0 | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PEN | MT | PPL | Reserved | SN | |||
| #define Pn_BDPTHR | ( | n | ) | (_W5300_IO_BASE_ + 0x60 + n*4 + 2) |
PIN 'BRDYn' buffer depth Register.
It configures buffer depth of PIN "BRDYn". When monitoring TX memory and Sn_TX_FSR is same or bigger than Pn_BDPTHR, the PIN "BRDYn" is signaled. When monitoring RX memory and if Sn_RX_RSR is same or bigger than Pn_BDPTHR, PIN "BRDYn" is signaled. The value for Pn_BDPTHR can't exceed TX/RX memory size allocated by TMSR or RMSR such like as TMS01R or RMS01R.
| #define IDR (_W5300_IO_BASE_ + 0xFE) |
Generated on Wed May 4 2016 16:44:00 for Socket APIs by
1.8.9.1