Socket APIs: Ethernet/W5200/w5200.h Source File

Wiznet Socket API

Socket APIs
 //* ****************************************************************************
 //
 //*****************************************************************************
 
 #ifndef _W5200_H
 #define _W5200_H
 #include <stdint.h>
 #include "wizchip_conf.h"
 
 #if (_WIZCHIP_ == 5200)
 
 #define _WIZCHIP_SN_BASE_ (0x4000)
 #define _WIZCHIP_SN_SIZE_ (0x0100)
 #define _WIZCHIP_IO_TXBUF_ (0x8000) /* Internal Tx buffer address of the iinchip */
 #define _WIZCHIP_IO_RXBUF_ (0xC000) /* Internal Rx buffer address of the iinchip */
 
 #define _W5200_SPI_READ_ (0x00 << 7) 
 #define _W5200_SPI_WRITE_ (0x01 << 7) 
 
 #define WIZCHIP_CREG_BLOCK 0x00 
 #define WIZCHIP_SREG_BLOCK(N) (_WIZCHIP_SN_BASE_+ _WIZCHIP_SN_SIZE_*N) 
 
 #define WIZCHIP_OFFSET_INC(ADDR, N) (ADDR + N) 
 
 #if (_WIZCHIP_IO_MODE_ & _WIZCHIP_IO_MODE_BUS_)
  #define IDM_AR0 ((_WIZCHIP_IO_BASE_ + 0x0001))
  #define IDM_AR1 ((_WIZCHIP_IO_BASE_ + 0x0002))
  #define IDM_DR ((_WIZCHIP_IO_BASE_ + 0x0003))
  #define _W5200_IO_BASE_ 0x0000
 #elif (_WIZCHIP_IO_MODE_ & _WIZCHIP_IO_MODE_SPI_)
  #define _W5200_IO_BASE_ 0x0000
 #endif
 
 // Definition For Legacy Chip Driver //
 #define IINCHIP_READ(ADDR) WIZCHIP_READ(ADDR) 
 #define IINCHIP_WRITE(ADDR,VAL) WIZCHIP_WRITE(ADDR,VAL) 
 #define IINCHIP_READ_BUF(ADDR,BUF,LEN) WIZCHIP_READ_BUF(ADDR,BUF,LEN) 
 #define IINCHIP_WRITE_BUF(ADDR,BUF,LEN) WIZCHIP_WRITE(ADDR,BUF,LEN) 
 
 
 //----------- defgroup --------------------------------
 
  //-----------------------------------------------------------------------------------
 
 //----------------------------- W5200 Common Registers IOMAP -----------------------------
 #if (_WIZCHIP_IO_MODE_ & _WIZCHIP_IO_MODE_BUS_) 
  #define MR (_WIZCHIP_IO_BASE_ + (0x0000)) // Mode
 #else 
  #define MR (_W5200_IO_BASE_ + (0x0000)) // Mode
 #endif 
 
 #define GAR (_W5200_IO_BASE_ + (0x0001)) // GW Address
 
 #define SUBR (_W5200_IO_BASE_ + (0x0005)) // SN Mask Address
 
 #define SHAR (_W5200_IO_BASE_ + (0x0009)) // Source Hardware Address
 
 #define SIPR (_W5200_IO_BASE_ + (0x000F)) // Source IP Address
 
 // Reserved (_W5200_IO_BASE_ + (0x0013))
 // Reserved (_W5200_IO_BASE_ + (0x0014))
 
 #define IR (_W5200_IO_BASE_ + (0x0015)) // Interrupt
 
 #define _IMR_ (_W5200_IO_BASE_ + (0x0016)) // Socket Interrupt Mask
 
 #define _RTR_ (_W5200_IO_BASE_ + (0x0017)) // Retry Time
 
 #define _RCR_ (_W5200_IO_BASE_ + (0x0019)) // Retry Count
 
 // Reserved (_W5200_IO_BASE_ + (0x001A))
 // Reserved (_W5200_IO_BASE_ + (0x001B))
 
 #define PATR (_W5200_IO_BASE_ + (0x001C))
 
 #define PPPALGO (_W5200_IO_BASE_ + (0x001E)) // Authentication Algorithm in PPPoE
 
 #define VERSIONR (_W5200_IO_BASE_ + (0x001F)) // Chip version
 
 // Reserved (_W5200_IO_BASE_ + (0x0020))
 // Reserved (_W5200_IO_BASE_ + (0x0021))
 // Reserved (_W5200_IO_BASE_ + (0x0022))
 // Reserved (_W5200_IO_BASE_ + (0x0023))
 // Reserved (_W5200_IO_BASE_ + (0x0024))
 // Reserved (_W5200_IO_BASE_ + (0x0025))
 // Reserved (_W5200_IO_BASE_ + (0x0026))
 // Reserved (_W5200_IO_BASE_ + (0x0027))
 
 #define PTIMER (_W5200_IO_BASE_ + (0x0028)) // PPP LCP RequestTimer
 
 #define PMAGIC (_W5200_IO_BASE_ + (0x0029)) // PPP LCP Magic number
 
 // Reserved (_W5200_IO_BASE_ + (0x002A))
 // Reserved (_W5200_IO_BASE_ + (0x002B))
 // Reserved (_W5200_IO_BASE_ + (0x002C))
 // Reserved (_W5200_IO_BASE_ + (0x002D))
 // Reserved (_W5200_IO_BASE_ + (0x002E))
 // Reserved (_W5200_IO_BASE_ + (0x002F))
 
 #define INTLEVEL (_W5200_IO_BASE_ + (0x0030)) // Interrupt Low Level Timer
 
 // Reserved (_W5200_IO_BASE_ + (0x0032))
 // Reserved (_W5200_IO_BASE_ + (0x0033))
 
 #define IR2 (_W5200_IO_BASE_ + (0x0034)) // Socket Interrupt
 
 #define PHYSTATUS (_W5200_IO_BASE_ + (0x0035)) // PHY Status
 
 #define IMR2 (_W5200_IO_BASE_ + (0x0036)) // Interrupt Mask
 
 
 //----------------------------- W5200 Socket Registers -----------------------------
 
 //--------------------------- For Backward Compatibility ---------------------------
 
 #define Sn_MR(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0000)) // socket Mode register
 
 #define Sn_CR(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0001)) // channel Sn_CR register
 
 #define Sn_IR(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0002)) // channel interrupt register
 
 #define Sn_SR(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0003)) // channel status register
 
 #define Sn_PORT(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0004)) // source port register
 
 #define Sn_DHAR(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0006)) // Peer MAC register address
 
 #define Sn_DIPR(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x000C)) // Peer IP register address
 
 #define Sn_DPORT(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0010)) // Peer port register address
 
 #define Sn_MSSR(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0012)) // Maximum Segment Size(Sn_MSSR0) register address
 
 #define Sn_PROTO(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0014)) // Protocol of IP Header field register in IP raw mode
 
 #define Sn_TOS(sn) (WIZCHIP_SREG_BLOCK(sn) + 0x0015) // IP Type of Service(TOS) Register 
 
 #define Sn_TTL(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0016)) // IP Time to live(TTL) Register 
 
 // Reserved (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0017))
 // Reserved (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0018))
 // Reserved (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0019))
 // Reserved (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x001A))
 // Reserved (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x001B))
 // Reserved (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x001C))
 // Reserved (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x001D))
 
 #define Sn_RXMEM_SIZE(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x001E)) // Receive memory size reigster
 
 #define Sn_TXMEM_SIZE(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x001F)) // Transmit memory size reigster
 
 #define Sn_TX_FSR(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0020)) // Transmit free memory size register
 
 #define Sn_TX_RD(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0022)) // Transmit memory read pointer register address
 
 #define Sn_TX_WR(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0024)) // Transmit memory write pointer register address
 
 #define Sn_RX_RSR(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0026)) // Received data size register
 
 #define Sn_RX_RD(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0028)) // Read point of Receive memory
 
 #define Sn_RX_WR(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x002A)) // Write point of Receive memory
 
 #define Sn_IMR(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x002C)) // socket interrupt mask register
 
 #define Sn_FRAG(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x002D)) // frag field value in IP header register
 
 
 //----------------------------- W5200 Register values -----------------------------
 
 /* MODE register values */
 #define MR_RST 0x80 
 
 
 #define MR_WOL 0x20 
 
 
 #define MR_PB 0x10 
 
 
 #define MR_PPPOE 0x08 
 
 
 #define MR_AI 0x02 
 
 
 #define MR_IND 0x01 
 
 /* IR register values */
 #define IR_CONFLICT 0x80 
 
 
 #define IR_PPPoE 0x20 
 
 
 #define PHYSTATUS_LINK 0x20
 
 #define PHYSTATUS_POWERSAVE 0x10
 
 #define PHYSTATUS_POWERDOWN 0x08
 
 // Sn_MR values 
 /* Sn_MR Default values */
 #define Sn_MR_CLOSE 0x00 
 
 
 #define Sn_MR_TCP 0x01 
 
 
 #define Sn_MR_UDP 0x02 
 #define Sn_MR_IPRAW 0x03 
 
 
 #define Sn_MR_MACRAW 0x04 
 
 
 #define Sn_MR_PPPOE 0x05 
 
 
 #define Sn_MR_ND 0x20 
 
 /* Sn_MR Default values */
 #define Sn_MR_MC Sn_MR_ND 
 
 
 #define Sn_MR_MF 0x40 
 #define Sn_MR_MFEN Sn_MR_MF
 
 /* Sn_MR Default values */
 #define Sn_MR_MULTI 0x80 
 
 /* Sn_CR values */
 #define Sn_CR_OPEN 0x01 
 
 
 #define Sn_CR_LISTEN 0x02 
 
 
 #define Sn_CR_CONNECT 0x04 
 
 
 #define Sn_CR_DISCON 0x08 
 
 
 #define Sn_CR_CLOSE 0x10
 
 #define Sn_CR_SEND 0x20
 
 #define Sn_CR_SEND_MAC 0x21
 
 #define Sn_CR_SEND_KEEP 0x22
 
 #define Sn_CR_RECV 0x40
 
 #define Sn_CR_PCON 0x23
 
 #define Sn_CR_PDISCON 0x24 
 
 #define Sn_CR_PCR 0x25 
 
 #define Sn_CR_PCN 0x26 
 
 #define Sn_CR_PCJ 0x27 
 
 /* Sn_IR values */
 #define Sn_IR_PRECV 0x80 
 
 #define Sn_IR_PFAIL 0x40 
 
 #define Sn_IR_PNEXT 0x20 
 
 #define Sn_IR_SENDOK 0x10 
 
 
 #define Sn_IR_TIMEOUT 0x08 
 
 
 #define Sn_IR_RECV 0x04
 
 #define Sn_IR_DISCON 0x02
 
 #define Sn_IR_CON 0x01
 
 /* Sn_SR values */
 #define SOCK_CLOSED 0x00 
 
 
 #define SOCK_INIT 0x13 
 
 
 #define SOCK_LISTEN 0x14
 
 #define SOCK_SYNSENT 0x15
 
 #define SOCK_SYNRECV 0x16
 
 #define SOCK_ESTABLISHED 0x17
 
 #define SOCK_FIN_WAIT 0x18
 
 #define SOCK_CLOSING 0x1A
 
 #define SOCK_TIME_WAIT 0x1B
 
 #define SOCK_CLOSE_WAIT 0x1C
 
 #define SOCK_LAST_ACK 0x1D
 
 #define SOCK_UDP 0x22 
 
 
 #define SOCK_IPRAW 0x32 
 
 
 #define SOCK_MACRAW 0x42 
 
 
 #define SOCK_PPPOE 0x5F 
 
 // IP PROTOCOL 
 #define IPPROTO_IP 0 
 #define IPPROTO_ICMP 1 
 #define IPPROTO_IGMP 2 
 #define IPPROTO_GGP 3 
 #define IPPROTO_TCP 6 
 #define IPPROTO_PUP 12 
 #define IPPROTO_UDP 17 
 #define IPPROTO_IDP 22 
 #define IPPROTO_ND 77 
 #define IPPROTO_RAW 255 
 
 
 #define WIZCHIP_CRITICAL_ENTER() WIZCHIP.CRIS._enter()
 
 #ifdef _exit
 #undef _exit
 #endif
 
 #define WIZCHIP_CRITICAL_EXIT() WIZCHIP.CRIS._exit()
 
 
 
 // Basic I/O Function //
 
 uint8_t WIZCHIP_READ (uint32_t AddrSel);
 
 void WIZCHIP_WRITE(uint32_t AddrSel, uint8_t wb );
 
 void WIZCHIP_READ_BUF (uint32_t AddrSel, uint8_t* pBuf, uint16_t len);
 
 void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len);
 
 
 // Common Register IO function //
 
 #if (_WIZCHIP_IO_MODE_ & _WIZCHIP_IO_MODE_SPI_)
  #define setMR(mr) WIZCHIP_WRITE(MR,mr)
 #else 
  #define setMR(mr) (*((uint8_t*)MR) = mr)
 #endif
 
 #if (_WIZCHIP_IO_MODE_ & _WIZCHIP_IO_MODE_SPI_)
  #define getMR() WIZCHIP_READ(MR)
 #else
  #define getMR() (*(uint8_t*)MR)
 #endif
 
 #define setGAR(gar) \
  WIZCHIP_WRITE_BUF(GAR,gar,4)
 
 #define getGAR(gar) \
  WIZCHIP_READ_BUF(GAR,gar,4)
 
 #define setSUBR(subr) \
  WIZCHIP_WRITE_BUF(SUBR, subr,4)
 
 #define getSUBR(subr) \
  WIZCHIP_READ_BUF(SUBR, subr, 4)
 
 #define setSHAR(shar) \
  WIZCHIP_WRITE_BUF(SHAR, shar, 6)
 
 #define getSHAR(shar) \
  WIZCHIP_READ_BUF(SHAR, shar, 6)
 
 #define setSIPR(sipr) \
  WIZCHIP_WRITE_BUF(SIPR, sipr, 4)
 
 #define getSIPR(sipr) \
  WIZCHIP_READ_BUF(SIPR, sipr, 4)
 
 #define setIR(ir) \
  WIZCHIP_WRITE(IR, (ir & 0xA0))
 
 #define getIR() \
  (WIZCHIP_READ(IR) & 0xA0)
 
 //M20150410 : Replace _IMR_ with IMR2 for integrating with ioLibrary
 /*
 #define setIMR(imr) \
  WIZCHIP_WRITE(_IMR_, imr)
 */ 
 #define setIMR(imr) \
  WIZCHIP_WRITE(IMR2, imr & 0xA0)
 
 //M20150410 : Replace _IMR_ with IMR2 for integrating with ioLibrary
 /*
 #define getIMR() \
  WIZCHIP_READ(_IMR_)
 */ 
 #define getIMR() \
  (WIZCHIP_READ(IMR2) & 0xA0)
 
 #define setRTR(rtr) {\
  WIZCHIP_WRITE(_RTR_, (uint8_t)(rtr >> 8)); \
  WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_RTR_,1), (uint8_t) rtr); \
  }
 
 #define getRTR() \
  (((uint16_t)WIZCHIP_READ(_RTR_) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_RTR_,1)))
 
 #define setRCR(rcr) \
  WIZCHIP_WRITE(_RCR_, rcr)
 
 #define getRCR() \
  WIZCHIP_READ(_RCR_)
 
 #define getPATR() \
  (((uint16_t)WIZCHIP_READ(PATR) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(PATR,1)))
 
 #define getPPPALGO() \
  WIZCHIP_READ(PPPALGO)
 
 
 #define getVERSIONR() \
  WIZCHIP_READ(VERSIONR)
 
 #define setPTIMER(ptimer) \
  WIZCHIP_WRITE(PTIMER, ptimer)
 
 #define getPTIMER() \
  WIZCHIP_READ(PTIMER)
 
 #define setPMAGIC(pmagic) \
  WIZCHIP_WRITE(PMAGIC, pmagic)
 
 #define getPMAGIC() \
  WIZCHIP_READ(PMAGIC)
 
 #define setINTLEVEL(intlevel) {\
  WIZCHIP_WRITE(INTLEVEL, (uint8_t)(intlevel >> 8)); \
  WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(INTLEVEL,1), (uint8_t) intlevel); \
  }
 
 #define getINTLEVEL() \
  (((uint16_t)WIZCHIP_READ(INTLEVEL) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(INTLEVEL,1)))
 
 #define setIR2(ir2) \
  WIZCHIP_WRITE(IR2, ir2)
 #define setSIR(ir2) setIR2(ir2)
 
 #define getIR2() \
  WIZCHIP_READ(IR2)
 #define getSIR() getIR2()
 
 #define getPHYSTATUS() \
  WIZCHIP_READ(PHYSTATUS)
 
  //M20150410 : Replace IMR2 with _IMR_ for integrating with ioLibrary
 /*
 #define setIMR2(imr2) \
  WIZCHIP_WRITE(IMR2, (imr2 & 0xA0))
 */ 
 #define setIMR2(imr2) \
  WIZCHIP_WRITE(_IMR_, imr2)
 #define setSIMR(imr2) setIMR2(imr2)
 
  //M20150410 : Replace IMR2 with _IMR_ for integrating with ioLibrary
 /*
 #define getIMR2() \
  (WIZCHIP_READ(IMR2) & 0xA0)
 */ 
 #define getIMR2() \
  WIZCHIP_READ(_IMR_)
 #define getSIMR() getIMR2()
 // Socket N register I/O function //
 
 #define setSn_MR(sn, mr) \
  WIZCHIP_WRITE(Sn_MR(sn),mr)
 
 #define getSn_MR(sn) \
  WIZCHIP_READ(Sn_MR(sn))
 
 #define setSn_CR(sn, cr) \
  WIZCHIP_WRITE(Sn_CR(sn), cr)
 
 #define getSn_CR(sn) \
  WIZCHIP_READ(Sn_CR(sn))
 
 #define setSn_IR(sn, ir) \
  WIZCHIP_WRITE(Sn_IR(sn), ir)
 
 #define getSn_IR(sn) \
  WIZCHIP_READ(Sn_IR(sn))
 
 #define setSn_IMR(sn, imr) \
  WIZCHIP_WRITE(Sn_IMR(sn), imr)
 
 #define getSn_IMR(sn) \
  WIZCHIP_READ(Sn_IMR(sn))
 
 #define getSn_SR(sn) \
  WIZCHIP_READ(Sn_SR(sn))
 
 #define setSn_PORT(sn, port) { \
  WIZCHIP_WRITE(Sn_PORT(sn), (uint8_t)(port >> 8)); \
  WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_PORT(sn),1), (uint8_t) port); \
  }
 
 #define getSn_PORT(sn) \
  (((uint16_t)WIZCHIP_READ(Sn_PORT(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_PORT(sn),1)))
 
 #define setSn_DHAR(sn, dhar) \
  WIZCHIP_WRITE_BUF(Sn_DHAR(sn), dhar, 6)
 
 #define getSn_DHAR(sn, dhar) \
  WIZCHIP_READ_BUF(Sn_DHAR(sn), dhar, 6)
 
 #define setSn_DIPR(sn, dipr) \
  WIZCHIP_WRITE_BUF(Sn_DIPR(sn), dipr, 4)
 
 #define getSn_DIPR(sn, dipr) \
  WIZCHIP_READ_BUF(Sn_DIPR(sn), dipr, 4)
 
 #define setSn_DPORT(sn, dport) { \
  WIZCHIP_WRITE(Sn_DPORT(sn), (uint8_t) (dport>>8)); \
  WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_DPORT(sn),1), (uint8_t) dport); \
  }
 
 #define getSn_DPORT(sn) \
  (((uint16_t)WIZCHIP_READ(Sn_DPORT(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_DPORT(sn),1)))
 
 #define setSn_MSSR(sn, mss) { \
  WIZCHIP_WRITE(Sn_MSSR(sn), (uint8_t)(mss>>8)); \
  WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_MSSR(sn),1), (uint8_t) mss); \
  }
 
 #define getSn_MSSR(sn) \
  (((uint16_t)WIZCHIP_READ(Sn_MSSR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_MSSR(sn),1)))
 
 //M20150601 : Fixed Wrong Register address
 /*
 #define setSn_PROTO(sn, proto) \
  WIZCHIP_WRITE(Sn_TOS(sn), tos)
 */
 #define setSn_PROTO(sn, proto) \
  WIZCHIP_WRITE(Sn_PROTO(sn), proto)
 
 //M20150601 : Fixed Wrong Register address
 /*
 #define getSn_PROTO(sn) \
  WIZCHIP_READ(Sn_TOS(sn))
 */
 #define getSn_PROTO(sn) \
  WIZCHIP_READ(Sn_PROTO(sn))
 
 #define setSn_TOS(sn, tos) \
  WIZCHIP_WRITE(Sn_TOS(sn), tos)
 
 #define getSn_TOS(sn) \
  WIZCHIP_READ(Sn_TOS(sn))
 
 #define setSn_TTL(sn, ttl) \
  WIZCHIP_WRITE(Sn_TTL(sn), ttl)
 
 #define getSn_TTL(sn) \
  WIZCHIP_READ(Sn_TTL(sn))
 
 #define setSn_RXMEM_SIZE(sn, rxmemsize) \
  WIZCHIP_WRITE(Sn_RXMEM_SIZE(sn),rxmemsize)
 
 #define setSn_RXBUF_SIZE(sn,rxmemsize) setSn_RXMEM_SIZE(sn,rxmemsize)
 
 #define getSn_RXMEM_SIZE(sn) \
  WIZCHIP_READ(Sn_RXMEM_SIZE(sn))
 
 #define getSn_RXBUF_SIZE(sn) getSn_RXMEM_SIZE(sn)
 
 #define setSn_TXMEM_SIZE(sn, txmemsize) \
  WIZCHIP_WRITE(Sn_TXMEM_SIZE(sn), txmemsize)
 
 #define setSn_TXBUF_SIZE(sn, txmemsize) setSn_TXMEM_SIZE(sn,txmemsize)
 
 #define getSn_TXMEM_SIZE(sn) \
  WIZCHIP_READ(Sn_TXMEM_SIZE(sn))
 
 #define getSn_TXBUF_SIZE(sn) getSn_TXMEM_SIZE(sn)
 
 uint16_t getSn_TX_FSR(uint8_t sn);
 
 #define getSn_TX_RD(sn) \
  (((uint16_t)WIZCHIP_READ(Sn_TX_RD(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_RD(sn),1)))
 
 #define setSn_TX_WR(sn, txwr) { \
  WIZCHIP_WRITE(Sn_TX_WR(sn), (uint8_t)(txwr>>8)); \
  WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_TX_WR(sn),1), (uint8_t) txwr); \
  }
 
 #define getSn_TX_WR(sn) \
  (((uint16_t)WIZCHIP_READ(Sn_TX_WR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_WR(sn),1)))
 
 uint16_t getSn_RX_RSR(uint8_t sn);
 
 #define setSn_RX_RD(sn, rxrd) { \
  WIZCHIP_WRITE(Sn_RX_RD(sn), (uint8_t)(rxrd>>8)); \
  WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_RX_RD(sn),1), (uint8_t) rxrd); \
  }
 
 #define getSn_RX_RD(sn) \
  (((uint16_t)WIZCHIP_READ(Sn_RX_RD(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RX_RD(sn),1)))
 
 #define setSn_RX_WR(sn, rxwr) { \
  WIZCHIP_WRITE(Sn_RX_WR(sn), (uint8_t)(rxwr>>8)); \
  WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_RX_WR(sn),1), (uint8_t) rxwr); \
  }
 
 
 #define getSn_RX_WR(sn) \
  (((uint16_t)WIZCHIP_READ(Sn_RX_WR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RX_WR(sn),1)))
 
 #define setSn_IMR(sn ,imr) \
  WIZCHIP_WRITE(Sn_IMR(sn), imr)
 
 #define getSn_IMR(sn) \
  WIZCHIP_READ(Sn_IMR(sn))
 
 #define setSn_FRAG(sn, frag) { \
  WIZCHIP_WRITE(Sn_FRAG(sn), (uint8_t)(frag >>8)); \
  WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_FRAG(sn),1), (uint8_t) frag); \
  }
 
 #define getSn_FRAG(sn) \
  (((uint16_t)WIZCHIP_READ(Sn_FRAG(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_FRAG(sn),1)))
 
 #define getSn_RxMAX(sn) \
  ((uint16_t)getSn_RXMEM_SIZE(sn) << 10)
 
 #define getSn_TxMAX(sn) \
  ((uint16_t)getSn_TXMEM_SIZE(sn) << 10)
 
 #define getSn_RxMASK(sn) \
  ((uint16_t)getSn_RxMAX(sn) - 1)
 
 #define getSn_TxMASK(sn) \
  ((uint16_t)getSn_TxMAX(sn) - 1)
 
 uint16_t getSn_RxBASE(uint8_t sn);
 
 uint16_t getSn_TxBASE(uint8_t sn);
 
 // Sn_TXBUF & Sn_RXBUF IO function //
 
 void wiz_send_data(uint8_t sn, uint8_t *wizdata, uint16_t len);
 
 void wiz_recv_data(uint8_t sn, uint8_t *wizdata, uint16_t len);
 
 void wiz_recv_ignore(uint8_t sn, uint16_t len);
 
 #endif
 
 #endif //_W5200_H_
 
 
 
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