Socket APIs: Ethernet/W5200/w5200.h Source File

Wiznet Socket API

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w5200.h
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1 //* ****************************************************************************
38 //
39 //*****************************************************************************
40 
41 #ifndef _W5200_H
42 #define _W5200_H
43 #include <stdint.h>
44 #include "wizchip_conf.h"
45 
47 #if (_WIZCHIP_ == 5200)
48 
50 #define _WIZCHIP_SN_BASE_ (0x4000)
51 #define _WIZCHIP_SN_SIZE_ (0x0100)
52 #define _WIZCHIP_IO_TXBUF_ (0x8000) /* Internal Tx buffer address of the iinchip */
53 #define _WIZCHIP_IO_RXBUF_ (0xC000) /* Internal Rx buffer address of the iinchip */
54 
55 #define _W5200_SPI_READ_ (0x00 << 7)
56 #define _W5200_SPI_WRITE_ (0x01 << 7)
57 
58 #define WIZCHIP_CREG_BLOCK 0x00
59 #define WIZCHIP_SREG_BLOCK(N) (_WIZCHIP_SN_BASE_+ _WIZCHIP_SN_SIZE_*N)
60 
61 #define WIZCHIP_OFFSET_INC(ADDR, N) (ADDR + N)
62 
63 #if (_WIZCHIP_IO_MODE_ & _WIZCHIP_IO_MODE_BUS_)
64  #define IDM_AR0 ((_WIZCHIP_IO_BASE_ + 0x0001))
65  #define IDM_AR1 ((_WIZCHIP_IO_BASE_ + 0x0002))
66  #define IDM_DR ((_WIZCHIP_IO_BASE_ + 0x0003))
67  #define _W5200_IO_BASE_ 0x0000
68 #elif (_WIZCHIP_IO_MODE_ & _WIZCHIP_IO_MODE_SPI_)
69  #define _W5200_IO_BASE_ 0x0000
70 #endif
71 
73 // Definition For Legacy Chip Driver //
75 #define IINCHIP_READ(ADDR) WIZCHIP_READ(ADDR)
76 #define IINCHIP_WRITE(ADDR,VAL) WIZCHIP_WRITE(ADDR,VAL)
77 #define IINCHIP_READ_BUF(ADDR,BUF,LEN) WIZCHIP_READ_BUF(ADDR,BUF,LEN)
78 #define IINCHIP_WRITE_BUF(ADDR,BUF,LEN) WIZCHIP_WRITE(ADDR,BUF,LEN)
79 
80 
81 //----------- defgroup --------------------------------
82 
185  //-----------------------------------------------------------------------------------
186 
187 //----------------------------- W5200 Common Registers IOMAP -----------------------------
204 #if (_WIZCHIP_IO_MODE_ & _WIZCHIP_IO_MODE_BUS_)
205  #define MR (_WIZCHIP_IO_BASE_ + (0x0000)) // Mode
206 #else
207  #define MR (_W5200_IO_BASE_ + (0x0000)) // Mode
208 #endif
209 
215 #define GAR (_W5200_IO_BASE_ + (0x0001)) // GW Address
216 
222 #define SUBR (_W5200_IO_BASE_ + (0x0005)) // SN Mask Address
223 
229 #define SHAR (_W5200_IO_BASE_ + (0x0009)) // Source Hardware Address
230 
236 #define SIPR (_W5200_IO_BASE_ + (0x000F)) // Source IP Address
237 
238 // Reserved (_W5200_IO_BASE_ + (0x0013))
239 // Reserved (_W5200_IO_BASE_ + (0x0014))
240 
254 #define IR (_W5200_IO_BASE_ + (0x0015)) // Interrupt
255 
265 #define _IMR_ (_W5200_IO_BASE_ + (0x0016)) // Socket Interrupt Mask
266 
275 #define _RTR_ (_W5200_IO_BASE_ + (0x0017)) // Retry Time
276 
283 #define _RCR_ (_W5200_IO_BASE_ + (0x0019)) // Retry Count
284 
285 // Reserved (_W5200_IO_BASE_ + (0x001A))
286 // Reserved (_W5200_IO_BASE_ + (0x001B))
287 
294 #define PATR (_W5200_IO_BASE_ + (0x001C))
295 
302 #define PPPALGO (_W5200_IO_BASE_ + (0x001E)) // Authentication Algorithm in PPPoE
303 
309 #define VERSIONR (_W5200_IO_BASE_ + (0x001F)) // Chip version
310 
311 // Reserved (_W5200_IO_BASE_ + (0x0020))
312 // Reserved (_W5200_IO_BASE_ + (0x0021))
313 // Reserved (_W5200_IO_BASE_ + (0x0022))
314 // Reserved (_W5200_IO_BASE_ + (0x0023))
315 // Reserved (_W5200_IO_BASE_ + (0x0024))
316 // Reserved (_W5200_IO_BASE_ + (0x0025))
317 // Reserved (_W5200_IO_BASE_ + (0x0026))
318 // Reserved (_W5200_IO_BASE_ + (0x0027))
319 
325 #define PTIMER (_W5200_IO_BASE_ + (0x0028)) // PPP LCP RequestTimer
326 
332 #define PMAGIC (_W5200_IO_BASE_ + (0x0029)) // PPP LCP Magic number
333 
334 // Reserved (_W5200_IO_BASE_ + (0x002A))
335 // Reserved (_W5200_IO_BASE_ + (0x002B))
336 // Reserved (_W5200_IO_BASE_ + (0x002C))
337 // Reserved (_W5200_IO_BASE_ + (0x002D))
338 // Reserved (_W5200_IO_BASE_ + (0x002E))
339 // Reserved (_W5200_IO_BASE_ + (0x002F))
340 
346 #define INTLEVEL (_W5200_IO_BASE_ + (0x0030)) // Interrupt Low Level Timer
347 
348 // Reserved (_W5200_IO_BASE_ + (0x0032))
349 // Reserved (_W5200_IO_BASE_ + (0x0033))
350 
357 #define IR2 (_W5200_IO_BASE_ + (0x0034)) // Socket Interrupt
358 
371 #define PHYSTATUS (_W5200_IO_BASE_ + (0x0035)) // PHY Status
372 
389 #define IMR2 (_W5200_IO_BASE_ + (0x0036)) // Interrupt Mask
390 
391 
392 //----------------------------- W5200 Socket Registers -----------------------------
393 
394 //--------------------------- For Backward Compatibility ---------------------------
395 
429 #define Sn_MR(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0000)) // socket Mode register
430 
457 #define Sn_CR(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0001)) // channel Sn_CR register
458 
478 #define Sn_IR(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0002)) // channel interrupt register
479 
501 #define Sn_SR(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0003)) // channel status register
502 
509 #define Sn_PORT(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0004)) // source port register
510 
517 #define Sn_DHAR(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0006)) // Peer MAC register address
518 
527 #define Sn_DIPR(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x000C)) // Peer IP register address
528 
537 #define Sn_DPORT(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0010)) // Peer port register address
538 
544 #define Sn_MSSR(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0012)) // Maximum Segment Size(Sn_MSSR0) register address
545 
552 #define Sn_PROTO(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0014)) // Protocol of IP Header field register in IP raw mode
553 
560 #define Sn_TOS(sn) (WIZCHIP_SREG_BLOCK(sn) + 0x0015) // IP Type of Service(TOS) Register
561 
568 #define Sn_TTL(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0016)) // IP Time to live(TTL) Register
569 
570 // Reserved (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0017))
571 // Reserved (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0018))
572 // Reserved (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0019))
573 // Reserved (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x001A))
574 // Reserved (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x001B))
575 // Reserved (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x001C))
576 // Reserved (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x001D))
577 
588 #define Sn_RXMEM_SIZE(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x001E)) // Receive memory size reigster
589 
599 #define Sn_TXMEM_SIZE(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x001F)) // Transmit memory size reigster
600 
610 #define Sn_TX_FSR(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0020)) // Transmit free memory size register
611 
622 #define Sn_TX_RD(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0022)) // Transmit memory read pointer register address
623 
636 #define Sn_TX_WR(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0024)) // Transmit memory write pointer register address
637 
645 #define Sn_RX_RSR(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0026)) // Received data size register
646 
658 #define Sn_RX_RD(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x0028)) // Read point of Receive memory
659 
667 #define Sn_RX_WR(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x002A)) // Write point of Receive memory
668 
677 #define Sn_IMR(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x002C)) // socket interrupt mask register
678 
684 #define Sn_FRAG(sn) (_W5200_IO_BASE_ + WIZCHIP_SREG_BLOCK(sn) + (0x002D)) // frag field value in IP header register
685 
686 
687 //----------------------------- W5200 Register values -----------------------------
688 
689 /* MODE register values */
694 #define MR_RST 0x80
695 
696 
705 #define MR_WOL 0x20
706 
707 
713 #define MR_PB 0x10
714 
715 
721 #define MR_PPPOE 0x08
722 
723 
730 #define MR_AI 0x02
731 
732 
738 #define MR_IND 0x01
739 
740 /* IR register values */
745 #define IR_CONFLICT 0x80
746 
747 
751 #define IR_PPPoE 0x20
752 
753 
757 #define PHYSTATUS_LINK 0x20
758 
763 #define PHYSTATUS_POWERSAVE 0x10
764 
769 #define PHYSTATUS_POWERDOWN 0x08
770 
771 // Sn_MR values
772 /* Sn_MR Default values */
777 #define Sn_MR_CLOSE 0x00
778 
779 
783 #define Sn_MR_TCP 0x01
784 
785 
789 #define Sn_MR_UDP 0x02
790 #define Sn_MR_IPRAW 0x03
791 
792 
797 #define Sn_MR_MACRAW 0x04
798 
799 
804 #define Sn_MR_PPPOE 0x05
805 
806 
814 #define Sn_MR_ND 0x20
815 
816 /* Sn_MR Default values */
825 #define Sn_MR_MC Sn_MR_ND
826 
827 
834 #define Sn_MR_MF 0x40
835 #define Sn_MR_MFEN Sn_MR_MF
836 
837 /* Sn_MR Default values */
846 #define Sn_MR_MULTI 0x80
847 
848 /* Sn_CR values */
863 #define Sn_CR_OPEN 0x01
864 
865 
874 #define Sn_CR_LISTEN 0x02
875 
876 
886 #define Sn_CR_CONNECT 0x04
887 
888 
899 #define Sn_CR_DISCON 0x08
900 
901 
905 #define Sn_CR_CLOSE 0x10
906 
913 #define Sn_CR_SEND 0x20
914 
923 #define Sn_CR_SEND_MAC 0x21
924 
931 #define Sn_CR_SEND_KEEP 0x22
932 
939 #define Sn_CR_RECV 0x40
940 
945 #define Sn_CR_PCON 0x23
946 
951 #define Sn_CR_PDISCON 0x24
952 
957 #define Sn_CR_PCR 0x25
958 
963 #define Sn_CR_PCN 0x26
964 
969 #define Sn_CR_PCJ 0x27
970 
971 /* Sn_IR values */
976 #define Sn_IR_PRECV 0x80
977 
982 #define Sn_IR_PFAIL 0x40
983 
988 #define Sn_IR_PNEXT 0x20
989 
994 #define Sn_IR_SENDOK 0x10
995 
996 
1000 #define Sn_IR_TIMEOUT 0x08
1001 
1002 
1006 #define Sn_IR_RECV 0x04
1007 
1012 #define Sn_IR_DISCON 0x02
1013 
1018 #define Sn_IR_CON 0x01
1019 
1020 /* Sn_SR values */
1026 #define SOCK_CLOSED 0x00
1027 
1028 
1034 #define SOCK_INIT 0x13
1035 
1036 
1042 #define SOCK_LISTEN 0x14
1043 
1051 #define SOCK_SYNSENT 0x15
1052 
1059 #define SOCK_SYNRECV 0x16
1060 
1068 #define SOCK_ESTABLISHED 0x17
1069 
1076 #define SOCK_FIN_WAIT 0x18
1077 
1084 #define SOCK_CLOSING 0x1A
1085 
1092 #define SOCK_TIME_WAIT 0x1B
1093 
1100 #define SOCK_CLOSE_WAIT 0x1C
1101 
1107 #define SOCK_LAST_ACK 0x1D
1108 
1115 #define SOCK_UDP 0x22
1116 
1117 
1123 #define SOCK_IPRAW 0x32
1124 
1125 
1131 #define SOCK_MACRAW 0x42
1132 
1133 
1140 #define SOCK_PPPOE 0x5F
1141 
1142 // IP PROTOCOL
1143 #define IPPROTO_IP 0
1144 #define IPPROTO_ICMP 1
1145 #define IPPROTO_IGMP 2
1146 #define IPPROTO_GGP 3
1147 #define IPPROTO_TCP 6
1148 #define IPPROTO_PUP 12
1149 #define IPPROTO_UDP 17
1150 #define IPPROTO_IDP 22
1151 #define IPPROTO_ND 77
1152 #define IPPROTO_RAW 255
1153 
1154 
1165 #define WIZCHIP_CRITICAL_ENTER() WIZCHIP.CRIS._enter()
1166 
1167 #ifdef _exit
1168 #undef _exit
1169 #endif
1170 
1182 #define WIZCHIP_CRITICAL_EXIT() WIZCHIP.CRIS._exit()
1183 
1184 
1185 
1187 // Basic I/O Function //
1189 
1195 uint8_t WIZCHIP_READ (uint32_t AddrSel);
1196 
1204 void WIZCHIP_WRITE(uint32_t AddrSel, uint8_t wb );
1205 
1213 void WIZCHIP_READ_BUF (uint32_t AddrSel, uint8_t* pBuf, uint16_t len);
1214 
1222 void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t* pBuf, uint16_t len);
1223 
1224 
1226 // Common Register IO function //
1228 
1235 #if (_WIZCHIP_IO_MODE_ & _WIZCHIP_IO_MODE_SPI_)
1236  #define setMR(mr) WIZCHIP_WRITE(MR,mr)
1237 #else
1238  #define setMR(mr) (*((uint8_t*)MR) = mr)
1239 #endif
1240 
1247 #if (_WIZCHIP_IO_MODE_ & _WIZCHIP_IO_MODE_SPI_)
1248  #define getMR() WIZCHIP_READ(MR)
1249 #else
1250  #define getMR() (*(uint8_t*)MR)
1251 #endif
1252 
1259 #define setGAR(gar) \
1260  WIZCHIP_WRITE_BUF(GAR,gar,4)
1261 
1268 #define getGAR(gar) \
1269  WIZCHIP_READ_BUF(GAR,gar,4)
1270 
1280 #define setSUBR(subr) \
1281  WIZCHIP_WRITE_BUF(SUBR, subr,4)
1282 
1289 #define getSUBR(subr) \
1290  WIZCHIP_READ_BUF(SUBR, subr, 4)
1291 
1298 #define setSHAR(shar) \
1299  WIZCHIP_WRITE_BUF(SHAR, shar, 6)
1300 
1307 #define getSHAR(shar) \
1308  WIZCHIP_READ_BUF(SHAR, shar, 6)
1309 
1316 #define setSIPR(sipr) \
1317  WIZCHIP_WRITE_BUF(SIPR, sipr, 4)
1318 
1325 #define getSIPR(sipr) \
1326  WIZCHIP_READ_BUF(SIPR, sipr, 4)
1327 
1334 #define setIR(ir) \
1335  WIZCHIP_WRITE(IR, (ir & 0xA0))
1336 
1342 #define getIR() \
1343  (WIZCHIP_READ(IR) & 0xA0)
1344 
1351 //M20150410 : Replace _IMR_ with IMR2 for integrating with ioLibrary
1352 /*
1353 #define setIMR(imr) \
1354  WIZCHIP_WRITE(_IMR_, imr)
1355 */
1356 #define setIMR(imr) \
1357  WIZCHIP_WRITE(IMR2, imr & 0xA0)
1358 
1365 //M20150410 : Replace _IMR_ with IMR2 for integrating with ioLibrary
1366 /*
1367 #define getIMR() \
1368  WIZCHIP_READ(_IMR_)
1369 */
1370 #define getIMR() \
1371  (WIZCHIP_READ(IMR2) & 0xA0)
1372 
1379 #define setRTR(rtr) {\
1380  WIZCHIP_WRITE(_RTR_, (uint8_t)(rtr >> 8)); \
1381  WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(_RTR_,1), (uint8_t) rtr); \
1382  }
1383 
1390 #define getRTR() \
1391  (((uint16_t)WIZCHIP_READ(_RTR_) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(_RTR_,1)))
1392 
1399 #define setRCR(rcr) \
1400  WIZCHIP_WRITE(_RCR_, rcr)
1401 
1408 #define getRCR() \
1409  WIZCHIP_READ(_RCR_)
1410 
1416 #define getPATR() \
1417  (((uint16_t)WIZCHIP_READ(PATR) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(PATR,1)))
1418 
1424 #define getPPPALGO() \
1425  WIZCHIP_READ(PPPALGO)
1426 
1427 
1433 #define getVERSIONR() \
1434  WIZCHIP_READ(VERSIONR)
1435 
1442 #define setPTIMER(ptimer) \
1443  WIZCHIP_WRITE(PTIMER, ptimer)
1444 
1451 #define getPTIMER() \
1452  WIZCHIP_READ(PTIMER)
1453 
1460 #define setPMAGIC(pmagic) \
1461  WIZCHIP_WRITE(PMAGIC, pmagic)
1462 
1469 #define getPMAGIC() \
1470  WIZCHIP_READ(PMAGIC)
1471 
1478 #define setINTLEVEL(intlevel) {\
1479  WIZCHIP_WRITE(INTLEVEL, (uint8_t)(intlevel >> 8)); \
1480  WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(INTLEVEL,1), (uint8_t) intlevel); \
1481  }
1482 
1488 #define getINTLEVEL() \
1489  (((uint16_t)WIZCHIP_READ(INTLEVEL) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(INTLEVEL,1)))
1490 
1497 #define setIR2(ir2) \
1498  WIZCHIP_WRITE(IR2, ir2)
1499 #define setSIR(ir2) setIR2(ir2)
1500 
1507 #define getIR2() \
1508  WIZCHIP_READ(IR2)
1509 #define getSIR() getIR2()
1510 
1516 #define getPHYSTATUS() \
1517  WIZCHIP_READ(PHYSTATUS)
1518 
1526  //M20150410 : Replace IMR2 with _IMR_ for integrating with ioLibrary
1527 /*
1528 #define setIMR2(imr2) \
1529  WIZCHIP_WRITE(IMR2, (imr2 & 0xA0))
1530 */
1531 #define setIMR2(imr2) \
1532  WIZCHIP_WRITE(_IMR_, imr2)
1533 #define setSIMR(imr2) setIMR2(imr2)
1534 
1541  //M20150410 : Replace IMR2 with _IMR_ for integrating with ioLibrary
1542 /*
1543 #define getIMR2() \
1544  (WIZCHIP_READ(IMR2) & 0xA0)
1545 */
1546 #define getIMR2() \
1547  WIZCHIP_READ(_IMR_)
1548 #define getSIMR() getIMR2()
1549 // Socket N register I/O function //
1552 
1559 #define setSn_MR(sn, mr) \
1560  WIZCHIP_WRITE(Sn_MR(sn),mr)
1561 
1569 #define getSn_MR(sn) \
1570  WIZCHIP_READ(Sn_MR(sn))
1571 
1579 #define setSn_CR(sn, cr) \
1580  WIZCHIP_WRITE(Sn_CR(sn), cr)
1581 
1589 #define getSn_CR(sn) \
1590  WIZCHIP_READ(Sn_CR(sn))
1591 
1599 #define setSn_IR(sn, ir) \
1600  WIZCHIP_WRITE(Sn_IR(sn), ir)
1601 
1609 #define getSn_IR(sn) \
1610  WIZCHIP_READ(Sn_IR(sn))
1611 
1619 #define setSn_IMR(sn, imr) \
1620  WIZCHIP_WRITE(Sn_IMR(sn), imr)
1621 
1629 #define getSn_IMR(sn) \
1630  WIZCHIP_READ(Sn_IMR(sn))
1631 
1638 #define getSn_SR(sn) \
1639  WIZCHIP_READ(Sn_SR(sn))
1640 
1648 #define setSn_PORT(sn, port) { \
1649  WIZCHIP_WRITE(Sn_PORT(sn), (uint8_t)(port >> 8)); \
1650  WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_PORT(sn),1), (uint8_t) port); \
1651  }
1652 
1660 #define getSn_PORT(sn) \
1661  (((uint16_t)WIZCHIP_READ(Sn_PORT(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_PORT(sn),1)))
1662 
1670 #define setSn_DHAR(sn, dhar) \
1671  WIZCHIP_WRITE_BUF(Sn_DHAR(sn), dhar, 6)
1672 
1680 #define getSn_DHAR(sn, dhar) \
1681  WIZCHIP_READ_BUF(Sn_DHAR(sn), dhar, 6)
1682 
1690 #define setSn_DIPR(sn, dipr) \
1691  WIZCHIP_WRITE_BUF(Sn_DIPR(sn), dipr, 4)
1692 
1700 #define getSn_DIPR(sn, dipr) \
1701  WIZCHIP_READ_BUF(Sn_DIPR(sn), dipr, 4)
1702 
1710 #define setSn_DPORT(sn, dport) { \
1711  WIZCHIP_WRITE(Sn_DPORT(sn), (uint8_t) (dport>>8)); \
1712  WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_DPORT(sn),1), (uint8_t) dport); \
1713  }
1714 
1722 #define getSn_DPORT(sn) \
1723  (((uint16_t)WIZCHIP_READ(Sn_DPORT(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_DPORT(sn),1)))
1724 
1732 #define setSn_MSSR(sn, mss) { \
1733  WIZCHIP_WRITE(Sn_MSSR(sn), (uint8_t)(mss>>8)); \
1734  WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_MSSR(sn),1), (uint8_t) mss); \
1735  }
1736 
1744 #define getSn_MSSR(sn) \
1745  (((uint16_t)WIZCHIP_READ(Sn_MSSR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_MSSR(sn),1)))
1746 
1754 //M20150601 : Fixed Wrong Register address
1755 /*
1756 #define setSn_PROTO(sn, proto) \
1757  WIZCHIP_WRITE(Sn_TOS(sn), tos)
1758 */
1759 #define setSn_PROTO(sn, proto) \
1760  WIZCHIP_WRITE(Sn_PROTO(sn), proto)
1761 
1769 //M20150601 : Fixed Wrong Register address
1770 /*
1771 #define getSn_PROTO(sn) \
1772  WIZCHIP_READ(Sn_TOS(sn))
1773 */
1774 #define getSn_PROTO(sn) \
1775  WIZCHIP_READ(Sn_PROTO(sn))
1776 
1784 #define setSn_TOS(sn, tos) \
1785  WIZCHIP_WRITE(Sn_TOS(sn), tos)
1786 
1794 #define getSn_TOS(sn) \
1795  WIZCHIP_READ(Sn_TOS(sn))
1796 
1804 #define setSn_TTL(sn, ttl) \
1805  WIZCHIP_WRITE(Sn_TTL(sn), ttl)
1806 
1814 #define getSn_TTL(sn) \
1815  WIZCHIP_READ(Sn_TTL(sn))
1816 
1824 #define setSn_RXMEM_SIZE(sn, rxmemsize) \
1825  WIZCHIP_WRITE(Sn_RXMEM_SIZE(sn),rxmemsize)
1826 
1827 #define setSn_RXBUF_SIZE(sn,rxmemsize) setSn_RXMEM_SIZE(sn,rxmemsize)
1828 
1836 #define getSn_RXMEM_SIZE(sn) \
1837  WIZCHIP_READ(Sn_RXMEM_SIZE(sn))
1838 
1839 #define getSn_RXBUF_SIZE(sn) getSn_RXMEM_SIZE(sn)
1840 
1848 #define setSn_TXMEM_SIZE(sn, txmemsize) \
1849  WIZCHIP_WRITE(Sn_TXMEM_SIZE(sn), txmemsize)
1850 
1851 #define setSn_TXBUF_SIZE(sn, txmemsize) setSn_TXMEM_SIZE(sn,txmemsize)
1852 
1860 #define getSn_TXMEM_SIZE(sn) \
1861  WIZCHIP_READ(Sn_TXMEM_SIZE(sn))
1862 
1863 #define getSn_TXBUF_SIZE(sn) getSn_TXMEM_SIZE(sn)
1864 
1871 uint16_t getSn_TX_FSR(uint8_t sn);
1872 
1879 #define getSn_TX_RD(sn) \
1880  (((uint16_t)WIZCHIP_READ(Sn_TX_RD(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_RD(sn),1)))
1881 
1889 #define setSn_TX_WR(sn, txwr) { \
1890  WIZCHIP_WRITE(Sn_TX_WR(sn), (uint8_t)(txwr>>8)); \
1891  WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_TX_WR(sn),1), (uint8_t) txwr); \
1892  }
1893 
1901 #define getSn_TX_WR(sn) \
1902  (((uint16_t)WIZCHIP_READ(Sn_TX_WR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_WR(sn),1)))
1903 
1910 uint16_t getSn_RX_RSR(uint8_t sn);
1911 
1919 #define setSn_RX_RD(sn, rxrd) { \
1920  WIZCHIP_WRITE(Sn_RX_RD(sn), (uint8_t)(rxrd>>8)); \
1921  WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_RX_RD(sn),1), (uint8_t) rxrd); \
1922  }
1923 
1931 #define getSn_RX_RD(sn) \
1932  (((uint16_t)WIZCHIP_READ(Sn_RX_RD(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RX_RD(sn),1)))
1933 
1941 #define setSn_RX_WR(sn, rxwr) { \
1942  WIZCHIP_WRITE(Sn_RX_WR(sn), (uint8_t)(rxwr>>8)); \
1943  WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_RX_WR(sn),1), (uint8_t) rxwr); \
1944  }
1945 
1946 
1953 #define getSn_RX_WR(sn) \
1954  (((uint16_t)WIZCHIP_READ(Sn_RX_WR(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_RX_WR(sn),1)))
1955 
1963 #define setSn_IMR(sn ,imr) \
1964  WIZCHIP_WRITE(Sn_IMR(sn), imr)
1965 
1973 #define getSn_IMR(sn) \
1974  WIZCHIP_READ(Sn_IMR(sn))
1975 
1983 #define setSn_FRAG(sn, frag) { \
1984  WIZCHIP_WRITE(Sn_FRAG(sn), (uint8_t)(frag >>8)); \
1985  WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_FRAG(sn),1), (uint8_t) frag); \
1986  }
1987 
1995 #define getSn_FRAG(sn) \
1996  (((uint16_t)WIZCHIP_READ(Sn_FRAG(sn)) << 8) + WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_FRAG(sn),1)))
1997 
2004 #define getSn_RxMAX(sn) \
2005  ((uint16_t)getSn_RXMEM_SIZE(sn) << 10)
2006 
2013 #define getSn_TxMAX(sn) \
2014  ((uint16_t)getSn_TXMEM_SIZE(sn) << 10)
2015 
2022 #define getSn_RxMASK(sn) \
2023  ((uint16_t)getSn_RxMAX(sn) - 1)
2024 
2031 #define getSn_TxMASK(sn) \
2032  ((uint16_t)getSn_TxMAX(sn) - 1)
2033 
2040 uint16_t getSn_RxBASE(uint8_t sn);
2041 
2048 uint16_t getSn_TxBASE(uint8_t sn);
2049 
2051 // Sn_TXBUF & Sn_RXBUF IO function //
2053 
2067 void wiz_send_data(uint8_t sn, uint8_t *wizdata, uint16_t len);
2068 
2083 void wiz_recv_data(uint8_t sn, uint8_t *wizdata, uint16_t len);
2084 
2092 void wiz_recv_ignore(uint8_t sn, uint16_t len);
2093 
2095 #endif
2096 
2098 #endif //_W5200_H_
2099 
2100 
2101 
getSn_RxBASE
uint16_t getSn_RxBASE(uint8_t sn)
Get the base address of socket sn RX buffer.
WIZCHIP_WRITE_BUF
void WIZCHIP_WRITE_BUF(uint32_t AddrSel, uint8_t *pBuf, uint16_t len)
It writes sequence data to registers.
WIZCHIP_WRITE
void WIZCHIP_WRITE(uint32_t AddrSel, uint8_t wb)
It writes 1 byte value to a register.
getSn_RX_RSR
uint16_t getSn_RX_RSR(uint8_t sn)
Get Sn_RX_RSR register.
wiz_recv_ignore
void wiz_recv_ignore(uint8_t sn, uint16_t len)
It discard the received data in RX memory.
WIZCHIP_READ_BUF
void WIZCHIP_READ_BUF(uint32_t AddrSel, uint8_t *pBuf, uint16_t len)
It reads sequence data from registers.
wiz_send_data
void wiz_send_data(uint8_t sn, uint8_t *wizdata, uint16_t len)
It copies data to internal TX memory.
getSn_TX_FSR
uint16_t getSn_TX_FSR(uint8_t sn)
Get Sn_TX_FSR register.
wiz_recv_data
void wiz_recv_data(uint8_t sn, uint8_t *wizdata, uint16_t len)
It copies data to your buffer from internal RX memory.
WIZCHIP_READ
uint8_t WIZCHIP_READ(uint32_t AddrSel)
It reads 1 byte value from a register.
getSn_TxBASE
uint16_t getSn_TxBASE(uint8_t sn)
Get the base address of socket sn TX buffer.
wizchip_conf.h
WIZCHIP Config Header File.
Generated on Wed May 4 2016 16:43:58 for Socket APIs by   doxygen 1.8.9.1
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