Common register group
It set the basic for the networking
It set the configuration such as interrupt, network information, ICMP, etc.
More...
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| #define | MR (_W5200_IO_BASE_ + (0x0000)) |
| | Mode Register address(R/W)
MR is used for S/W reset, ping block mode, PPPoE mode and etc. More...
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| #define | GAR (_W5200_IO_BASE_ + (0x0001)) |
| | Gateway IP Register address(R/W) More...
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| #define | SUBR (_W5200_IO_BASE_ + (0x0005)) |
| | Subnet mask Register address(R/W) More...
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| #define | SHAR (_W5200_IO_BASE_ + (0x0009)) |
| | Source MAC Register address(R/W) More...
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| #define | SIPR (_W5200_IO_BASE_ + (0x000F)) |
| | Source IP Register address(R/W) More...
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| #define | IR (_W5200_IO_BASE_ + (0x0015)) |
| | Interrupt Register(R/W) More...
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| #define | _IMR_ (_W5200_IO_BASE_ + (0x0016)) |
| | Socket Interrupt Mask Register(R/W) More...
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| #define | _RTR_ (_W5200_IO_BASE_ + (0x0017)) |
| | Timeout register address( 1 is 100us )(R/W) More...
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| #define | _RCR_ (_W5200_IO_BASE_ + (0x0019)) |
| | Retry count register(R/W) More...
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| #define | PATR (_W5200_IO_BASE_ + (0x001C)) |
| | PPP LCP Request Timer register in PPPoE mode(R) More...
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| #define | PPPALGO (_W5200_IO_BASE_ + (0x001E)) |
| | PPP LCP Request Timer register in PPPoE mode(R) More...
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| #define | VERSIONR (_W5200_IO_BASE_ + (0x001F)) |
| | chip version register address(R) More...
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| #define | PTIMER (_W5200_IO_BASE_ + (0x0028)) |
| | PPP LCP Request Timer register in PPPoE mode(R) More...
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| #define | PMAGIC (_W5200_IO_BASE_ + (0x0029)) |
| | PPP LCP Magic number register in PPPoE mode(R) More...
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| #define | INTLEVEL (_W5200_IO_BASE_ + (0x0030)) |
| | Set Interrupt low level timer register address(R/W) More...
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| #define | IR2 (_W5200_IO_BASE_ + (0x0034)) |
| | Socket Interrupt Register(R/W) More...
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| #define | PHYSTATUS (_W5200_IO_BASE_ + (0x0035)) |
| | PHYSTATUS(R/W) More...
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| #define | IMR2 (_W5200_IO_BASE_ + (0x0036)) |
| | Interrupt mask register(R/W) More...
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Common register group
It set the basic for the networking
It set the configuration such as interrupt, network information, ICMP, etc.
- See also
- MR : Mode register.
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GAR, SUBR, SHAR, SIPR
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INTLEVEL, IR, IMR, IR2, IMR2 : Interrupt.
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RTR, RCR : Data retransmission.
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PTIMER, PMAGIC : PPPoE.
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PHYSTATUS, VERSIONR : etc.
| #define MR (_W5200_IO_BASE_ + (0x0000)) |
Mode Register address(R/W)
MR is used for S/W reset, ping block mode, PPPoE mode and etc.
Each bit of MR defined as follows.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RST | Reserved | WOL | PB | PPPoE | Reserved | AI | IND |
Definition at line 207 of file w5200.h.
| #define GAR (_W5200_IO_BASE_ + (0x0001)) |
Gateway IP Register address(R/W)
GAR configures the default gateway address.
Definition at line 215 of file w5200.h.
| #define SUBR (_W5200_IO_BASE_ + (0x0005)) |
Subnet mask Register address(R/W)
SUBR configures the subnet mask address.
Definition at line 222 of file w5200.h.
| #define SHAR (_W5200_IO_BASE_ + (0x0009)) |
Source MAC Register address(R/W)
SHAR configures the source hardware address.
Definition at line 229 of file w5200.h.
| #define SIPR (_W5200_IO_BASE_ + (0x000F)) |
Source IP Register address(R/W)
SIPR configures the source IP address.
Definition at line 236 of file w5200.h.
| #define IR (_W5200_IO_BASE_ + (0x0015)) |
Interrupt Register(R/W)
IR indicates the interrupt status. Each bit of IR will be still until the bit will be written to by the host. If IR is not equal to x00 INTn PIN is asserted to low until it is x00
Each bit of IR defined as follows.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CONFLICT | Reserved | PPPoE | Reserved | Reserved | Reserved | Reserved | Reserved |
Definition at line 254 of file w5200.h.
| #define _IMR_ (_W5200_IO_BASE_ + (0x0016)) |
Socket Interrupt Mask Register(R/W)
Each bit of IMR corresponds to each bit of IR2. When a bit of IMR is and the corresponding bit of IR2 is Interrupt will be issued. In other words, if a bit of IMR, an interrupt will be not issued even if the corresponding bit of IR2 is set
- Note
- This Register is same operated as SMIR of W5100, W5300 and W5550.
So, setSIMR() set a value to IMR for integrating with ioLibrary
Definition at line 265 of file w5200.h.
| #define _RTR_ (_W5200_IO_BASE_ + (0x0017)) |
Timeout register address( 1 is 100us )(R/W)
RTR configures the retransmission timeout period. The unit of timeout period is 100us and the default of RTR is x07D0. And so the default timeout period is 200ms(100us X 2000). During the time configured by RTR, W5200 waits for the peer response to the packet that is transmitted by Sn_CR (CONNECT, DISCON, CLOSE, SEND, SEND_MAC, SEND_KEEP command). If the peer does not respond within the RTR time, W5200 retransmits the packet or issues timeout.
Definition at line 275 of file w5200.h.
| #define _RCR_ (_W5200_IO_BASE_ + (0x0019)) |
Retry count register(R/W)
RCR configures the number of time of retransmission. When retransmission occurs as many as ref RCR+1 Timeout interrupt is issued (Sn_IR_TIMEOUT = '1').
Definition at line 283 of file w5200.h.
| #define PATR (_W5200_IO_BASE_ + (0x001C)) |
PPP LCP Request Timer register in PPPoE mode(R)
PATR notifies authentication method that has been agreed at the connection with PPPoE Server. W5200 supports two types of Authentication method - PAP and CHAP.
Definition at line 294 of file w5200.h.
| #define PPPALGO (_W5200_IO_BASE_ + (0x001E)) |
PPP LCP Request Timer register in PPPoE mode(R)
PPPALGO notifies authentication algorithm in PPPoE mode. For detailed information, please refer to PPPoE application note.
Definition at line 302 of file w5200.h.
| #define VERSIONR (_W5200_IO_BASE_ + (0x001F)) |
chip version register address(R)
VERSIONR always indicates the W5200 version as 0x03.
Definition at line 309 of file w5200.h.
| #define PTIMER (_W5200_IO_BASE_ + (0x0028)) |
PPP LCP Request Timer register in PPPoE mode(R)
PTIMER configures the time for sending LCP echo request. The unit of time is 25ms.
Definition at line 325 of file w5200.h.
| #define PMAGIC (_W5200_IO_BASE_ + (0x0029)) |
PPP LCP Magic number register in PPPoE mode(R)
PMAGIC configures the 4bytes magic number to be used in LCP negotiation.
Definition at line 332 of file w5200.h.
| #define INTLEVEL (_W5200_IO_BASE_ + (0x0030)) |
Set Interrupt low level timer register address(R/W)
INTLEVEL configures the Interrupt Assert Time.
Definition at line 346 of file w5200.h.
| #define IR2 (_W5200_IO_BASE_ + (0x0034)) |
Socket Interrupt Register(R/W)
IR2 indicates the interrupt status of Socket.
Each bit of IR2 be still until Sn_IR is cleared by the host.
If Sn_IR is not equal to x00 the n-th bit of IR2 is and INTn PIN is asserted until IR2 is x00
Definition at line 357 of file w5200.h.
| #define PHYSTATUS (_W5200_IO_BASE_ + (0x0035)) |
PHYSTATUS(R/W)
PHYSTATUS is the Register to indicate W5200 status of PHY.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reserved | Reserved | LINK | POWERSAVE | POWERDOWN | Reserved | Reserved | Reserved |
Definition at line 371 of file w5200.h.
| #define IMR2 (_W5200_IO_BASE_ + (0x0036)) |
Interrupt mask register(R/W)
IMR2 is used to mask interrupts. Each bit of IMR corresponds to each bit of IR. When a bit of IMR2 is and the corresponding bit of IR is an interrupt will be issued. In other words, if a bit of IMR2 is an interrupt will not be issued even if the corresponding bit of IR is
Each bit of IMR2 defined as the following.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| IM_IR7 | Reserved | IM_IR5 | Reserved | Reserved | Reserved | Reserved | Reserved |
- IM_IR7 : IP Conflict Interrupt Mask
- IM_IR5 : PPPoE Close Interrupt Mask
- Note
- This Register is same operated as _IMR_ of W5100, W5300 and W5550.
So, setIMR() set a value to IMR2 for integrating with ioLibrary
Definition at line 389 of file w5200.h.
1.8.9.1