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STM8S/A Standard Peripherals Firmware Library
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stm8s_itc.c
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00001 /** 00002 ****************************************************************************** 00003 * @file stm8s_itc.c 00004 * @author MCD Application Team 00005 * @version V2.2.0 00006 * @date 30-September-2014 00007 * @brief This file contains all the functions for the ITC peripheral. 00008 ****************************************************************************** 00009 * @attention 00010 * 00011 * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> 00012 * 00013 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 00014 * You may not use this file except in compliance with the License. 00015 * You may obtain a copy of the License at: 00016 * 00017 * http://www.st.com/software_license_agreement_liberty_v2 00018 * 00019 * Unless required by applicable law or agreed to in writing, software 00020 * distributed under the License is distributed on an "AS IS" BASIS, 00021 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 00022 * See the License for the specific language governing permissions and 00023 * limitations under the License. 00024 * 00025 ****************************************************************************** 00026 */ 00027 00028 /* Includes ------------------------------------------------------------------*/ 00029 #include "stm8s_itc.h" 00030 00031 /** @addtogroup STM8S_StdPeriph_Driver 00032 * @{ 00033 */ 00034 /* Private typedef -----------------------------------------------------------*/ 00035 /* Private define ------------------------------------------------------------*/ 00036 /* Private macro -------------------------------------------------------------*/ 00037 /* Private variables ---------------------------------------------------------*/ 00038 /* Private function prototypes -----------------------------------------------*/ 00039 /* Private functions ---------------------------------------------------------*/ 00040 00041 /** @addtogroup ITC_Private_Functions 00042 * @{ 00043 */ 00044 00045 /** 00046 * @brief Utility function used to read CC register. 00047 * @param None 00048 * @retval CPU CC register value 00049 */ 00050 uint8_t ITC_GetCPUCC(void) 00051 { 00052 #ifdef _COSMIC_ 00053 _asm("push cc"); 00054 _asm("pop a"); 00055 return; /* Ignore compiler warning, the returned value is in A register */ 00056 #elif defined _RAISONANCE_ /* _RAISONANCE_ */ 00057 return _getCC_(); 00058 #else /* _IAR_ */ 00059 asm("push cc"); 00060 asm("pop a"); /* Ignore compiler warning, the returned value is in A register */ 00061 #endif /* _COSMIC_*/ 00062 } 00063 00064 00065 /** 00066 * @} 00067 */ 00068 00069 /* Public functions ----------------------------------------------------------*/ 00070 00071 /** @addtogroup ITC_Public_Functions 00072 * @{ 00073 */ 00074 00075 /** 00076 * @brief Deinitializes the ITC registers to their default reset value. 00077 * @param None 00078 * @retval None 00079 */ 00080 void ITC_DeInit(void) 00081 { 00082 ITC->ISPR1 = ITC_SPRX_RESET_VALUE; 00083 ITC->ISPR2 = ITC_SPRX_RESET_VALUE; 00084 ITC->ISPR3 = ITC_SPRX_RESET_VALUE; 00085 ITC->ISPR4 = ITC_SPRX_RESET_VALUE; 00086 ITC->ISPR5 = ITC_SPRX_RESET_VALUE; 00087 ITC->ISPR6 = ITC_SPRX_RESET_VALUE; 00088 ITC->ISPR7 = ITC_SPRX_RESET_VALUE; 00089 ITC->ISPR8 = ITC_SPRX_RESET_VALUE; 00090 } 00091 00092 /** 00093 * @brief Gets the interrupt software priority bits (I1, I0) value from CPU CC register. 00094 * @param None 00095 * @retval The interrupt software priority bits value. 00096 */ 00097 uint8_t ITC_GetSoftIntStatus(void) 00098 { 00099 return (uint8_t)(ITC_GetCPUCC() & CPU_CC_I1I0); 00100 } 00101 00102 /** 00103 * @brief Gets the software priority of the specified interrupt source. 00104 * @param IrqNum : Specifies the peripheral interrupt source. 00105 * @retval ITC_PriorityLevel_TypeDef : Specifies the software priority of the interrupt source. 00106 */ 00107 ITC_PriorityLevel_TypeDef ITC_GetSoftwarePriority(ITC_Irq_TypeDef IrqNum) 00108 { 00109 uint8_t Value = 0; 00110 uint8_t Mask = 0; 00111 00112 /* Check function parameters */ 00113 assert_param(IS_ITC_IRQ_OK((uint8_t)IrqNum)); 00114 00115 /* Define the mask corresponding to the bits position in the SPR register */ 00116 Mask = (uint8_t)(0x03U << (((uint8_t)IrqNum % 4U) * 2U)); 00117 00118 switch (IrqNum) 00119 { 00120 case ITC_IRQ_TLI: /* TLI software priority can be read but has no meaning */ 00121 case ITC_IRQ_AWU: 00122 case ITC_IRQ_CLK: 00123 case ITC_IRQ_PORTA: 00124 Value = (uint8_t)(ITC->ISPR1 & Mask); /* Read software priority */ 00125 break; 00126 00127 case ITC_IRQ_PORTB: 00128 case ITC_IRQ_PORTC: 00129 case ITC_IRQ_PORTD: 00130 case ITC_IRQ_PORTE: 00131 Value = (uint8_t)(ITC->ISPR2 & Mask); /* Read software priority */ 00132 break; 00133 00134 #if defined(STM8S208) || defined(STM8AF52Ax) 00135 case ITC_IRQ_CAN_RX: 00136 case ITC_IRQ_CAN_TX: 00137 #endif /*STM8S208 or STM8AF52Ax */ 00138 #if defined(STM8S903) || defined(STM8AF622x) 00139 case ITC_IRQ_PORTF: 00140 #endif /*STM8S903 or STM8AF622x */ 00141 case ITC_IRQ_SPI: 00142 case ITC_IRQ_TIM1_OVF: 00143 Value = (uint8_t)(ITC->ISPR3 & Mask); /* Read software priority */ 00144 break; 00145 00146 case ITC_IRQ_TIM1_CAPCOM: 00147 #if defined (STM8S903) || defined (STM8AF622x) 00148 case ITC_IRQ_TIM5_OVFTRI: 00149 case ITC_IRQ_TIM5_CAPCOM: 00150 #else 00151 case ITC_IRQ_TIM2_OVF: 00152 case ITC_IRQ_TIM2_CAPCOM: 00153 #endif /* STM8S903 or STM8AF622x*/ 00154 case ITC_IRQ_TIM3_OVF: 00155 Value = (uint8_t)(ITC->ISPR4 & Mask); /* Read software priority */ 00156 break; 00157 00158 case ITC_IRQ_TIM3_CAPCOM: 00159 #if defined(STM8S208) ||defined(STM8S207) || defined (STM8S007) || defined(STM8S103) || \ 00160 defined(STM8S003) ||defined(STM8S903) || defined (STM8AF52Ax) || defined (STM8AF62Ax) 00161 case ITC_IRQ_UART1_TX: 00162 case ITC_IRQ_UART1_RX: 00163 #endif /*STM8S208 or STM8S207 or STM8S007 or STM8S103 or STM8S003 or STM8S903 or STM8AF52Ax or STM8AF62Ax */ 00164 #if defined(STM8AF622x) 00165 case ITC_IRQ_UART4_TX: 00166 case ITC_IRQ_UART4_RX: 00167 #endif /*STM8AF622x */ 00168 case ITC_IRQ_I2C: 00169 Value = (uint8_t)(ITC->ISPR5 & Mask); /* Read software priority */ 00170 break; 00171 00172 #if defined(STM8S105) || defined(STM8S005) || defined(STM8AF626x) 00173 case ITC_IRQ_UART2_TX: 00174 case ITC_IRQ_UART2_RX: 00175 #endif /*STM8S105 or STM8AF626x*/ 00176 #if defined(STM8S208) || defined(STM8S207) || defined(STM8S007) || defined(STM8AF52Ax) || \ 00177 defined(STM8AF62Ax) 00178 case ITC_IRQ_UART3_TX: 00179 case ITC_IRQ_UART3_RX: 00180 case ITC_IRQ_ADC2: 00181 #endif /*STM8S208 or STM8S207 or STM8AF52Ax or STM8AF62Ax */ 00182 #if defined(STM8S105) || defined(STM8S005) || defined(STM8S103) || defined(STM8S003) || \ 00183 defined(STM8S903) || defined(STM8AF626x) || defined(STM8AF622x) 00184 case ITC_IRQ_ADC1: 00185 #endif /*STM8S105, STM8S005, STM8S103 or STM8S003 or STM8S903 or STM8AF626x or STM8AF622x */ 00186 #if defined (STM8S903) || defined (STM8AF622x) 00187 case ITC_IRQ_TIM6_OVFTRI: 00188 #else 00189 case ITC_IRQ_TIM4_OVF: 00190 #endif /*STM8S903 or STM8AF622x */ 00191 Value = (uint8_t)(ITC->ISPR6 & Mask); /* Read software priority */ 00192 break; 00193 00194 case ITC_IRQ_EEPROM_EEC: 00195 Value = (uint8_t)(ITC->ISPR7 & Mask); /* Read software priority */ 00196 break; 00197 00198 default: 00199 break; 00200 } 00201 00202 Value >>= (uint8_t)(((uint8_t)IrqNum % 4u) * 2u); 00203 00204 return((ITC_PriorityLevel_TypeDef)Value); 00205 } 00206 00207 /** 00208 * @brief Sets the software priority of the specified interrupt source. 00209 * @note - The modification of the software priority is only possible when 00210 * the interrupts are disabled. 00211 * - The normal behavior is to disable the interrupt before calling 00212 * this function, and re-enable it after. 00213 * - The priority level 0 cannot be set (see product specification 00214 * for more details). 00215 * @param IrqNum : Specifies the peripheral interrupt source. 00216 * @param PriorityValue : Specifies the software priority value to set, 00217 * can be a value of @ref ITC_PriorityLevel_TypeDef . 00218 * @retval None 00219 */ 00220 void ITC_SetSoftwarePriority(ITC_Irq_TypeDef IrqNum, ITC_PriorityLevel_TypeDef PriorityValue) 00221 { 00222 uint8_t Mask = 0; 00223 uint8_t NewPriority = 0; 00224 00225 /* Check function parameters */ 00226 assert_param(IS_ITC_IRQ_OK((uint8_t)IrqNum)); 00227 assert_param(IS_ITC_PRIORITY_OK(PriorityValue)); 00228 00229 /* Check if interrupts are disabled */ 00230 assert_param(IS_ITC_INTERRUPTS_DISABLED); 00231 00232 /* Define the mask corresponding to the bits position in the SPR register */ 00233 /* The mask is reversed in order to clear the 2 bits after more easily */ 00234 Mask = (uint8_t)(~(uint8_t)(0x03U << (((uint8_t)IrqNum % 4U) * 2U))); 00235 00236 /* Define the new priority to write */ 00237 NewPriority = (uint8_t)((uint8_t)(PriorityValue) << (((uint8_t)IrqNum % 4U) * 2U)); 00238 00239 switch (IrqNum) 00240 { 00241 case ITC_IRQ_TLI: /* TLI software priority can be written but has no meaning */ 00242 case ITC_IRQ_AWU: 00243 case ITC_IRQ_CLK: 00244 case ITC_IRQ_PORTA: 00245 ITC->ISPR1 &= Mask; 00246 ITC->ISPR1 |= NewPriority; 00247 break; 00248 00249 case ITC_IRQ_PORTB: 00250 case ITC_IRQ_PORTC: 00251 case ITC_IRQ_PORTD: 00252 case ITC_IRQ_PORTE: 00253 ITC->ISPR2 &= Mask; 00254 ITC->ISPR2 |= NewPriority; 00255 break; 00256 00257 #if defined(STM8S208) || defined(STM8AF52Ax) 00258 case ITC_IRQ_CAN_RX: 00259 case ITC_IRQ_CAN_TX: 00260 #endif /*STM8S208 or STM8AF52Ax */ 00261 #if defined(STM8S903) || defined(STM8AF622x) 00262 case ITC_IRQ_PORTF: 00263 #endif /*STM8S903 or STM8AF622x */ 00264 case ITC_IRQ_SPI: 00265 case ITC_IRQ_TIM1_OVF: 00266 ITC->ISPR3 &= Mask; 00267 ITC->ISPR3 |= NewPriority; 00268 break; 00269 00270 case ITC_IRQ_TIM1_CAPCOM: 00271 #if defined(STM8S903) || defined(STM8AF622x) 00272 case ITC_IRQ_TIM5_OVFTRI: 00273 case ITC_IRQ_TIM5_CAPCOM: 00274 #else 00275 case ITC_IRQ_TIM2_OVF: 00276 case ITC_IRQ_TIM2_CAPCOM: 00277 #endif /*STM8S903 or STM8AF622x */ 00278 case ITC_IRQ_TIM3_OVF: 00279 ITC->ISPR4 &= Mask; 00280 ITC->ISPR4 |= NewPriority; 00281 break; 00282 00283 case ITC_IRQ_TIM3_CAPCOM: 00284 #if defined(STM8S208) ||defined(STM8S207) || defined (STM8S007) || defined(STM8S103) || \ 00285 defined(STM8S003) ||defined(STM8S903) || defined (STM8AF52Ax) || defined (STM8AF62Ax) 00286 case ITC_IRQ_UART1_TX: 00287 case ITC_IRQ_UART1_RX: 00288 #endif /*STM8S208 or STM8S207 or STM8S007 or STM8S103 or STM8S003 or STM8S903 or STM8AF52Ax or STM8AF62Ax */ 00289 #if defined(STM8AF622x) 00290 case ITC_IRQ_UART4_TX: 00291 case ITC_IRQ_UART4_RX: 00292 #endif /*STM8AF622x */ 00293 case ITC_IRQ_I2C: 00294 ITC->ISPR5 &= Mask; 00295 ITC->ISPR5 |= NewPriority; 00296 break; 00297 00298 #if defined(STM8S105) || defined(STM8S005) || defined(STM8AF626x) 00299 case ITC_IRQ_UART2_TX: 00300 case ITC_IRQ_UART2_RX: 00301 #endif /*STM8S105 or STM8AF626x */ 00302 00303 #if defined(STM8S208) || defined(STM8S207) || defined(STM8S007) || defined(STM8AF52Ax) || \ 00304 defined(STM8AF62Ax) 00305 case ITC_IRQ_UART3_TX: 00306 case ITC_IRQ_UART3_RX: 00307 case ITC_IRQ_ADC2: 00308 #endif /*STM8S208 or STM8S207 or STM8AF52Ax or STM8AF62Ax */ 00309 00310 #if defined(STM8S105) || defined(STM8S005) || defined(STM8S103) || defined(STM8S003) || \ 00311 defined(STM8S903) || defined(STM8AF626x) || defined (STM8AF622x) 00312 case ITC_IRQ_ADC1: 00313 #endif /*STM8S105, STM8S005, STM8S103 or STM8S003 or STM8S903 or STM8AF626x or STM8AF622x */ 00314 00315 #if defined (STM8S903) || defined (STM8AF622x) 00316 case ITC_IRQ_TIM6_OVFTRI: 00317 #else 00318 case ITC_IRQ_TIM4_OVF: 00319 #endif /* STM8S903 or STM8AF622x */ 00320 ITC->ISPR6 &= Mask; 00321 ITC->ISPR6 |= NewPriority; 00322 break; 00323 00324 case ITC_IRQ_EEPROM_EEC: 00325 ITC->ISPR7 &= Mask; 00326 ITC->ISPR7 |= NewPriority; 00327 break; 00328 00329 default: 00330 break; 00331 } 00332 } 00333 00334 /** 00335 * @} 00336 */ 00337 00338 /** 00339 * @} 00340 */ 00341 00342 00343 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/