STM8S/A Standard Peripherals Drivers: stm8s.h File Reference

STM8S/A

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Data Structures | Defines | Typedefs | Enumerations
stm8s.h File Reference

This file contains all HW registers definitions and memory mapping. More...

#include "stm8s_conf.h" #include <intrinsics.h>

Go to the source code of this file.

Data Structures

struct  AWU_struct
 Auto Wake Up (AWU) peripheral registers. More...
struct  BEEP_struct
 Beeper (BEEP) peripheral registers. More...
struct  CAN_TypeDef
 Controller Area Network (CAN) More...
struct  CFG_struct
 Configuration Registers (CFG) More...
struct  CLK_struct
 Clock Controller (CLK) More...
struct  EXTI_struct
 External Interrupt Controller (EXTI) More...
struct  FLASH_struct
 FLASH program and Data memory (FLASH) More...
struct  GPIO_struct
 General Purpose I/Os (GPIO) More...
struct  I2C_struct
 Inter-Integrated Circuit (I2C) More...
struct  ITC_struct
 Interrupt Controller (ITC) More...
struct  IWDG_struct
 Independent Watchdog (IWDG) More...
struct  OPT_struct
 Option Bytes (OPT) More...
struct  RST_struct
 Reset Controller (RST) More...
struct  SPI_struct
 Serial Peripheral Interface (SPI) More...
struct  TIM1_struct
 16-bit timer with complementary PWM outputs (TIM1) More...
struct  TIM2_struct
 16-bit timer (TIM2) More...
struct  TIM3_struct
 16-bit timer (TIM3) More...
struct  TIM4_struct
 8-bit system timer (TIM4) More...
struct  TIM5_struct
 16-bit timer with synchro module (TIM5) More...
struct  TIM6_struct
 8-bit system timer with synchro module(TIM6) More...
struct  UART1_struct
 Universal Synchronous Asynchronous Receiver Transmitter (UART1) More...
struct  UART2_struct
 Universal Synchronous Asynchronous Receiver Transmitter (UART2) More...
struct  UART3_struct
 LIN Universal Asynchronous Receiver Transmitter (UART3) More...
struct  WWDG_struct
 Window Watchdog (WWDG) More...

Defines

#define __I   volatile const
 IO definitions.
#define __IO   volatile
#define __O   volatile
#define __STM8S_STDPERIPH_VERSION
#define __STM8S_STDPERIPH_VERSION_MAIN   ((uint8_t)0x02)
#define __STM8S_STDPERIPH_VERSION_RC   ((uint8_t)0x00)
#define __STM8S_STDPERIPH_VERSION_SUB1   ((uint8_t)0x03)
#define __STM8S_STDPERIPH_VERSION_SUB2   ((uint8_t)0x00)
#define ADC1_BaseAddress   0x53E0
#define ADC2_BaseAddress   0x5400
#define AffBit(VAR, Place, Value)
#define AREA   0x00
#define AWU   ((AWU_TypeDef *) AWU_BaseAddress)
#define AWU_APR_APR   ((uint8_t)0x3F)
#define AWU_APR_RESET_VALUE   ((uint8_t)0x3F)
#define AWU_BaseAddress   0x50F0
#define AWU_CSR_AWUEN   ((uint8_t)0x10)
#define AWU_CSR_AWUF   ((uint8_t)0x20)
#define AWU_CSR_MSR   ((uint8_t)0x01)
#define AWU_CSR_RESET_VALUE   ((uint8_t)0x00)
#define AWU_TBR_AWUTB   ((uint8_t)0x0F)
#define AWU_TBR_RESET_VALUE   ((uint8_t)0x00)
#define BEEP   ((BEEP_TypeDef *) BEEP_BaseAddress)
#define BEEP_BaseAddress   0x50F3
#define BEEP_CSR_BEEPDIV   ((uint8_t)0x1F)
#define BEEP_CSR_BEEPEN   ((uint8_t)0x20)
#define BEEP_CSR_BEEPSEL   ((uint8_t)0xC0)
#define BEEP_CSR_RESET_VALUE   ((uint8_t)0x1F)
#define BitClr(BIT)   ( *((unsigned char *) (AREA+(BIT)/8)) &= (~(1<<(7-(BIT)%8))) )
#define BitSet(BIT)   ( *((unsigned char *) (AREA+(BIT)/8)) |= (1<<(7-(BIT)%8)) )
#define BitVal(BIT)   ( *((unsigned char *) (AREA+(BIT)/8)) & (1<<(7-(BIT)%8)) )
#define BYTE_0(n)   ((uint8_t)((n) & (uint8_t)0xFF))
#define BYTE_1(n)   ((uint8_t)(BYTE_0((n) >> (uint8_t)8)))
#define BYTE_2(n)   ((uint8_t)(BYTE_0((n) >> (uint8_t)16)))
#define BYTE_3(n)   ((uint8_t)(BYTE_0((n) >> (uint8_t)24)))
#define CAN_BaseAddress   0x5420
#define CAN_BTR1_RESET_VALUE   ((uint8_t)0x40)
#define CAN_BTR2_RESET_VALUE   ((uint8_t)0x23)
#define CAN_DGR_LBKM   ((uint8_t)0x01)
#define CAN_DGR_RESET_VALUE   ((uint8_t)0x0C)
#define CAN_DGR_RX   ((uint8_t)0x08)
#define CAN_DGR_SAMP   ((uint8_t)0x04)
#define CAN_DGR_SLIM   ((uint8_t)0x02)
#define CAN_DGR_TXM2E   ((uint8_t)0x10)
#define CAN_EIER_BOFIE   ((uint8_t)0x04)
#define CAN_EIER_EPVIE   ((uint8_t)0x02)
#define CAN_EIER_ERRIE   ((uint8_t)0x80)
#define CAN_EIER_EWGIE   ((uint8_t)0x01)
#define CAN_EIER_LECIE   ((uint8_t)0x10)
#define CAN_EIER_RESET_VALUE   ((uint8_t)0x00)
#define CAN_ESR_BOFF   ((uint8_t)0x04)
#define CAN_ESR_EPVF   ((uint8_t)0x02)
#define CAN_ESR_EWGF   ((uint8_t)0x01)
#define CAN_ESR_LEC   ((uint8_t)0x70)
#define CAN_ESR_LEC0   ((uint8_t)0x10)
#define CAN_ESR_LEC1   ((uint8_t)0x20)
#define CAN_ESR_LEC2   ((uint8_t)0x40)
#define CAN_ESR_RESET_VALUE   ((uint8_t)0x00)
#define CAN_FCR1_FACT0   ((uint8_t)0x01)
#define CAN_FCR1_FACT1   ((uint8_t)0x10)
#define CAN_FCR1_FSC00   ((uint8_t)0x02)
#define CAN_FCR1_FSC01   ((uint8_t)0x04)
#define CAN_FCR1_FSC10   ((uint8_t)0x20)
#define CAN_FCR1_FSC11   ((uint8_t)0x40)
#define CAN_FCR2_FACT2   ((uint8_t)0x01)
#define CAN_FCR2_FACT3   ((uint8_t)0x10)
#define CAN_FCR2_FSC20   ((uint8_t)0x02)
#define CAN_FCR2_FSC21   ((uint8_t)0x04)
#define CAN_FCR2_FSC30   ((uint8_t)0x20)
#define CAN_FCR2_FSC31   ((uint8_t)0x40)
#define CAN_FCR3_FACT4   ((uint8_t)0x01)
#define CAN_FCR3_FACT5   ((uint8_t)0x10)
#define CAN_FCR3_FSC40   ((uint8_t)0x02)
#define CAN_FCR3_FSC41   ((uint8_t)0x04)
#define CAN_FCR3_FSC50   ((uint8_t)0x20)
#define CAN_FCR3_FSC51   ((uint8_t)0x40)
#define CAN_FCR_RESET_VALUE   ((uint8_t)0x00)
#define CAN_FMR1_FMH0   ((uint8_t)0x02)
#define CAN_FMR1_FMH1   ((uint8_t)0x08)
#define CAN_FMR1_FMH2   ((uint8_t)0x20)
#define CAN_FMR1_FMH3   ((uint8_t)0x80)
#define CAN_FMR1_FML0   ((uint8_t)0x01)
#define CAN_FMR1_FML1   ((uint8_t)0x04)
#define CAN_FMR1_FML2   ((uint8_t)0x10)
#define CAN_FMR1_FML3   ((uint8_t)0x40)
#define CAN_FMR1_RESET_VALUE   ((uint8_t)0x00)
#define CAN_FMR2_FMH4   ((uint8_t)0x02)
#define CAN_FMR2_FMH5   ((uint8_t)0x08)
#define CAN_FMR2_FML4   ((uint8_t)0x01)
#define CAN_FMR2_FML5   ((uint8_t)0x04)
#define CAN_FMR2_RESET_VALUE   ((uint8_t)0x00)
#define CAN_IER_FFIE   ((uint8_t)0x04)
#define CAN_IER_FMPIE   ((uint8_t)0x02)
#define CAN_IER_FOVIE   ((uint8_t)0x08)
#define CAN_IER_RESET_VALUE   ((uint8_t)0x00)
#define CAN_IER_TMEIE   ((uint8_t)0x01)
#define CAN_IER_WKUIE   ((uint8_t)0x80)
#define CAN_MCR_ABOM   ((uint8_t)0x40)
#define CAN_MCR_AWUM   ((uint8_t)0x20)
#define CAN_MCR_INRQ   ((uint8_t)0x01)
#define CAN_MCR_NART   ((uint8_t)0x10)
#define CAN_MCR_RESET_VALUE   ((uint8_t)0x02)
#define CAN_MCR_RFLM   ((uint8_t)0x08)
#define CAN_MCR_SLEEP   ((uint8_t)0x02)
#define CAN_MCR_TTCM   ((uint8_t)0x80)
#define CAN_MCR_TXFP   ((uint8_t)0x04)
#define CAN_MCSR_ABRQ   ((uint8_t)0x02)
#define CAN_MCSR_ALST   ((uint8_t)0x10)
#define CAN_MCSR_RESET_VALUE   ((uint8_t)0x00)
#define CAN_MCSR_RQCP   ((uint8_t)0x04)
#define CAN_MCSR_TERR   ((uint8_t)0x20)
#define CAN_MCSR_TXOK   ((uint8_t)0x08)
#define CAN_MCSR_TXRQ   ((uint8_t)0x01)
#define CAN_MDLC_RESET_VALUE   ((uint8_t)0x00)
#define CAN_MDLCR_DLC   ((uint8_t)0x0F)
#define CAN_MDLCR_TGT   ((uint8_t)0x80)
#define CAN_MFMI_RESET_VALUE   ((uint8_t)0x00)
#define CAN_MIDR1_IDE   ((uint8_t)0x40)
#define CAN_MIDR1_RTR   ((uint8_t)0x20)
#define CAN_MSR_ERRI   ((uint8_t)0x04)
#define CAN_MSR_INAK   ((uint8_t)0x01)
#define CAN_MSR_RESET_VALUE   ((uint8_t)0x02)
#define CAN_MSR_RX   ((uint8_t)0x20)
#define CAN_MSR_SLAK   ((uint8_t)0x02)
#define CAN_MSR_TX   ((uint8_t)0x10)
#define CAN_MSR_WKUI   ((uint8_t)0x08)
#define CAN_PSR_PS0   ((uint8_t)0x01)
#define CAN_PSR_PS1   ((uint8_t)0x02)
#define CAN_PSR_PS2   ((uint8_t)0x04)
#define CAN_PSR_RESET_VALUE   ((uint8_t)0x00)
#define CAN_RECR_REC0   ((uint8_t)0x01)
#define CAN_RECR_REC1   ((uint8_t)0x02)
#define CAN_RECR_REC2   ((uint8_t)0x04)
#define CAN_RECR_REC3   ((uint8_t)0x08)
#define CAN_RECR_REC4   ((uint8_t)0x10)
#define CAN_RECR_REC5   ((uint8_t)0x20)
#define CAN_RECR_REC6   ((uint8_t)0x40)
#define CAN_RECR_REC7   ((uint8_t)0x80)
#define CAN_RECR_RESET_VALUE   ((uint8_t)0x00)
#define CAN_RFR_FMP01   ((uint8_t)0x03)
#define CAN_RFR_FOVR   ((uint8_t)0x10)
#define CAN_RFR_FULL   ((uint8_t)0x08)
#define CAN_RFR_RESET_VALUE   ((uint8_t)0x00)
#define CAN_RFR_RFOM   ((uint8_t)0x20)
#define CAN_TECR_RESET_VALUE   ((uint8_t)0x00)
#define CAN_TECR_TEC0   ((uint8_t)0x01)
#define CAN_TECR_TEC1   ((uint8_t)0x02)
#define CAN_TECR_TEC2   ((uint8_t)0x04)
#define CAN_TECR_TEC3   ((uint8_t)0x08)
#define CAN_TECR_TEC4   ((uint8_t)0x10)
#define CAN_TECR_TEC5   ((uint8_t)0x20)
#define CAN_TECR_TEC6   ((uint8_t)0x40)
#define CAN_TECR_TEC7   ((uint8_t)0x80)
#define CAN_TPR_CODE0   ((uint8_t)0x01)
#define CAN_TPR_LOW0   ((uint8_t)0x20)
#define CAN_TPR_LOW1   ((uint8_t)0x40)
#define CAN_TPR_LOW2   ((uint8_t)0x80)
#define CAN_TPR_RESET_VALUE   ((uint8_t)0x0C)
#define CAN_TPR_TME0   ((uint8_t)0x04)
#define CAN_TPR_TME1   ((uint8_t)0x08)
#define CAN_TPR_TME2   ((uint8_t)0x10)
#define CAN_TSR_RESET_VALUE   ((uint8_t)0x00)
#define CAN_TSR_RQCP0   ((uint8_t)0x01)
#define CAN_TSR_RQCP012   ((uint8_t)0x07)
#define CAN_TSR_RQCP1   ((uint8_t)0x02)
#define CAN_TSR_RQCP2   ((uint8_t)0x04)
#define CAN_TSR_TXOK0   ((uint8_t)0x10)
#define CAN_TSR_TXOK1   ((uint8_t)0x20)
#define CAN_TSR_TXOK2   ((uint8_t)0x40)
#define CCMR_TIxDirect_Set   ((uint8_t)0x01)
#define CFG   ((CFG_TypeDef *) CFG_BaseAddress)
#define CFG_BaseAddress   0x7F60
#define CFG_GCR_AL   ((uint8_t)0x02)
#define CFG_GCR_RESET_VALUE   ((uint8_t)0x00)
#define CFG_GCR_SWD   ((uint8_t)0x01)
#define ChgBit(VAR, Place)   ( (VAR) ^= (uint8_t)((uint8_t)1<<(uint8_t)(Place)) )
#define CLK   ((CLK_TypeDef *) CLK_BaseAddress)
#define CLK_BaseAddress   0x50C0
#define CLK_CCOR_CCOBSY   ((uint8_t)0x40)
#define CLK_CCOR_CCOEN   ((uint8_t)0x01)
#define CLK_CCOR_CCORDY   ((uint8_t)0x20)
#define CLK_CCOR_CCOSEL   ((uint8_t)0x1E)
#define CLK_CCOR_RESET_VALUE   ((uint8_t)0x00)
#define CLK_CKDIVR_CPUDIV   ((uint8_t)0x07)
#define CLK_CKDIVR_HSIDIV   ((uint8_t)0x18)
#define CLK_CKDIVR_RESET_VALUE   ((uint8_t)0x18)
#define CLK_CMSR_CKM   ((uint8_t)0xFF)
#define CLK_CMSR_RESET_VALUE   ((uint8_t)0xE1)
#define CLK_CSSR_AUX   ((uint8_t)0x02)
#define CLK_CSSR_CSSD   ((uint8_t)0x08)
#define CLK_CSSR_CSSDIE   ((uint8_t)0x04)
#define CLK_CSSR_CSSEN   ((uint8_t)0x01)
#define CLK_CSSR_RESET_VALUE   ((uint8_t)0x00)
#define CLK_ECKR_HSEEN   ((uint8_t)0x01)
#define CLK_ECKR_HSERDY   ((uint8_t)0x02)
#define CLK_ECKR_RESET_VALUE   ((uint8_t)0x00)
#define CLK_HSITRIMR_HSITRIM   ((uint8_t)0x07)
#define CLK_HSITRIMR_RESET_VALUE   ((uint8_t)0x00)
#define CLK_ICKR_FHWU   ((uint8_t)0x04)
#define CLK_ICKR_HSIEN   ((uint8_t)0x01)
#define CLK_ICKR_HSIRDY   ((uint8_t)0x02)
#define CLK_ICKR_LSIEN   ((uint8_t)0x08)
#define CLK_ICKR_LSIRDY   ((uint8_t)0x10)
#define CLK_ICKR_RESET_VALUE   ((uint8_t)0x01)
#define CLK_ICKR_SWUAH   ((uint8_t)0x20)
#define CLK_PCKENR1_I2C   ((uint8_t)0x01)
#define CLK_PCKENR1_RESET_VALUE   ((uint8_t)0xFF)
#define CLK_PCKENR1_SPI   ((uint8_t)0x02)
#define CLK_PCKENR1_TIM1   ((uint8_t)0x80)
#define CLK_PCKENR1_TIM2   ((uint8_t)0x20)
#define CLK_PCKENR1_TIM3   ((uint8_t)0x40)
#define CLK_PCKENR1_TIM4   ((uint8_t)0x10)
#define CLK_PCKENR1_TIM5   ((uint8_t)0x20)
#define CLK_PCKENR1_TIM6   ((uint8_t)0x10)
#define CLK_PCKENR1_UART1   ((uint8_t)0x04)
#define CLK_PCKENR1_UART2   ((uint8_t)0x08)
#define CLK_PCKENR1_UART3   ((uint8_t)0x08)
#define CLK_PCKENR2_ADC   ((uint8_t)0x08)
#define CLK_PCKENR2_AWU   ((uint8_t)0x04)
#define CLK_PCKENR2_CAN   ((uint8_t)0x80)
#define CLK_PCKENR2_RESET_VALUE   ((uint8_t)0xFF)
#define CLK_SWCR_RESET_VALUE   ((uint8_t)0x00)
#define CLK_SWCR_SWBSY   ((uint8_t)0x01)
#define CLK_SWCR_SWEN   ((uint8_t)0x02)
#define CLK_SWCR_SWIEN   ((uint8_t)0x04)
#define CLK_SWCR_SWIF   ((uint8_t)0x08)
#define CLK_SWIMCCR_RESET_VALUE   ((uint8_t)0x00)
#define CLK_SWIMCCR_SWIMDIV   ((uint8_t)0x01)
#define CLK_SWR_RESET_VALUE   ((uint8_t)0xE1)
#define CLK_SWR_SWI   ((uint8_t)0xFF)
#define ClrBit(VAR, Place)   ( (VAR) &= (uint8_t)((uint8_t)((uint8_t)1<<(uint8_t)(Place))^(uint8_t)255) )
#define CONST   const
#define CPU_CC_I1I0   ((uint8_t)0x28)
#define disableInterrupts()   __disable_interrupt()
#define DM   ((DM_TypeDef *) DM_BaseAddress)
#define DM_BaseAddress   0x7F90
#define EEPROM   __eeprom
#define enableInterrupts()   __enable_interrupt()
#define EXTI   ((EXTI_TypeDef *) EXTI_BaseAddress)
#define EXTI_BaseAddress   0x50A0
#define EXTI_CR1_PAIS   ((uint8_t)0x03)
#define EXTI_CR1_PBIS   ((uint8_t)0x0C)
#define EXTI_CR1_PCIS   ((uint8_t)0x30)
#define EXTI_CR1_PDIS   ((uint8_t)0xC0)
#define EXTI_CR1_RESET_VALUE   ((uint8_t)0x00)
#define EXTI_CR2_PEIS   ((uint8_t)0x03)
#define EXTI_CR2_RESET_VALUE   ((uint8_t)0x00)
#define EXTI_CR2_TLIS   ((uint8_t)0x04)
#define FAR   __far
#define FLASH   ((FLASH_TypeDef *) FLASH_BaseAddress)
#define FLASH_BaseAddress   0x505A
#define FLASH_CR1_AHALT   ((uint8_t)0x04)
#define FLASH_CR1_FIX   ((uint8_t)0x01)
#define FLASH_CR1_HALT   ((uint8_t)0x08)
#define FLASH_CR1_IE   ((uint8_t)0x02)
#define FLASH_CR1_RESET_VALUE   ((uint8_t)0x00)
#define FLASH_CR2_ERASE   ((uint8_t)0x20)
#define FLASH_CR2_FPRG   ((uint8_t)0x10)
#define FLASH_CR2_OPT   ((uint8_t)0x80)
#define FLASH_CR2_PRG   ((uint8_t)0x01)
#define FLASH_CR2_RESET_VALUE   ((uint8_t)0x00)
#define FLASH_CR2_WPRG   ((uint8_t)0x40)
#define FLASH_DUKR_DUK   ((uint8_t)0xFF)
#define FLASH_DUKR_RESET_VALUE   ((uint8_t)0x00)
#define FLASH_IAPSR_DUL   ((uint8_t)0x08)
#define FLASH_IAPSR_EOP   ((uint8_t)0x04)
#define FLASH_IAPSR_HVOFF   ((uint8_t)0x40)
#define FLASH_IAPSR_PUL   ((uint8_t)0x02)
#define FLASH_IAPSR_RESET_VALUE   ((uint8_t)0x40)
#define FLASH_IAPSR_WR_PG_DIS   ((uint8_t)0x01)
#define FLASH_NCR2_NERASE   ((uint8_t)0x20)
#define FLASH_NCR2_NFPRG   ((uint8_t)0x10)
#define FLASH_NCR2_NOPT   ((uint8_t)0x80)
#define FLASH_NCR2_NPRG   ((uint8_t)0x01)
#define FLASH_NCR2_NWPRG   ((uint8_t)0x40)
#define FLASH_NCR2_RESET_VALUE   ((uint8_t)0xFF)
#define FLASH_PUKR_PUK   ((uint8_t)0xFF)
#define FLASH_PUKR_RESET_VALUE   ((uint8_t)0x00)
#define GPIO_CR1_RESET_VALUE   ((uint8_t)0x00)
#define GPIO_CR2_RESET_VALUE   ((uint8_t)0x00)
#define GPIO_DDR_RESET_VALUE   ((uint8_t)0x00)
#define GPIO_ODR_RESET_VALUE   ((uint8_t)0x00)
#define GPIOA   ((GPIO_TypeDef *) GPIOA_BaseAddress)
#define GPIOA_BaseAddress   0x5000
#define GPIOB   ((GPIO_TypeDef *) GPIOB_BaseAddress)
#define GPIOB_BaseAddress   0x5005
#define GPIOC   ((GPIO_TypeDef *) GPIOC_BaseAddress)
#define GPIOC_BaseAddress   0x500A
#define GPIOD   ((GPIO_TypeDef *) GPIOD_BaseAddress)
#define GPIOD_BaseAddress   0x500F
#define GPIOE   ((GPIO_TypeDef *) GPIOE_BaseAddress)
#define GPIOE_BaseAddress   0x5014
#define GPIOF   ((GPIO_TypeDef *) GPIOF_BaseAddress)
#define GPIOF_BaseAddress   0x5019
#define GPIOG_BaseAddress   0x501E
#define GPIOH_BaseAddress   0x5023
#define GPIOI_BaseAddress   0x5028
#define halt()   __halt()
#define HSE_VALUE   ((uint32_t)16000000)
 In the following line adjust the value of External High Speed oscillator (HSE) used in your application.
#define HSI_VALUE   ((uint32_t)16000000)
 Definition of Device on-chip RC oscillator frequencies.
#define I2C   ((I2C_TypeDef *) I2C_BaseAddress)
#define I2C_BaseAddress   0x5210
#define I2C_CCRH_CCR   ((uint8_t)0x0F)
#define I2C_CCRH_DUTY   ((uint8_t)0x40)
#define I2C_CCRH_FS   ((uint8_t)0x80)
#define I2C_CCRH_RESET_VALUE   ((uint8_t)0x00)
#define I2C_CCRL_CCR   ((uint8_t)0xFF)
#define I2C_CCRL_RESET_VALUE   ((uint8_t)0x00)
#define I2C_CR1_ENGC   ((uint8_t)0x40)
#define I2C_CR1_NOSTRETCH   ((uint8_t)0x80)
#define I2C_CR1_PE   ((uint8_t)0x01)
#define I2C_CR1_RESET_VALUE   ((uint8_t)0x00)
#define I2C_CR2_ACK   ((uint8_t)0x04)
#define I2C_CR2_POS   ((uint8_t)0x08)
#define I2C_CR2_RESET_VALUE   ((uint8_t)0x00)
#define I2C_CR2_START   ((uint8_t)0x01)
#define I2C_CR2_STOP   ((uint8_t)0x02)
#define I2C_CR2_SWRST   ((uint8_t)0x80)
#define I2C_DR_DR   ((uint8_t)0xFF)
#define I2C_DR_RESET_VALUE   ((uint8_t)0x00)
#define I2C_FREQR_FREQ   ((uint8_t)0x3F)
#define I2C_FREQR_RESET_VALUE   ((uint8_t)0x00)
#define I2C_ITR_ITBUFEN   ((uint8_t)0x04)
#define I2C_ITR_ITERREN   ((uint8_t)0x01)
#define I2C_ITR_ITEVTEN   ((uint8_t)0x02)
#define I2C_ITR_RESET_VALUE   ((uint8_t)0x00)
#define I2C_OARH_ADD   ((uint8_t)0x06)
#define I2C_OARH_ADDCONF   ((uint8_t)0x40)
#define I2C_OARH_ADDMODE   ((uint8_t)0x80)
#define I2C_OARH_RESET_VALUE   ((uint8_t)0x00)
#define I2C_OARL_ADD   ((uint8_t)0xFE)
#define I2C_OARL_ADD0   ((uint8_t)0x01)
#define I2C_OARL_RESET_VALUE   ((uint8_t)0x00)
#define I2C_SR1_ADD10   ((uint8_t)0x08)
#define I2C_SR1_ADDR   ((uint8_t)0x02)
#define I2C_SR1_BTF   ((uint8_t)0x04)
#define I2C_SR1_RESET_VALUE   ((uint8_t)0x00)
#define I2C_SR1_RXNE   ((uint8_t)0x40)
#define I2C_SR1_SB   ((uint8_t)0x01)
#define I2C_SR1_STOPF   ((uint8_t)0x10)
#define I2C_SR1_TXE   ((uint8_t)0x80)
#define I2C_SR2_AF   ((uint8_t)0x04)
#define I2C_SR2_ARLO   ((uint8_t)0x02)
#define I2C_SR2_BERR   ((uint8_t)0x01)
#define I2C_SR2_OVR   ((uint8_t)0x08)
#define I2C_SR2_RESET_VALUE   ((uint8_t)0x00)
#define I2C_SR2_WUFH   ((uint8_t)0x20)
#define I2C_SR3_BUSY   ((uint8_t)0x02)
#define I2C_SR3_GENCALL   ((uint8_t)0x10)
#define I2C_SR3_MSL   ((uint8_t)0x01)
#define I2C_SR3_RESET_VALUE   ((uint8_t)0x00)
#define I2C_SR3_TRA   ((uint8_t)0x04)
#define I2C_TRISER_RESET_VALUE   ((uint8_t)0x02)
#define I2C_TRISER_TRISE   ((uint8_t)0x3F)
#define IN_RAM(a)   a
#define IS_FUNCTIONALSTATE_OK(STATE)   (((STATE) == DISABLE) || ((STATE) == ENABLE))
#define IS_STATE_VALUE_OK(SensitivityValue)
#define ITC   ((ITC_TypeDef *) ITC_BaseAddress)
#define ITC_BaseAddress   0x7F70
#define ITC_SPRX_RESET_VALUE   ((uint8_t)0xFF)
#define IWDG   ((IWDG_TypeDef *) IWDG_BaseAddress)
#define IWDG_BaseAddress   0x50E0
#define IWDG_PR_RESET_VALUE   ((uint8_t)0x00)
#define IWDG_RLR_RESET_VALUE   ((uint8_t)0xFF)
#define LSI_VALUE   ((uint32_t)128000)
#define MemoryAddressCast   uint32_t
#define MskBit(Dest, Msk, Src)   ( (Dest) = ((Msk) & (Src)) | ((~(Msk)) & (Dest)) )
#define NEAR   __near
#define nop()   __no_operation()
#define OPT   ((OPT_TypeDef *) OPT_BaseAddress)
#define OPT_BaseAddress   0x4800
#define PointerAttr   FAR
#define rim()   __enable_interrupt()
#define RST   ((RST_TypeDef *) RST_BaseAddress)
#define RST_BaseAddress   0x50B3
#define RST_SR_EMCF   ((uint8_t)0x10)
#define RST_SR_ILLOPF   ((uint8_t)0x04)
#define RST_SR_IWDGF   ((uint8_t)0x02)
#define RST_SR_SWIMF   ((uint8_t)0x08)
#define RST_SR_WWDGF   ((uint8_t)0x01)
#define S16_MAX   (32767)
#define S16_MIN   (-32768)
#define S32_MAX   (2147483647)
#define S32_MIN   (-2147483648uL)
#define S8_MAX   (127)
#define S8_MIN   (-128)
#define SetBit(VAR, Place)   ( (VAR) |= (uint8_t)((uint8_t)1<<(uint8_t)(Place)) )
#define sim()   __disable_interrupt()
#define SPI   ((SPI_TypeDef *) SPI_BaseAddress)
#define SPI_BaseAddress   0x5200
#define SPI_CR1_BR   ((uint8_t)0x38)
#define SPI_CR1_CPHA   ((uint8_t)0x01)
#define SPI_CR1_CPOL   ((uint8_t)0x02)
#define SPI_CR1_LSBFIRST   ((uint8_t)0x80)
#define SPI_CR1_MSTR   ((uint8_t)0x04)
#define SPI_CR1_RESET_VALUE   ((uint8_t)0x00)
#define SPI_CR1_SPE   ((uint8_t)0x40)
#define SPI_CR2_BDM   ((uint8_t)0x80)
#define SPI_CR2_BDOE   ((uint8_t)0x40)
#define SPI_CR2_CRCEN   ((uint8_t)0x20)
#define SPI_CR2_CRCNEXT   ((uint8_t)0x10)
#define SPI_CR2_RESET_VALUE   ((uint8_t)0x00)
#define SPI_CR2_RXONLY   ((uint8_t)0x04)
#define SPI_CR2_SSI   ((uint8_t)0x01)
#define SPI_CR2_SSM   ((uint8_t)0x02)
#define SPI_CRCPR_RESET_VALUE   ((uint8_t)0x07)
#define SPI_DR_RESET_VALUE   ((uint8_t)0x00)
#define SPI_ICR_ERRIE   ((uint8_t)0x20)
#define SPI_ICR_RESET_VALUE   ((uint8_t)0x00)
#define SPI_ICR_RXEI   ((uint8_t)0x40)
#define SPI_ICR_TXEI   ((uint8_t)0x80)
#define SPI_ICR_WKIE   ((uint8_t)0x10)
#define SPI_RXCRCR_RESET_VALUE   ((uint8_t)0x00)
#define SPI_SR_BSY   ((uint8_t)0x80)
#define SPI_SR_CRCERR   ((uint8_t)0x10)
#define SPI_SR_MODF   ((uint8_t)0x20)
#define SPI_SR_OVR   ((uint8_t)0x40)
#define SPI_SR_RESET_VALUE   ((uint8_t)0x02)
#define SPI_SR_RXNE   ((uint8_t)0x01)
#define SPI_SR_TXE   ((uint8_t)0x02)
#define SPI_SR_WKUP   ((uint8_t)0x08)
#define SPI_TXCRCR_RESET_VALUE   ((uint8_t)0x00)
#define TIM1   ((TIM1_TypeDef *) TIM1_BaseAddress)
#define TIM1_ARRH_ARR   ((uint8_t)0xFF)
#define TIM1_ARRH_RESET_VALUE   ((uint8_t)0xFF)
#define TIM1_ARRL_ARR   ((uint8_t)0xFF)
#define TIM1_ARRL_RESET_VALUE   ((uint8_t)0xFF)
#define TIM1_BaseAddress   0x5250
#define TIM1_BKR_AOE   ((uint8_t)0x40)
#define TIM1_BKR_BKE   ((uint8_t)0x10)
#define TIM1_BKR_BKP   ((uint8_t)0x20)
#define TIM1_BKR_LOCK   ((uint8_t)0x03)
#define TIM1_BKR_MOE   ((uint8_t)0x80)
#define TIM1_BKR_OSSI   ((uint8_t)0x04)
#define TIM1_BKR_OSSR   ((uint8_t)0x08)
#define TIM1_BKR_RESET_VALUE   ((uint8_t)0x00)
#define TIM1_CCER1_CC1E   ((uint8_t)0x01)
#define TIM1_CCER1_CC1NE   ((uint8_t)0x04)
#define TIM1_CCER1_CC1NP   ((uint8_t)0x08)
#define TIM1_CCER1_CC1P   ((uint8_t)0x02)
#define TIM1_CCER1_CC2E   ((uint8_t)0x10)
#define TIM1_CCER1_CC2NE   ((uint8_t)0x40)
#define TIM1_CCER1_CC2NP   ((uint8_t)0x80)
#define TIM1_CCER1_CC2P   ((uint8_t)0x20)
#define TIM1_CCER1_RESET_VALUE   ((uint8_t)0x00)
#define TIM1_CCER2_CC3E   ((uint8_t)0x01)
#define TIM1_CCER2_CC3NE   ((uint8_t)0x04)
#define TIM1_CCER2_CC3NP   ((uint8_t)0x08)
#define TIM1_CCER2_CC3P   ((uint8_t)0x02)
#define TIM1_CCER2_CC4E   ((uint8_t)0x10)
#define TIM1_CCER2_CC4P   ((uint8_t)0x20)
#define TIM1_CCER2_RESET_VALUE   ((uint8_t)0x00)
#define TIM1_CCMR1_RESET_VALUE   ((uint8_t)0x00)
#define TIM1_CCMR2_RESET_VALUE   ((uint8_t)0x00)
#define TIM1_CCMR3_RESET_VALUE   ((uint8_t)0x00)
#define TIM1_CCMR4_RESET_VALUE   ((uint8_t)0x00)
#define TIM1_CCMR_CCxS   ((uint8_t)0x03)
#define TIM1_CCMR_ICxF   ((uint8_t)0xF0)
#define TIM1_CCMR_ICxPSC   ((uint8_t)0x0C)
#define TIM1_CCMR_OCM   ((uint8_t)0x70)
#define TIM1_CCMR_OCxFE   ((uint8_t)0x04)
#define TIM1_CCMR_OCxPE   ((uint8_t)0x08)
#define TIM1_CCR1H_CCR1   ((uint8_t)0xFF)
#define TIM1_CCR1H_RESET_VALUE   ((uint8_t)0x00)
#define TIM1_CCR1L_CCR1   ((uint8_t)0xFF)
#define TIM1_CCR1L_RESET_VALUE   ((uint8_t)0x00)
#define TIM1_CCR2H_CCR2   ((uint8_t)0xFF)
#define TIM1_CCR2H_RESET_VALUE   ((uint8_t)0x00)
#define TIM1_CCR2L_CCR2   ((uint8_t)0xFF)
#define TIM1_CCR2L_RESET_VALUE   ((uint8_t)0x00)
#define TIM1_CCR3H_CCR3   ((uint8_t)0xFF)
#define TIM1_CCR3H_RESET_VALUE   ((uint8_t)0x00)
#define TIM1_CCR3L_CCR3   ((uint8_t)0xFF)
#define TIM1_CCR3L_RESET_VALUE   ((uint8_t)0x00)
#define TIM1_CCR4H_CCR4   ((uint8_t)0xFF)
#define TIM1_CCR4H_RESET_VALUE   ((uint8_t)0x00)
#define TIM1_CCR4L_CCR4   ((uint8_t)0xFF)
#define TIM1_CCR4L_RESET_VALUE   ((uint8_t)0x00)
#define TIM1_CNTRH_CNT   ((uint8_t)0xFF)
#define TIM1_CNTRH_RESET_VALUE   ((uint8_t)0x00)
#define TIM1_CNTRL_CNT   ((uint8_t)0xFF)
#define TIM1_CNTRL_RESET_VALUE   ((uint8_t)0x00)
#define TIM1_CR1_ARPE   ((uint8_t)0x80)
#define TIM1_CR1_CEN   ((uint8_t)0x01)
#define TIM1_CR1_CMS   ((uint8_t)0x60)
#define TIM1_CR1_DIR   ((uint8_t)0x10)
#define TIM1_CR1_OPM   ((uint8_t)0x08)
#define TIM1_CR1_RESET_VALUE   ((uint8_t)0x00)
#define TIM1_CR1_UDIS   ((uint8_t)0x02)
#define TIM1_CR1_URS   ((uint8_t)0x04)
#define TIM1_CR2_CCPC   ((uint8_t)0x01)
#define TIM1_CR2_COMS   ((uint8_t)0x04)
#define TIM1_CR2_MMS   ((uint8_t)0x70)
#define TIM1_CR2_RESET_VALUE   ((uint8_t)0x00)
#define TIM1_CR2_TI1S   ((uint8_t)0x80)
#define TIM1_DTR_DTG   ((uint8_t)0xFF)
#define TIM1_DTR_RESET_VALUE   ((uint8_t)0x00)
#define TIM1_EGR_BG   ((uint8_t)0x80)
#define TIM1_EGR_CC1G   ((uint8_t)0x02)
#define TIM1_EGR_CC2G   ((uint8_t)0x04)
#define TIM1_EGR_CC3G   ((uint8_t)0x08)
#define TIM1_EGR_CC4G   ((uint8_t)0x10)
#define TIM1_EGR_COMG   ((uint8_t)0x20)
#define TIM1_EGR_RESET_VALUE   ((uint8_t)0x00)
#define TIM1_EGR_TG   ((uint8_t)0x40)
#define TIM1_EGR_UG   ((uint8_t)0x01)
#define TIM1_ETR_ECE   ((uint8_t)0x40)
#define TIM1_ETR_ETF   ((uint8_t)0x0F)
#define TIM1_ETR_ETP   ((uint8_t)0x80)
#define TIM1_ETR_ETPS   ((uint8_t)0x30)
#define TIM1_ETR_RESET_VALUE   ((uint8_t)0x00)
#define TIM1_IER_BIE   ((uint8_t)0x80)
#define TIM1_IER_CC1IE   ((uint8_t)0x02)
#define TIM1_IER_CC2IE   ((uint8_t)0x04)
#define TIM1_IER_CC3IE   ((uint8_t)0x08)
#define TIM1_IER_CC4IE   ((uint8_t)0x10)
#define TIM1_IER_COMIE   ((uint8_t)0x20)
#define TIM1_IER_RESET_VALUE   ((uint8_t)0x00)
#define TIM1_IER_TIE   ((uint8_t)0x40)
#define TIM1_IER_UIE   ((uint8_t)0x01)
#define TIM1_OISR_OIS1   ((uint8_t)0x01)
#define TIM1_OISR_OIS1N   ((uint8_t)0x02)
#define TIM1_OISR_OIS2   ((uint8_t)0x04)
#define TIM1_OISR_OIS2N   ((uint8_t)0x08)
#define TIM1_OISR_OIS3   ((uint8_t)0x10)
#define TIM1_OISR_OIS3N   ((uint8_t)0x20)
#define TIM1_OISR_OIS4   ((uint8_t)0x40)
#define TIM1_OISR_RESET_VALUE   ((uint8_t)0x00)
#define TIM1_PSCH_PSC   ((uint8_t)0xFF)
#define TIM1_PSCL_PSC   ((uint8_t)0xFF)
#define TIM1_PSCRH_RESET_VALUE   ((uint8_t)0x00)
#define TIM1_PSCRL_RESET_VALUE   ((uint8_t)0x00)
#define TIM1_RCR_REP   ((uint8_t)0xFF)
#define TIM1_RCR_RESET_VALUE   ((uint8_t)0x00)
#define TIM1_SMCR_MSM   ((uint8_t)0x80)
#define TIM1_SMCR_RESET_VALUE   ((uint8_t)0x00)
#define TIM1_SMCR_SMS   ((uint8_t)0x07)
#define TIM1_SMCR_TS   ((uint8_t)0x70)
#define TIM1_SR1_BIF   ((uint8_t)0x80)
#define TIM1_SR1_CC1IF   ((uint8_t)0x02)
#define TIM1_SR1_CC2IF   ((uint8_t)0x04)
#define TIM1_SR1_CC3IF   ((uint8_t)0x08)
#define TIM1_SR1_CC4IF   ((uint8_t)0x10)
#define TIM1_SR1_COMIF   ((uint8_t)0x20)
#define TIM1_SR1_RESET_VALUE   ((uint8_t)0x00)
#define TIM1_SR1_TIF   ((uint8_t)0x40)
#define TIM1_SR1_UIF   ((uint8_t)0x01)
#define TIM1_SR2_CC1OF   ((uint8_t)0x02)
#define TIM1_SR2_CC2OF   ((uint8_t)0x04)
#define TIM1_SR2_CC3OF   ((uint8_t)0x08)
#define TIM1_SR2_CC4OF   ((uint8_t)0x10)
#define TIM1_SR2_RESET_VALUE   ((uint8_t)0x00)
#define TIM2_ARRH_ARR   ((uint8_t)0xFF)
#define TIM2_ARRH_RESET_VALUE   ((uint8_t)0xFF)
#define TIM2_ARRL_ARR   ((uint8_t)0xFF)
#define TIM2_ARRL_RESET_VALUE   ((uint8_t)0xFF)
#define TIM2_BaseAddress   0x5300
#define TIM2_CCER1_CC1E   ((uint8_t)0x01)
#define TIM2_CCER1_CC1P   ((uint8_t)0x02)
#define TIM2_CCER1_CC2E   ((uint8_t)0x10)
#define TIM2_CCER1_CC2P   ((uint8_t)0x20)
#define TIM2_CCER1_RESET_VALUE   ((uint8_t)0x00)
#define TIM2_CCER2_CC3E   ((uint8_t)0x01)
#define TIM2_CCER2_CC3P   ((uint8_t)0x02)
#define TIM2_CCER2_RESET_VALUE   ((uint8_t)0x00)
#define TIM2_CCMR1_RESET_VALUE   ((uint8_t)0x00)
#define TIM2_CCMR2_RESET_VALUE   ((uint8_t)0x00)
#define TIM2_CCMR3_RESET_VALUE   ((uint8_t)0x00)
#define TIM2_CCMR_CCxS   ((uint8_t)0x03)
#define TIM2_CCMR_ICxF   ((uint8_t)0xF0)
#define TIM2_CCMR_ICxPSC   ((uint8_t)0x0C)
#define TIM2_CCMR_OCM   ((uint8_t)0x70)
#define TIM2_CCMR_OCxPE   ((uint8_t)0x08)
#define TIM2_CCR1H_CCR1   ((uint8_t)0xFF)
#define TIM2_CCR1H_RESET_VALUE   ((uint8_t)0x00)
#define TIM2_CCR1L_CCR1   ((uint8_t)0xFF)
#define TIM2_CCR1L_RESET_VALUE   ((uint8_t)0x00)
#define TIM2_CCR2H_CCR2   ((uint8_t)0xFF)
#define TIM2_CCR2H_RESET_VALUE   ((uint8_t)0x00)
#define TIM2_CCR2L_CCR2   ((uint8_t)0xFF)
#define TIM2_CCR2L_RESET_VALUE   ((uint8_t)0x00)
#define TIM2_CCR3H_CCR3   ((uint8_t)0xFF)
#define TIM2_CCR3H_RESET_VALUE   ((uint8_t)0x00)
#define TIM2_CCR3L_CCR3   ((uint8_t)0xFF)
#define TIM2_CCR3L_RESET_VALUE   ((uint8_t)0x00)
#define TIM2_CNTRH_CNT   ((uint8_t)0xFF)
#define TIM2_CNTRH_RESET_VALUE   ((uint8_t)0x00)
#define TIM2_CNTRL_CNT   ((uint8_t)0xFF)
#define TIM2_CNTRL_RESET_VALUE   ((uint8_t)0x00)
#define TIM2_CR1_ARPE   ((uint8_t)0x80)
#define TIM2_CR1_CEN   ((uint8_t)0x01)
#define TIM2_CR1_OPM   ((uint8_t)0x08)
#define TIM2_CR1_RESET_VALUE   ((uint8_t)0x00)
#define TIM2_CR1_UDIS   ((uint8_t)0x02)
#define TIM2_CR1_URS   ((uint8_t)0x04)
#define TIM2_EGR_CC1G   ((uint8_t)0x02)
#define TIM2_EGR_CC2G   ((uint8_t)0x04)
#define TIM2_EGR_CC3G   ((uint8_t)0x08)
#define TIM2_EGR_RESET_VALUE   ((uint8_t)0x00)
#define TIM2_EGR_UG   ((uint8_t)0x01)
#define TIM2_IER_CC1IE   ((uint8_t)0x02)
#define TIM2_IER_CC2IE   ((uint8_t)0x04)
#define TIM2_IER_CC3IE   ((uint8_t)0x08)
#define TIM2_IER_RESET_VALUE   ((uint8_t)0x00)
#define TIM2_IER_UIE   ((uint8_t)0x01)
#define TIM2_PSCR_PSC   ((uint8_t)0xFF)
#define TIM2_PSCR_RESET_VALUE   ((uint8_t)0x00)
#define TIM2_SR1_CC1IF   ((uint8_t)0x02)
#define TIM2_SR1_CC2IF   ((uint8_t)0x04)
#define TIM2_SR1_CC3IF   ((uint8_t)0x08)
#define TIM2_SR1_RESET_VALUE   ((uint8_t)0x00)
#define TIM2_SR1_UIF   ((uint8_t)0x01)
#define TIM2_SR2_CC1OF   ((uint8_t)0x02)
#define TIM2_SR2_CC2OF   ((uint8_t)0x04)
#define TIM2_SR2_CC3OF   ((uint8_t)0x08)
#define TIM2_SR2_RESET_VALUE   ((uint8_t)0x00)
#define TIM3_ARRH_ARR   ((uint8_t)0xFF)
#define TIM3_ARRH_RESET_VALUE   ((uint8_t)0xFF)
#define TIM3_ARRL_ARR   ((uint8_t)0xFF)
#define TIM3_ARRL_RESET_VALUE   ((uint8_t)0xFF)
#define TIM3_BaseAddress   0x5320
#define TIM3_CCER1_CC1E   ((uint8_t)0x01)
#define TIM3_CCER1_CC1P   ((uint8_t)0x02)
#define TIM3_CCER1_CC2E   ((uint8_t)0x10)
#define TIM3_CCER1_CC2P   ((uint8_t)0x20)
#define TIM3_CCER1_RESET_VALUE   ((uint8_t)0x00)
#define TIM3_CCMR1_RESET_VALUE   ((uint8_t)0x00)
#define TIM3_CCMR2_RESET_VALUE   ((uint8_t)0x00)
#define TIM3_CCMR_CCxS   ((uint8_t)0x03)
#define TIM3_CCMR_ICxF   ((uint8_t)0xF0)
#define TIM3_CCMR_ICxPSC   ((uint8_t)0x0C)
#define TIM3_CCMR_OCM   ((uint8_t)0x70)
#define TIM3_CCMR_OCxPE   ((uint8_t)0x08)
#define TIM3_CCR1H_CCR1   ((uint8_t)0xFF)
#define TIM3_CCR1H_RESET_VALUE   ((uint8_t)0x00)
#define TIM3_CCR1L_CCR1   ((uint8_t)0xFF)
#define TIM3_CCR1L_RESET_VALUE   ((uint8_t)0x00)
#define TIM3_CCR2H_CCR2   ((uint8_t)0xFF)
#define TIM3_CCR2H_RESET_VALUE   ((uint8_t)0x00)
#define TIM3_CCR2L_CCR2   ((uint8_t)0xFF)
#define TIM3_CCR2L_RESET_VALUE   ((uint8_t)0x00)
#define TIM3_CNTRH_CNT   ((uint8_t)0xFF)
#define TIM3_CNTRH_RESET_VALUE   ((uint8_t)0x00)
#define TIM3_CNTRL_CNT   ((uint8_t)0xFF)
#define TIM3_CNTRL_RESET_VALUE   ((uint8_t)0x00)
#define TIM3_CR1_ARPE   ((uint8_t)0x80)
#define TIM3_CR1_CEN   ((uint8_t)0x01)
#define TIM3_CR1_OPM   ((uint8_t)0x08)
#define TIM3_CR1_RESET_VALUE   ((uint8_t)0x00)
#define TIM3_CR1_UDIS   ((uint8_t)0x02)
#define TIM3_CR1_URS   ((uint8_t)0x04)
#define TIM3_EGR_CC1G   ((uint8_t)0x02)
#define TIM3_EGR_CC2G   ((uint8_t)0x04)
#define TIM3_EGR_RESET_VALUE   ((uint8_t)0x00)
#define TIM3_EGR_UG   ((uint8_t)0x01)
#define TIM3_IER_CC1IE   ((uint8_t)0x02)
#define TIM3_IER_CC2IE   ((uint8_t)0x04)
#define TIM3_IER_RESET_VALUE   ((uint8_t)0x00)
#define TIM3_IER_UIE   ((uint8_t)0x01)
#define TIM3_PSCR_PSC   ((uint8_t)0xFF)
#define TIM3_PSCR_RESET_VALUE   ((uint8_t)0x00)
#define TIM3_SR1_CC1IF   ((uint8_t)0x02)
#define TIM3_SR1_CC2IF   ((uint8_t)0x04)
#define TIM3_SR1_RESET_VALUE   ((uint8_t)0x00)
#define TIM3_SR1_UIF   ((uint8_t)0x01)
#define TIM3_SR2_CC1OF   ((uint8_t)0x02)
#define TIM3_SR2_CC2OF   ((uint8_t)0x04)
#define TIM3_SR2_RESET_VALUE   ((uint8_t)0x00)
#define TIM4_ARR_ARR   ((uint8_t)0xFF)
#define TIM4_ARR_RESET_VALUE   ((uint8_t)0xFF)
#define TIM4_BaseAddress   0x5340
#define TIM4_CNTR_CNT   ((uint8_t)0xFF)
#define TIM4_CNTR_RESET_VALUE   ((uint8_t)0x00)
#define TIM4_CR1_ARPE   ((uint8_t)0x80)
#define TIM4_CR1_CEN   ((uint8_t)0x01)
#define TIM4_CR1_OPM   ((uint8_t)0x08)
#define TIM4_CR1_RESET_VALUE   ((uint8_t)0x00)
#define TIM4_CR1_UDIS   ((uint8_t)0x02)
#define TIM4_CR1_URS   ((uint8_t)0x04)
#define TIM4_EGR_RESET_VALUE   ((uint8_t)0x00)
#define TIM4_EGR_UG   ((uint8_t)0x01)
#define TIM4_IER_RESET_VALUE   ((uint8_t)0x00)
#define TIM4_IER_UIE   ((uint8_t)0x01)
#define TIM4_PSCR_PSC   ((uint8_t)0x07)
#define TIM4_PSCR_RESET_VALUE   ((uint8_t)0x00)
#define TIM4_SR1_RESET_VALUE   ((uint8_t)0x00)
#define TIM4_SR1_UIF   ((uint8_t)0x01)
#define TIM5_ARRH_ARR   ((uint8_t)0xFF)
#define TIM5_ARRH_RESET_VALUE   ((uint8_t)0xFF)
#define TIM5_ARRL_ARR   ((uint8_t)0xFF)
#define TIM5_ARRL_RESET_VALUE   ((uint8_t)0xFF)
#define TIM5_BaseAddress   0x5300
#define TIM5_CCER1_CC1E   ((uint8_t)0x01)
#define TIM5_CCER1_CC1P   ((uint8_t)0x02)
#define TIM5_CCER1_CC2E   ((uint8_t)0x10)
#define TIM5_CCER1_CC2P   ((uint8_t)0x20)
#define TIM5_CCER1_RESET_VALUE   ((uint8_t)0x00)
#define TIM5_CCER2_CC3E   ((uint8_t)0x01)
#define TIM5_CCER2_CC3P   ((uint8_t)0x02)
#define TIM5_CCER2_RESET_VALUE   ((uint8_t)0x00)
#define TIM5_CCMR1_RESET_VALUE   ((uint8_t)0x00)
#define TIM5_CCMR2_RESET_VALUE   ((uint8_t)0x00)
#define TIM5_CCMR3_RESET_VALUE   ((uint8_t)0x00)
#define TIM5_CCMR_CCxS   ((uint8_t)0x03)
#define TIM5_CCMR_ICxF   ((uint8_t)0xF0)
#define TIM5_CCMR_ICxPSC   ((uint8_t)0x0C)
#define TIM5_CCMR_OCM   ((uint8_t)0x70)
#define TIM5_CCMR_OCxPE   ((uint8_t)0x08)
#define TIM5_CCMR_TIxDirect_Set   ((uint8_t)0x01)
#define TIM5_CCR1H_CCR1   ((uint8_t)0xFF)
#define TIM5_CCR1H_RESET_VALUE   ((uint8_t)0x00)
#define TIM5_CCR1L_CCR1   ((uint8_t)0xFF)
#define TIM5_CCR1L_RESET_VALUE   ((uint8_t)0x00)
#define TIM5_CCR2H_CCR2   ((uint8_t)0xFF)
#define TIM5_CCR2H_RESET_VALUE   ((uint8_t)0x00)
#define TIM5_CCR2L_CCR2   ((uint8_t)0xFF)
#define TIM5_CCR2L_RESET_VALUE   ((uint8_t)0x00)
#define TIM5_CCR3H_CCR3   ((uint8_t)0xFF)
#define TIM5_CCR3H_RESET_VALUE   ((uint8_t)0x00)
#define TIM5_CCR3L_CCR3   ((uint8_t)0xFF)
#define TIM5_CCR3L_RESET_VALUE   ((uint8_t)0x00)
#define TIM5_CNTRH_CNT   ((uint8_t)0xFF)
#define TIM5_CNTRH_RESET_VALUE   ((uint8_t)0x00)
#define TIM5_CNTRL_CNT   ((uint8_t)0xFF)
#define TIM5_CNTRL_RESET_VALUE   ((uint8_t)0x00)
#define TIM5_CR1_ARPE   ((uint8_t)0x80)
#define TIM5_CR1_CEN   ((uint8_t)0x01)
#define TIM5_CR1_OPM   ((uint8_t)0x08)
#define TIM5_CR1_RESET_VALUE   ((uint8_t)0x00)
#define TIM5_CR1_UDIS   ((uint8_t)0x02)
#define TIM5_CR1_URS   ((uint8_t)0x04)
#define TIM5_CR2_MMS   ((uint8_t)0x70)
#define TIM5_CR2_RESET_VALUE   ((uint8_t)0x00)
#define TIM5_CR2_TI1S   ((uint8_t)0x80)
#define TIM5_EGR_CC1G   ((uint8_t)0x02)
#define TIM5_EGR_CC2G   ((uint8_t)0x04)
#define TIM5_EGR_CC3G   ((uint8_t)0x08)
#define TIM5_EGR_RESET_VALUE   ((uint8_t)0x00)
#define TIM5_EGR_TG   ((uint8_t)0x40)
#define TIM5_EGR_UG   ((uint8_t)0x01)
#define TIM5_IER_CC1IE   ((uint8_t)0x02)
#define TIM5_IER_CC2IE   ((uint8_t)0x04)
#define TIM5_IER_CC3IE   ((uint8_t)0x08)
#define TIM5_IER_RESET_VALUE   ((uint8_t)0x00)
#define TIM5_IER_TIE   ((uint8_t)0x40)
#define TIM5_IER_UIE   ((uint8_t)0x01)
#define TIM5_PSCR_PSC   ((uint8_t)0xFF)
#define TIM5_PSCR_RESET_VALUE   ((uint8_t)0x00)
#define TIM5_SMCR_MSM   ((uint8_t)0x80)
#define TIM5_SMCR_RESET_VALUE   ((uint8_t)0x00)
#define TIM5_SMCR_SMS   ((uint8_t)0x07)
#define TIM5_SMCR_TS   ((uint8_t)0x70)
#define TIM5_SR1_CC1IF   ((uint8_t)0x02)
#define TIM5_SR1_CC2IF   ((uint8_t)0x04)
#define TIM5_SR1_CC3IF   ((uint8_t)0x08)
#define TIM5_SR1_RESET_VALUE   ((uint8_t)0x00)
#define TIM5_SR1_TIF   ((uint8_t)0x40)
#define TIM5_SR1_UIF   ((uint8_t)0x01)
#define TIM5_SR2_CC1OF   ((uint8_t)0x02)
#define TIM5_SR2_CC2OF   ((uint8_t)0x04)
#define TIM5_SR2_CC3OF   ((uint8_t)0x08)
#define TIM5_SR2_RESET_VALUE   ((uint8_t)0x00)
#define TIM6_ARR_ARR   ((uint8_t)0xFF)
#define TIM6_ARR_RESET_VALUE   ((uint8_t)0xFF)
#define TIM6_BaseAddress   0x5340
#define TIM6_CNTR_CNT   ((uint8_t)0xFF)
#define TIM6_CNTR_RESET_VALUE   ((uint8_t)0x00)
#define TIM6_CR1_ARPE   ((uint8_t)0x80)
#define TIM6_CR1_CEN   ((uint8_t)0x01)
#define TIM6_CR1_OPM   ((uint8_t)0x08)
#define TIM6_CR1_RESET_VALUE   ((uint8_t)0x00)
#define TIM6_CR1_UDIS   ((uint8_t)0x02)
#define TIM6_CR1_URS   ((uint8_t)0x04)
#define TIM6_CR2_MMS   ((uint8_t)0x70)
#define TIM6_CR2_RESET_VALUE   ((uint8_t)0x00)
#define TIM6_EGR_RESET_VALUE   ((uint8_t)0x00)
#define TIM6_EGR_TG   ((uint8_t)0x40)
#define TIM6_EGR_UG   ((uint8_t)0x01)
#define TIM6_IER_RESET_VALUE   ((uint8_t)0x00)
#define TIM6_IER_TIE   ((uint8_t)0x40)
#define TIM6_IER_UIE   ((uint8_t)0x01)
#define TIM6_PSCR_PSC   ((uint8_t)0x07)
#define TIM6_PSCR_RESET_VALUE   ((uint8_t)0x00)
#define TIM6_SMCR_MSM   ((uint8_t)0x80)
#define TIM6_SMCR_RESET_VALUE   ((uint8_t)0x00)
#define TIM6_SMCR_SMS   ((uint8_t)0x07)
#define TIM6_SMCR_TS   ((uint8_t)0x70)
#define TIM6_SR1_RESET_VALUE   ((uint8_t)0x00)
#define TIM6_SR1_TIF   ((uint8_t)0x40)
#define TIM6_SR1_UIF   ((uint8_t)0x01)
#define TINY   __tiny
#define trap()   __trap()
#define U16_MAX   (65535u)
#define U32_MAX   (4294967295uL)
#define U8_MAX   (255)
#define UART1_BaseAddress   0x5230
#define UART1_BRR1_DIVM   ((uint8_t)0xFF)
#define UART1_BRR1_RESET_VALUE   ((uint8_t)0x00)
#define UART1_BRR2_DIVF   ((uint8_t)0x0F)
#define UART1_BRR2_DIVM   ((uint8_t)0xF0)
#define UART1_BRR2_RESET_VALUE   ((uint8_t)0x00)
#define UART1_CR1_M   ((uint8_t)0x10)
#define UART1_CR1_PCEN   ((uint8_t)0x04)
#define UART1_CR1_PIEN   ((uint8_t)0x01)
#define UART1_CR1_PS   ((uint8_t)0x02)
#define UART1_CR1_R8   ((uint8_t)0x80)
#define UART1_CR1_RESET_VALUE   ((uint8_t)0x00)
#define UART1_CR1_T8   ((uint8_t)0x40)
#define UART1_CR1_UARTD   ((uint8_t)0x20)
#define UART1_CR1_WAKE   ((uint8_t)0x08)
#define UART1_CR2_ILIEN   ((uint8_t)0x10)
#define UART1_CR2_REN   ((uint8_t)0x04)
#define UART1_CR2_RESET_VALUE   ((uint8_t)0x00)
#define UART1_CR2_RIEN   ((uint8_t)0x20)
#define UART1_CR2_RWU   ((uint8_t)0x02)
#define UART1_CR2_SBK   ((uint8_t)0x01)
#define UART1_CR2_TCIEN   ((uint8_t)0x40)
#define UART1_CR2_TEN   ((uint8_t)0x08)
#define UART1_CR2_TIEN   ((uint8_t)0x80)
#define UART1_CR3_CKEN   ((uint8_t)0x08)
#define UART1_CR3_CPHA   ((uint8_t)0x02)
#define UART1_CR3_CPOL   ((uint8_t)0x04)
#define UART1_CR3_LBCL   ((uint8_t)0x01)
#define UART1_CR3_LINEN   ((uint8_t)0x40)
#define UART1_CR3_RESET_VALUE   ((uint8_t)0x00)
#define UART1_CR3_STOP   ((uint8_t)0x30)
#define UART1_CR4_ADD   ((uint8_t)0x0F)
#define UART1_CR4_LBDF   ((uint8_t)0x10)
#define UART1_CR4_LBDIEN   ((uint8_t)0x40)
#define UART1_CR4_LBDL   ((uint8_t)0x20)
#define UART1_CR4_RESET_VALUE   ((uint8_t)0x00)
#define UART1_CR5_HDSEL   ((uint8_t)0x08)
#define UART1_CR5_IREN   ((uint8_t)0x02)
#define UART1_CR5_IRLP   ((uint8_t)0x04)
#define UART1_CR5_NACK   ((uint8_t)0x10)
#define UART1_CR5_RESET_VALUE   ((uint8_t)0x00)
#define UART1_CR5_SCEN   ((uint8_t)0x20)
#define UART1_GTR_RESET_VALUE   ((uint8_t)0x00)
#define UART1_PSCR_RESET_VALUE   ((uint8_t)0x00)
#define UART1_SR_FE   ((uint8_t)0x02)
#define UART1_SR_IDLE   ((uint8_t)0x10)
#define UART1_SR_NF   ((uint8_t)0x04)
#define UART1_SR_OR   ((uint8_t)0x08)
#define UART1_SR_PE   ((uint8_t)0x01)
#define UART1_SR_RESET_VALUE   ((uint8_t)0xC0)
#define UART1_SR_RXNE   ((uint8_t)0x20)
#define UART1_SR_TC   ((uint8_t)0x40)
#define UART1_SR_TXE   ((uint8_t)0x80)
#define UART2_BaseAddress   0x5240
#define UART2_BRR1_DIVM   ((uint8_t)0xFF)
#define UART2_BRR1_RESET_VALUE   ((uint8_t)0x00)
#define UART2_BRR2_DIVF   ((uint8_t)0x0F)
#define UART2_BRR2_DIVM   ((uint8_t)0xF0)
#define UART2_BRR2_RESET_VALUE   ((uint8_t)0x00)
#define UART2_CR1_M   ((uint8_t)0x10)
#define UART2_CR1_PCEN   ((uint8_t)0x04)
#define UART2_CR1_PIEN   ((uint8_t)0x01)
#define UART2_CR1_PS   ((uint8_t)0x02)
#define UART2_CR1_R8   ((uint8_t)0x80)
#define UART2_CR1_RESET_VALUE   ((uint8_t)0x00)
#define UART2_CR1_T8   ((uint8_t)0x40)
#define UART2_CR1_UARTD   ((uint8_t)0x20)
#define UART2_CR1_WAKE   ((uint8_t)0x08)
#define UART2_CR2_ILIEN   ((uint8_t)0x10)
#define UART2_CR2_REN   ((uint8_t)0x04)
#define UART2_CR2_RESET_VALUE   ((uint8_t)0x00)
#define UART2_CR2_RIEN   ((uint8_t)0x20)
#define UART2_CR2_RWU   ((uint8_t)0x02)
#define UART2_CR2_SBK   ((uint8_t)0x01)
#define UART2_CR2_TCIEN   ((uint8_t)0x40)
#define UART2_CR2_TEN   ((uint8_t)0x08)
#define UART2_CR2_TIEN   ((uint8_t)0x80)
#define UART2_CR3_CKEN   ((uint8_t)0x08)
#define UART2_CR3_CPHA   ((uint8_t)0x02)
#define UART2_CR3_CPOL   ((uint8_t)0x04)
#define UART2_CR3_LBCL   ((uint8_t)0x01)
#define UART2_CR3_LINEN   ((uint8_t)0x40)
#define UART2_CR3_RESET_VALUE   ((uint8_t)0x00)
#define UART2_CR3_STOP   ((uint8_t)0x30)
#define UART2_CR4_ADD   ((uint8_t)0x0F)
#define UART2_CR4_LBDF   ((uint8_t)0x10)
#define UART2_CR4_LBDIEN   ((uint8_t)0x40)
#define UART2_CR4_LBDL   ((uint8_t)0x20)
#define UART2_CR4_RESET_VALUE   ((uint8_t)0x00)
#define UART2_CR5_IREN   ((uint8_t)0x02)
#define UART2_CR5_IRLP   ((uint8_t)0x04)
#define UART2_CR5_NACK   ((uint8_t)0x10)
#define UART2_CR5_RESET_VALUE   ((uint8_t)0x00)
#define UART2_CR5_SCEN   ((uint8_t)0x20)
#define UART2_CR6_LASE   ((uint8_t)0x10)
#define UART2_CR6_LDUM   ((uint8_t)0x80)
#define UART2_CR6_LHDF   ((uint8_t)0x02)
#define UART2_CR6_LHDIEN   ((uint8_t)0x04)
#define UART2_CR6_LSF   ((uint8_t)0x01)
#define UART2_CR6_LSLV   ((uint8_t)0x20)
#define UART2_CR6_RESET_VALUE   ((uint8_t)0x00)
#define UART2_GTR_RESET_VALUE   ((uint8_t)0x00)
#define UART2_PSCR_RESET_VALUE   ((uint8_t)0x00)
#define UART2_SR_FE   ((uint8_t)0x02)
#define UART2_SR_IDLE   ((uint8_t)0x10)
#define UART2_SR_NF   ((uint8_t)0x04)
#define UART2_SR_OR   ((uint8_t)0x08)
#define UART2_SR_PE   ((uint8_t)0x01)
#define UART2_SR_RESET_VALUE   ((uint8_t)0xC0)
#define UART2_SR_RXNE   ((uint8_t)0x20)
#define UART2_SR_TC   ((uint8_t)0x40)
#define UART2_SR_TXE   ((uint8_t)0x80)
#define UART3_BaseAddress   0x5240
#define UART3_BRR1_DIVM   ((uint8_t)0xFF)
#define UART3_BRR1_RESET_VALUE   ((uint8_t)0x00)
#define UART3_BRR2_DIVF   ((uint8_t)0x0F)
#define UART3_BRR2_DIVM   ((uint8_t)0xF0)
#define UART3_BRR2_RESET_VALUE   ((uint8_t)0x00)
#define UART3_CR1_M   ((uint8_t)0x10)
#define UART3_CR1_PCEN   ((uint8_t)0x04)
#define UART3_CR1_PIEN   ((uint8_t)0x01)
#define UART3_CR1_PS   ((uint8_t)0x02)
#define UART3_CR1_R8   ((uint8_t)0x80)
#define UART3_CR1_RESET_VALUE   ((uint8_t)0x00)
#define UART3_CR1_T8   ((uint8_t)0x40)
#define UART3_CR1_UARTD   ((uint8_t)0x20)
#define UART3_CR1_WAKE   ((uint8_t)0x08)
#define UART3_CR2_ILIEN   ((uint8_t)0x10)
#define UART3_CR2_REN   ((uint8_t)0x04)
#define UART3_CR2_RESET_VALUE   ((uint8_t)0x00)
#define UART3_CR2_RIEN   ((uint8_t)0x20)
#define UART3_CR2_RWU   ((uint8_t)0x02)
#define UART3_CR2_SBK   ((uint8_t)0x01)
#define UART3_CR2_TCIEN   ((uint8_t)0x40)
#define UART3_CR2_TEN   ((uint8_t)0x08)
#define UART3_CR2_TIEN   ((uint8_t)0x80)
#define UART3_CR3_LINEN   ((uint8_t)0x40)
#define UART3_CR3_RESET_VALUE   ((uint8_t)0x00)
#define UART3_CR3_STOP   ((uint8_t)0x30)
#define UART3_CR4_ADD   ((uint8_t)0x0F)
#define UART3_CR4_LBDF   ((uint8_t)0x10)
#define UART3_CR4_LBDIEN   ((uint8_t)0x40)
#define UART3_CR4_LBDL   ((uint8_t)0x20)
#define UART3_CR4_RESET_VALUE   ((uint8_t)0x00)
#define UART3_CR6_LASE   ((uint8_t)0x10)
#define UART3_CR6_LDUM   ((uint8_t)0x80)
#define UART3_CR6_LHDF   ((uint8_t)0x02)
#define UART3_CR6_LHDIEN   ((uint8_t)0x04)
#define UART3_CR6_LSF   ((uint8_t)0x01)
#define UART3_CR6_LSLV   ((uint8_t)0x20)
#define UART3_CR6_RESET_VALUE   ((uint8_t)0x00)
#define UART3_SR_FE   ((uint8_t)0x02)
#define UART3_SR_IDLE   ((uint8_t)0x10)
#define UART3_SR_NF   ((uint8_t)0x04)
#define UART3_SR_OR   ((uint8_t)0x08)
#define UART3_SR_PE   ((uint8_t)0x01)
#define UART3_SR_RESET_VALUE   ((uint8_t)0xC0)
#define UART3_SR_RXNE   ((uint8_t)0x20)
#define UART3_SR_TC   ((uint8_t)0x40)
#define UART3_SR_TXE   ((uint8_t)0x80)
#define UART4_BaseAddress   0x5230
#define USE_STDPERIPH_DRIVER
#define ValBit(VAR, Place)   ((uint8_t)(VAR) & (uint8_t)((uint8_t)1<<(uint8_t)(Place)))
#define wfi()   __wait_for_interrupt()
#define WWDG   ((WWDG_TypeDef *) WWDG_BaseAddress)
#define WWDG_BaseAddress   0x50D1
#define WWDG_CR_RESET_VALUE   ((uint8_t)0x7F)
#define WWDG_CR_T   ((uint8_t)0x7F)
#define WWDG_CR_T6   ((uint8_t)0x40)
#define WWDG_CR_WDGA   ((uint8_t)0x80)
#define WWDG_WR_MSB   ((uint8_t)0x80)
#define WWDG_WR_RESET_VALUE   ((uint8_t)0x7F)
#define WWDG_WR_W   ((uint8_t)0x7F)

Typedefs

typedef struct AWU_struct AWU_TypeDef
 Auto Wake Up (AWU) peripheral registers.
typedef struct BEEP_struct BEEP_TypeDef
 Beeper (BEEP) peripheral registers.
typedef enum FlagStatus BitAction
typedef enum FlagStatus BitStatus
typedef struct CFG_struct CFG_TypeDef
 Configuration Registers (CFG)
typedef struct CLK_struct CLK_TypeDef
 Clock Controller (CLK)
typedef struct EXTI_struct EXTI_TypeDef
 External Interrupt Controller (EXTI)
typedef struct FLASH_struct FLASH_TypeDef
 FLASH program and Data memory (FLASH)
typedef struct GPIO_struct GPIO_TypeDef
 General Purpose I/Os (GPIO)
typedef struct I2C_struct I2C_TypeDef
 Inter-Integrated Circuit (I2C)
typedef signed short int16_t
typedef signed long int32_t
typedef signed char int8_t
typedef struct ITC_struct ITC_TypeDef
 Interrupt Controller (ITC)
typedef enum FlagStatus ITStatus
typedef struct IWDG_struct IWDG_TypeDef
 Independent Watchdog (IWDG)
typedef struct OPT_struct OPT_TypeDef
 Option Bytes (OPT)
typedef struct RST_struct RST_TypeDef
 Reset Controller (RST)
typedef int16_t s16
typedef int32_t s32
typedef int8_t s8
typedef struct SPI_struct SPI_TypeDef
 Serial Peripheral Interface (SPI)
typedef struct TIM1_struct TIM1_TypeDef
 16-bit timer with complementary PWM outputs (TIM1)
typedef struct TIM2_struct TIM2_TypeDef
 16-bit timer (TIM2)
typedef struct TIM3_struct TIM3_TypeDef
 16-bit timer (TIM3)
typedef struct TIM4_struct TIM4_TypeDef
 8-bit system timer (TIM4)
typedef struct TIM5_struct TIM5_TypeDef
 16-bit timer with synchro module (TIM5)
typedef struct TIM6_struct TIM6_TypeDef
 8-bit system timer with synchro module(TIM6)
typedef uint16_t u16
typedef uint32_t u32
typedef uint8_t u8
typedef struct UART1_struct UART1_TypeDef
 Universal Synchronous Asynchronous Receiver Transmitter (UART1)
typedef struct UART2_struct UART2_TypeDef
 Universal Synchronous Asynchronous Receiver Transmitter (UART2)
typedef struct UART3_struct UART3_TypeDef
 LIN Universal Asynchronous Receiver Transmitter (UART3)
typedef unsigned short uint16_t
typedef unsigned long uint32_t
typedef unsigned char uint8_t
typedef struct WWDG_struct WWDG_TypeDef
 Window Watchdog (WWDG)

Enumerations

enum  bool { FALSE = 0, TRUE = !FALSE }
enum  ErrorStatus { ERROR = 0, SUCCESS = !ERROR }
enum  FlagStatus { RESET = 0, SET = !RESET }
enum  FunctionalState { DISABLE = 0, ENABLE = !DISABLE }

Detailed Description

This file contains all HW registers definitions and memory mapping.

Author:
MCD Application Team
Version:
V2.3.0
Date:
16-June-2017
Attention:

© COPYRIGHT 2014 STMicroelectronics

Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at:

http://www.st.com/software_license_agreement_liberty_v2

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Definition in file stm8s.h.

Define Documentation

#define AffBit (   VAR,
  Place,
  Value 
)
Value:
((Value) ? \
                                   ((VAR) |= ((uint8_t)1<<(Place))) : \
                                   ((VAR) &= (((uint8_t)1<<(Place))^(uint8_t)255)))

Definition at line 2793 of file stm8s.h.

#define AREA   0x00

Definition at line 2819 of file stm8s.h.

#define AWU   ((AWU_TypeDef *) AWU_BaseAddress)

Definition at line 2611 of file stm8s.h.

Referenced by AWU_Cmd(), AWU_DeInit(), AWU_GetFlagStatus(), AWU_IdleModeEnable(), AWU_Init(), and AWU_LSICalibrationConfig().

#define BEEP   ((BEEP_TypeDef *) BEEP_BaseAddress)

Definition at line 2613 of file stm8s.h.

Referenced by BEEP_Cmd(), BEEP_DeInit(), BEEP_Init(), and BEEP_LSICalibrationConfig().

#define BitClr (   BIT)    ( *((unsigned char *) (AREA+(BIT)/8)) &= (~(1<<(7-(BIT)%8))) )

Definition at line 2821 of file stm8s.h.

#define BitSet (   BIT)    ( *((unsigned char *) (AREA+(BIT)/8)) |= (1<<(7-(BIT)%8)) )

Definition at line 2822 of file stm8s.h.

#define BitVal (   BIT)    ( *((unsigned char *) (AREA+(BIT)/8)) & (1<<(7-(BIT)%8)) )

Definition at line 2823 of file stm8s.h.

#define BYTE_0 (   n)    ((uint8_t)((n) & (uint8_t)0xFF))

Returns the low byte of the 32-bit value

Definition at line 2800 of file stm8s.h.

#define BYTE_1 (   n)    ((uint8_t)(BYTE_0((n) >> (uint8_t)8)))

Returns the second byte of the 32-bit value

Definition at line 2801 of file stm8s.h.

#define BYTE_2 (   n)    ((uint8_t)(BYTE_0((n) >> (uint8_t)16)))

Returns the third byte of the 32-bit value

Definition at line 2802 of file stm8s.h.

#define BYTE_3 (   n)    ((uint8_t)(BYTE_0((n) >> (uint8_t)24)))

Returns the high byte of the 32-bit value

Definition at line 2803 of file stm8s.h.

#define CFG   ((CFG_TypeDef *) CFG_BaseAddress)

Definition at line 2702 of file stm8s.h.

#define ChgBit (   VAR,
  Place 
)    ( (VAR) ^= (uint8_t)((uint8_t)1<<(uint8_t)(Place)) )

Definition at line 2792 of file stm8s.h.

#define CLK   ((CLK_TypeDef *) CLK_BaseAddress)

Definition at line 2619 of file stm8s.h.

Referenced by CLK_AdjustHSICalibrationValue(), CLK_CCOCmd(), CLK_CCOConfig(), CLK_ClearITPendingBit(), CLK_ClockSecuritySystemEnable(), CLK_ClockSwitchCmd(), CLK_ClockSwitchConfig(), CLK_DeInit(), CLK_FastHaltWakeUpCmd(), CLK_GetClockFreq(), CLK_GetFlagStatus(), CLK_GetITStatus(), CLK_GetSYSCLKSource(), CLK_HSECmd(), CLK_HSICmd(), CLK_HSIPrescalerConfig(), CLK_ITConfig(), CLK_LSICmd(), CLK_PeripheralClockConfig(), CLK_SlowActiveHaltWakeUpCmd(), CLK_SWIMConfig(), CLK_SYSCLKConfig(), and CLK_SYSCLKEmergencyClear().

#define ClrBit (   VAR,
  Place 
)    ( (VAR) &= (uint8_t)((uint8_t)((uint8_t)1<<(uint8_t)(Place))^(uint8_t)255) )

Definition at line 2790 of file stm8s.h.

#define disableInterrupts ( )    __disable_interrupt()

Definition at line 2736 of file stm8s.h.

#define DM   ((DM_TypeDef *) DM_BaseAddress)

Definition at line 2704 of file stm8s.h.

#define enableInterrupts ( )    __enable_interrupt()

Definition at line 2735 of file stm8s.h.

#define EXTI   ((EXTI_TypeDef *) EXTI_BaseAddress)

Definition at line 2621 of file stm8s.h.

Referenced by EXTI_DeInit(), EXTI_GetExtIntSensitivity(), EXTI_GetTLISensitivity(), EXTI_SetExtIntSensitivity(), and EXTI_SetTLISensitivity().

#define FLASH   ((FLASH_TypeDef *) FLASH_BaseAddress)

Definition at line 2623 of file stm8s.h.

Referenced by FLASH_DeInit(), FLASH_EraseOptionByte(), FLASH_GetBootSize(), FLASH_GetFlagStatus(), FLASH_GetLowPowerMode(), FLASH_GetProgrammingTime(), FLASH_ITConfig(), FLASH_Lock(), FLASH_ProgramOptionByte(), FLASH_ProgramWord(), FLASH_SetLowPowerMode(), FLASH_SetProgrammingTime(), and FLASH_Unlock().

#define GPIOA   ((GPIO_TypeDef *) GPIOA_BaseAddress)

Definition at line 2627 of file stm8s.h.

#define GPIOB   ((GPIO_TypeDef *) GPIOB_BaseAddress)

Definition at line 2629 of file stm8s.h.

#define GPIOC   ((GPIO_TypeDef *) GPIOC_BaseAddress)

Definition at line 2631 of file stm8s.h.

#define GPIOD   ((GPIO_TypeDef *) GPIOD_BaseAddress)

Definition at line 2633 of file stm8s.h.

#define GPIOE   ((GPIO_TypeDef *) GPIOE_BaseAddress)

Definition at line 2635 of file stm8s.h.

#define GPIOF   ((GPIO_TypeDef *) GPIOF_BaseAddress)

Definition at line 2637 of file stm8s.h.

#define halt ( )    __halt()

Definition at line 2742 of file stm8s.h.

#define I2C   ((I2C_TypeDef *) I2C_BaseAddress)

Definition at line 2656 of file stm8s.h.

Referenced by I2C_AcknowledgeConfig(), I2C_CheckEvent(), I2C_ClearFlag(), I2C_ClearITPendingBit(), I2C_Cmd(), I2C_DeInit(), I2C_FastModeDutyCycleConfig(), I2C_GeneralCallCmd(), I2C_GenerateSTART(), I2C_GenerateSTOP(), I2C_GetFlagStatus(), I2C_GetITStatus(), I2C_GetLastEvent(), I2C_Init(), I2C_ITConfig(), I2C_ReceiveData(), I2C_Send7bitAddress(), I2C_SendData(), I2C_SoftwareResetCmd(), and I2C_StretchClockCmd().

#define IS_STATE_VALUE_OK (   SensitivityValue)
Value:
(((SensitivityValue) == ENABLE) || \
   ((SensitivityValue) == DISABLE))

Definition at line 2806 of file stm8s.h.

#define ITC   ((ITC_TypeDef *) ITC_BaseAddress)

Definition at line 2700 of file stm8s.h.

Referenced by ITC_DeInit(), ITC_GetSoftwarePriority(), and ITC_SetSoftwarePriority().

#define IWDG   ((IWDG_TypeDef *) IWDG_BaseAddress)

Definition at line 2653 of file stm8s.h.

Referenced by IWDG_Enable(), IWDG_ReloadCounter(), IWDG_SetPrescaler(), IWDG_SetReload(), and IWDG_WriteAccessCmd().

#define MskBit (   Dest,
  Msk,
  Src 
)    ( (Dest) = ((Msk) & (Src)) | ((~(Msk)) & (Dest)) )

Definition at line 2796 of file stm8s.h.

#define nop ( )    __no_operation()

Definition at line 2739 of file stm8s.h.

#define OPT   ((OPT_TypeDef *) OPT_BaseAddress)

Definition at line 2625 of file stm8s.h.

#define rim ( )    __enable_interrupt()

Definition at line 2737 of file stm8s.h.

#define RST   ((RST_TypeDef *) RST_BaseAddress)

Definition at line 2650 of file stm8s.h.

Referenced by RST_ClearFlag(), and RST_GetFlagStatus().

#define SetBit (   VAR,
  Place 
)    ( (VAR) |= (uint8_t)((uint8_t)1<<(uint8_t)(Place)) )

Definition at line 2789 of file stm8s.h.

#define sim ( )    __disable_interrupt()

Definition at line 2738 of file stm8s.h.

#define SPI   ((SPI_TypeDef *) SPI_BaseAddress)

Definition at line 2655 of file stm8s.h.

Referenced by SPI_BiDirectionalLineConfig(), SPI_CalculateCRCCmd(), SPI_ClearFlag(), SPI_ClearITPendingBit(), SPI_Cmd(), SPI_DeInit(), SPI_GetCRC(), SPI_GetCRCPolynomial(), SPI_GetFlagStatus(), SPI_GetITStatus(), SPI_Init(), SPI_ITConfig(), SPI_NSSInternalSoftwareCmd(), SPI_ReceiveData(), SPI_SendData(), and SPI_TransmitCRC().

#define TIM1   ((TIM1_TypeDef *) TIM1_BaseAddress)

Definition at line 2676 of file stm8s.h.

Referenced by TI1_Config(), TI2_Config(), TI3_Config(), TI4_Config(), TIM1_ARRPreloadConfig(), TIM1_BDTRConfig(), TIM1_CCPreloadControl(), TIM1_CCxCmd(), TIM1_CCxNCmd(), TIM1_ClearFlag(), TIM1_ClearITPendingBit(), TIM1_Cmd(), TIM1_CounterModeConfig(), TIM1_CtrlPWMOutputs(), TIM1_DeInit(), TIM1_EncoderInterfaceConfig(), TIM1_ETRClockMode1Config(), TIM1_ETRClockMode2Config(), TIM1_ETRConfig(), TIM1_ForcedOC1Config(), TIM1_ForcedOC2Config(), TIM1_ForcedOC3Config(), TIM1_ForcedOC4Config(), TIM1_GenerateEvent(), TIM1_GetCapture1(), TIM1_GetCapture2(), TIM1_GetCapture3(), TIM1_GetCapture4(), TIM1_GetCounter(), TIM1_GetFlagStatus(), TIM1_GetITStatus(), TIM1_GetPrescaler(), TIM1_InternalClockConfig(), TIM1_ITConfig(), TIM1_OC1FastConfig(), TIM1_OC1Init(), TIM1_OC1NPolarityConfig(), TIM1_OC1PolarityConfig(), TIM1_OC1PreloadConfig(), TIM1_OC2FastConfig(), TIM1_OC2Init(), TIM1_OC2NPolarityConfig(), TIM1_OC2PolarityConfig(), TIM1_OC2PreloadConfig(), TIM1_OC3FastConfig(), TIM1_OC3Init(), TIM1_OC3NPolarityConfig(), TIM1_OC3PolarityConfig(), TIM1_OC3PreloadConfig(), TIM1_OC4FastConfig(), TIM1_OC4Init(), TIM1_OC4PolarityConfig(), TIM1_OC4PreloadConfig(), TIM1_PrescalerConfig(), TIM1_SelectCOM(), TIM1_SelectHallSensor(), TIM1_SelectInputTrigger(), TIM1_SelectMasterSlaveMode(), TIM1_SelectOCxM(), TIM1_SelectOnePulseMode(), TIM1_SelectOutputTrigger(), TIM1_SelectSlaveMode(), TIM1_SetAutoreload(), TIM1_SetCompare1(), TIM1_SetCompare2(), TIM1_SetCompare3(), TIM1_SetCompare4(), TIM1_SetCounter(), TIM1_SetIC1Prescaler(), TIM1_SetIC2Prescaler(), TIM1_SetIC3Prescaler(), TIM1_SetIC4Prescaler(), TIM1_TimeBaseInit(), TIM1_TIxExternalClockConfig(), TIM1_UpdateDisableConfig(), and TIM1_UpdateRequestConfig().

#define trap ( )    __trap()

Definition at line 2740 of file stm8s.h.

#define ValBit (   VAR,
  Place 
)    ((uint8_t)(VAR) & (uint8_t)((uint8_t)1<<(uint8_t)(Place)))

Definition at line 2798 of file stm8s.h.

#define wfi ( )    __wait_for_interrupt()

Definition at line 2741 of file stm8s.h.

#define WWDG   ((WWDG_TypeDef *) WWDG_BaseAddress)

Definition at line 2652 of file stm8s.h.

Referenced by WWDG_GetCounter(), WWDG_Init(), WWDG_SetCounter(), WWDG_SetWindowValue(), and WWDG_SWReset().

Typedef Documentation

typedef struct AWU_struct AWU_TypeDef

Auto Wake Up (AWU) peripheral registers.

typedef struct BEEP_struct BEEP_TypeDef

Beeper (BEEP) peripheral registers.

typedef struct CFG_struct CFG_TypeDef

Configuration Registers (CFG)

typedef struct CLK_struct CLK_TypeDef

Clock Controller (CLK)

typedef struct EXTI_struct EXTI_TypeDef

External Interrupt Controller (EXTI)

typedef struct FLASH_struct FLASH_TypeDef

FLASH program and Data memory (FLASH)

typedef struct I2C_struct I2C_TypeDef

Inter-Integrated Circuit (I2C)

typedef struct ITC_struct ITC_TypeDef

Interrupt Controller (ITC)

typedef struct IWDG_struct IWDG_TypeDef

Independent Watchdog (IWDG)

typedef struct OPT_struct OPT_TypeDef

Option Bytes (OPT)

typedef struct RST_struct RST_TypeDef

Reset Controller (RST)

typedef struct SPI_struct SPI_TypeDef

Serial Peripheral Interface (SPI)

typedef struct TIM1_struct TIM1_TypeDef

16-bit timer with complementary PWM outputs (TIM1)

typedef struct TIM2_struct TIM2_TypeDef

16-bit timer (TIM2)

typedef struct TIM3_struct TIM3_TypeDef

16-bit timer (TIM3)

typedef struct TIM4_struct TIM4_TypeDef

8-bit system timer (TIM4)

typedef struct TIM5_struct TIM5_TypeDef

16-bit timer with synchro module (TIM5)

typedef struct TIM6_struct TIM6_TypeDef

8-bit system timer with synchro module(TIM6)

typedef struct UART1_struct UART1_TypeDef

Universal Synchronous Asynchronous Receiver Transmitter (UART1)

typedef struct UART2_struct UART2_TypeDef

Universal Synchronous Asynchronous Receiver Transmitter (UART2)

typedef struct UART3_struct UART3_TypeDef

LIN Universal Asynchronous Receiver Transmitter (UART3)

typedef struct WWDG_struct WWDG_TypeDef

Window Watchdog (WWDG)

STM8 Standard Peripherals Library: Footer

 

 

 

      For complete documentation on STM8 8-bit Microcontrollers platform visit www.st.com

 

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