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STM8S/A Standard Peripherals Drivers
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stm8s.h
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00001 /** 00002 ****************************************************************************** 00003 * @file stm8s.h 00004 * @author MCD Application Team 00005 * @version V2.3.0 00006 * @date 16-June-2017 00007 * @brief This file contains all HW registers definitions and memory mapping. 00008 ****************************************************************************** 00009 * @attention 00010 * 00011 * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> 00012 * 00013 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 00014 * You may not use this file except in compliance with the License. 00015 * You may obtain a copy of the License at: 00016 * 00017 * http://www.st.com/software_license_agreement_liberty_v2 00018 * 00019 * Unless required by applicable law or agreed to in writing, software 00020 * distributed under the License is distributed on an "AS IS" BASIS, 00021 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 00022 * See the License for the specific language governing permissions and 00023 * limitations under the License. 00024 * 00025 ****************************************************************************** 00026 */ 00027 00028 /* Define to prevent recursive inclusion -------------------------------------*/ 00029 #ifndef __STM8S_H 00030 #define __STM8S_H 00031 00032 /** @addtogroup STM8S_StdPeriph_Driver 00033 * @{ 00034 */ 00035 00036 /* Uncomment the line below according to the target STM8S or STM8A device used in your 00037 application. */ 00038 00039 /* #define STM8S208 */ /*!< STM8S High density devices with CAN */ 00040 /* #define STM8S207 */ /*!< STM8S High density devices without CAN */ 00041 /* #define STM8S007 */ /*!< STM8S Value Line High density devices */ 00042 /* #define STM8AF52Ax */ /*!< STM8A High density devices with CAN */ 00043 /* #define STM8AF62Ax */ /*!< STM8A High density devices without CAN */ 00044 /* #define STM8S105 */ /*!< STM8S Medium density devices */ 00045 /* #define STM8S005 */ /*!< STM8S Value Line Medium density devices */ 00046 /* #define STM8AF626x */ /*!< STM8A Medium density devices */ 00047 /* #define STM8AF622x */ /*!< STM8A Low density devices */ 00048 /* #define STM8S103 */ /*!< STM8S Low density devices */ 00049 /* #define STM8S003 */ /*!< STM8S Value Line Low density devices */ 00050 /* #define STM8S903 */ /*!< STM8S Low density devices */ 00051 /* #define STM8S001 */ /*!< STM8S Value Line Low denisty devices */ 00052 00053 /* Tip: To avoid modifying this file each time you need to switch between these 00054 devices, you can define the device in your toolchain compiler preprocessor. 00055 00056 - High-Density STM8A devices are the STM8AF52xx STM8AF6269/8x/Ax, 00057 STM8AF51xx, and STM8AF6169/7x/8x/9x/Ax microcontrollers where the Flash memory 00058 density ranges between 32 to 128 Kbytes 00059 - Medium-Density STM8A devices are the STM8AF622x/4x, STM8AF6266/68, 00060 STM8AF612x/4x, and STM8AF6166/68 microcontrollers where the Flash memory 00061 density ranges between 8 to 32 Kbytes 00062 - High-Density STM8S devices are the STM8S207xx, STM8S007 and STM8S208xx microcontrollers 00063 where the Flash memory density ranges between 32 to 128 Kbytes. 00064 - Medium-Density STM8S devices are the STM8S105x and STM8S005 microcontrollers 00065 where the Flash memory density ranges between 16 to 32-Kbytes. 00066 - Low-Density STM8A devices are the STM8AF622x microcontrollers where the Flash 00067 density is 8 Kbytes. 00068 - Low-Density STM8S devices are the STM8S103xx, STM8S003, STM8S903xx and STM8S001 microcontrollers 00069 where the Flash density is 8 Kbytes. */ 00070 00071 #if !defined (STM8S208) && !defined (STM8S207) && !defined (STM8S105) && \ 00072 !defined (STM8S103) && !defined (STM8S903) && !defined (STM8AF52Ax) && \ 00073 !defined (STM8AF62Ax) && !defined (STM8AF626x) && !defined (STM8S007) && \ 00074 !defined (STM8S003)&& !defined (STM8S005) && !defined(STM8S001) && !defined (STM8AF622x) 00075 #error "Please select first the target STM8S/A device used in your application (in stm8s.h file)" 00076 #endif 00077 00078 /******************************************************************************/ 00079 /* Library configuration section */ 00080 /******************************************************************************/ 00081 /* Check the used compiler */ 00082 #if defined(__CSMC__) 00083 #define _COSMIC_ 00084 #elif defined(__RCST7__) 00085 #define _RAISONANCE_ 00086 #elif defined(__ICCSTM8__) 00087 #define _IAR_ 00088 #else 00089 #error "Unsupported Compiler!" /* Compiler defines not found */ 00090 #endif 00091 00092 #if !defined USE_STDPERIPH_DRIVER 00093 /* Comment the line below if you will not use the peripherals drivers. 00094 In this case, these drivers will not be included and the application code will be 00095 based on direct access to peripherals registers */ 00096 #define USE_STDPERIPH_DRIVER 00097 #endif 00098 00099 /** 00100 * @brief In the following line adjust the value of External High Speed oscillator (HSE) 00101 used in your application 00102 00103 Tip: To avoid modifying this file each time you need to use different HSE, you 00104 can define the HSE value in your toolchain compiler preprocessor. 00105 */ 00106 #if !defined HSE_Value 00107 #if defined (STM8S208) || defined (STM8S207) || defined (STM8S007) || defined (STM8AF52Ax) || \ 00108 defined (STM8AF62Ax) || defined (STM8AF622x) 00109 #define HSE_VALUE ((uint32_t)24000000) /* Value of the External oscillator in Hz*/ 00110 #else 00111 #define HSE_VALUE ((uint32_t)16000000) /* Value of the External oscillator in Hz*/ 00112 #endif /* STM8S208 || STM8S207 || STM8S007 || STM8AF62Ax || STM8AF52Ax || STM8AF622x */ 00113 #endif /* HSE_Value */ 00114 00115 /** 00116 * @brief Definition of Device on-chip RC oscillator frequencies 00117 */ 00118 #define HSI_VALUE ((uint32_t)16000000) /*!< Typical Value of the HSI in Hz */ 00119 #define LSI_VALUE ((uint32_t)128000) /*!< Typical Value of the LSI in Hz */ 00120 00121 #ifdef _COSMIC_ 00122 #define FAR @far 00123 #define NEAR @near 00124 #define TINY @tiny 00125 #define EEPROM @eeprom 00126 #define CONST const 00127 #elif defined (_RAISONANCE_) /* __RCST7__ */ 00128 #define FAR far 00129 #define NEAR data 00130 #define TINY page0 00131 #define EEPROM eeprom 00132 #define CONST code 00133 #if defined (STM8S208) || defined (STM8S207) || defined (STM8S007) || defined (STM8AF52Ax) || \ 00134 defined (STM8AF62Ax) 00135 /*!< Used with memory Models for code higher than 64K */ 00136 #define MEMCPY fmemcpy 00137 #else /* STM8S903, STM8S103, STM8S001, STM8S003, STM8S105, STM8AF626x, STM8AF622x */ 00138 /*!< Used with memory Models for code less than 64K */ 00139 #define MEMCPY memcpy 00140 #endif /* STM8S208 or STM8S207 or STM8S007 or STM8AF62Ax or STM8AF52Ax */ 00141 #else /*_IAR_*/ 00142 #define FAR __far 00143 #define NEAR __near 00144 #define TINY __tiny 00145 #define EEPROM __eeprom 00146 #define CONST const 00147 #endif /* __CSMC__ */ 00148 00149 /* For FLASH routines, select whether pointer will be declared as near (2 bytes, 00150 to handle code smaller than 64KB) or far (3 bytes, to handle code larger 00151 than 64K) */ 00152 00153 #if defined (STM8S105) || defined (STM8S005) || defined (STM8S103) || defined (STM8S003) || \ 00154 defined (STM8S001) || defined (STM8S903) || defined (STM8AF626x) || defined (STM8AF622x) 00155 /*!< Used with memory Models for code smaller than 64K */ 00156 #define PointerAttr NEAR 00157 #define MemoryAddressCast uint16_t 00158 #else /* STM8S208 or STM8S207 or STM8AF62Ax or STM8AF52Ax */ 00159 /*!< Used with memory Models for code higher than 64K */ 00160 #define PointerAttr FAR 00161 #define MemoryAddressCast uint32_t 00162 #endif /* STM8S105 or STM8S103 or STM8S003 or STM8S001 or STM8S903 or STM8AF626x or STM8AF622x */ 00163 00164 /* Uncomment the line below to enable the FLASH functions execution from RAM */ 00165 #if !defined (RAM_EXECUTION) 00166 /* #define RAM_EXECUTION (1) */ 00167 #endif /* RAM_EXECUTION */ 00168 00169 #ifdef RAM_EXECUTION 00170 #ifdef _COSMIC_ 00171 #define IN_RAM(a) a 00172 #elif defined (_RAISONANCE_) /* __RCST7__ */ 00173 #define IN_RAM(a) a inram 00174 #else /*_IAR_*/ 00175 #define IN_RAM(a) __ramfunc a 00176 #endif /* _COSMIC_ */ 00177 #else 00178 #define IN_RAM(a) a 00179 #endif /* RAM_EXECUTION */ 00180 00181 /*!< [31:16] STM8S Standard Peripheral Library main version V2.3.0*/ 00182 #define __STM8S_STDPERIPH_VERSION_MAIN ((uint8_t)0x02) /*!< [31:24] main version */ 00183 #define __STM8S_STDPERIPH_VERSION_SUB1 ((uint8_t)0x03) /*!< [23:16] sub1 version */ 00184 #define __STM8S_STDPERIPH_VERSION_SUB2 ((uint8_t)0x00) /*!< [15:8] sub2 version */ 00185 #define __STM8S_STDPERIPH_VERSION_RC ((uint8_t)0x00) /*!< [7:0] release candidate */ 00186 #define __STM8S_STDPERIPH_VERSION ( (__STM8S_STDPERIPH_VERSION_MAIN << 24)\ 00187 |(__STM8S_STDPERIPH_VERSION_SUB1 << 16)\ 00188 |(__STM8S_STDPERIPH_VERSION_SUB2 << 8)\ 00189 |(__STM8S_STDPERIPH_VERSION_RC)) 00190 00191 /******************************************************************************/ 00192 00193 /* Includes ------------------------------------------------------------------*/ 00194 00195 /* Exported types and constants ----------------------------------------------*/ 00196 00197 /** @addtogroup Exported_types 00198 * @{ 00199 */ 00200 00201 /** 00202 * IO definitions 00203 * 00204 * define access restrictions to peripheral registers 00205 */ 00206 #define __I volatile const /*!< defines 'read only' permissions */ 00207 #define __O volatile /*!< defines 'write only' permissions */ 00208 #define __IO volatile /*!< defines 'read / write' permissions */ 00209 00210 /*!< Signed integer types */ 00211 typedef signed char int8_t; 00212 typedef signed short int16_t; 00213 typedef signed long int32_t; 00214 00215 /*!< Unsigned integer types */ 00216 typedef unsigned char uint8_t; 00217 typedef unsigned short uint16_t; 00218 typedef unsigned long uint32_t; 00219 00220 /*!< STM8 Standard Peripheral Library old types (maintained for legacy purpose) */ 00221 00222 typedef int32_t s32; 00223 typedef int16_t s16; 00224 typedef int8_t s8; 00225 00226 typedef uint32_t u32; 00227 typedef uint16_t u16; 00228 typedef uint8_t u8; 00229 00230 00231 typedef enum {FALSE = 0, TRUE = !FALSE} bool; 00232 00233 typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus, BitStatus, BitAction; 00234 00235 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; 00236 #define IS_FUNCTIONALSTATE_OK(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) 00237 00238 typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; 00239 00240 #define U8_MAX (255) 00241 #define S8_MAX (127) 00242 #define S8_MIN (-128) 00243 #define U16_MAX (65535u) 00244 #define S16_MAX (32767) 00245 #define S16_MIN (-32768) 00246 #define U32_MAX (4294967295uL) 00247 #define S32_MAX (2147483647) 00248 #define S32_MIN (-2147483648uL) 00249 00250 /** 00251 * @} 00252 */ 00253 00254 /** @addtogroup MAP_FILE_Exported_Types_and_Constants 00255 * @{ 00256 */ 00257 00258 /******************************************************************************/ 00259 /* IP registers structures */ 00260 /******************************************************************************/ 00261 00262 /** 00263 * @brief General Purpose I/Os (GPIO) 00264 */ 00265 typedef struct GPIO_struct 00266 { 00267 __IO uint8_t ODR; /*!< Output Data Register */ 00268 __IO uint8_t IDR; /*!< Input Data Register */ 00269 __IO uint8_t DDR; /*!< Data Direction Register */ 00270 __IO uint8_t CR1; /*!< Configuration Register 1 */ 00271 __IO uint8_t CR2; /*!< Configuration Register 2 */ 00272 } 00273 GPIO_TypeDef; 00274 00275 /** 00276 * @} 00277 */ 00278 00279 /** @addtogroup GPIO_Registers_Reset_Value 00280 * @{ 00281 */ 00282 00283 #define GPIO_ODR_RESET_VALUE ((uint8_t)0x00) 00284 #define GPIO_DDR_RESET_VALUE ((uint8_t)0x00) 00285 #define GPIO_CR1_RESET_VALUE ((uint8_t)0x00) 00286 #define GPIO_CR2_RESET_VALUE ((uint8_t)0x00) 00287 00288 /** 00289 * @} 00290 */ 00291 00292 /*----------------------------------------------------------------------------*/ 00293 #if defined(STM8S105) || defined(STM8S005) || defined(STM8S103) || defined(STM8S003) || \ 00294 defined(STM8S001) || defined(STM8S903) || defined(STM8AF626x) || defined(STM8AF622x) 00295 /** 00296 * @brief Analog to Digital Converter (ADC1) 00297 */ 00298 typedef struct ADC1_struct 00299 { 00300 __IO uint8_t DB0RH; /*!< ADC1 Data Buffer Register (MSB) */ 00301 __IO uint8_t DB0RL; /*!< ADC1 Data Buffer Register (LSB) */ 00302 __IO uint8_t DB1RH; /*!< ADC1 Data Buffer Register (MSB) */ 00303 __IO uint8_t DB1RL; /*!< ADC1 Data Buffer Register (LSB) */ 00304 __IO uint8_t DB2RH; /*!< ADC1 Data Buffer Register (MSB) */ 00305 __IO uint8_t DB2RL; /*!< ADC1 Data Buffer Register (LSB) */ 00306 __IO uint8_t DB3RH; /*!< ADC1 Data Buffer Register (MSB) */ 00307 __IO uint8_t DB3RL; /*!< ADC1 Data Buffer Register (LSB) */ 00308 __IO uint8_t DB4RH; /*!< ADC1 Data Buffer Register (MSB) */ 00309 __IO uint8_t DB4RL; /*!< ADC1 Data Buffer Register (LSB) */ 00310 __IO uint8_t DB5RH; /*!< ADC1 Data Buffer Register (MSB) */ 00311 __IO uint8_t DB5RL; /*!< ADC1 Data Buffer Register (LSB) */ 00312 __IO uint8_t DB6RH; /*!< ADC1 Data Buffer Register (MSB) */ 00313 __IO uint8_t DB6RL; /*!< ADC1 Data Buffer Register (LSB) */ 00314 __IO uint8_t DB7RH; /*!< ADC1 Data Buffer Register (MSB) */ 00315 __IO uint8_t DB7RL; /*!< ADC1 Data Buffer Register (LSB) */ 00316 __IO uint8_t DB8RH; /*!< ADC1 Data Buffer Register (MSB) */ 00317 __IO uint8_t DB8RL; /*!< ADC1 Data Buffer Register (LSB) */ 00318 __IO uint8_t DB9RH; /*!< ADC1 Data Buffer Register (MSB) */ 00319 __IO uint8_t DB9RL; /*!< ADC1 Data Buffer Register (LSB) */ 00320 uint8_t RESERVED[12]; /*!< Reserved byte */ 00321 __IO uint8_t CSR; /*!< ADC1 control status register */ 00322 __IO uint8_t CR1; /*!< ADC1 configuration register 1 */ 00323 __IO uint8_t CR2; /*!< ADC1 configuration register 2 */ 00324 __IO uint8_t CR3; /*!< ADC1 configuration register 3 */ 00325 __IO uint8_t DRH; /*!< ADC1 Data high */ 00326 __IO uint8_t DRL; /*!< ADC1 Data low */ 00327 __IO uint8_t TDRH; /*!< ADC1 Schmitt trigger disable register high */ 00328 __IO uint8_t TDRL; /*!< ADC1 Schmitt trigger disable register low */ 00329 __IO uint8_t HTRH; /*!< ADC1 high threshold register High*/ 00330 __IO uint8_t HTRL; /*!< ADC1 high threshold register Low*/ 00331 __IO uint8_t LTRH; /*!< ADC1 low threshold register high */ 00332 __IO uint8_t LTRL; /*!< ADC1 low threshold register low */ 00333 __IO uint8_t AWSRH; /*!< ADC1 watchdog status register high */ 00334 __IO uint8_t AWSRL; /*!< ADC1 watchdog status register low */ 00335 __IO uint8_t AWCRH; /*!< ADC1 watchdog control register high */ 00336 __IO uint8_t AWCRL; /*!< ADC1 watchdog control register low */ 00337 } 00338 ADC1_TypeDef; 00339 00340 /** @addtogroup ADC1_Registers_Reset_Value 00341 * @{ 00342 */ 00343 #define ADC1_CSR_RESET_VALUE ((uint8_t)0x00) 00344 #define ADC1_CR1_RESET_VALUE ((uint8_t)0x00) 00345 #define ADC1_CR2_RESET_VALUE ((uint8_t)0x00) 00346 #define ADC1_CR3_RESET_VALUE ((uint8_t)0x00) 00347 #define ADC1_TDRL_RESET_VALUE ((uint8_t)0x00) 00348 #define ADC1_TDRH_RESET_VALUE ((uint8_t)0x00) 00349 #define ADC1_HTRL_RESET_VALUE ((uint8_t)0x03) 00350 #define ADC1_HTRH_RESET_VALUE ((uint8_t)0xFF) 00351 #define ADC1_LTRH_RESET_VALUE ((uint8_t)0x00) 00352 #define ADC1_LTRL_RESET_VALUE ((uint8_t)0x00) 00353 #define ADC1_AWCRH_RESET_VALUE ((uint8_t)0x00) 00354 #define ADC1_AWCRL_RESET_VALUE ((uint8_t)0x00) 00355 /** 00356 * @} 00357 */ 00358 00359 /** @addtogroup ADC1_Registers_Bits_Definition 00360 * @{ 00361 */ 00362 #define ADC1_CSR_EOC ((uint8_t)0x80) /*!< End of Conversion mask */ 00363 #define ADC1_CSR_AWD ((uint8_t)0x40) /*!< Analog Watch Dog Status mask */ 00364 #define ADC1_CSR_EOCIE ((uint8_t)0x20) /*!< Interrupt Enable for EOC mask */ 00365 #define ADC1_CSR_AWDIE ((uint8_t)0x10) /*!< Analog Watchdog interrupt enable mask */ 00366 #define ADC1_CSR_CH ((uint8_t)0x0F) /*!< Channel selection bits mask */ 00367 00368 #define ADC1_CR1_SPSEL ((uint8_t)0x70) /*!< Prescaler selection mask */ 00369 #define ADC1_CR1_CONT ((uint8_t)0x02) /*!< Continuous conversion mask */ 00370 #define ADC1_CR1_ADON ((uint8_t)0x01) /*!< A/D Converter on/off mask */ 00371 00372 #define ADC1_CR2_EXTTRIG ((uint8_t)0x40) /*!< External trigger enable mask */ 00373 #define ADC1_CR2_EXTSEL ((uint8_t)0x30) /*!< External event selection mask */ 00374 #define ADC1_CR2_ALIGN ((uint8_t)0x08) /*!< Data Alignment mask */ 00375 #define ADC1_CR2_SCAN ((uint8_t)0x02) /*!< Scan mode mask */ 00376 00377 #define ADC1_CR3_DBUF ((uint8_t)0x80) /*!< Data Buffer Enable mask */ 00378 #define ADC1_CR3_OVR ((uint8_t)0x40) /*!< Overrun Status Flag mask */ 00379 00380 #endif /* (STM8S105) ||(STM8S103) || (STM8S005) ||(STM8S003) || (STM8S001) || (STM8S903) || (STM8AF626x) || (STM8AF622x) */ 00381 /** 00382 * @} 00383 */ 00384 00385 /*----------------------------------------------------------------------------*/ 00386 /** 00387 * @brief Analog to Digital Converter (ADC2) 00388 */ 00389 #if defined(STM8S208) || defined(STM8S207) || defined (STM8S007) || defined (STM8AF52Ax) || defined (STM8AF62Ax) 00390 typedef struct ADC2_struct 00391 { 00392 __IO uint8_t CSR; /*!< ADC2 control status register */ 00393 __IO uint8_t CR1; /*!< ADC2 configuration register 1 */ 00394 __IO uint8_t CR2; /*!< ADC2 configuration register 2 */ 00395 uint8_t RESERVED; /*!< Reserved byte */ 00396 __IO uint8_t DRH; /*!< ADC2 Data high */ 00397 __IO uint8_t DRL; /*!< ADC2 Data low */ 00398 __IO uint8_t TDRH; /*!< ADC2 Schmitt trigger disable register high */ 00399 __IO uint8_t TDRL; /*!< ADC2 Schmitt trigger disable register low */ 00400 } 00401 ADC2_TypeDef; 00402 00403 /** @addtogroup ADC2_Registers_Reset_Value 00404 * @{ 00405 */ 00406 #define ADC2_CSR_RESET_VALUE ((uint8_t)0x00) 00407 #define ADC2_CR1_RESET_VALUE ((uint8_t)0x00) 00408 #define ADC2_CR2_RESET_VALUE ((uint8_t)0x00) 00409 #define ADC2_TDRL_RESET_VALUE ((uint8_t)0x00) 00410 #define ADC2_TDRH_RESET_VALUE ((uint8_t)0x00) 00411 /** 00412 * @} 00413 */ 00414 00415 /** @addtogroup ADC2_Registers_Bits_Definition 00416 * @{ 00417 */ 00418 #define ADC2_CSR_EOC ((uint8_t)0x80) /*!< End of Conversion mask */ 00419 #define ADC2_CSR_EOCIE ((uint8_t)0x20) /*!< Interrupt Enable for EOC mask */ 00420 #define ADC2_CSR_CH ((uint8_t)0x0F) /*!< Channel selection bits mask */ 00421 00422 #define ADC2_CR1_SPSEL ((uint8_t)0x70) /*!< Prescaler selection mask */ 00423 #define ADC2_CR1_CONT ((uint8_t)0x02) /*!< Continuous conversion mask */ 00424 #define ADC2_CR1_ADON ((uint8_t)0x01) /*!< A/D Converter on/off mask */ 00425 00426 #define ADC2_CR2_EXTTRIG ((uint8_t)0x40) /*!< External trigger enable mask */ 00427 #define ADC2_CR2_EXTSEL ((uint8_t)0x30) /*!< External event selection mask */ 00428 #define ADC2_CR2_ALIGN ((uint8_t)0x08) /*!< Data Alignment mask */ 00429 00430 #endif /* (STM8S208) ||(STM8S207) || defined (STM8S007) || (STM8AF62Ax) || (STM8AF52Ax) */ 00431 /** 00432 * @} 00433 */ 00434 00435 /*----------------------------------------------------------------------------*/ 00436 00437 /** 00438 * @brief Auto Wake Up (AWU) peripheral registers. 00439 */ 00440 typedef struct AWU_struct 00441 { 00442 __IO uint8_t CSR; /*!< AWU Control status register */ 00443 __IO uint8_t APR; /*!< AWU Asynchronous prescaler buffer */ 00444 __IO uint8_t TBR; /*!< AWU Time base selection register */ 00445 } 00446 AWU_TypeDef; 00447 00448 /** @addtogroup AWU_Registers_Reset_Value 00449 * @{ 00450 */ 00451 #define AWU_CSR_RESET_VALUE ((uint8_t)0x00) 00452 #define AWU_APR_RESET_VALUE ((uint8_t)0x3F) 00453 #define AWU_TBR_RESET_VALUE ((uint8_t)0x00) 00454 00455 /** 00456 * @} 00457 */ 00458 00459 /** @addtogroup AWU_Registers_Bits_Definition 00460 * @{ 00461 */ 00462 00463 #define AWU_CSR_AWUF ((uint8_t)0x20) /*!< Interrupt flag mask */ 00464 #define AWU_CSR_AWUEN ((uint8_t)0x10) /*!< Auto Wake-up enable mask */ 00465 #define AWU_CSR_MSR ((uint8_t)0x01) /*!< LSI Measurement enable mask */ 00466 00467 #define AWU_APR_APR ((uint8_t)0x3F) /*!< Asynchronous Prescaler divider mask */ 00468 00469 #define AWU_TBR_AWUTB ((uint8_t)0x0F) /*!< Timebase selection mask */ 00470 00471 /** 00472 * @} 00473 */ 00474 00475 /*----------------------------------------------------------------------------*/ 00476 /** 00477 * @brief Beeper (BEEP) peripheral registers. 00478 */ 00479 00480 typedef struct BEEP_struct 00481 { 00482 __IO uint8_t CSR; /*!< BEEP Control status register */ 00483 } 00484 BEEP_TypeDef; 00485 00486 /** @addtogroup BEEP_Registers_Reset_Value 00487 * @{ 00488 */ 00489 #define BEEP_CSR_RESET_VALUE ((uint8_t)0x1F) 00490 /** 00491 * @} 00492 */ 00493 00494 /** @addtogroup BEEP_Registers_Bits_Definition 00495 * @{ 00496 */ 00497 #define BEEP_CSR_BEEPSEL ((uint8_t)0xC0) /*!< Beeper frequency selection mask */ 00498 #define BEEP_CSR_BEEPEN ((uint8_t)0x20) /*!< Beeper enable mask */ 00499 #define BEEP_CSR_BEEPDIV ((uint8_t)0x1F) /*!< Beeper Divider prescalar mask */ 00500 /** 00501 * @} 00502 */ 00503 00504 /*----------------------------------------------------------------------------*/ 00505 /** 00506 * @brief Clock Controller (CLK) 00507 */ 00508 typedef struct CLK_struct 00509 { 00510 __IO uint8_t ICKR; /*!< Internal Clocks Control Register */ 00511 __IO uint8_t ECKR; /*!< External Clocks Control Register */ 00512 uint8_t RESERVED; /*!< Reserved byte */ 00513 __IO uint8_t CMSR; /*!< Clock Master Status Register */ 00514 __IO uint8_t SWR; /*!< Clock Master Switch Register */ 00515 __IO uint8_t SWCR; /*!< Switch Control Register */ 00516 __IO uint8_t CKDIVR; /*!< Clock Divider Register */ 00517 __IO uint8_t PCKENR1; /*!< Peripheral Clock Gating Register 1 */ 00518 __IO uint8_t CSSR; /*!< Clock Security System Register */ 00519 __IO uint8_t CCOR; /*!< Configurable Clock Output Register */ 00520 __IO uint8_t PCKENR2; /*!< Peripheral Clock Gating Register 2 */ 00521 uint8_t RESERVED1; /*!< Reserved byte */ 00522 __IO uint8_t HSITRIMR; /*!< HSI Calibration Trimmer Register */ 00523 __IO uint8_t SWIMCCR; /*!< SWIM clock control register */ 00524 } 00525 CLK_TypeDef; 00526 00527 /** @addtogroup CLK_Registers_Reset_Value 00528 * @{ 00529 */ 00530 00531 #define CLK_ICKR_RESET_VALUE ((uint8_t)0x01) 00532 #define CLK_ECKR_RESET_VALUE ((uint8_t)0x00) 00533 #define CLK_CMSR_RESET_VALUE ((uint8_t)0xE1) 00534 #define CLK_SWR_RESET_VALUE ((uint8_t)0xE1) 00535 #define CLK_SWCR_RESET_VALUE ((uint8_t)0x00) 00536 #define CLK_CKDIVR_RESET_VALUE ((uint8_t)0x18) 00537 #define CLK_PCKENR1_RESET_VALUE ((uint8_t)0xFF) 00538 #define CLK_PCKENR2_RESET_VALUE ((uint8_t)0xFF) 00539 #define CLK_CSSR_RESET_VALUE ((uint8_t)0x00) 00540 #define CLK_CCOR_RESET_VALUE ((uint8_t)0x00) 00541 #define CLK_HSITRIMR_RESET_VALUE ((uint8_t)0x00) 00542 #define CLK_SWIMCCR_RESET_VALUE ((uint8_t)0x00) 00543 00544 /** 00545 * @} 00546 */ 00547 00548 /** @addtogroup CLK_Registers_Bits_Definition 00549 * @{ 00550 */ 00551 #define CLK_ICKR_SWUAH ((uint8_t)0x20) /*!< Slow Wake-up from Active Halt/Halt modes */ 00552 #define CLK_ICKR_LSIRDY ((uint8_t)0x10) /*!< Low speed internal oscillator ready */ 00553 #define CLK_ICKR_LSIEN ((uint8_t)0x08) /*!< Low speed internal RC oscillator enable */ 00554 #define CLK_ICKR_FHWU ((uint8_t)0x04) /*!< Fast Wake-up from Active Halt/Halt mode */ 00555 #define CLK_ICKR_HSIRDY ((uint8_t)0x02) /*!< High speed internal RC oscillator ready */ 00556 #define CLK_ICKR_HSIEN ((uint8_t)0x01) /*!< High speed internal RC oscillator enable */ 00557 00558 #define CLK_ECKR_HSERDY ((uint8_t)0x02) /*!< High speed external crystal oscillator ready */ 00559 #define CLK_ECKR_HSEEN ((uint8_t)0x01) /*!< High speed external crystal oscillator enable */ 00560 00561 #define CLK_CMSR_CKM ((uint8_t)0xFF) /*!< Clock master status bits */ 00562 00563 #define CLK_SWR_SWI ((uint8_t)0xFF) /*!< Clock master selection bits */ 00564 00565 #define CLK_SWCR_SWIF ((uint8_t)0x08) /*!< Clock switch interrupt flag */ 00566 #define CLK_SWCR_SWIEN ((uint8_t)0x04) /*!< Clock switch interrupt enable */ 00567 #define CLK_SWCR_SWEN ((uint8_t)0x02) /*!< Switch start/stop */ 00568 #define CLK_SWCR_SWBSY ((uint8_t)0x01) /*!< Switch busy flag*/ 00569 00570 #define CLK_CKDIVR_HSIDIV ((uint8_t)0x18) /*!< High speed internal clock prescaler */ 00571 #define CLK_CKDIVR_CPUDIV ((uint8_t)0x07) /*!< CPU clock prescaler */ 00572 00573 #define CLK_PCKENR1_TIM1 ((uint8_t)0x80) /*!< Timer 1 clock enable */ 00574 #define CLK_PCKENR1_TIM3 ((uint8_t)0x40) /*!< Timer 3 clock enable */ 00575 #define CLK_PCKENR1_TIM2 ((uint8_t)0x20) /*!< Timer 2 clock enable */ 00576 #define CLK_PCKENR1_TIM5 ((uint8_t)0x20) /*!< Timer 5 clock enable */ 00577 #define CLK_PCKENR1_TIM4 ((uint8_t)0x10) /*!< Timer 4 clock enable */ 00578 #define CLK_PCKENR1_TIM6 ((uint8_t)0x10) /*!< Timer 6 clock enable */ 00579 #define CLK_PCKENR1_UART3 ((uint8_t)0x08) /*!< UART3 clock enable */ 00580 #define CLK_PCKENR1_UART2 ((uint8_t)0x08) /*!< UART2 clock enable */ 00581 #define CLK_PCKENR1_UART1 ((uint8_t)0x04) /*!< UART1 clock enable */ 00582 #define CLK_PCKENR1_SPI ((uint8_t)0x02) /*!< SPI clock enable */ 00583 #define CLK_PCKENR1_I2C ((uint8_t)0x01) /*!< I2C clock enable */ 00584 00585 #define CLK_PCKENR2_CAN ((uint8_t)0x80) /*!< CAN clock enable */ 00586 #define CLK_PCKENR2_ADC ((uint8_t)0x08) /*!< ADC clock enable */ 00587 #define CLK_PCKENR2_AWU ((uint8_t)0x04) /*!< AWU clock enable */ 00588 00589 #define CLK_CSSR_CSSD ((uint8_t)0x08) /*!< Clock security system detection */ 00590 #define CLK_CSSR_CSSDIE ((uint8_t)0x04) /*!< Clock security system detection interrupt enable */ 00591 #define CLK_CSSR_AUX ((uint8_t)0x02) /*!< Auxiliary oscillator connected to master clock */ 00592 #define CLK_CSSR_CSSEN ((uint8_t)0x01) /*!< Clock security system enable */ 00593 00594 #define CLK_CCOR_CCOBSY ((uint8_t)0x40) /*!< Configurable clock output busy */ 00595 #define CLK_CCOR_CCORDY ((uint8_t)0x20) /*!< Configurable clock output ready */ 00596 #define CLK_CCOR_CCOSEL ((uint8_t)0x1E) /*!< Configurable clock output selection */ 00597 #define CLK_CCOR_CCOEN ((uint8_t)0x01) /*!< Configurable clock output enable */ 00598 00599 #define CLK_HSITRIMR_HSITRIM ((uint8_t)0x07) /*!< High speed internal oscillator trimmer */ 00600 00601 #define CLK_SWIMCCR_SWIMDIV ((uint8_t)0x01) /*!< SWIM Clock Dividing Factor */ 00602 00603 /** 00604 * @} 00605 */ 00606 00607 /*----------------------------------------------------------------------------*/ 00608 /** 00609 * @brief 16-bit timer with complementary PWM outputs (TIM1) 00610 */ 00611 00612 typedef struct TIM1_struct 00613 { 00614 __IO uint8_t CR1; /*!< control register 1 */ 00615 __IO uint8_t CR2; /*!< control register 2 */ 00616 __IO uint8_t SMCR; /*!< Synchro mode control register */ 00617 __IO uint8_t ETR; /*!< external trigger register */ 00618 __IO uint8_t IER; /*!< interrupt enable register*/ 00619 __IO uint8_t SR1; /*!< status register 1 */ 00620 __IO uint8_t SR2; /*!< status register 2 */ 00621 __IO uint8_t EGR; /*!< event generation register */ 00622 __IO uint8_t CCMR1; /*!< CC mode register 1 */ 00623 __IO uint8_t CCMR2; /*!< CC mode register 2 */ 00624 __IO uint8_t CCMR3; /*!< CC mode register 3 */ 00625 __IO uint8_t CCMR4; /*!< CC mode register 4 */ 00626 __IO uint8_t CCER1; /*!< CC enable register 1 */ 00627 __IO uint8_t CCER2; /*!< CC enable register 2 */ 00628 __IO uint8_t CNTRH; /*!< counter high */ 00629 __IO uint8_t CNTRL; /*!< counter low */ 00630 __IO uint8_t PSCRH; /*!< prescaler high */ 00631 __IO uint8_t PSCRL; /*!< prescaler low */ 00632 __IO uint8_t ARRH; /*!< auto-reload register high */ 00633 __IO uint8_t ARRL; /*!< auto-reload register low */ 00634 __IO uint8_t RCR; /*!< Repetition Counter register */ 00635 __IO uint8_t CCR1H; /*!< capture/compare register 1 high */ 00636 __IO uint8_t CCR1L; /*!< capture/compare register 1 low */ 00637 __IO uint8_t CCR2H; /*!< capture/compare register 2 high */ 00638 __IO uint8_t CCR2L; /*!< capture/compare register 2 low */ 00639 __IO uint8_t CCR3H; /*!< capture/compare register 3 high */ 00640 __IO uint8_t CCR3L; /*!< capture/compare register 3 low */ 00641 __IO uint8_t CCR4H; /*!< capture/compare register 3 high */ 00642 __IO uint8_t CCR4L; /*!< capture/compare register 3 low */ 00643 __IO uint8_t BKR; /*!< Break Register */ 00644 __IO uint8_t DTR; /*!< dead-time register */ 00645 __IO uint8_t OISR; /*!< Output idle register */ 00646 } 00647 TIM1_TypeDef; 00648 00649 /** @addtogroup TIM1_Registers_Reset_Value 00650 * @{ 00651 */ 00652 00653 #define TIM1_CR1_RESET_VALUE ((uint8_t)0x00) 00654 #define TIM1_CR2_RESET_VALUE ((uint8_t)0x00) 00655 #define TIM1_SMCR_RESET_VALUE ((uint8_t)0x00) 00656 #define TIM1_ETR_RESET_VALUE ((uint8_t)0x00) 00657 #define TIM1_IER_RESET_VALUE ((uint8_t)0x00) 00658 #define TIM1_SR1_RESET_VALUE ((uint8_t)0x00) 00659 #define TIM1_SR2_RESET_VALUE ((uint8_t)0x00) 00660 #define TIM1_EGR_RESET_VALUE ((uint8_t)0x00) 00661 #define TIM1_CCMR1_RESET_VALUE ((uint8_t)0x00) 00662 #define TIM1_CCMR2_RESET_VALUE ((uint8_t)0x00) 00663 #define TIM1_CCMR3_RESET_VALUE ((uint8_t)0x00) 00664 #define TIM1_CCMR4_RESET_VALUE ((uint8_t)0x00) 00665 #define TIM1_CCER1_RESET_VALUE ((uint8_t)0x00) 00666 #define TIM1_CCER2_RESET_VALUE ((uint8_t)0x00) 00667 #define TIM1_CNTRH_RESET_VALUE ((uint8_t)0x00) 00668 #define TIM1_CNTRL_RESET_VALUE ((uint8_t)0x00) 00669 #define TIM1_PSCRH_RESET_VALUE ((uint8_t)0x00) 00670 #define TIM1_PSCRL_RESET_VALUE ((uint8_t)0x00) 00671 #define TIM1_ARRH_RESET_VALUE ((uint8_t)0xFF) 00672 #define TIM1_ARRL_RESET_VALUE ((uint8_t)0xFF) 00673 #define TIM1_RCR_RESET_VALUE ((uint8_t)0x00) 00674 #define TIM1_CCR1H_RESET_VALUE ((uint8_t)0x00) 00675 #define TIM1_CCR1L_RESET_VALUE ((uint8_t)0x00) 00676 #define TIM1_CCR2H_RESET_VALUE ((uint8_t)0x00) 00677 #define TIM1_CCR2L_RESET_VALUE ((uint8_t)0x00) 00678 #define TIM1_CCR3H_RESET_VALUE ((uint8_t)0x00) 00679 #define TIM1_CCR3L_RESET_VALUE ((uint8_t)0x00) 00680 #define TIM1_CCR4H_RESET_VALUE ((uint8_t)0x00) 00681 #define TIM1_CCR4L_RESET_VALUE ((uint8_t)0x00) 00682 #define TIM1_BKR_RESET_VALUE ((uint8_t)0x00) 00683 #define TIM1_DTR_RESET_VALUE ((uint8_t)0x00) 00684 #define TIM1_OISR_RESET_VALUE ((uint8_t)0x00) 00685 00686 /** 00687 * @} 00688 */ 00689 00690 /** @addtogroup TIM1_Registers_Bits_Definition 00691 * @{ 00692 */ 00693 /* CR1*/ 00694 #define TIM1_CR1_ARPE ((uint8_t)0x80) /*!< Auto-Reload Preload Enable mask. */ 00695 #define TIM1_CR1_CMS ((uint8_t)0x60) /*!< Center-aligned Mode Selection mask. */ 00696 #define TIM1_CR1_DIR ((uint8_t)0x10) /*!< Direction mask. */ 00697 #define TIM1_CR1_OPM ((uint8_t)0x08) /*!< One Pulse Mode mask. */ 00698 #define TIM1_CR1_URS ((uint8_t)0x04) /*!< Update Request Source mask. */ 00699 #define TIM1_CR1_UDIS ((uint8_t)0x02) /*!< Update DIsable mask. */ 00700 #define TIM1_CR1_CEN ((uint8_t)0x01) /*!< Counter Enable mask. */ 00701 /* CR2*/ 00702 #define TIM1_CR2_TI1S ((uint8_t)0x80) /*!< TI1S Selection mask. */ 00703 #define TIM1_CR2_MMS ((uint8_t)0x70) /*!< MMS Selection mask. */ 00704 #define TIM1_CR2_COMS ((uint8_t)0x04) /*!< Capture/Compare Control Update Selection mask. */ 00705 #define TIM1_CR2_CCPC ((uint8_t)0x01) /*!< Capture/Compare Preloaded Control mask. */ 00706 /* SMCR*/ 00707 #define TIM1_SMCR_MSM ((uint8_t)0x80) /*!< Master/Slave Mode mask. */ 00708 #define TIM1_SMCR_TS ((uint8_t)0x70) /*!< Trigger Selection mask. */ 00709 #define TIM1_SMCR_SMS ((uint8_t)0x07) /*!< Slave Mode Selection mask. */ 00710 /*ETR*/ 00711 #define TIM1_ETR_ETP ((uint8_t)0x80) /*!< External Trigger Polarity mask. */ 00712 #define TIM1_ETR_ECE ((uint8_t)0x40)/*!< External Clock mask. */ 00713 #define TIM1_ETR_ETPS ((uint8_t)0x30) /*!< External Trigger Prescaler mask. */ 00714 #define TIM1_ETR_ETF ((uint8_t)0x0F) /*!< External Trigger Filter mask. */ 00715 /*IER*/ 00716 #define TIM1_IER_BIE ((uint8_t)0x80) /*!< Break Interrupt Enable mask. */ 00717 #define TIM1_IER_TIE ((uint8_t)0x40) /*!< Trigger Interrupt Enable mask. */ 00718 #define TIM1_IER_COMIE ((uint8_t)0x20) /*!< Commutation Interrupt Enable mask.*/ 00719 #define TIM1_IER_CC4IE ((uint8_t)0x10) /*!< Capture/Compare 4 Interrupt Enable mask. */ 00720 #define TIM1_IER_CC3IE ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt Enable mask. */ 00721 #define TIM1_IER_CC2IE ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Enable mask. */ 00722 #define TIM1_IER_CC1IE ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Enable mask. */ 00723 #define TIM1_IER_UIE ((uint8_t)0x01) /*!< Update Interrupt Enable mask. */ 00724 /*SR1*/ 00725 #define TIM1_SR1_BIF ((uint8_t)0x80) /*!< Break Interrupt Flag mask. */ 00726 #define TIM1_SR1_TIF ((uint8_t)0x40) /*!< Trigger Interrupt Flag mask. */ 00727 #define TIM1_SR1_COMIF ((uint8_t)0x20) /*!< Commutation Interrupt Flag mask. */ 00728 #define TIM1_SR1_CC4IF ((uint8_t)0x10) /*!< Capture/Compare 4 Interrupt Flag mask. */ 00729 #define TIM1_SR1_CC3IF ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt Flag mask. */ 00730 #define TIM1_SR1_CC2IF ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Flag mask. */ 00731 #define TIM1_SR1_CC1IF ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Flag mask. */ 00732 #define TIM1_SR1_UIF ((uint8_t)0x01) /*!< Update Interrupt Flag mask. */ 00733 /*SR2*/ 00734 #define TIM1_SR2_CC4OF ((uint8_t)0x10) /*!< Capture/Compare 4 Overcapture Flag mask. */ 00735 #define TIM1_SR2_CC3OF ((uint8_t)0x08) /*!< Capture/Compare 3 Overcapture Flag mask. */ 00736 #define TIM1_SR2_CC2OF ((uint8_t)0x04) /*!< Capture/Compare 2 Overcapture Flag mask. */ 00737 #define TIM1_SR2_CC1OF ((uint8_t)0x02) /*!< Capture/Compare 1 Overcapture Flag mask. */ 00738 /*EGR*/ 00739 #define TIM1_EGR_BG ((uint8_t)0x80) /*!< Break Generation mask. */ 00740 #define TIM1_EGR_TG ((uint8_t)0x40) /*!< Trigger Generation mask. */ 00741 #define TIM1_EGR_COMG ((uint8_t)0x20) /*!< Capture/Compare Control Update Generation mask. */ 00742 #define TIM1_EGR_CC4G ((uint8_t)0x10) /*!< Capture/Compare 4 Generation mask. */ 00743 #define TIM1_EGR_CC3G ((uint8_t)0x08) /*!< Capture/Compare 3 Generation mask. */ 00744 #define TIM1_EGR_CC2G ((uint8_t)0x04) /*!< Capture/Compare 2 Generation mask. */ 00745 #define TIM1_EGR_CC1G ((uint8_t)0x02) /*!< Capture/Compare 1 Generation mask. */ 00746 #define TIM1_EGR_UG ((uint8_t)0x01) /*!< Update Generation mask. */ 00747 /*CCMR*/ 00748 #define TIM1_CCMR_ICxPSC ((uint8_t)0x0C) /*!< Input Capture x Prescaler mask. */ 00749 #define TIM1_CCMR_ICxF ((uint8_t)0xF0) /*!< Input Capture x Filter mask. */ 00750 #define TIM1_CCMR_OCM ((uint8_t)0x70) /*!< Output Compare x Mode mask. */ 00751 #define TIM1_CCMR_OCxPE ((uint8_t)0x08) /*!< Output Compare x Preload Enable mask. */ 00752 #define TIM1_CCMR_OCxFE ((uint8_t)0x04) /*!< Output Compare x Fast Enable mask. */ 00753 #define TIM1_CCMR_CCxS ((uint8_t)0x03) /*!< Capture/Compare x Selection mask. */ 00754 00755 #define CCMR_TIxDirect_Set ((uint8_t)0x01) 00756 /*CCER1*/ 00757 #define TIM1_CCER1_CC2NP ((uint8_t)0x80) /*!< Capture/Compare 2 Complementary output Polarity mask. */ 00758 #define TIM1_CCER1_CC2NE ((uint8_t)0x40) /*!< Capture/Compare 2 Complementary output enable mask. */ 00759 #define TIM1_CCER1_CC2P ((uint8_t)0x20) /*!< Capture/Compare 2 output Polarity mask. */ 00760 #define TIM1_CCER1_CC2E ((uint8_t)0x10) /*!< Capture/Compare 2 output enable mask. */ 00761 #define TIM1_CCER1_CC1NP ((uint8_t)0x08) /*!< Capture/Compare 1 Complementary output Polarity mask. */ 00762 #define TIM1_CCER1_CC1NE ((uint8_t)0x04) /*!< Capture/Compare 1 Complementary output enable mask. */ 00763 #define TIM1_CCER1_CC1P ((uint8_t)0x02) /*!< Capture/Compare 1 output Polarity mask. */ 00764 #define TIM1_CCER1_CC1E ((uint8_t)0x01) /*!< Capture/Compare 1 output enable mask. */ 00765 /*CCER2*/ 00766 #define TIM1_CCER2_CC4P ((uint8_t)0x20) /*!< Capture/Compare 4 output Polarity mask. */ 00767 #define TIM1_CCER2_CC4E ((uint8_t)0x10) /*!< Capture/Compare 4 output enable mask. */ 00768 #define TIM1_CCER2_CC3NP ((uint8_t)0x08) /*!< Capture/Compare 3 Complementary output Polarity mask. */ 00769 #define TIM1_CCER2_CC3NE ((uint8_t)0x04) /*!< Capture/Compare 3 Complementary output enable mask. */ 00770 #define TIM1_CCER2_CC3P ((uint8_t)0x02) /*!< Capture/Compare 3 output Polarity mask. */ 00771 #define TIM1_CCER2_CC3E ((uint8_t)0x01) /*!< Capture/Compare 3 output enable mask. */ 00772 /*CNTRH*/ 00773 #define TIM1_CNTRH_CNT ((uint8_t)0xFF) /*!< Counter Value (MSB) mask. */ 00774 /*CNTRL*/ 00775 #define TIM1_CNTRL_CNT ((uint8_t)0xFF) /*!< Counter Value (LSB) mask. */ 00776 /*PSCH*/ 00777 #define TIM1_PSCH_PSC ((uint8_t)0xFF) /*!< Prescaler Value (MSB) mask. */ 00778 /*PSCL*/ 00779 #define TIM1_PSCL_PSC ((uint8_t)0xFF) /*!< Prescaler Value (LSB) mask. */ 00780 /*ARR*/ 00781 #define TIM1_ARRH_ARR ((uint8_t)0xFF) /*!< Autoreload Value (MSB) mask. */ 00782 #define TIM1_ARRL_ARR ((uint8_t)0xFF) /*!< Autoreload Value (LSB) mask. */ 00783 /*RCR*/ 00784 #define TIM1_RCR_REP ((uint8_t)0xFF) /*!< Repetition Counter Value mask. */ 00785 /*CCR1*/ 00786 #define TIM1_CCR1H_CCR1 ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (MSB) mask. */ 00787 #define TIM1_CCR1L_CCR1 ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (LSB) mask. */ 00788 /*CCR2*/ 00789 #define TIM1_CCR2H_CCR2 ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (MSB) mask. */ 00790 #define TIM1_CCR2L_CCR2 ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (LSB) mask. */ 00791 /*CCR3*/ 00792 #define TIM1_CCR3H_CCR3 ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (MSB) mask. */ 00793 #define TIM1_CCR3L_CCR3 ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (LSB) mask. */ 00794 /*CCR4*/ 00795 #define TIM1_CCR4H_CCR4 ((uint8_t)0xFF) /*!< Capture/Compare 4 Value (MSB) mask. */ 00796 #define TIM1_CCR4L_CCR4 ((uint8_t)0xFF) /*!< Capture/Compare 4 Value (LSB) mask. */ 00797 /*BKR*/ 00798 #define TIM1_BKR_MOE ((uint8_t)0x80) /*!< Main Output Enable mask. */ 00799 #define TIM1_BKR_AOE ((uint8_t)0x40) /*!< Automatic Output Enable mask. */ 00800 #define TIM1_BKR_BKP ((uint8_t)0x20) /*!< Break Polarity mask. */ 00801 #define TIM1_BKR_BKE ((uint8_t)0x10) /*!< Break Enable mask. */ 00802 #define TIM1_BKR_OSSR ((uint8_t)0x08) /*!< Off-State Selection for Run mode mask. */ 00803 #define TIM1_BKR_OSSI ((uint8_t)0x04) /*!< Off-State Selection for Idle mode mask. */ 00804 #define TIM1_BKR_LOCK ((uint8_t)0x03) /*!< Lock Configuration mask. */ 00805 /*DTR*/ 00806 #define TIM1_DTR_DTG ((uint8_t)0xFF) /*!< Dead-Time Generator set-up mask. */ 00807 /*OISR*/ 00808 #define TIM1_OISR_OIS4 ((uint8_t)0x40) /*!< Output Idle state 4 (OC4 output) mask. */ 00809 #define TIM1_OISR_OIS3N ((uint8_t)0x20) /*!< Output Idle state 3 (OC3N output) mask. */ 00810 #define TIM1_OISR_OIS3 ((uint8_t)0x10) /*!< Output Idle state 3 (OC3 output) mask. */ 00811 #define TIM1_OISR_OIS2N ((uint8_t)0x08) /*!< Output Idle state 2 (OC2N output) mask. */ 00812 #define TIM1_OISR_OIS2 ((uint8_t)0x04) /*!< Output Idle state 2 (OC2 output) mask. */ 00813 #define TIM1_OISR_OIS1N ((uint8_t)0x02) /*!< Output Idle state 1 (OC1N output) mask. */ 00814 #define TIM1_OISR_OIS1 ((uint8_t)0x01) /*!< Output Idle state 1 (OC1 output) mask. */ 00815 /** 00816 * @} 00817 */ 00818 00819 /*----------------------------------------------------------------------------*/ 00820 /** 00821 * @brief 16-bit timer (TIM2) 00822 */ 00823 00824 typedef struct TIM2_struct 00825 { 00826 __IO uint8_t CR1; /*!< control register 1 */ 00827 #if defined(STM8S103) || defined(STM8S003) || defined(STM8S001) 00828 uint8_t RESERVED1; /*!< Reserved register */ 00829 uint8_t RESERVED2; /*!< Reserved register */ 00830 #endif 00831 __IO uint8_t IER; /*!< interrupt enable register */ 00832 __IO uint8_t SR1; /*!< status register 1 */ 00833 __IO uint8_t SR2; /*!< status register 2 */ 00834 __IO uint8_t EGR; /*!< event generation register */ 00835 __IO uint8_t CCMR1; /*!< CC mode register 1 */ 00836 __IO uint8_t CCMR2; /*!< CC mode register 2 */ 00837 __IO uint8_t CCMR3; /*!< CC mode register 3 */ 00838 __IO uint8_t CCER1; /*!< CC enable register 1 */ 00839 __IO uint8_t CCER2; /*!< CC enable register 2 */ 00840 __IO uint8_t CNTRH; /*!< counter high */ 00841 __IO uint8_t CNTRL; /*!< counter low */ 00842 __IO uint8_t PSCR; /*!< prescaler register */ 00843 __IO uint8_t ARRH; /*!< auto-reload register high */ 00844 __IO uint8_t ARRL; /*!< auto-reload register low */ 00845 __IO uint8_t CCR1H; /*!< capture/compare register 1 high */ 00846 __IO uint8_t CCR1L; /*!< capture/compare register 1 low */ 00847 __IO uint8_t CCR2H; /*!< capture/compare register 2 high */ 00848 __IO uint8_t CCR2L; /*!< capture/compare register 2 low */ 00849 __IO uint8_t CCR3H; /*!< capture/compare register 3 high */ 00850 __IO uint8_t CCR3L; /*!< capture/compare register 3 low */ 00851 } 00852 TIM2_TypeDef; 00853 00854 /** @addtogroup TIM2_Registers_Reset_Value 00855 * @{ 00856 */ 00857 00858 #define TIM2_CR1_RESET_VALUE ((uint8_t)0x00) 00859 #define TIM2_IER_RESET_VALUE ((uint8_t)0x00) 00860 #define TIM2_SR1_RESET_VALUE ((uint8_t)0x00) 00861 #define TIM2_SR2_RESET_VALUE ((uint8_t)0x00) 00862 #define TIM2_EGR_RESET_VALUE ((uint8_t)0x00) 00863 #define TIM2_CCMR1_RESET_VALUE ((uint8_t)0x00) 00864 #define TIM2_CCMR2_RESET_VALUE ((uint8_t)0x00) 00865 #define TIM2_CCMR3_RESET_VALUE ((uint8_t)0x00) 00866 #define TIM2_CCER1_RESET_VALUE ((uint8_t)0x00) 00867 #define TIM2_CCER2_RESET_VALUE ((uint8_t)0x00) 00868 #define TIM2_CNTRH_RESET_VALUE ((uint8_t)0x00) 00869 #define TIM2_CNTRL_RESET_VALUE ((uint8_t)0x00) 00870 #define TIM2_PSCR_RESET_VALUE ((uint8_t)0x00) 00871 #define TIM2_ARRH_RESET_VALUE ((uint8_t)0xFF) 00872 #define TIM2_ARRL_RESET_VALUE ((uint8_t)0xFF) 00873 #define TIM2_CCR1H_RESET_VALUE ((uint8_t)0x00) 00874 #define TIM2_CCR1L_RESET_VALUE ((uint8_t)0x00) 00875 #define TIM2_CCR2H_RESET_VALUE ((uint8_t)0x00) 00876 #define TIM2_CCR2L_RESET_VALUE ((uint8_t)0x00) 00877 #define TIM2_CCR3H_RESET_VALUE ((uint8_t)0x00) 00878 #define TIM2_CCR3L_RESET_VALUE ((uint8_t)0x00) 00879 00880 /** 00881 * @} 00882 */ 00883 00884 /** @addtogroup TIM2_Registers_Bits_Definition 00885 * @{ 00886 */ 00887 /*CR1*/ 00888 #define TIM2_CR1_ARPE ((uint8_t)0x80) /*!< Auto-Reload Preload Enable mask. */ 00889 #define TIM2_CR1_OPM ((uint8_t)0x08) /*!< One Pulse Mode mask. */ 00890 #define TIM2_CR1_URS ((uint8_t)0x04) /*!< Update Request Source mask. */ 00891 #define TIM2_CR1_UDIS ((uint8_t)0x02) /*!< Update DIsable mask. */ 00892 #define TIM2_CR1_CEN ((uint8_t)0x01) /*!< Counter Enable mask. */ 00893 /*IER*/ 00894 #define TIM2_IER_CC3IE ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt Enable mask. */ 00895 #define TIM2_IER_CC2IE ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Enable mask. */ 00896 #define TIM2_IER_CC1IE ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Enable mask. */ 00897 #define TIM2_IER_UIE ((uint8_t)0x01) /*!< Update Interrupt Enable mask. */ 00898 /*SR1*/ 00899 #define TIM2_SR1_CC3IF ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt Flag mask. */ 00900 #define TIM2_SR1_CC2IF ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Flag mask. */ 00901 #define TIM2_SR1_CC1IF ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Flag mask. */ 00902 #define TIM2_SR1_UIF ((uint8_t)0x01) /*!< Update Interrupt Flag mask. */ 00903 /*SR2*/ 00904 #define TIM2_SR2_CC3OF ((uint8_t)0x08) /*!< Capture/Compare 3 Overcapture Flag mask. */ 00905 #define TIM2_SR2_CC2OF ((uint8_t)0x04) /*!< Capture/Compare 2 Overcapture Flag mask. */ 00906 #define TIM2_SR2_CC1OF ((uint8_t)0x02) /*!< Capture/Compare 1 Overcapture Flag mask. */ 00907 /*EGR*/ 00908 #define TIM2_EGR_CC3G ((uint8_t)0x08) /*!< Capture/Compare 3 Generation mask. */ 00909 #define TIM2_EGR_CC2G ((uint8_t)0x04) /*!< Capture/Compare 2 Generation mask. */ 00910 #define TIM2_EGR_CC1G ((uint8_t)0x02) /*!< Capture/Compare 1 Generation mask. */ 00911 #define TIM2_EGR_UG ((uint8_t)0x01) /*!< Update Generation mask. */ 00912 /*CCMR*/ 00913 #define TIM2_CCMR_ICxPSC ((uint8_t)0x0C) /*!< Input Capture x Prescaler mask. */ 00914 #define TIM2_CCMR_ICxF ((uint8_t)0xF0) /*!< Input Capture x Filter mask. */ 00915 #define TIM2_CCMR_OCM ((uint8_t)0x70) /*!< Output Compare x Mode mask. */ 00916 #define TIM2_CCMR_OCxPE ((uint8_t)0x08) /*!< Output Compare x Preload Enable mask. */ 00917 #define TIM2_CCMR_CCxS ((uint8_t)0x03) /*!< Capture/Compare x Selection mask. */ 00918 /*CCER1*/ 00919 #define TIM2_CCER1_CC2P ((uint8_t)0x20) /*!< Capture/Compare 2 output Polarity mask. */ 00920 #define TIM2_CCER1_CC2E ((uint8_t)0x10) /*!< Capture/Compare 2 output enable mask. */ 00921 #define TIM2_CCER1_CC1P ((uint8_t)0x02) /*!< Capture/Compare 1 output Polarity mask. */ 00922 #define TIM2_CCER1_CC1E ((uint8_t)0x01) /*!< Capture/Compare 1 output enable mask. */ 00923 /*CCER2*/ 00924 #define TIM2_CCER2_CC3P ((uint8_t)0x02) /*!< Capture/Compare 3 output Polarity mask. */ 00925 #define TIM2_CCER2_CC3E ((uint8_t)0x01) /*!< Capture/Compare 3 output enable mask. */ 00926 /*CNTR*/ 00927 #define TIM2_CNTRH_CNT ((uint8_t)0xFF) /*!< Counter Value (MSB) mask. */ 00928 #define TIM2_CNTRL_CNT ((uint8_t)0xFF) /*!< Counter Value (LSB) mask. */ 00929 /*PSCR*/ 00930 #define TIM2_PSCR_PSC ((uint8_t)0xFF) /*!< Prescaler Value (MSB) mask. */ 00931 /*ARR*/ 00932 #define TIM2_ARRH_ARR ((uint8_t)0xFF) /*!< Autoreload Value (MSB) mask. */ 00933 #define TIM2_ARRL_ARR ((uint8_t)0xFF) /*!< Autoreload Value (LSB) mask. */ 00934 /*CCR1*/ 00935 #define TIM2_CCR1H_CCR1 ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (MSB) mask. */ 00936 #define TIM2_CCR1L_CCR1 ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (LSB) mask. */ 00937 /*CCR2*/ 00938 #define TIM2_CCR2H_CCR2 ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (MSB) mask. */ 00939 #define TIM2_CCR2L_CCR2 ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (LSB) mask. */ 00940 /*CCR3*/ 00941 #define TIM2_CCR3H_CCR3 ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (MSB) mask. */ 00942 #define TIM2_CCR3L_CCR3 ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (LSB) mask. */ 00943 00944 /** 00945 * @} 00946 */ 00947 00948 /*----------------------------------------------------------------------------*/ 00949 /** 00950 * @brief 16-bit timer (TIM3) 00951 */ 00952 typedef struct TIM3_struct 00953 { 00954 __IO uint8_t CR1; /*!< control register 1 */ 00955 __IO uint8_t IER; /*!< interrupt enable register */ 00956 __IO uint8_t SR1; /*!< status register 1 */ 00957 __IO uint8_t SR2; /*!< status register 2 */ 00958 __IO uint8_t EGR; /*!< event generation register */ 00959 __IO uint8_t CCMR1; /*!< CC mode register 1 */ 00960 __IO uint8_t CCMR2; /*!< CC mode register 2 */ 00961 __IO uint8_t CCER1; /*!< CC enable register 1 */ 00962 __IO uint8_t CNTRH; /*!< counter high */ 00963 __IO uint8_t CNTRL; /*!< counter low */ 00964 __IO uint8_t PSCR; /*!< prescaler register */ 00965 __IO uint8_t ARRH; /*!< auto-reload register high */ 00966 __IO uint8_t ARRL; /*!< auto-reload register low */ 00967 __IO uint8_t CCR1H; /*!< capture/compare register 1 high */ 00968 __IO uint8_t CCR1L; /*!< capture/compare register 1 low */ 00969 __IO uint8_t CCR2H; /*!< capture/compare register 2 high */ 00970 __IO uint8_t CCR2L; /*!< capture/compare register 2 low */ 00971 } 00972 TIM3_TypeDef; 00973 00974 /** @addtogroup TIM3_Registers_Reset_Value 00975 * @{ 00976 */ 00977 00978 #define TIM3_CR1_RESET_VALUE ((uint8_t)0x00) 00979 #define TIM3_IER_RESET_VALUE ((uint8_t)0x00) 00980 #define TIM3_SR1_RESET_VALUE ((uint8_t)0x00) 00981 #define TIM3_SR2_RESET_VALUE ((uint8_t)0x00) 00982 #define TIM3_EGR_RESET_VALUE ((uint8_t)0x00) 00983 #define TIM3_CCMR1_RESET_VALUE ((uint8_t)0x00) 00984 #define TIM3_CCMR2_RESET_VALUE ((uint8_t)0x00) 00985 #define TIM3_CCER1_RESET_VALUE ((uint8_t)0x00) 00986 #define TIM3_CNTRH_RESET_VALUE ((uint8_t)0x00) 00987 #define TIM3_CNTRL_RESET_VALUE ((uint8_t)0x00) 00988 #define TIM3_PSCR_RESET_VALUE ((uint8_t)0x00) 00989 #define TIM3_ARRH_RESET_VALUE ((uint8_t)0xFF) 00990 #define TIM3_ARRL_RESET_VALUE ((uint8_t)0xFF) 00991 #define TIM3_CCR1H_RESET_VALUE ((uint8_t)0x00) 00992 #define TIM3_CCR1L_RESET_VALUE ((uint8_t)0x00) 00993 #define TIM3_CCR2H_RESET_VALUE ((uint8_t)0x00) 00994 #define TIM3_CCR2L_RESET_VALUE ((uint8_t)0x00) 00995 00996 /** 00997 * @} 00998 */ 00999 01000 /** @addtogroup TIM3_Registers_Bits_Definition 01001 * @{ 01002 */ 01003 /*CR1*/ 01004 #define TIM3_CR1_ARPE ((uint8_t)0x80) /*!< Auto-Reload Preload Enable mask. */ 01005 #define TIM3_CR1_OPM ((uint8_t)0x08) /*!< One Pulse Mode mask. */ 01006 #define TIM3_CR1_URS ((uint8_t)0x04) /*!< Update Request Source mask. */ 01007 #define TIM3_CR1_UDIS ((uint8_t)0x02) /*!< Update DIsable mask. */ 01008 #define TIM3_CR1_CEN ((uint8_t)0x01) /*!< Counter Enable mask. */ 01009 /*IER*/ 01010 #define TIM3_IER_CC2IE ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Enable mask. */ 01011 #define TIM3_IER_CC1IE ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Enable mask. */ 01012 #define TIM3_IER_UIE ((uint8_t)0x01) /*!< Update Interrupt Enable mask. */ 01013 /*SR1*/ 01014 #define TIM3_SR1_CC2IF ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Flag mask. */ 01015 #define TIM3_SR1_CC1IF ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Flag mask. */ 01016 #define TIM3_SR1_UIF ((uint8_t)0x01) /*!< Update Interrupt Flag mask. */ 01017 /*SR2*/ 01018 #define TIM3_SR2_CC2OF ((uint8_t)0x04) /*!< Capture/Compare 2 Overcapture Flag mask. */ 01019 #define TIM3_SR2_CC1OF ((uint8_t)0x02) /*!< Capture/Compare 1 Overcapture Flag mask. */ 01020 /*EGR*/ 01021 #define TIM3_EGR_CC2G ((uint8_t)0x04) /*!< Capture/Compare 2 Generation mask. */ 01022 #define TIM3_EGR_CC1G ((uint8_t)0x02) /*!< Capture/Compare 1 Generation mask. */ 01023 #define TIM3_EGR_UG ((uint8_t)0x01) /*!< Update Generation mask. */ 01024 /*CCMR*/ 01025 #define TIM3_CCMR_ICxPSC ((uint8_t)0x0C) /*!< Input Capture x Prescaler mask. */ 01026 #define TIM3_CCMR_ICxF ((uint8_t)0xF0) /*!< Input Capture x Filter mask. */ 01027 #define TIM3_CCMR_OCM ((uint8_t)0x70) /*!< Output Compare x Mode mask. */ 01028 #define TIM3_CCMR_OCxPE ((uint8_t)0x08) /*!< Output Compare x Preload Enable mask. */ 01029 #define TIM3_CCMR_CCxS ((uint8_t)0x03) /*!< Capture/Compare x Selection mask. */ 01030 /*CCER1*/ 01031 #define TIM3_CCER1_CC2P ((uint8_t)0x20) /*!< Capture/Compare 2 output Polarity mask. */ 01032 #define TIM3_CCER1_CC2E ((uint8_t)0x10) /*!< Capture/Compare 2 output enable mask. */ 01033 #define TIM3_CCER1_CC1P ((uint8_t)0x02) /*!< Capture/Compare 1 output Polarity mask. */ 01034 #define TIM3_CCER1_CC1E ((uint8_t)0x01) /*!< Capture/Compare 1 output enable mask. */ 01035 /*CNTR*/ 01036 #define TIM3_CNTRH_CNT ((uint8_t)0xFF) /*!< Counter Value (MSB) mask. */ 01037 #define TIM3_CNTRL_CNT ((uint8_t)0xFF) /*!< Counter Value (LSB) mask. */ 01038 /*PSCR*/ 01039 #define TIM3_PSCR_PSC ((uint8_t)0xFF) /*!< Prescaler Value (MSB) mask. */ 01040 /*ARR*/ 01041 #define TIM3_ARRH_ARR ((uint8_t)0xFF) /*!< Autoreload Value (MSB) mask. */ 01042 #define TIM3_ARRL_ARR ((uint8_t)0xFF) /*!< Autoreload Value (LSB) mask. */ 01043 /*CCR1*/ 01044 #define TIM3_CCR1H_CCR1 ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (MSB) mask. */ 01045 #define TIM3_CCR1L_CCR1 ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (LSB) mask. */ 01046 /*CCR2*/ 01047 #define TIM3_CCR2H_CCR2 ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (MSB) mask. */ 01048 #define TIM3_CCR2L_CCR2 ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (LSB) mask. */ 01049 /** 01050 * @} 01051 */ 01052 01053 /*----------------------------------------------------------------------------*/ 01054 /** 01055 * @brief 8-bit system timer (TIM4) 01056 */ 01057 01058 typedef struct TIM4_struct 01059 { 01060 __IO uint8_t CR1; /*!< control register 1 */ 01061 #if defined(STM8S103) || defined(STM8S003) || defined(STM8S001) 01062 uint8_t RESERVED1; /*!< Reserved register */ 01063 uint8_t RESERVED2; /*!< Reserved register */ 01064 #endif 01065 __IO uint8_t IER; /*!< interrupt enable register */ 01066 __IO uint8_t SR1; /*!< status register 1 */ 01067 __IO uint8_t EGR; /*!< event generation register */ 01068 __IO uint8_t CNTR; /*!< counter register */ 01069 __IO uint8_t PSCR; /*!< prescaler register */ 01070 __IO uint8_t ARR; /*!< auto-reload register */ 01071 } 01072 TIM4_TypeDef; 01073 01074 /** @addtogroup TIM4_Registers_Reset_Value 01075 * @{ 01076 */ 01077 01078 #define TIM4_CR1_RESET_VALUE ((uint8_t)0x00) 01079 #define TIM4_IER_RESET_VALUE ((uint8_t)0x00) 01080 #define TIM4_SR1_RESET_VALUE ((uint8_t)0x00) 01081 #define TIM4_EGR_RESET_VALUE ((uint8_t)0x00) 01082 #define TIM4_CNTR_RESET_VALUE ((uint8_t)0x00) 01083 #define TIM4_PSCR_RESET_VALUE ((uint8_t)0x00) 01084 #define TIM4_ARR_RESET_VALUE ((uint8_t)0xFF) 01085 01086 /** 01087 * @} 01088 */ 01089 01090 /** @addtogroup TIM4_Registers_Bits_Definition 01091 * @{ 01092 */ 01093 /*CR1*/ 01094 #define TIM4_CR1_ARPE ((uint8_t)0x80) /*!< Auto-Reload Preload Enable mask. */ 01095 #define TIM4_CR1_OPM ((uint8_t)0x08) /*!< One Pulse Mode mask. */ 01096 #define TIM4_CR1_URS ((uint8_t)0x04) /*!< Update Request Source mask. */ 01097 #define TIM4_CR1_UDIS ((uint8_t)0x02) /*!< Update DIsable mask. */ 01098 #define TIM4_CR1_CEN ((uint8_t)0x01) /*!< Counter Enable mask. */ 01099 /*IER*/ 01100 #define TIM4_IER_UIE ((uint8_t)0x01) /*!< Update Interrupt Enable mask. */ 01101 /*SR1*/ 01102 #define TIM4_SR1_UIF ((uint8_t)0x01) /*!< Update Interrupt Flag mask. */ 01103 /*EGR*/ 01104 #define TIM4_EGR_UG ((uint8_t)0x01) /*!< Update Generation mask. */ 01105 /*CNTR*/ 01106 #define TIM4_CNTR_CNT ((uint8_t)0xFF) /*!< Counter Value (LSB) mask. */ 01107 /*PSCR*/ 01108 #define TIM4_PSCR_PSC ((uint8_t)0x07) /*!< Prescaler Value mask. */ 01109 /*ARR*/ 01110 #define TIM4_ARR_ARR ((uint8_t)0xFF) /*!< Autoreload Value mask. */ 01111 01112 /** 01113 * @} 01114 */ 01115 01116 /*----------------------------------------------------------------------------*/ 01117 /** 01118 * @brief 16-bit timer with synchro module (TIM5) 01119 */ 01120 01121 typedef struct TIM5_struct 01122 { 01123 __IO uint8_t CR1; /*!<TIM5 Control Register 1 */ 01124 __IO uint8_t CR2; /*!<TIM5 Control Register 2 */ 01125 __IO uint8_t SMCR; /*!<TIM5 Slave Mode Control Register */ 01126 __IO uint8_t IER; /*!<TIM5 Interrupt Enable Register */ 01127 __IO uint8_t SR1; /*!<TIM5 Status Register 1 */ 01128 __IO uint8_t SR2; /*!<TIM5 Status Register 2 */ 01129 __IO uint8_t EGR; /*!<TIM5 Event Generation Register */ 01130 __IO uint8_t CCMR1; /*!<TIM5 Capture/Compare Mode Register 1 */ 01131 __IO uint8_t CCMR2; /*!<TIM5 Capture/Compare Mode Register 2 */ 01132 __IO uint8_t CCMR3; /*!<TIM5 Capture/Compare Mode Register 3 */ 01133 __IO uint8_t CCER1; /*!<TIM5 Capture/Compare Enable Register 1 */ 01134 __IO uint8_t CCER2; /*!<TIM5 Capture/Compare Enable Register 2 */ 01135 __IO uint8_t CNTRH; /*!<TIM5 Counter High */ 01136 __IO uint8_t CNTRL; /*!<TIM5 Counter Low */ 01137 __IO uint8_t PSCR; /*!<TIM5 Prescaler Register */ 01138 __IO uint8_t ARRH; /*!<TIM5 Auto-Reload Register High */ 01139 __IO uint8_t ARRL; /*!<TIM5 Auto-Reload Register Low */ 01140 __IO uint8_t CCR1H; /*!<TIM5 Capture/Compare Register 1 High */ 01141 __IO uint8_t CCR1L; /*!<TIM5 Capture/Compare Register 1 Low */ 01142 __IO uint8_t CCR2H; /*!<TIM5 Capture/Compare Register 2 High */ 01143 __IO uint8_t CCR2L; /*!<TIM5 Capture/Compare Register 2 Low */ 01144 __IO uint8_t CCR3H; /*!<TIM5 Capture/Compare Register 3 High */ 01145 __IO uint8_t CCR3L; /*!<TIM5 Capture/Compare Register 3 Low */ 01146 }TIM5_TypeDef; 01147 01148 /** @addtogroup TIM5_Registers_Reset_Value 01149 * @{ 01150 */ 01151 01152 #define TIM5_CR1_RESET_VALUE ((uint8_t)0x00) 01153 #define TIM5_CR2_RESET_VALUE ((uint8_t)0x00) 01154 #define TIM5_SMCR_RESET_VALUE ((uint8_t)0x00) 01155 #define TIM5_IER_RESET_VALUE ((uint8_t)0x00) 01156 #define TIM5_SR1_RESET_VALUE ((uint8_t)0x00) 01157 #define TIM5_SR2_RESET_VALUE ((uint8_t)0x00) 01158 #define TIM5_EGR_RESET_VALUE ((uint8_t)0x00) 01159 #define TIM5_CCMR1_RESET_VALUE ((uint8_t)0x00) 01160 #define TIM5_CCMR2_RESET_VALUE ((uint8_t)0x00) 01161 #define TIM5_CCMR3_RESET_VALUE ((uint8_t)0x00) 01162 #define TIM5_CCER1_RESET_VALUE ((uint8_t)0x00) 01163 #define TIM5_CCER2_RESET_VALUE ((uint8_t)0x00) 01164 #define TIM5_CNTRH_RESET_VALUE ((uint8_t)0x00) 01165 #define TIM5_CNTRL_RESET_VALUE ((uint8_t)0x00) 01166 #define TIM5_PSCR_RESET_VALUE ((uint8_t)0x00) 01167 #define TIM5_ARRH_RESET_VALUE ((uint8_t)0xFF) 01168 #define TIM5_ARRL_RESET_VALUE ((uint8_t)0xFF) 01169 #define TIM5_CCR1H_RESET_VALUE ((uint8_t)0x00) 01170 #define TIM5_CCR1L_RESET_VALUE ((uint8_t)0x00) 01171 #define TIM5_CCR2H_RESET_VALUE ((uint8_t)0x00) 01172 #define TIM5_CCR2L_RESET_VALUE ((uint8_t)0x00) 01173 #define TIM5_CCR3H_RESET_VALUE ((uint8_t)0x00) 01174 #define TIM5_CCR3L_RESET_VALUE ((uint8_t)0x00) 01175 01176 /** 01177 * @} 01178 */ 01179 01180 /** @addtogroup TIM5_Registers_Bits_Definition 01181 * @{ 01182 */ 01183 /* CR1*/ 01184 #define TIM5_CR1_ARPE ((uint8_t)0x80) /*!< Auto-Reload Preload Enable mask. */ 01185 #define TIM5_CR1_OPM ((uint8_t)0x08) /*!< One Pulse Mode mask. */ 01186 #define TIM5_CR1_URS ((uint8_t)0x04) /*!< Update Request Source mask. */ 01187 #define TIM5_CR1_UDIS ((uint8_t)0x02) /*!< Update DIsable mask. */ 01188 #define TIM5_CR1_CEN ((uint8_t)0x01) /*!< Counter Enable mask. */ 01189 /* CR2*/ 01190 #define TIM5_CR2_TI1S ((uint8_t)0x80) /*!< TI1S Selection Mask. */ 01191 #define TIM5_CR2_MMS ((uint8_t)0x70) /*!< MMS Selection Mask. */ 01192 /* SMCR*/ 01193 #define TIM5_SMCR_MSM ((uint8_t)0x80) /*!< Master/Slave Mode Mask. */ 01194 #define TIM5_SMCR_TS ((uint8_t)0x70) /*!< Trigger Selection Mask. */ 01195 #define TIM5_SMCR_SMS ((uint8_t)0x07) /*!< Slave Mode Selection Mask. */ 01196 /*IER*/ 01197 #define TIM5_IER_TIE ((uint8_t)0x40) /*!< Trigger Interrupt Enable mask. */ 01198 #define TIM5_IER_CC3IE ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt Enable mask. */ 01199 #define TIM5_IER_CC2IE ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Enable mask. */ 01200 #define TIM5_IER_CC1IE ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Enable mask. */ 01201 #define TIM5_IER_UIE ((uint8_t)0x01) /*!< Update Interrupt Enable mask. */ 01202 /*SR1*/ 01203 #define TIM5_SR1_TIF ((uint8_t)0x40) /*!< Trigger Interrupt Flag mask. */ 01204 #define TIM5_SR1_CC3IF ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt Flag mask. */ 01205 #define TIM5_SR1_CC2IF ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Flag mask. */ 01206 #define TIM5_SR1_CC1IF ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Flag mask. */ 01207 #define TIM5_SR1_UIF ((uint8_t)0x01) /*!< Update Interrupt Flag mask. */ 01208 /*SR2*/ 01209 #define TIM5_SR2_CC3OF ((uint8_t)0x08) /*!< Capture/Compare 3 Overcapture Flag mask. */ 01210 #define TIM5_SR2_CC2OF ((uint8_t)0x04) /*!< Capture/Compare 2 Overcapture Flag mask. */ 01211 #define TIM5_SR2_CC1OF ((uint8_t)0x02) /*!< Capture/Compare 1 Overcapture Flag mask. */ 01212 /*EGR*/ 01213 #define TIM5_EGR_TG ((uint8_t)0x40) /*!< Trigger Generation mask. */ 01214 #define TIM5_EGR_CC3G ((uint8_t)0x08) /*!< Capture/Compare 3 Generation mask. */ 01215 #define TIM5_EGR_CC2G ((uint8_t)0x04) /*!< Capture/Compare 2 Generation mask. */ 01216 #define TIM5_EGR_CC1G ((uint8_t)0x02) /*!< Capture/Compare 1 Generation mask. */ 01217 #define TIM5_EGR_UG ((uint8_t)0x01) /*!< Update Generation mask. */ 01218 /*CCMR*/ 01219 #define TIM5_CCMR_ICxPSC ((uint8_t)0x0C) /*!< Input Capture x Prescaler mask. */ 01220 #define TIM5_CCMR_ICxF ((uint8_t)0xF0) /*!< Input Capture x Filter mask. */ 01221 #define TIM5_CCMR_OCM ((uint8_t)0x70) /*!< Output Compare x Mode mask. */ 01222 #define TIM5_CCMR_OCxPE ((uint8_t)0x08) /*!< Output Compare x Preload Enable mask. */ 01223 #define TIM5_CCMR_CCxS ((uint8_t)0x03) /*!< Capture/Compare x Selection mask. */ 01224 /*CCER1*/ 01225 #define TIM5_CCER1_CC2P ((uint8_t)0x20) /*!< Capture/Compare 2 output Polarity mask. */ 01226 #define TIM5_CCER1_CC2E ((uint8_t)0x10) /*!< Capture/Compare 2 output enable mask. */ 01227 #define TIM5_CCER1_CC1P ((uint8_t)0x02) /*!< Capture/Compare 1 output Polarity mask. */ 01228 #define TIM5_CCER1_CC1E ((uint8_t)0x01) /*!< Capture/Compare 1 output enable mask. */ 01229 /*CCER2*/ 01230 #define TIM5_CCER2_CC3P ((uint8_t)0x02) /*!< Capture/Compare 3 output Polarity mask. */ 01231 #define TIM5_CCER2_CC3E ((uint8_t)0x01) /*!< Capture/Compare 3 output enable mask. */ 01232 /*CNTR*/ 01233 #define TIM5_CNTRH_CNT ((uint8_t)0xFF) /*!< Counter Value (MSB) mask. */ 01234 #define TIM5_CNTRL_CNT ((uint8_t)0xFF) /*!< Counter Value (LSB) mask. */ 01235 /*PSCR*/ 01236 #define TIM5_PSCR_PSC ((uint8_t)0xFF) /*!< Prescaler Value (MSB) mask. */ 01237 /*ARR*/ 01238 #define TIM5_ARRH_ARR ((uint8_t)0xFF) /*!< Autoreload Value (MSB) mask. */ 01239 #define TIM5_ARRL_ARR ((uint8_t)0xFF) /*!< Autoreload Value (LSB) mask. */ 01240 /*CCR1*/ 01241 #define TIM5_CCR1H_CCR1 ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (MSB) mask. */ 01242 #define TIM5_CCR1L_CCR1 ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (LSB) mask. */ 01243 /*CCR2*/ 01244 #define TIM5_CCR2H_CCR2 ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (MSB) mask. */ 01245 #define TIM5_CCR2L_CCR2 ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (LSB) mask. */ 01246 /*CCR3*/ 01247 #define TIM5_CCR3H_CCR3 ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (MSB) mask. */ 01248 #define TIM5_CCR3L_CCR3 ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (LSB) mask. */ 01249 /*CCMR*/ 01250 #define TIM5_CCMR_TIxDirect_Set ((uint8_t)0x01) 01251 /** 01252 * @} 01253 */ 01254 01255 /*----------------------------------------------------------------------------*/ 01256 /** 01257 * @brief 8-bit system timer with synchro module(TIM6) 01258 */ 01259 01260 typedef struct TIM6_struct 01261 { 01262 __IO uint8_t CR1; /*!< control register 1 */ 01263 __IO uint8_t CR2; /*!< control register 2 */ 01264 __IO uint8_t SMCR; /*!< Synchro mode control register */ 01265 __IO uint8_t IER; /*!< interrupt enable register */ 01266 __IO uint8_t SR1; /*!< status register 1 */ 01267 __IO uint8_t EGR; /*!< event generation register */ 01268 __IO uint8_t CNTR; /*!< counter register */ 01269 __IO uint8_t PSCR; /*!< prescaler register */ 01270 __IO uint8_t ARR; /*!< auto-reload register */ 01271 } 01272 TIM6_TypeDef; 01273 /** @addtogroup TIM6_Registers_Reset_Value 01274 * @{ 01275 */ 01276 #define TIM6_CR1_RESET_VALUE ((uint8_t)0x00) 01277 #define TIM6_CR2_RESET_VALUE ((uint8_t)0x00) 01278 #define TIM6_SMCR_RESET_VALUE ((uint8_t)0x00) 01279 #define TIM6_IER_RESET_VALUE ((uint8_t)0x00) 01280 #define TIM6_SR1_RESET_VALUE ((uint8_t)0x00) 01281 #define TIM6_EGR_RESET_VALUE ((uint8_t)0x00) 01282 #define TIM6_CNTR_RESET_VALUE ((uint8_t)0x00) 01283 #define TIM6_PSCR_RESET_VALUE ((uint8_t)0x00) 01284 #define TIM6_ARR_RESET_VALUE ((uint8_t)0xFF) 01285 01286 /** 01287 * @} 01288 */ 01289 01290 /** @addtogroup TIM6_Registers_Bits_Definition 01291 * @{ 01292 */ 01293 /* CR1*/ 01294 #define TIM6_CR1_ARPE ((uint8_t)0x80) /*!< Auto-Reload Preload Enable Mask. */ 01295 #define TIM6_CR1_OPM ((uint8_t)0x08) /*!< One Pulse Mode Mask. */ 01296 #define TIM6_CR1_URS ((uint8_t)0x04) /*!< Update Request Source Mask. */ 01297 #define TIM6_CR1_UDIS ((uint8_t)0x02) /*!< Update DIsable Mask. */ 01298 #define TIM6_CR1_CEN ((uint8_t)0x01) /*!< Counter Enable Mask. */ 01299 /* CR2*/ 01300 #define TIM6_CR2_MMS ((uint8_t)0x70) /*!< MMS Selection Mask. */ 01301 /* SMCR*/ 01302 #define TIM6_SMCR_MSM ((uint8_t)0x80) /*!< Master/Slave Mode Mask. */ 01303 #define TIM6_SMCR_TS ((uint8_t)0x70) /*!< Trigger Selection Mask. */ 01304 #define TIM6_SMCR_SMS ((uint8_t)0x07) /*!< Slave Mode Selection Mask. */ 01305 /* IER*/ 01306 #define TIM6_IER_TIE ((uint8_t)0x40) /*!< Trigger Interrupt Enable Mask. */ 01307 #define TIM6_IER_UIE ((uint8_t)0x01) /*!< Update Interrupt Enable Mask. */ 01308 /* SR1*/ 01309 #define TIM6_SR1_TIF ((uint8_t)0x40) /*!< Trigger Interrupt Flag mask. */ 01310 #define TIM6_SR1_UIF ((uint8_t)0x01) /*!< Update Interrupt Flag Mask. */ 01311 /* EGR*/ 01312 #define TIM6_EGR_TG ((uint8_t)0x40) /*!< Trigger Generation mask. */ 01313 #define TIM6_EGR_UG ((uint8_t)0x01) /*!< Update Generation Mask. */ 01314 /* CNTR*/ 01315 #define TIM6_CNTR_CNT ((uint8_t)0xFF) /*!<Counter Value (LSB) Mask. */ 01316 /* PSCR*/ 01317 #define TIM6_PSCR_PSC ((uint8_t)0x07) /*!<Prescaler Value Mask. */ 01318 01319 #define TIM6_ARR_ARR ((uint8_t)0xFF) /*!<Autoreload Value Mask. */ 01320 /** 01321 * @} 01322 */ 01323 /*----------------------------------------------------------------------------*/ 01324 /** 01325 * @brief Inter-Integrated Circuit (I2C) 01326 */ 01327 01328 typedef struct I2C_struct 01329 { 01330 __IO uint8_t CR1; /*!< I2C control register 1 */ 01331 __IO uint8_t CR2; /*!< I2C control register 2 */ 01332 __IO uint8_t FREQR; /*!< I2C frequency register */ 01333 __IO uint8_t OARL; /*!< I2C own address register LSB */ 01334 __IO uint8_t OARH; /*!< I2C own address register MSB */ 01335 uint8_t RESERVED1; /*!< Reserved byte */ 01336 __IO uint8_t DR; /*!< I2C data register */ 01337 __IO uint8_t SR1; /*!< I2C status register 1 */ 01338 __IO uint8_t SR2; /*!< I2C status register 2 */ 01339 __IO uint8_t SR3; /*!< I2C status register 3 */ 01340 __IO uint8_t ITR; /*!< I2C interrupt register */ 01341 __IO uint8_t CCRL; /*!< I2C clock control register low */ 01342 __IO uint8_t CCRH; /*!< I2C clock control register high */ 01343 __IO uint8_t TRISER; /*!< I2C maximum rise time register */ 01344 uint8_t RESERVED2; /*!< Reserved byte */ 01345 } 01346 I2C_TypeDef; 01347 01348 /** @addtogroup I2C_Registers_Reset_Value 01349 * @{ 01350 */ 01351 01352 #define I2C_CR1_RESET_VALUE ((uint8_t)0x00) 01353 #define I2C_CR2_RESET_VALUE ((uint8_t)0x00) 01354 #define I2C_FREQR_RESET_VALUE ((uint8_t)0x00) 01355 #define I2C_OARL_RESET_VALUE ((uint8_t)0x00) 01356 #define I2C_OARH_RESET_VALUE ((uint8_t)0x00) 01357 #define I2C_DR_RESET_VALUE ((uint8_t)0x00) 01358 #define I2C_SR1_RESET_VALUE ((uint8_t)0x00) 01359 #define I2C_SR2_RESET_VALUE ((uint8_t)0x00) 01360 #define I2C_SR3_RESET_VALUE ((uint8_t)0x00) 01361 #define I2C_ITR_RESET_VALUE ((uint8_t)0x00) 01362 #define I2C_CCRL_RESET_VALUE ((uint8_t)0x00) 01363 #define I2C_CCRH_RESET_VALUE ((uint8_t)0x00) 01364 #define I2C_TRISER_RESET_VALUE ((uint8_t)0x02) 01365 01366 /** 01367 * @} 01368 */ 01369 01370 /** @addtogroup I2C_Registers_Bits_Definition 01371 * @{ 01372 */ 01373 01374 #define I2C_CR1_NOSTRETCH ((uint8_t)0x80) /*!< Clock Stretching Disable (Slave mode) */ 01375 #define I2C_CR1_ENGC ((uint8_t)0x40) /*!< General Call Enable */ 01376 #define I2C_CR1_PE ((uint8_t)0x01) /*!< Peripheral Enable */ 01377 01378 #define I2C_CR2_SWRST ((uint8_t)0x80) /*!< Software Reset */ 01379 #define I2C_CR2_POS ((uint8_t)0x08) /*!< Acknowledge */ 01380 #define I2C_CR2_ACK ((uint8_t)0x04) /*!< Acknowledge Enable */ 01381 #define I2C_CR2_STOP ((uint8_t)0x02) /*!< Stop Generation */ 01382 #define I2C_CR2_START ((uint8_t)0x01) /*!< Start Generation */ 01383 01384 #define I2C_FREQR_FREQ ((uint8_t)0x3F) /*!< Peripheral Clock Frequency */ 01385 01386 #define I2C_OARL_ADD ((uint8_t)0xFE) /*!< Interface Address bits [7..1] */ 01387 #define I2C_OARL_ADD0 ((uint8_t)0x01) /*!< Interface Address bit0 */ 01388 01389 #define I2C_OARH_ADDMODE ((uint8_t)0x80) /*!< Addressing Mode (Slave mode) */ 01390 #define I2C_OARH_ADDCONF ((uint8_t)0x40) /*!< Address Mode Configuration */ 01391 #define I2C_OARH_ADD ((uint8_t)0x06) /*!< Interface Address bits [9..8] */ 01392 01393 #define I2C_DR_DR ((uint8_t)0xFF) /*!< Data Register */ 01394 01395 #define I2C_SR1_TXE ((uint8_t)0x80) /*!< Data Register Empty (transmitters) */ 01396 #define I2C_SR1_RXNE ((uint8_t)0x40) /*!< Data Register not Empty (receivers) */ 01397 #define I2C_SR1_STOPF ((uint8_t)0x10) /*!< Stop detection (Slave mode) */ 01398 #define I2C_SR1_ADD10 ((uint8_t)0x08) /*!< 10-bit header sent (Master mode) */ 01399 #define I2C_SR1_BTF ((uint8_t)0x04) /*!< Byte Transfer Finished */ 01400 #define I2C_SR1_ADDR ((uint8_t)0x02) /*!< Address sent (master mode)/matched (slave mode) */ 01401 #define I2C_SR1_SB ((uint8_t)0x01) /*!< Start Bit (Master mode) */ 01402 01403 #define I2C_SR2_WUFH ((uint8_t)0x20) /*!< Wake-up from Halt */ 01404 #define I2C_SR2_OVR ((uint8_t)0x08) /*!< Overrun/Underrun */ 01405 #define I2C_SR2_AF ((uint8_t)0x04) /*!< Acknowledge Failure */ 01406 #define I2C_SR2_ARLO ((uint8_t)0x02) /*!< Arbitration Lost (master mode) */ 01407 #define I2C_SR2_BERR ((uint8_t)0x01) /*!< Bus Error */ 01408 01409 #define I2C_SR3_GENCALL ((uint8_t)0x10) /*!< General Call Header (Slave mode) */ 01410 #define I2C_SR3_TRA ((uint8_t)0x04) /*!< Transmitter/Receiver */ 01411 #define I2C_SR3_BUSY ((uint8_t)0x02) /*!< Bus Busy */ 01412 #define I2C_SR3_MSL ((uint8_t)0x01) /*!< Master/Slave */ 01413 01414 #define I2C_ITR_ITBUFEN ((uint8_t)0x04) /*!< Buffer Interrupt Enable */ 01415 #define I2C_ITR_ITEVTEN ((uint8_t)0x02) /*!< Event Interrupt Enable */ 01416 #define I2C_ITR_ITERREN ((uint8_t)0x01) /*!< Error Interrupt Enable */ 01417 01418 #define I2C_CCRL_CCR ((uint8_t)0xFF) /*!< Clock Control Register (Master mode) */ 01419 01420 #define I2C_CCRH_FS ((uint8_t)0x80) /*!< Master Mode Selection */ 01421 #define I2C_CCRH_DUTY ((uint8_t)0x40) /*!< Fast Mode Duty Cycle */ 01422 #define I2C_CCRH_CCR ((uint8_t)0x0F) /*!< Clock Control Register in Fast/Standard mode (Master mode) bits [11..8] */ 01423 01424 #define I2C_TRISER_TRISE ((uint8_t)0x3F) /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */ 01425 01426 /** 01427 * @} 01428 */ 01429 01430 /*----------------------------------------------------------------------------*/ 01431 /** 01432 * @brief Interrupt Controller (ITC) 01433 */ 01434 01435 typedef struct ITC_struct 01436 { 01437 __IO uint8_t ISPR1; /*!< Interrupt Software Priority register 1 */ 01438 __IO uint8_t ISPR2; /*!< Interrupt Software Priority register 2 */ 01439 __IO uint8_t ISPR3; /*!< Interrupt Software Priority register 3 */ 01440 __IO uint8_t ISPR4; /*!< Interrupt Software Priority register 4 */ 01441 __IO uint8_t ISPR5; /*!< Interrupt Software Priority register 5 */ 01442 __IO uint8_t ISPR6; /*!< Interrupt Software Priority register 6 */ 01443 __IO uint8_t ISPR7; /*!< Interrupt Software Priority register 7 */ 01444 __IO uint8_t ISPR8; /*!< Interrupt Software Priority register 8 */ 01445 } 01446 ITC_TypeDef; 01447 01448 /** @addtogroup ITC_Registers_Reset_Value 01449 * @{ 01450 */ 01451 01452 #define ITC_SPRX_RESET_VALUE ((uint8_t)0xFF) /*!< Reset value of Software Priority registers */ 01453 01454 /** 01455 * @} 01456 */ 01457 01458 /** @addtogroup CPU_Registers_Bits_Definition 01459 * @{ 01460 */ 01461 01462 #define CPU_CC_I1I0 ((uint8_t)0x28) /*!< Condition Code register, I1 and I0 bits mask */ 01463 01464 /** 01465 * @} 01466 */ 01467 01468 /*----------------------------------------------------------------------------*/ 01469 /** 01470 * @brief External Interrupt Controller (EXTI) 01471 */ 01472 01473 typedef struct EXTI_struct 01474 { 01475 __IO uint8_t CR1; /*!< External Interrupt Control Register for PORTA to PORTD */ 01476 __IO uint8_t CR2; /*!< External Interrupt Control Register for PORTE and TLI */ 01477 } 01478 EXTI_TypeDef; 01479 01480 /** @addtogroup EXTI_Registers_Reset_Value 01481 * @{ 01482 */ 01483 01484 #define EXTI_CR1_RESET_VALUE ((uint8_t)0x00) 01485 #define EXTI_CR2_RESET_VALUE ((uint8_t)0x00) 01486 01487 /** 01488 * @} 01489 */ 01490 01491 /** @addtogroup EXTI_Registers_Bits_Definition 01492 * @{ 01493 */ 01494 01495 #define EXTI_CR1_PDIS ((uint8_t)0xC0) /*!< PORTD external interrupt sensitivity bits mask */ 01496 #define EXTI_CR1_PCIS ((uint8_t)0x30) /*!< PORTC external interrupt sensitivity bits mask */ 01497 #define EXTI_CR1_PBIS ((uint8_t)0x0C) /*!< PORTB external interrupt sensitivity bits mask */ 01498 #define EXTI_CR1_PAIS ((uint8_t)0x03) /*!< PORTA external interrupt sensitivity bits mask */ 01499 01500 #define EXTI_CR2_TLIS ((uint8_t)0x04) /*!< Top level interrupt sensitivity bit mask */ 01501 #define EXTI_CR2_PEIS ((uint8_t)0x03) /*!< PORTE external interrupt sensitivity bits mask */ 01502 01503 /** 01504 * @} 01505 */ 01506 01507 01508 01509 /*----------------------------------------------------------------------------*/ 01510 /** 01511 * @brief FLASH program and Data memory (FLASH) 01512 */ 01513 01514 typedef struct FLASH_struct 01515 { 01516 __IO uint8_t CR1; /*!< Flash control register 1 */ 01517 __IO uint8_t CR2; /*!< Flash control register 2 */ 01518 __IO uint8_t NCR2; /*!< Flash complementary control register 2 */ 01519 __IO uint8_t FPR; /*!< Flash protection register */ 01520 __IO uint8_t NFPR; /*!< Flash complementary protection register */ 01521 __IO uint8_t IAPSR; /*!< Flash in-application programming status register */ 01522 uint8_t RESERVED1; /*!< Reserved byte */ 01523 uint8_t RESERVED2; /*!< Reserved byte */ 01524 __IO uint8_t PUKR; /*!< Flash program memory unprotection register */ 01525 uint8_t RESERVED3; /*!< Reserved byte */ 01526 __IO uint8_t DUKR; /*!< Data EEPROM unprotection register */ 01527 } 01528 FLASH_TypeDef; 01529 01530 /** @addtogroup FLASH_Registers_Reset_Value 01531 * @{ 01532 */ 01533 01534 #define FLASH_CR1_RESET_VALUE ((uint8_t)0x00) 01535 #define FLASH_CR2_RESET_VALUE ((uint8_t)0x00) 01536 #define FLASH_NCR2_RESET_VALUE ((uint8_t)0xFF) 01537 #define FLASH_IAPSR_RESET_VALUE ((uint8_t)0x40) 01538 #define FLASH_PUKR_RESET_VALUE ((uint8_t)0x00) 01539 #define FLASH_DUKR_RESET_VALUE ((uint8_t)0x00) 01540 01541 /** 01542 * @} 01543 */ 01544 01545 /** @addtogroup FLASH_Registers_Bits_Definition 01546 * @{ 01547 */ 01548 01549 #define FLASH_CR1_HALT ((uint8_t)0x08) /*!< Standby in Halt mode mask */ 01550 #define FLASH_CR1_AHALT ((uint8_t)0x04) /*!< Standby in Active Halt mode mask */ 01551 #define FLASH_CR1_IE ((uint8_t)0x02) /*!< Flash Interrupt enable mask */ 01552 #define FLASH_CR1_FIX ((uint8_t)0x01) /*!< Fix programming time mask */ 01553 01554 #define FLASH_CR2_OPT ((uint8_t)0x80) /*!< Select option byte mask */ 01555 #define FLASH_CR2_WPRG ((uint8_t)0x40) /*!< Word Programming mask */ 01556 #define FLASH_CR2_ERASE ((uint8_t)0x20) /*!< Erase block mask */ 01557 #define FLASH_CR2_FPRG ((uint8_t)0x10) /*!< Fast programming mode mask */ 01558 #define FLASH_CR2_PRG ((uint8_t)0x01) /*!< Program block mask */ 01559 01560 #define FLASH_NCR2_NOPT ((uint8_t)0x80) /*!< Select option byte mask */ 01561 #define FLASH_NCR2_NWPRG ((uint8_t)0x40) /*!< Word Programming mask */ 01562 #define FLASH_NCR2_NERASE ((uint8_t)0x20) /*!< Erase block mask */ 01563 #define FLASH_NCR2_NFPRG ((uint8_t)0x10) /*!< Fast programming mode mask */ 01564 #define FLASH_NCR2_NPRG ((uint8_t)0x01) /*!< Program block mask */ 01565 01566 #define FLASH_IAPSR_HVOFF ((uint8_t)0x40) /*!< End of high voltage flag mask */ 01567 #define FLASH_IAPSR_DUL ((uint8_t)0x08) /*!< Data EEPROM unlocked flag mask */ 01568 #define FLASH_IAPSR_EOP ((uint8_t)0x04) /*!< End of operation flag mask */ 01569 #define FLASH_IAPSR_PUL ((uint8_t)0x02) /*!< Flash Program memory unlocked flag mask */ 01570 #define FLASH_IAPSR_WR_PG_DIS ((uint8_t)0x01) /*!< Write attempted to protected page mask */ 01571 01572 #define FLASH_PUKR_PUK ((uint8_t)0xFF) /*!< Flash Program memory unprotection mask */ 01573 01574 #define FLASH_DUKR_DUK ((uint8_t)0xFF) /*!< Data EEPROM unprotection mask */ 01575 01576 /** 01577 * @} 01578 */ 01579 01580 /*----------------------------------------------------------------------------*/ 01581 /** 01582 * @brief Option Bytes (OPT) 01583 */ 01584 typedef struct OPT_struct 01585 { 01586 __IO uint8_t OPT0; /*!< Option byte 0: Read-out protection (not accessible in IAP mode) */ 01587 __IO uint8_t OPT1; /*!< Option byte 1: User boot code */ 01588 __IO uint8_t NOPT1; /*!< Complementary Option byte 1 */ 01589 __IO uint8_t OPT2; /*!< Option byte 2: Alternate function remapping */ 01590 __IO uint8_t NOPT2; /*!< Complementary Option byte 2 */ 01591 __IO uint8_t OPT3; /*!< Option byte 3: Watchdog option */ 01592 __IO uint8_t NOPT3; /*!< Complementary Option byte 3 */ 01593 __IO uint8_t OPT4; /*!< Option byte 4: Clock option */ 01594 __IO uint8_t NOPT4; /*!< Complementary Option byte 4 */ 01595 __IO uint8_t OPT5; /*!< Option byte 5: HSE clock startup */ 01596 __IO uint8_t NOPT5; /*!< Complementary Option byte 5 */ 01597 uint8_t RESERVED1; /*!< Reserved Option byte*/ 01598 uint8_t RESERVED2; /*!< Reserved Option byte*/ 01599 __IO uint8_t OPT7; /*!< Option byte 7: flash wait states */ 01600 __IO uint8_t NOPT7; /*!< Complementary Option byte 7 */ 01601 } 01602 OPT_TypeDef; 01603 01604 /*----------------------------------------------------------------------------*/ 01605 /** 01606 * @brief Independent Watchdog (IWDG) 01607 */ 01608 01609 typedef struct IWDG_struct 01610 { 01611 __IO uint8_t KR; /*!< Key Register */ 01612 __IO uint8_t PR; /*!< Prescaler Register */ 01613 __IO uint8_t RLR; /*!< Reload Register */ 01614 } 01615 IWDG_TypeDef; 01616 01617 /** @addtogroup IWDG_Registers_Reset_Value 01618 * @{ 01619 */ 01620 01621 #define IWDG_PR_RESET_VALUE ((uint8_t)0x00) 01622 #define IWDG_RLR_RESET_VALUE ((uint8_t)0xFF) 01623 01624 /** 01625 * @} 01626 */ 01627 01628 /*----------------------------------------------------------------------------*/ 01629 /** 01630 * @brief Window Watchdog (WWDG) 01631 */ 01632 01633 typedef struct WWDG_struct 01634 { 01635 __IO uint8_t CR; /*!< Control Register */ 01636 __IO uint8_t WR; /*!< Window Register */ 01637 } 01638 WWDG_TypeDef; 01639 01640 /** @addtogroup WWDG_Registers_Reset_Value 01641 * @{ 01642 */ 01643 01644 #define WWDG_CR_RESET_VALUE ((uint8_t)0x7F) 01645 #define WWDG_WR_RESET_VALUE ((uint8_t)0x7F) 01646 01647 /** 01648 * @} 01649 */ 01650 01651 /** @addtogroup WWDG_Registers_Bits_Definition 01652 * @{ 01653 */ 01654 01655 #define WWDG_CR_WDGA ((uint8_t)0x80) /*!< WDGA bit mask */ 01656 #define WWDG_CR_T6 ((uint8_t)0x40) /*!< T6 bit mask */ 01657 #define WWDG_CR_T ((uint8_t)0x7F) /*!< T bits mask */ 01658 01659 #define WWDG_WR_MSB ((uint8_t)0x80) /*!< MSB bit mask */ 01660 #define WWDG_WR_W ((uint8_t)0x7F) /*!< W bits mask */ 01661 01662 /** 01663 * @} 01664 */ 01665 01666 /*----------------------------------------------------------------------------*/ 01667 /** 01668 * @brief Reset Controller (RST) 01669 */ 01670 01671 typedef struct RST_struct 01672 { 01673 __IO uint8_t SR; /*!< Reset status register */ 01674 } 01675 RST_TypeDef; 01676 01677 /** @addtogroup RST_Registers_Bits_Definition 01678 * @{ 01679 */ 01680 01681 #define RST_SR_EMCF ((uint8_t)0x10) /*!< EMC reset flag bit mask */ 01682 #define RST_SR_SWIMF ((uint8_t)0x08) /*!< SWIM reset flag bit mask */ 01683 #define RST_SR_ILLOPF ((uint8_t)0x04) /*!< Illegal opcode reset flag bit mask */ 01684 #define RST_SR_IWDGF ((uint8_t)0x02) /*!< IWDG reset flag bit mask */ 01685 #define RST_SR_WWDGF ((uint8_t)0x01) /*!< WWDG reset flag bit mask */ 01686 01687 /** 01688 * @} 01689 */ 01690 01691 /*----------------------------------------------------------------------------*/ 01692 /** 01693 * @brief Serial Peripheral Interface (SPI) 01694 */ 01695 01696 typedef struct SPI_struct 01697 { 01698 __IO uint8_t CR1; /*!< SPI control register 1 */ 01699 __IO uint8_t CR2; /*!< SPI control register 2 */ 01700 __IO uint8_t ICR; /*!< SPI interrupt control register */ 01701 __IO uint8_t SR; /*!< SPI status register */ 01702 __IO uint8_t DR; /*!< SPI data I/O register */ 01703 __IO uint8_t CRCPR; /*!< SPI CRC polynomial register */ 01704 __IO uint8_t RXCRCR; /*!< SPI Rx CRC register */ 01705 __IO uint8_t TXCRCR; /*!< SPI Tx CRC register */ 01706 } 01707 SPI_TypeDef; 01708 01709 /** @addtogroup SPI_Registers_Reset_Value 01710 * @{ 01711 */ 01712 01713 #define SPI_CR1_RESET_VALUE ((uint8_t)0x00) /*!< Control Register 1 reset value */ 01714 #define SPI_CR2_RESET_VALUE ((uint8_t)0x00) /*!< Control Register 2 reset value */ 01715 #define SPI_ICR_RESET_VALUE ((uint8_t)0x00) /*!< Interrupt Control Register reset value */ 01716 #define SPI_SR_RESET_VALUE ((uint8_t)0x02) /*!< Status Register reset value */ 01717 #define SPI_DR_RESET_VALUE ((uint8_t)0x00) /*!< Data Register reset value */ 01718 #define SPI_CRCPR_RESET_VALUE ((uint8_t)0x07) /*!< Polynomial Register reset value */ 01719 #define SPI_RXCRCR_RESET_VALUE ((uint8_t)0x00) /*!< RX CRC Register reset value */ 01720 #define SPI_TXCRCR_RESET_VALUE ((uint8_t)0x00) /*!< TX CRC Register reset value */ 01721 01722 /** 01723 * @} 01724 */ 01725 01726 /** @addtogroup SPI_Registers_Bits_Definition 01727 * @{ 01728 */ 01729 01730 #define SPI_CR1_LSBFIRST ((uint8_t)0x80) /*!< Frame format mask */ 01731 #define SPI_CR1_SPE ((uint8_t)0x40) /*!< Enable bits mask */ 01732 #define SPI_CR1_BR ((uint8_t)0x38) /*!< Baud rate control mask */ 01733 #define SPI_CR1_MSTR ((uint8_t)0x04) /*!< Master Selection mask */ 01734 #define SPI_CR1_CPOL ((uint8_t)0x02) /*!< Clock Polarity mask */ 01735 #define SPI_CR1_CPHA ((uint8_t)0x01) /*!< Clock Phase mask */ 01736 01737 #define SPI_CR2_BDM ((uint8_t)0x80) /*!< Bi-directional data mode enable mask */ 01738 #define SPI_CR2_BDOE ((uint8_t)0x40) /*!< Output enable in bi-directional mode mask */ 01739 #define SPI_CR2_CRCEN ((uint8_t)0x20) /*!< Hardware CRC calculation enable mask */ 01740 #define SPI_CR2_CRCNEXT ((uint8_t)0x10) /*!< Transmit CRC next mask */ 01741 #define SPI_CR2_RXONLY ((uint8_t)0x04) /*!< Receive only mask */ 01742 #define SPI_CR2_SSM ((uint8_t)0x02) /*!< Software slave management mask */ 01743 #define SPI_CR2_SSI ((uint8_t)0x01) /*!< Internal slave select mask */ 01744 01745 #define SPI_ICR_TXEI ((uint8_t)0x80) /*!< Tx buffer empty interrupt enable mask */ 01746 #define SPI_ICR_RXEI ((uint8_t)0x40) /*!< Rx buffer empty interrupt enable mask */ 01747 #define SPI_ICR_ERRIE ((uint8_t)0x20) /*!< Error interrupt enable mask */ 01748 #define SPI_ICR_WKIE ((uint8_t)0x10) /*!< Wake-up interrupt enable mask */ 01749 01750 #define SPI_SR_BSY ((uint8_t)0x80) /*!< Busy flag */ 01751 #define SPI_SR_OVR ((uint8_t)0x40) /*!< Overrun flag */ 01752 #define SPI_SR_MODF ((uint8_t)0x20) /*!< Mode fault */ 01753 #define SPI_SR_CRCERR ((uint8_t)0x10) /*!< CRC error flag */ 01754 #define SPI_SR_WKUP ((uint8_t)0x08) /*!< Wake-Up flag */ 01755 #define SPI_SR_TXE ((uint8_t)0x02) /*!< Transmit buffer empty */ 01756 #define SPI_SR_RXNE ((uint8_t)0x01) /*!< Receive buffer not empty */ 01757 01758 /** 01759 * @} 01760 */ 01761 01762 /*----------------------------------------------------------------------------*/ 01763 /** 01764 * @brief Universal Synchronous Asynchronous Receiver Transmitter (UART1) 01765 */ 01766 01767 typedef struct UART1_struct 01768 { 01769 __IO uint8_t SR; /*!< UART1 status register */ 01770 __IO uint8_t DR; /*!< UART1 data register */ 01771 __IO uint8_t BRR1; /*!< UART1 baud rate register */ 01772 __IO uint8_t BRR2; /*!< UART1 DIV mantissa[11:8] SCIDIV fraction */ 01773 __IO uint8_t CR1; /*!< UART1 control register 1 */ 01774 __IO uint8_t CR2; /*!< UART1 control register 2 */ 01775 __IO uint8_t CR3; /*!< UART1 control register 3 */ 01776 __IO uint8_t CR4; /*!< UART1 control register 4 */ 01777 __IO uint8_t CR5; /*!< UART1 control register 5 */ 01778 __IO uint8_t GTR; /*!< UART1 guard time register */ 01779 __IO uint8_t PSCR; /*!< UART1 prescaler register */ 01780 } 01781 UART1_TypeDef; 01782 01783 /** @addtogroup UART1_Registers_Reset_Value 01784 * @{ 01785 */ 01786 01787 #define UART1_SR_RESET_VALUE ((uint8_t)0xC0) 01788 #define UART1_BRR1_RESET_VALUE ((uint8_t)0x00) 01789 #define UART1_BRR2_RESET_VALUE ((uint8_t)0x00) 01790 #define UART1_CR1_RESET_VALUE ((uint8_t)0x00) 01791 #define UART1_CR2_RESET_VALUE ((uint8_t)0x00) 01792 #define UART1_CR3_RESET_VALUE ((uint8_t)0x00) 01793 #define UART1_CR4_RESET_VALUE ((uint8_t)0x00) 01794 #define UART1_CR5_RESET_VALUE ((uint8_t)0x00) 01795 #define UART1_GTR_RESET_VALUE ((uint8_t)0x00) 01796 #define UART1_PSCR_RESET_VALUE ((uint8_t)0x00) 01797 01798 /** 01799 * @} 01800 */ 01801 01802 /** @addtogroup UART1_Registers_Bits_Definition 01803 * @{ 01804 */ 01805 01806 #define UART1_SR_TXE ((uint8_t)0x80) /*!< Transmit Data Register Empty mask */ 01807 #define UART1_SR_TC ((uint8_t)0x40) /*!< Transmission Complete mask */ 01808 #define UART1_SR_RXNE ((uint8_t)0x20) /*!< Read Data Register Not Empty mask */ 01809 #define UART1_SR_IDLE ((uint8_t)0x10) /*!< IDLE line detected mask */ 01810 #define UART1_SR_OR ((uint8_t)0x08) /*!< OverRun error mask */ 01811 #define UART1_SR_NF ((uint8_t)0x04) /*!< Noise Flag mask */ 01812 #define UART1_SR_FE ((uint8_t)0x02) /*!< Framing Error mask */ 01813 #define UART1_SR_PE ((uint8_t)0x01) /*!< Parity Error mask */ 01814 01815 #define UART1_BRR1_DIVM ((uint8_t)0xFF) /*!< LSB mantissa of UART1DIV [7:0] mask */ 01816 01817 #define UART1_BRR2_DIVM ((uint8_t)0xF0) /*!< MSB mantissa of UART1DIV [11:8] mask */ 01818 #define UART1_BRR2_DIVF ((uint8_t)0x0F) /*!< Fraction bits of UART1DIV [3:0] mask */ 01819 01820 #define UART1_CR1_R8 ((uint8_t)0x80) /*!< Receive Data bit 8 */ 01821 #define UART1_CR1_T8 ((uint8_t)0x40) /*!< Transmit data bit 8 */ 01822 #define UART1_CR1_UARTD ((uint8_t)0x20) /*!< UART1 Disable (for low power consumption) */ 01823 #define UART1_CR1_M ((uint8_t)0x10) /*!< Word length mask */ 01824 #define UART1_CR1_WAKE ((uint8_t)0x08) /*!< Wake-up method mask */ 01825 #define UART1_CR1_PCEN ((uint8_t)0x04) /*!< Parity Control Enable mask */ 01826 #define UART1_CR1_PS ((uint8_t)0x02) /*!< UART1 Parity Selection */ 01827 #define UART1_CR1_PIEN ((uint8_t)0x01) /*!< UART1 Parity Interrupt Enable mask */ 01828 01829 #define UART1_CR2_TIEN ((uint8_t)0x80) /*!< Transmitter Interrupt Enable mask */ 01830 #define UART1_CR2_TCIEN ((uint8_t)0x40) /*!< Transmission Complete Interrupt Enable mask */ 01831 #define UART1_CR2_RIEN ((uint8_t)0x20) /*!< Receiver Interrupt Enable mask */ 01832 #define UART1_CR2_ILIEN ((uint8_t)0x10) /*!< IDLE Line Interrupt Enable mask */ 01833 #define UART1_CR2_TEN ((uint8_t)0x08) /*!< Transmitter Enable mask */ 01834 #define UART1_CR2_REN ((uint8_t)0x04) /*!< Receiver Enable mask */ 01835 #define UART1_CR2_RWU ((uint8_t)0x02) /*!< Receiver Wake-Up mask */ 01836 #define UART1_CR2_SBK ((uint8_t)0x01) /*!< Send Break mask */ 01837 01838 #define UART1_CR3_LINEN ((uint8_t)0x40) /*!< Alternate Function output mask */ 01839 #define UART1_CR3_STOP ((uint8_t)0x30) /*!< STOP bits [1:0] mask */ 01840 #define UART1_CR3_CKEN ((uint8_t)0x08) /*!< Clock Enable mask */ 01841 #define UART1_CR3_CPOL ((uint8_t)0x04) /*!< Clock Polarity mask */ 01842 #define UART1_CR3_CPHA ((uint8_t)0x02) /*!< Clock Phase mask */ 01843 #define UART1_CR3_LBCL ((uint8_t)0x01) /*!< Last Bit Clock pulse mask */ 01844 01845 #define UART1_CR4_LBDIEN ((uint8_t)0x40) /*!< LIN Break Detection Interrupt Enable mask */ 01846 #define UART1_CR4_LBDL ((uint8_t)0x20) /*!< LIN Break Detection Length mask */ 01847 #define UART1_CR4_LBDF ((uint8_t)0x10) /*!< LIN Break Detection Flag mask */ 01848 #define UART1_CR4_ADD ((uint8_t)0x0F) /*!< Address of the UART1 node mask */ 01849 01850 #define UART1_CR5_SCEN ((uint8_t)0x20) /*!< Smart Card Enable mask */ 01851 #define UART1_CR5_NACK ((uint8_t)0x10) /*!< Smart Card Nack Enable mask */ 01852 #define UART1_CR5_HDSEL ((uint8_t)0x08) /*!< Half-Duplex Selection mask */ 01853 #define UART1_CR5_IRLP ((uint8_t)0x04) /*!< Irda Low Power Selection mask */ 01854 #define UART1_CR5_IREN ((uint8_t)0x02) /*!< Irda Enable mask */ 01855 01856 /** 01857 * @} 01858 */ 01859 01860 /*----------------------------------------------------------------------------*/ 01861 /** 01862 * @brief Universal Synchronous Asynchronous Receiver Transmitter (UART2) 01863 */ 01864 01865 typedef struct UART2_struct 01866 { 01867 __IO uint8_t SR; /*!< UART1 status register */ 01868 __IO uint8_t DR; /*!< UART1 data register */ 01869 __IO uint8_t BRR1; /*!< UART1 baud rate register */ 01870 __IO uint8_t BRR2; /*!< UART1 DIV mantissa[11:8] SCIDIV fraction */ 01871 __IO uint8_t CR1; /*!< UART1 control register 1 */ 01872 __IO uint8_t CR2; /*!< UART1 control register 2 */ 01873 __IO uint8_t CR3; /*!< UART1 control register 3 */ 01874 __IO uint8_t CR4; /*!< UART1 control register 4 */ 01875 __IO uint8_t CR5; /*!< UART1 control register 5 */ 01876 __IO uint8_t CR6; /*!< UART1 control register 6 */ 01877 __IO uint8_t GTR; /*!< UART1 guard time register */ 01878 __IO uint8_t PSCR; /*!< UART1 prescaler register */ 01879 } 01880 UART2_TypeDef; 01881 01882 /** @addtogroup UART2_Registers_Reset_Value 01883 * @{ 01884 */ 01885 01886 #define UART2_SR_RESET_VALUE ((uint8_t)0xC0) 01887 #define UART2_BRR1_RESET_VALUE ((uint8_t)0x00) 01888 #define UART2_BRR2_RESET_VALUE ((uint8_t)0x00) 01889 #define UART2_CR1_RESET_VALUE ((uint8_t)0x00) 01890 #define UART2_CR2_RESET_VALUE ((uint8_t)0x00) 01891 #define UART2_CR3_RESET_VALUE ((uint8_t)0x00) 01892 #define UART2_CR4_RESET_VALUE ((uint8_t)0x00) 01893 #define UART2_CR5_RESET_VALUE ((uint8_t)0x00) 01894 #define UART2_CR6_RESET_VALUE ((uint8_t)0x00) 01895 #define UART2_GTR_RESET_VALUE ((uint8_t)0x00) 01896 #define UART2_PSCR_RESET_VALUE ((uint8_t)0x00) 01897 01898 /** 01899 * @} 01900 */ 01901 01902 /** @addtogroup UART2_Registers_Bits_Definition 01903 * @{ 01904 */ 01905 01906 #define UART2_SR_TXE ((uint8_t)0x80) /*!< Transmit Data Register Empty mask */ 01907 #define UART2_SR_TC ((uint8_t)0x40) /*!< Transmission Complete mask */ 01908 #define UART2_SR_RXNE ((uint8_t)0x20) /*!< Read Data Register Not Empty mask */ 01909 #define UART2_SR_IDLE ((uint8_t)0x10) /*!< IDLE line detected mask */ 01910 #define UART2_SR_OR ((uint8_t)0x08) /*!< OverRun error mask */ 01911 #define UART2_SR_NF ((uint8_t)0x04) /*!< Noise Flag mask */ 01912 #define UART2_SR_FE ((uint8_t)0x02) /*!< Framing Error mask */ 01913 #define UART2_SR_PE ((uint8_t)0x01) /*!< Parity Error mask */ 01914 01915 #define UART2_BRR1_DIVM ((uint8_t)0xFF) /*!< LSB mantissa of UART2DIV [7:0] mask */ 01916 01917 #define UART2_BRR2_DIVM ((uint8_t)0xF0) /*!< MSB mantissa of UART2DIV [11:8] mask */ 01918 #define UART2_BRR2_DIVF ((uint8_t)0x0F) /*!< Fraction bits of UART2DIV [3:0] mask */ 01919 01920 #define UART2_CR1_R8 ((uint8_t)0x80) /*!< Receive Data bit 8 */ 01921 #define UART2_CR1_T8 ((uint8_t)0x40) /*!< Transmit data bit 8 */ 01922 #define UART2_CR1_UARTD ((uint8_t)0x20) /*!< UART2 Disable (for low power consumption) */ 01923 #define UART2_CR1_M ((uint8_t)0x10) /*!< Word length mask */ 01924 #define UART2_CR1_WAKE ((uint8_t)0x08) /*!< Wake-up method mask */ 01925 #define UART2_CR1_PCEN ((uint8_t)0x04) /*!< Parity Control Enable mask */ 01926 #define UART2_CR1_PS ((uint8_t)0x02) /*!< UART2 Parity Selection */ 01927 #define UART2_CR1_PIEN ((uint8_t)0x01) /*!< UART2 Parity Interrupt Enable mask */ 01928 01929 #define UART2_CR2_TIEN ((uint8_t)0x80) /*!< Transmitter Interrupt Enable mask */ 01930 #define UART2_CR2_TCIEN ((uint8_t)0x40) /*!< Transmission Complete Interrupt Enable mask */ 01931 #define UART2_CR2_RIEN ((uint8_t)0x20) /*!< Receiver Interrupt Enable mask */ 01932 #define UART2_CR2_ILIEN ((uint8_t)0x10) /*!< IDLE Line Interrupt Enable mask */ 01933 #define UART2_CR2_TEN ((uint8_t)0x08) /*!< Transmitter Enable mask */ 01934 #define UART2_CR2_REN ((uint8_t)0x04) /*!< Receiver Enable mask */ 01935 #define UART2_CR2_RWU ((uint8_t)0x02) /*!< Receiver Wake-Up mask */ 01936 #define UART2_CR2_SBK ((uint8_t)0x01) /*!< Send Break mask */ 01937 01938 #define UART2_CR3_LINEN ((uint8_t)0x40) /*!< Alternate Function output mask */ 01939 #define UART2_CR3_STOP ((uint8_t)0x30) /*!< STOP bits [1:0] mask */ 01940 #define UART2_CR3_CKEN ((uint8_t)0x08) /*!< Clock Enable mask */ 01941 #define UART2_CR3_CPOL ((uint8_t)0x04) /*!< Clock Polarity mask */ 01942 #define UART2_CR3_CPHA ((uint8_t)0x02) /*!< Clock Phase mask */ 01943 #define UART2_CR3_LBCL ((uint8_t)0x01) /*!< Last Bit Clock pulse mask */ 01944 01945 #define UART2_CR4_LBDIEN ((uint8_t)0x40) /*!< LIN Break Detection Interrupt Enable mask */ 01946 #define UART2_CR4_LBDL ((uint8_t)0x20) /*!< LIN Break Detection Length mask */ 01947 #define UART2_CR4_LBDF ((uint8_t)0x10) /*!< LIN Break Detection Flag mask */ 01948 #define UART2_CR4_ADD ((uint8_t)0x0F) /*!< Address of the UART2 node mask */ 01949 01950 #define UART2_CR5_SCEN ((uint8_t)0x20) /*!< Smart Card Enable mask */ 01951 #define UART2_CR5_NACK ((uint8_t)0x10) /*!< Smart Card Nack Enable mask */ 01952 #define UART2_CR5_IRLP ((uint8_t)0x04) /*!< Irda Low Power Selection mask */ 01953 #define UART2_CR5_IREN ((uint8_t)0x02) /*!< Irda Enable mask */ 01954 01955 #define UART2_CR6_LDUM ((uint8_t)0x80) /*!< LIN Divider Update Method */ 01956 #define UART2_CR6_LSLV ((uint8_t)0x20) /*!< LIN Slave Enable */ 01957 #define UART2_CR6_LASE ((uint8_t)0x10) /*!< LIN Auto synchronization Enable */ 01958 #define UART2_CR6_LHDIEN ((uint8_t)0x04) /*!< LIN Header Detection Interrupt Enable */ 01959 #define UART2_CR6_LHDF ((uint8_t)0x02) /*!< LIN Header Detection Flag */ 01960 #define UART2_CR6_LSF ((uint8_t)0x01) /*!< LIN Synch Field */ 01961 01962 /** 01963 * @} 01964 */ 01965 01966 01967 /*----------------------------------------------------------------------------*/ 01968 /** 01969 * @brief LIN Universal Asynchronous Receiver Transmitter (UART3) 01970 */ 01971 01972 typedef struct UART3_struct 01973 { 01974 __IO uint8_t SR; /*!< status register */ 01975 __IO uint8_t DR; /*!< data register */ 01976 __IO uint8_t BRR1; /*!< baud rate register */ 01977 __IO uint8_t BRR2; /*!< DIV mantissa[11:8] SCIDIV fraction */ 01978 __IO uint8_t CR1; /*!< control register 1 */ 01979 __IO uint8_t CR2; /*!< control register 2 */ 01980 __IO uint8_t CR3; /*!< control register 3 */ 01981 __IO uint8_t CR4; /*!< control register 4 */ 01982 uint8_t RESERVED; /*!< Reserved byte */ 01983 __IO uint8_t CR6; /*!< control register 5 */ 01984 } 01985 UART3_TypeDef; 01986 01987 /** @addtogroup UART3_Registers_Reset_Value 01988 * @{ 01989 */ 01990 01991 #define UART3_SR_RESET_VALUE ((uint8_t)0xC0) 01992 #define UART3_BRR1_RESET_VALUE ((uint8_t)0x00) 01993 #define UART3_BRR2_RESET_VALUE ((uint8_t)0x00) 01994 #define UART3_CR1_RESET_VALUE ((uint8_t)0x00) 01995 #define UART3_CR2_RESET_VALUE ((uint8_t)0x00) 01996 #define UART3_CR3_RESET_VALUE ((uint8_t)0x00) 01997 #define UART3_CR4_RESET_VALUE ((uint8_t)0x00) 01998 #define UART3_CR6_RESET_VALUE ((uint8_t)0x00) 01999 02000 /** 02001 * @} 02002 */ 02003 02004 /** @addtogroup UART3_Registers_Bits_Definition 02005 * @{ 02006 */ 02007 02008 #define UART3_SR_TXE ((uint8_t)0x80) /*!< Transmit Data Register Empty mask */ 02009 #define UART3_SR_TC ((uint8_t)0x40) /*!< Transmission Complete mask */ 02010 #define UART3_SR_RXNE ((uint8_t)0x20) /*!< Read Data Register Not Empty mask */ 02011 #define UART3_SR_IDLE ((uint8_t)0x10) /*!< IDLE line detected mask */ 02012 #define UART3_SR_OR ((uint8_t)0x08) /*!< OverRun error mask */ 02013 #define UART3_SR_NF ((uint8_t)0x04) /*!< Noise Flag mask */ 02014 #define UART3_SR_FE ((uint8_t)0x02) /*!< Framing Error mask */ 02015 #define UART3_SR_PE ((uint8_t)0x01) /*!< Parity Error mask */ 02016 02017 #define UART3_BRR1_DIVM ((uint8_t)0xFF) /*!< LSB mantissa of UARTDIV [7:0] mask */ 02018 02019 #define UART3_BRR2_DIVM ((uint8_t)0xF0) /*!< MSB mantissa of UARTDIV [11:8] mask */ 02020 #define UART3_BRR2_DIVF ((uint8_t)0x0F) /*!< Fraction bits of UARTDIV [3:0] mask */ 02021 02022 #define UART3_CR1_R8 ((uint8_t)0x80) /*!< Receive Data bit 8 */ 02023 #define UART3_CR1_T8 ((uint8_t)0x40) /*!< Transmit data bit 8 */ 02024 #define UART3_CR1_UARTD ((uint8_t)0x20) /*!< UART Disable (for low power consumption) */ 02025 #define UART3_CR1_M ((uint8_t)0x10) /*!< Word length mask */ 02026 #define UART3_CR1_WAKE ((uint8_t)0x08) /*!< Wake-up method mask */ 02027 #define UART3_CR1_PCEN ((uint8_t)0x04) /*!< Parity control enable mask */ 02028 #define UART3_CR1_PS ((uint8_t)0x02) /*!< Parity selection bit mask */ 02029 #define UART3_CR1_PIEN ((uint8_t)0x01) /*!< Parity interrupt enable bit mask */ 02030 02031 #define UART3_CR2_TIEN ((uint8_t)0x80) /*!< Transmitter Interrupt Enable mask */ 02032 #define UART3_CR2_TCIEN ((uint8_t)0x40) /*!< Transmission Complete Interrupt Enable mask */ 02033 #define UART3_CR2_RIEN ((uint8_t)0x20) /*!< Receiver Interrupt Enable mask */ 02034 #define UART3_CR2_ILIEN ((uint8_t)0x10) /*!< IDLE Line Interrupt Enable mask */ 02035 #define UART3_CR2_TEN ((uint8_t)0x08) /*!< Transmitter Enable mask */ 02036 #define UART3_CR2_REN ((uint8_t)0x04) /*!< Receiver Enable mask */ 02037 #define UART3_CR2_RWU ((uint8_t)0x02) /*!< Receiver Wake-Up mask */ 02038 #define UART3_CR2_SBK ((uint8_t)0x01) /*!< Send Break mask */ 02039 02040 #define UART3_CR3_LINEN ((uint8_t)0x40) /*!< Alternate Function output mask */ 02041 #define UART3_CR3_STOP ((uint8_t)0x30) /*!< STOP bits [1:0] mask */ 02042 02043 #define UART3_CR4_LBDIEN ((uint8_t)0x40) /*!< LIN Break Detection Interrupt Enable mask */ 02044 #define UART3_CR4_LBDL ((uint8_t)0x20) /*!< LIN Break Detection Length mask */ 02045 #define UART3_CR4_LBDF ((uint8_t)0x10) /*!< LIN Break Detection Flag mask */ 02046 #define UART3_CR4_ADD ((uint8_t)0x0F) /*!< Address of the UART3 node mask */ 02047 02048 #define UART3_CR6_LDUM ((uint8_t)0x80) /*!< LIN Divider Update Method */ 02049 #define UART3_CR6_LSLV ((uint8_t)0x20) /*!< LIN Slave Enable */ 02050 #define UART3_CR6_LASE ((uint8_t)0x10) /*!< LIN Auto synchronization Enable */ 02051 #define UART3_CR6_LHDIEN ((uint8_t)0x04) /*!< LIN Header Detection Interrupt Enable */ 02052 #define UART3_CR6_LHDF ((uint8_t)0x02) /*!< LIN Header Detection Flag */ 02053 #define UART3_CR6_LSF ((uint8_t)0x01) /*!< LIN Synch Field */ 02054 02055 /** 02056 * @} 02057 */ 02058 02059 /*----------------------------------------------------------------------------*/ 02060 /** 02061 * @brief Universal Synchronous Asynchronous Receiver Transmitter (UART4) 02062 */ 02063 #if defined(STM8AF622x) 02064 typedef struct UART4_struct 02065 { 02066 __IO uint8_t SR; /*!< UART4 status register */ 02067 __IO uint8_t DR; /*!< UART4 data register */ 02068 __IO uint8_t BRR1; /*!< UART4 baud rate register */ 02069 __IO uint8_t BRR2; /*!< UART4 DIV mantissa[11:8] SCIDIV fraction */ 02070 __IO uint8_t CR1; /*!< UART4 control register 1 */ 02071 __IO uint8_t CR2; /*!< UART4 control register 2 */ 02072 __IO uint8_t CR3; /*!< UART4 control register 3 */ 02073 __IO uint8_t CR4; /*!< UART4 control register 4 */ 02074 __IO uint8_t CR5; /*!< UART4 control register 5 */ 02075 __IO uint8_t CR6; /*!< UART4 control register 6 */ 02076 __IO uint8_t GTR; /*!< UART4 guard time register */ 02077 __IO uint8_t PSCR; /*!< UART4 prescaler register */ 02078 } 02079 UART4_TypeDef; 02080 02081 /** @addtogroup UART4_Registers_Reset_Value 02082 * @{ 02083 */ 02084 02085 #define UART4_SR_RESET_VALUE ((uint8_t)0xC0) 02086 #define UART4_BRR1_RESET_VALUE ((uint8_t)0x00) 02087 #define UART4_BRR2_RESET_VALUE ((uint8_t)0x00) 02088 #define UART4_CR1_RESET_VALUE ((uint8_t)0x00) 02089 #define UART4_CR2_RESET_VALUE ((uint8_t)0x00) 02090 #define UART4_CR3_RESET_VALUE ((uint8_t)0x00) 02091 #define UART4_CR4_RESET_VALUE ((uint8_t)0x00) 02092 #define UART4_CR5_RESET_VALUE ((uint8_t)0x00) 02093 #define UART4_CR6_RESET_VALUE ((uint8_t)0x00) 02094 #define UART4_GTR_RESET_VALUE ((uint8_t)0x00) 02095 #define UART4_PSCR_RESET_VALUE ((uint8_t)0x00) 02096 02097 /** 02098 * @} 02099 */ 02100 02101 /** @addtogroup UART4_Registers_Bits_Definition 02102 * @{ 02103 */ 02104 02105 #define UART4_SR_TXE ((uint8_t)0x80) /*!< Transmit Data Register Empty mask */ 02106 #define UART4_SR_TC ((uint8_t)0x40) /*!< Transmission Complete mask */ 02107 #define UART4_SR_RXNE ((uint8_t)0x20) /*!< Read Data Register Not Empty mask */ 02108 #define UART4_SR_IDLE ((uint8_t)0x10) /*!< IDLE line detected mask */ 02109 #define UART4_SR_OR ((uint8_t)0x08) /*!< OverRun error mask */ 02110 #define UART4_SR_NF ((uint8_t)0x04) /*!< Noise Flag mask */ 02111 #define UART4_SR_FE ((uint8_t)0x02) /*!< Framing Error mask */ 02112 #define UART4_SR_PE ((uint8_t)0x01) /*!< Parity Error mask */ 02113 02114 #define UART4_BRR1_DIVM ((uint8_t)0xFF) /*!< LSB mantissa of UART4DIV [7:0] mask */ 02115 02116 #define UART4_BRR2_DIVM ((uint8_t)0xF0) /*!< MSB mantissa of UART4DIV [11:8] mask */ 02117 #define UART4_BRR2_DIVF ((uint8_t)0x0F) /*!< Fraction bits of UART4DIV [3:0] mask */ 02118 02119 #define UART4_CR1_R8 ((uint8_t)0x80) /*!< Receive Data bit 8 */ 02120 #define UART4_CR1_T8 ((uint8_t)0x40) /*!< Transmit data bit 8 */ 02121 #define UART4_CR1_UARTD ((uint8_t)0x20) /*!< UART4 Disable (for low power consumption) */ 02122 #define UART4_CR1_M ((uint8_t)0x10) /*!< Word length mask */ 02123 #define UART4_CR1_WAKE ((uint8_t)0x08) /*!< Wake-up method mask */ 02124 #define UART4_CR1_PCEN ((uint8_t)0x04) /*!< Parity Control Enable mask */ 02125 #define UART4_CR1_PS ((uint8_t)0x02) /*!< UART4 Parity Selection */ 02126 #define UART4_CR1_PIEN ((uint8_t)0x01) /*!< UART4 Parity Interrupt Enable mask */ 02127 02128 #define UART4_CR2_TIEN ((uint8_t)0x80) /*!< Transmitter Interrupt Enable mask */ 02129 #define UART4_CR2_TCIEN ((uint8_t)0x40) /*!< Transmission Complete Interrupt Enable mask */ 02130 #define UART4_CR2_RIEN ((uint8_t)0x20) /*!< Receiver Interrupt Enable mask */ 02131 #define UART4_CR2_ILIEN ((uint8_t)0x10) /*!< IDLE Line Interrupt Enable mask */ 02132 #define UART4_CR2_TEN ((uint8_t)0x08) /*!< Transmitter Enable mask */ 02133 #define UART4_CR2_REN ((uint8_t)0x04) /*!< Receiver Enable mask */ 02134 #define UART4_CR2_RWU ((uint8_t)0x02) /*!< Receiver Wake-Up mask */ 02135 #define UART4_CR2_SBK ((uint8_t)0x01) /*!< Send Break mask */ 02136 02137 #define UART4_CR3_LINEN ((uint8_t)0x40) /*!< Alternate Function output mask */ 02138 #define UART4_CR3_STOP ((uint8_t)0x30) /*!< STOP bits [1:0] mask */ 02139 #define UART4_CR3_CKEN ((uint8_t)0x08) /*!< Clock Enable mask */ 02140 #define UART4_CR3_CPOL ((uint8_t)0x04) /*!< Clock Polarity mask */ 02141 #define UART4_CR3_CPHA ((uint8_t)0x02) /*!< Clock Phase mask */ 02142 #define UART4_CR3_LBCL ((uint8_t)0x01) /*!< Last Bit Clock pulse mask */ 02143 02144 #define UART4_CR4_LBDIEN ((uint8_t)0x40) /*!< LIN Break Detection Interrupt Enable mask */ 02145 #define UART4_CR4_LBDL ((uint8_t)0x20) /*!< LIN Break Detection Length mask */ 02146 #define UART4_CR4_LBDF ((uint8_t)0x10) /*!< LIN Break Detection Flag mask */ 02147 #define UART4_CR4_ADD ((uint8_t)0x0F) /*!< Address of the UART4 node mask */ 02148 02149 #define UART4_CR5_SCEN ((uint8_t)0x20) /*!< Smart Card Enable mask */ 02150 #define UART4_CR5_NACK ((uint8_t)0x10) /*!< Smart Card Nack Enable mask */ 02151 #define UART4_CR5_HDSEL ((uint8_t)0x08) /*!< Half-Duplex Selection mask */ 02152 #define UART4_CR5_IRLP ((uint8_t)0x04) /*!< Irda Low Power Selection mask */ 02153 #define UART4_CR5_IREN ((uint8_t)0x02) /*!< Irda Enable mask */ 02154 02155 #define UART4_CR6_LDUM ((uint8_t)0x80) /*!< LIN Divider Update Method */ 02156 #define UART4_CR6_LSLV ((uint8_t)0x20) /*!< LIN Slave Enable */ 02157 #define UART4_CR6_LASE ((uint8_t)0x10) /*!< LIN Auto synchronization Enable */ 02158 #define UART4_CR6_LHDIEN ((uint8_t)0x04) /*!< LIN Header Detection Interrupt Enable */ 02159 #define UART4_CR6_LHDF ((uint8_t)0x02) /*!< LIN Header Detection Flag */ 02160 #define UART4_CR6_LSF ((uint8_t)0x01) /*!< LIN Synch Field */ 02161 #endif /* STM8AF622x */ 02162 02163 /** 02164 * @} 02165 */ 02166 02167 /*----------------------------------------------------------------------------*/ 02168 02169 /*----------------------------------------------------------------------------*/ 02170 /** 02171 * @brief Controller Area Network (CAN) 02172 */ 02173 02174 typedef struct 02175 { 02176 __IO uint8_t MCR; /*!< CAN master control register */ 02177 __IO uint8_t MSR; /*!< CAN master status register */ 02178 __IO uint8_t TSR; /*!< CAN transmit status register */ 02179 __IO uint8_t TPR; /*!< CAN transmit priority register */ 02180 __IO uint8_t RFR; /*!< CAN receive FIFO register */ 02181 __IO uint8_t IER; /*!< CAN interrupt enable register */ 02182 __IO uint8_t DGR; /*!< CAN diagnosis register */ 02183 __IO uint8_t PSR; /*!< CAN page selection register */ 02184 02185 union 02186 { 02187 struct 02188 { 02189 __IO uint8_t MCSR; 02190 __IO uint8_t MDLCR; 02191 __IO uint8_t MIDR1; 02192 __IO uint8_t MIDR2; 02193 __IO uint8_t MIDR3; 02194 __IO uint8_t MIDR4; 02195 __IO uint8_t MDAR1; 02196 __IO uint8_t MDAR2; 02197 __IO uint8_t MDAR3; 02198 __IO uint8_t MDAR4; 02199 __IO uint8_t MDAR5; 02200 __IO uint8_t MDAR6; 02201 __IO uint8_t MDAR7; 02202 __IO uint8_t MDAR8; 02203 __IO uint8_t MTSRL; 02204 __IO uint8_t MTSRH; 02205 }TxMailbox; 02206 02207 struct 02208 { 02209 __IO uint8_t FR01; 02210 __IO uint8_t FR02; 02211 __IO uint8_t FR03; 02212 __IO uint8_t FR04; 02213 __IO uint8_t FR05; 02214 __IO uint8_t FR06; 02215 __IO uint8_t FR07; 02216 __IO uint8_t FR08; 02217 02218 __IO uint8_t FR09; 02219 __IO uint8_t FR10; 02220 __IO uint8_t FR11; 02221 __IO uint8_t FR12; 02222 __IO uint8_t FR13; 02223 __IO uint8_t FR14; 02224 __IO uint8_t FR15; 02225 __IO uint8_t FR16; 02226 }Filter; 02227 02228 struct 02229 { 02230 __IO uint8_t F0R1; 02231 __IO uint8_t F0R2; 02232 __IO uint8_t F0R3; 02233 __IO uint8_t F0R4; 02234 __IO uint8_t F0R5; 02235 __IO uint8_t F0R6; 02236 __IO uint8_t F0R7; 02237 __IO uint8_t F0R8; 02238 02239 __IO uint8_t F1R1; 02240 __IO uint8_t F1R2; 02241 __IO uint8_t F1R3; 02242 __IO uint8_t F1R4; 02243 __IO uint8_t F1R5; 02244 __IO uint8_t F1R6; 02245 __IO uint8_t F1R7; 02246 __IO uint8_t F1R8; 02247 }Filter01; 02248 02249 struct 02250 { 02251 __IO uint8_t F2R1; 02252 __IO uint8_t F2R2; 02253 __IO uint8_t F2R3; 02254 __IO uint8_t F2R4; 02255 __IO uint8_t F2R5; 02256 __IO uint8_t F2R6; 02257 __IO uint8_t F2R7; 02258 __IO uint8_t F2R8; 02259 02260 __IO uint8_t F3R1; 02261 __IO uint8_t F3R2; 02262 __IO uint8_t F3R3; 02263 __IO uint8_t F3R4; 02264 __IO uint8_t F3R5; 02265 __IO uint8_t F3R6; 02266 __IO uint8_t F3R7; 02267 __IO uint8_t F3R8; 02268 }Filter23; 02269 02270 struct 02271 { 02272 __IO uint8_t F4R1; 02273 __IO uint8_t F4R2; 02274 __IO uint8_t F4R3; 02275 __IO uint8_t F4R4; 02276 __IO uint8_t F4R5; 02277 __IO uint8_t F4R6; 02278 __IO uint8_t F4R7; 02279 __IO uint8_t F4R8; 02280 02281 __IO uint8_t F5R1; 02282 __IO uint8_t F5R2; 02283 __IO uint8_t F5R3; 02284 __IO uint8_t F5R4; 02285 __IO uint8_t F5R5; 02286 __IO uint8_t F5R6; 02287 __IO uint8_t F5R7; 02288 __IO uint8_t F5R8; 02289 } Filter45; 02290 02291 struct 02292 { 02293 __IO uint8_t ESR; 02294 __IO uint8_t EIER; 02295 __IO uint8_t TECR; 02296 __IO uint8_t RECR; 02297 __IO uint8_t BTR1; 02298 __IO uint8_t BTR2; 02299 uint8_t Reserved1[2]; 02300 __IO uint8_t FMR1; 02301 __IO uint8_t FMR2; 02302 __IO uint8_t FCR1; 02303 __IO uint8_t FCR2; 02304 __IO uint8_t FCR3; 02305 uint8_t Reserved2[3]; 02306 }Config; 02307 02308 struct 02309 { 02310 __IO uint8_t MFMI; 02311 __IO uint8_t MDLCR; 02312 __IO uint8_t MIDR1; 02313 __IO uint8_t MIDR2; 02314 __IO uint8_t MIDR3; 02315 __IO uint8_t MIDR4; 02316 __IO uint8_t MDAR1; 02317 __IO uint8_t MDAR2; 02318 __IO uint8_t MDAR3; 02319 __IO uint8_t MDAR4; 02320 __IO uint8_t MDAR5; 02321 __IO uint8_t MDAR6; 02322 __IO uint8_t MDAR7; 02323 __IO uint8_t MDAR8; 02324 __IO uint8_t MTSRL; 02325 __IO uint8_t MTSRH; 02326 }RxFIFO; 02327 }Page; 02328 } CAN_TypeDef; 02329 02330 /** @addtogroup CAN_Registers_Bits_Definition 02331 * @{ 02332 */ 02333 /******************************* Common ***************************************/ 02334 /* CAN Master Control Register bits */ 02335 #define CAN_MCR_INRQ ((uint8_t)0x01) 02336 #define CAN_MCR_SLEEP ((uint8_t)0x02) 02337 #define CAN_MCR_TXFP ((uint8_t)0x04) 02338 #define CAN_MCR_RFLM ((uint8_t)0x08) 02339 #define CAN_MCR_NART ((uint8_t)0x10) 02340 #define CAN_MCR_AWUM ((uint8_t)0x20) 02341 #define CAN_MCR_ABOM ((uint8_t)0x40) 02342 #define CAN_MCR_TTCM ((uint8_t)0x80) 02343 02344 /* CAN Master Status Register bits */ 02345 #define CAN_MSR_INAK ((uint8_t)0x01) 02346 #define CAN_MSR_SLAK ((uint8_t)0x02) 02347 #define CAN_MSR_ERRI ((uint8_t)0x04) 02348 #define CAN_MSR_WKUI ((uint8_t)0x08) 02349 #define CAN_MSR_TX ((uint8_t)0x10) 02350 #define CAN_MSR_RX ((uint8_t)0x20) 02351 02352 /* CAN Transmit Status Register bits */ 02353 #define CAN_TSR_RQCP0 ((uint8_t)0x01) 02354 #define CAN_TSR_RQCP1 ((uint8_t)0x02) 02355 #define CAN_TSR_RQCP2 ((uint8_t)0x04) 02356 #define CAN_TSR_RQCP012 ((uint8_t)0x07) 02357 #define CAN_TSR_TXOK0 ((uint8_t)0x10) 02358 #define CAN_TSR_TXOK1 ((uint8_t)0x20) 02359 #define CAN_TSR_TXOK2 ((uint8_t)0x40) 02360 02361 #define CAN_TPR_CODE0 ((uint8_t)0x01) 02362 #define CAN_TPR_TME0 ((uint8_t)0x04) 02363 #define CAN_TPR_TME1 ((uint8_t)0x08) 02364 #define CAN_TPR_TME2 ((uint8_t)0x10) 02365 #define CAN_TPR_LOW0 ((uint8_t)0x20) 02366 #define CAN_TPR_LOW1 ((uint8_t)0x40) 02367 #define CAN_TPR_LOW2 ((uint8_t)0x80) 02368 /* CAN Receive FIFO Register bits */ 02369 #define CAN_RFR_FMP01 ((uint8_t)0x03) 02370 #define CAN_RFR_FULL ((uint8_t)0x08) 02371 #define CAN_RFR_FOVR ((uint8_t)0x10) 02372 #define CAN_RFR_RFOM ((uint8_t)0x20) 02373 02374 /* CAN Interrupt Register bits */ 02375 #define CAN_IER_TMEIE ((uint8_t)0x01) 02376 #define CAN_IER_FMPIE ((uint8_t)0x02) 02377 #define CAN_IER_FFIE ((uint8_t)0x04) 02378 #define CAN_IER_FOVIE ((uint8_t)0x08) 02379 #define CAN_IER_WKUIE ((uint8_t)0x80) 02380 02381 02382 /* CAN diagnostic Register bits */ 02383 #define CAN_DGR_LBKM ((uint8_t)0x01) 02384 #define CAN_DGR_SLIM ((uint8_t)0x02) 02385 #define CAN_DGR_SAMP ((uint8_t)0x04) 02386 #define CAN_DGR_RX ((uint8_t)0x08) 02387 #define CAN_DGR_TXM2E ((uint8_t)0x10) 02388 02389 02390 /* CAN page select Register bits */ 02391 #define CAN_PSR_PS0 ((uint8_t)0x01) 02392 #define CAN_PSR_PS1 ((uint8_t)0x02) 02393 #define CAN_PSR_PS2 ((uint8_t)0x04) 02394 02395 /******************** Tx MailBox & Fifo Page common bits **********************/ 02396 #define CAN_MCSR_TXRQ ((uint8_t)0x01) 02397 #define CAN_MCSR_ABRQ ((uint8_t)0x02) 02398 #define CAN_MCSR_RQCP ((uint8_t)0x04) 02399 #define CAN_MCSR_TXOK ((uint8_t)0x08) 02400 #define CAN_MCSR_ALST ((uint8_t)0x10) 02401 #define CAN_MCSR_TERR ((uint8_t)0x20) 02402 02403 #define CAN_MDLCR_DLC ((uint8_t)0x0F) 02404 #define CAN_MDLCR_TGT ((uint8_t)0x80) 02405 02406 #define CAN_MIDR1_RTR ((uint8_t)0x20) 02407 #define CAN_MIDR1_IDE ((uint8_t)0x40) 02408 02409 02410 /************************* Filter Page ****************************************/ 02411 02412 /* CAN Error Status Register bits */ 02413 #define CAN_ESR_EWGF ((uint8_t)0x01) 02414 #define CAN_ESR_EPVF ((uint8_t)0x02) 02415 #define CAN_ESR_BOFF ((uint8_t)0x04) 02416 #define CAN_ESR_LEC0 ((uint8_t)0x10) 02417 #define CAN_ESR_LEC1 ((uint8_t)0x20) 02418 #define CAN_ESR_LEC2 ((uint8_t)0x40) 02419 #define CAN_ESR_LEC ((uint8_t)0x70) 02420 02421 /* CAN Error Status Register bits */ 02422 #define CAN_EIER_EWGIE ((uint8_t)0x01) 02423 #define CAN_EIER_EPVIE ((uint8_t)0x02) 02424 #define CAN_EIER_BOFIE ((uint8_t)0x04) 02425 #define CAN_EIER_LECIE ((uint8_t)0x10) 02426 #define CAN_EIER_ERRIE ((uint8_t)0x80) 02427 02428 /* CAN transmit error counter Register bits(CAN_TECR) */ 02429 #define CAN_TECR_TEC0 ((uint8_t)0x01) 02430 #define CAN_TECR_TEC1 ((uint8_t)0x02) 02431 #define CAN_TECR_TEC2 ((uint8_t)0x04) 02432 #define CAN_TECR_TEC3 ((uint8_t)0x08) 02433 #define CAN_TECR_TEC4 ((uint8_t)0x10) 02434 #define CAN_TECR_TEC5 ((uint8_t)0x20) 02435 #define CAN_TECR_TEC6 ((uint8_t)0x40) 02436 #define CAN_TECR_TEC7 ((uint8_t)0x80) 02437 02438 /* CAN RECEIVE error counter Register bits(CAN_TECR) */ 02439 #define CAN_RECR_REC0 ((uint8_t)0x01) 02440 #define CAN_RECR_REC1 ((uint8_t)0x02) 02441 #define CAN_RECR_REC2 ((uint8_t)0x04) 02442 #define CAN_RECR_REC3 ((uint8_t)0x08) 02443 #define CAN_RECR_REC4 ((uint8_t)0x10) 02444 #define CAN_RECR_REC5 ((uint8_t)0x20) 02445 #define CAN_RECR_REC6 ((uint8_t)0x40) 02446 #define CAN_RECR_REC7 ((uint8_t)0x80) 02447 02448 /* CAN filter mode register bits (CAN_FMR) */ 02449 #define CAN_FMR1_FML0 ((uint8_t)0x01) 02450 #define CAN_FMR1_FMH0 ((uint8_t)0x02) 02451 #define CAN_FMR1_FML1 ((uint8_t)0x04) 02452 #define CAN_FMR1_FMH1 ((uint8_t)0x08) 02453 #define CAN_FMR1_FML2 ((uint8_t)0x10) 02454 #define CAN_FMR1_FMH2 ((uint8_t)0x20) 02455 #define CAN_FMR1_FML3 ((uint8_t)0x40) 02456 #define CAN_FMR1_FMH3 ((uint8_t)0x80) 02457 02458 #define CAN_FMR2_FML4 ((uint8_t)0x01) 02459 #define CAN_FMR2_FMH4 ((uint8_t)0x02) 02460 #define CAN_FMR2_FML5 ((uint8_t)0x04) 02461 #define CAN_FMR2_FMH5 ((uint8_t)0x08) 02462 02463 /* CAN filter Config register bits (CAN_FCR) */ 02464 #define CAN_FCR1_FACT0 ((uint8_t)0x01) 02465 #define CAN_FCR1_FACT1 ((uint8_t)0x10) 02466 #define CAN_FCR2_FACT2 ((uint8_t)0x01) 02467 #define CAN_FCR2_FACT3 ((uint8_t)0x10) 02468 #define CAN_FCR3_FACT4 ((uint8_t)0x01) 02469 #define CAN_FCR3_FACT5 ((uint8_t)0x10) 02470 02471 #define CAN_FCR1_FSC00 ((uint8_t)0x02) 02472 #define CAN_FCR1_FSC01 ((uint8_t)0x04) 02473 #define CAN_FCR1_FSC10 ((uint8_t)0x20) 02474 #define CAN_FCR1_FSC11 ((uint8_t)0x40) 02475 #define CAN_FCR2_FSC20 ((uint8_t)0x02) 02476 #define CAN_FCR2_FSC21 ((uint8_t)0x04) 02477 #define CAN_FCR2_FSC30 ((uint8_t)0x20) 02478 #define CAN_FCR2_FSC31 ((uint8_t)0x40) 02479 #define CAN_FCR3_FSC40 ((uint8_t)0x02) 02480 #define CAN_FCR3_FSC41 ((uint8_t)0x04) 02481 #define CAN_FCR3_FSC50 ((uint8_t)0x20) 02482 #define CAN_FCR3_FSC51 ((uint8_t)0x40) 02483 02484 /** 02485 * @} 02486 */ 02487 02488 /** @addtogroup CAN_Registers_Reset_Value 02489 * @{ 02490 */ 02491 #define CAN_MCR_RESET_VALUE ((uint8_t)0x02) 02492 #define CAN_MSR_RESET_VALUE ((uint8_t)0x02) 02493 #define CAN_TSR_RESET_VALUE ((uint8_t)0x00) 02494 #define CAN_TPR_RESET_VALUE ((uint8_t)0x0C) 02495 #define CAN_RFR_RESET_VALUE ((uint8_t)0x00) 02496 #define CAN_IER_RESET_VALUE ((uint8_t)0x00) 02497 #define CAN_DGR_RESET_VALUE ((uint8_t)0x0C) 02498 #define CAN_PSR_RESET_VALUE ((uint8_t)0x00) 02499 02500 #define CAN_ESR_RESET_VALUE ((uint8_t)0x00) 02501 #define CAN_EIER_RESET_VALUE ((uint8_t)0x00) 02502 #define CAN_TECR_RESET_VALUE ((uint8_t)0x00) 02503 #define CAN_RECR_RESET_VALUE ((uint8_t)0x00) 02504 #define CAN_BTR1_RESET_VALUE ((uint8_t)0x40) 02505 #define CAN_BTR2_RESET_VALUE ((uint8_t)0x23) 02506 #define CAN_FMR1_RESET_VALUE ((uint8_t)0x00) 02507 #define CAN_FMR2_RESET_VALUE ((uint8_t)0x00) 02508 #define CAN_FCR_RESET_VALUE ((uint8_t)0x00) 02509 02510 #define CAN_MFMI_RESET_VALUE ((uint8_t)0x00) 02511 #define CAN_MDLC_RESET_VALUE ((uint8_t)0x00) 02512 #define CAN_MCSR_RESET_VALUE ((uint8_t)0x00) 02513 02514 /** 02515 * @} 02516 */ 02517 02518 /** 02519 * @brief Configuration Registers (CFG) 02520 */ 02521 02522 typedef struct CFG_struct 02523 { 02524 __IO uint8_t GCR; /*!< Global Configuration register */ 02525 } 02526 CFG_TypeDef; 02527 02528 /** @addtogroup CFG_Registers_Reset_Value 02529 * @{ 02530 */ 02531 02532 #define CFG_GCR_RESET_VALUE ((uint8_t)0x00) 02533 02534 /** 02535 * @} 02536 */ 02537 02538 /** @addtogroup CFG_Registers_Bits_Definition 02539 * @{ 02540 */ 02541 02542 #define CFG_GCR_SWD ((uint8_t)0x01) /*!< Swim disable bit mask */ 02543 #define CFG_GCR_AL ((uint8_t)0x02) /*!< Activation Level bit mask */ 02544 02545 /** 02546 * @} 02547 */ 02548 02549 /******************************************************************************/ 02550 /* Peripherals Base Address */ 02551 /******************************************************************************/ 02552 02553 /** @addtogroup MAP_FILE_Base_Addresses 02554 * @{ 02555 */ 02556 #define OPT_BaseAddress 0x4800 02557 #define GPIOA_BaseAddress 0x5000 02558 #define GPIOB_BaseAddress 0x5005 02559 #define GPIOC_BaseAddress 0x500A 02560 #define GPIOD_BaseAddress 0x500F 02561 #define GPIOE_BaseAddress 0x5014 02562 #define GPIOF_BaseAddress 0x5019 02563 #define GPIOG_BaseAddress 0x501E 02564 #define GPIOH_BaseAddress 0x5023 02565 #define GPIOI_BaseAddress 0x5028 02566 #define FLASH_BaseAddress 0x505A 02567 #define EXTI_BaseAddress 0x50A0 02568 #define RST_BaseAddress 0x50B3 02569 #define CLK_BaseAddress 0x50C0 02570 #define WWDG_BaseAddress 0x50D1 02571 #define IWDG_BaseAddress 0x50E0 02572 #define AWU_BaseAddress 0x50F0 02573 #define BEEP_BaseAddress 0x50F3 02574 #define SPI_BaseAddress 0x5200 02575 #define I2C_BaseAddress 0x5210 02576 #define UART1_BaseAddress 0x5230 02577 #define UART2_BaseAddress 0x5240 02578 #define UART3_BaseAddress 0x5240 02579 #define UART4_BaseAddress 0x5230 02580 #define TIM1_BaseAddress 0x5250 02581 #define TIM2_BaseAddress 0x5300 02582 #define TIM3_BaseAddress 0x5320 02583 #define TIM4_BaseAddress 0x5340 02584 #define TIM5_BaseAddress 0x5300 02585 #define TIM6_BaseAddress 0x5340 02586 #define ADC1_BaseAddress 0x53E0 02587 #define ADC2_BaseAddress 0x5400 02588 #define CAN_BaseAddress 0x5420 02589 #define CFG_BaseAddress 0x7F60 02590 #define ITC_BaseAddress 0x7F70 02591 #define DM_BaseAddress 0x7F90 02592 02593 /** 02594 * @} 02595 */ 02596 02597 /******************************************************************************/ 02598 /* Peripherals declarations */ 02599 /******************************************************************************/ 02600 02601 #if defined(STM8S105) || defined(STM8S005) || defined(STM8S103) || defined(STM8S003) || \ 02602 defined(STM8S001) || defined(STM8S903) || defined(STM8AF626x) || defined(STM8AF622x) 02603 #define ADC1 ((ADC1_TypeDef *) ADC1_BaseAddress) 02604 #endif /* (STM8S105)||(STM8S103)||(STM8S005)||(STM8S003)||(STM8S001)||(STM8S903)||(STM8AF626x)||(STM8AF622x)*/ 02605 02606 #if defined(STM8S208) || defined(STM8S207) || defined (STM8S007) || defined (STM8AF52Ax) || \ 02607 defined (STM8AF62Ax) 02608 #define ADC2 ((ADC2_TypeDef *) ADC2_BaseAddress) 02609 #endif /* (STM8S208) ||(STM8S207) || (STM8S007) || (STM8AF52Ax) || (STM8AF62Ax) */ 02610 02611 #define AWU ((AWU_TypeDef *) AWU_BaseAddress) 02612 02613 #define BEEP ((BEEP_TypeDef *) BEEP_BaseAddress) 02614 02615 #if defined (STM8S208) || defined (STM8AF52Ax) 02616 #define CAN ((CAN_TypeDef *) CAN_BaseAddress) 02617 #endif /* (STM8S208) || (STM8AF52Ax) */ 02618 02619 #define CLK ((CLK_TypeDef *) CLK_BaseAddress) 02620 02621 #define EXTI ((EXTI_TypeDef *) EXTI_BaseAddress) 02622 02623 #define FLASH ((FLASH_TypeDef *) FLASH_BaseAddress) 02624 02625 #define OPT ((OPT_TypeDef *) OPT_BaseAddress) 02626 02627 #define GPIOA ((GPIO_TypeDef *) GPIOA_BaseAddress) 02628 02629 #define GPIOB ((GPIO_TypeDef *) GPIOB_BaseAddress) 02630 02631 #define GPIOC ((GPIO_TypeDef *) GPIOC_BaseAddress) 02632 02633 #define GPIOD ((GPIO_TypeDef *) GPIOD_BaseAddress) 02634 02635 #define GPIOE ((GPIO_TypeDef *) GPIOE_BaseAddress) 02636 02637 #define GPIOF ((GPIO_TypeDef *) GPIOF_BaseAddress) 02638 02639 #if defined(STM8S207) || defined (STM8S007) || defined(STM8S208) || defined(STM8S105) || \ 02640 defined(STM8S005) || defined (STM8AF52Ax) || defined (STM8AF62Ax) || defined (STM8AF626x) 02641 #define GPIOG ((GPIO_TypeDef *) GPIOG_BaseAddress) 02642 #endif /* (STM8S208) ||(STM8S207) || (STM8S105) || (STM8AF52Ax) || (STM8AF62Ax) || (STM8AF626x) */ 02643 02644 #if defined(STM8S207) || defined (STM8S007) || defined(STM8S208) || defined (STM8AF52Ax) || \ 02645 defined (STM8AF62Ax) 02646 #define GPIOH ((GPIO_TypeDef *) GPIOH_BaseAddress) 02647 #define GPIOI ((GPIO_TypeDef *) GPIOI_BaseAddress) 02648 #endif /* (STM8S208) ||(STM8S207) || (STM8AF62Ax) || (STM8AF52Ax) */ 02649 02650 #define RST ((RST_TypeDef *) RST_BaseAddress) 02651 02652 #define WWDG ((WWDG_TypeDef *) WWDG_BaseAddress) 02653 #define IWDG ((IWDG_TypeDef *) IWDG_BaseAddress) 02654 02655 #define SPI ((SPI_TypeDef *) SPI_BaseAddress) 02656 #define I2C ((I2C_TypeDef *) I2C_BaseAddress) 02657 02658 #if defined(STM8S208) || defined(STM8S207) || defined (STM8S007) || defined(STM8S103) || \ 02659 defined(STM8S003) || defined(STM8S001) || defined(STM8S903) || defined (STM8AF52Ax) || defined (STM8AF62Ax) 02660 #define UART1 ((UART1_TypeDef *) UART1_BaseAddress) 02661 #endif /* (STM8S208) ||(STM8S207) || (STM8S103) || (STM8S001) || (STM8S903) || (STM8AF52Ax) || (STM8AF62Ax) */ 02662 02663 #if defined (STM8S105) || defined (STM8S005) || defined (STM8AF626x) 02664 #define UART2 ((UART2_TypeDef *) UART2_BaseAddress) 02665 #endif /* STM8S105 || STM8S005 || STM8AF626x */ 02666 02667 #if defined(STM8S208) ||defined(STM8S207) || defined (STM8S007) || defined (STM8AF52Ax) || \ 02668 defined (STM8AF62Ax) 02669 #define UART3 ((UART3_TypeDef *) UART3_BaseAddress) 02670 #endif /* (STM8S208) ||(STM8S207) || (STM8AF62Ax) || (STM8AF52Ax) */ 02671 02672 #if defined(STM8AF622x) 02673 #define UART4 ((UART4_TypeDef *) UART4_BaseAddress) 02674 #endif /* (STM8AF622x) */ 02675 02676 #define TIM1 ((TIM1_TypeDef *) TIM1_BaseAddress) 02677 02678 #if defined(STM8S208) || defined(STM8S207) || defined (STM8S007) || defined(STM8S103) || \ 02679 defined(STM8S003) || defined(STM8S001) || defined(STM8S105) || defined(STM8S005) || defined (STM8AF52Ax) || \ 02680 defined (STM8AF62Ax) || defined (STM8AF626x) 02681 #define TIM2 ((TIM2_TypeDef *) TIM2_BaseAddress) 02682 #endif /* (STM8S208) ||(STM8S207) || (STM8S103) || (STM8S001) || (STM8S105) || (STM8AF52Ax) || (STM8AF62Ax) || (STM8AF626x)*/ 02683 02684 #if defined(STM8S208) || defined(STM8S207) || defined (STM8S007) || defined(STM8S105) || \ 02685 defined(STM8S005) || defined (STM8AF52Ax) || defined (STM8AF62Ax) || defined (STM8AF626x) 02686 #define TIM3 ((TIM3_TypeDef *) TIM3_BaseAddress) 02687 #endif /* (STM8S208) ||(STM8S207) || (STM8S105) || (STM8AF62Ax) || (STM8AF52Ax) || (STM8AF626x)*/ 02688 02689 #if defined(STM8S208) ||defined(STM8S207) || defined (STM8S007) || defined(STM8S103) || \ 02690 defined(STM8S003) || defined(STM8S001) || defined(STM8S105) || defined(STM8S005) || defined (STM8AF52Ax) || \ 02691 defined (STM8AF62Ax) || defined (STM8AF626x) 02692 #define TIM4 ((TIM4_TypeDef *) TIM4_BaseAddress) 02693 #endif /* (STM8S208) ||(STM8S207) || (STM8S103) || (STM8S001) || (STM8S105) || (STM8AF52Ax) || (STM8AF62Ax) || (STM8AF626x)*/ 02694 02695 #if defined (STM8S903) || defined (STM8AF622x) 02696 #define TIM5 ((TIM5_TypeDef *) TIM5_BaseAddress) 02697 #define TIM6 ((TIM6_TypeDef *) TIM6_BaseAddress) 02698 #endif /* (STM8S903) || (STM8AF622x) */ 02699 02700 #define ITC ((ITC_TypeDef *) ITC_BaseAddress) 02701 02702 #define CFG ((CFG_TypeDef *) CFG_BaseAddress) 02703 02704 #define DM ((DM_TypeDef *) DM_BaseAddress) 02705 02706 02707 #ifdef USE_STDPERIPH_DRIVER 02708 #include "stm8s_conf.h" 02709 #endif 02710 02711 /* Exported macro --------------------------------------------------------------*/ 02712 02713 /*============================== Interrupts ====================================*/ 02714 #ifdef _RAISONANCE_ 02715 #include <intrins.h> 02716 #define enableInterrupts() _rim_() /* enable interrupts */ 02717 #define disableInterrupts() _sim_() /* disable interrupts */ 02718 #define rim() _rim_() /* enable interrupts */ 02719 #define sim() _sim_() /* disable interrupts */ 02720 #define nop() _nop_() /* No Operation */ 02721 #define trap() _trap_() /* Trap (soft IT) */ 02722 #define wfi() _wfi_() /* Wait For Interrupt */ 02723 #define halt() _halt_() /* Halt */ 02724 #elif defined(_COSMIC_) 02725 #define enableInterrupts() {_asm("rim\n");} /* enable interrupts */ 02726 #define disableInterrupts() {_asm("sim\n");} /* disable interrupts */ 02727 #define rim() {_asm("rim\n");} /* enable interrupts */ 02728 #define sim() {_asm("sim\n");} /* disable interrupts */ 02729 #define nop() {_asm("nop\n");} /* No Operation */ 02730 #define trap() {_asm("trap\n");} /* Trap (soft IT) */ 02731 #define wfi() {_asm("wfi\n");} /* Wait For Interrupt */ 02732 #define halt() {_asm("halt\n");} /* Halt */ 02733 #else /*_IAR_*/ 02734 #include <intrinsics.h> 02735 #define enableInterrupts() __enable_interrupt() /* enable interrupts */ 02736 #define disableInterrupts() __disable_interrupt() /* disable interrupts */ 02737 #define rim() __enable_interrupt() /* enable interrupts */ 02738 #define sim() __disable_interrupt() /* disable interrupts */ 02739 #define nop() __no_operation() /* No Operation */ 02740 #define trap() __trap() /* Trap (soft IT) */ 02741 #define wfi() __wait_for_interrupt() /* Wait For Interrupt */ 02742 #define halt() __halt() /* Halt */ 02743 #endif /*_RAISONANCE_*/ 02744 02745 /*============================== Interrupt vector Handling ========================*/ 02746 02747 #ifdef _COSMIC_ 02748 #define INTERRUPT_HANDLER(a,b) @far @interrupt void a(void) 02749 #define INTERRUPT_HANDLER_TRAP(a) void @far @interrupt a(void) 02750 #endif /* _COSMIC_ */ 02751 02752 #ifdef _RAISONANCE_ 02753 #define INTERRUPT_HANDLER(a,b) void a(void) interrupt b 02754 #define INTERRUPT_HANDLER_TRAP(a) void a(void) trap 02755 #endif /* _RAISONANCE_ */ 02756 02757 #ifdef _IAR_ 02758 #define STRINGVECTOR(x) #x 02759 #define VECTOR_ID(x) STRINGVECTOR( vector = (x) ) 02760 #define INTERRUPT_HANDLER( a, b ) \ 02761 _Pragma( VECTOR_ID( (b)+2 ) ) \ 02762 __interrupt void (a)( void ) 02763 #define INTERRUPT_HANDLER_TRAP(a) \ 02764 _Pragma( VECTOR_ID( 1 ) ) \ 02765 __interrupt void (a) (void) 02766 #endif /* _IAR_ */ 02767 02768 /*============================== Interrupt Handler declaration ========================*/ 02769 #ifdef _COSMIC_ 02770 #define INTERRUPT @far @interrupt 02771 #elif defined(_IAR_) 02772 #define INTERRUPT __interrupt 02773 #endif /* _COSMIC_ */ 02774 02775 /*============================== Handling bits ====================================*/ 02776 /*----------------------------------------------------------------------------- 02777 Method : I 02778 Description : Handle the bit from the character variables. 02779 Comments : The different parameters of commands are 02780 - VAR : Name of the character variable where the bit is located. 02781 - Place : Bit position in the variable (7 6 5 4 3 2 1 0) 02782 - Value : Can be 0 (reset bit) or not 0 (set bit) 02783 The "MskBit" command allows to select some bits in a source 02784 variables and copy it in a destination var (return the value). 02785 The "ValBit" command returns the value of a bit in a char 02786 variable: the bit is reset if it returns 0 else the bit is set. 02787 This method generates not an optimised code yet. 02788 -----------------------------------------------------------------------------*/ 02789 #define SetBit(VAR,Place) ( (VAR) |= (uint8_t)((uint8_t)1<<(uint8_t)(Place)) ) 02790 #define ClrBit(VAR,Place) ( (VAR) &= (uint8_t)((uint8_t)((uint8_t)1<<(uint8_t)(Place))^(uint8_t)255) ) 02791 02792 #define ChgBit(VAR,Place) ( (VAR) ^= (uint8_t)((uint8_t)1<<(uint8_t)(Place)) ) 02793 #define AffBit(VAR,Place,Value) ((Value) ? \ 02794 ((VAR) |= ((uint8_t)1<<(Place))) : \ 02795 ((VAR) &= (((uint8_t)1<<(Place))^(uint8_t)255))) 02796 #define MskBit(Dest,Msk,Src) ( (Dest) = ((Msk) & (Src)) | ((~(Msk)) & (Dest)) ) 02797 02798 #define ValBit(VAR,Place) ((uint8_t)(VAR) & (uint8_t)((uint8_t)1<<(uint8_t)(Place))) 02799 02800 #define BYTE_0(n) ((uint8_t)((n) & (uint8_t)0xFF)) /*!< Returns the low byte of the 32-bit value */ 02801 #define BYTE_1(n) ((uint8_t)(BYTE_0((n) >> (uint8_t)8))) /*!< Returns the second byte of the 32-bit value */ 02802 #define BYTE_2(n) ((uint8_t)(BYTE_0((n) >> (uint8_t)16))) /*!< Returns the third byte of the 32-bit value */ 02803 #define BYTE_3(n) ((uint8_t)(BYTE_0((n) >> (uint8_t)24))) /*!< Returns the high byte of the 32-bit value */ 02804 02805 /*============================== Assert Macros ====================================*/ 02806 #define IS_STATE_VALUE_OK(SensitivityValue) \ 02807 (((SensitivityValue) == ENABLE) || \ 02808 ((SensitivityValue) == DISABLE)) 02809 02810 /*----------------------------------------------------------------------------- 02811 Method : II 02812 Description : Handle directly the bit. 02813 Comments : The idea is to handle directly with the bit name. For that, it is 02814 necessary to have RAM area descriptions (example: HW register...) 02815 and the following command line for each area. 02816 This method generates the most optimized code. 02817 -----------------------------------------------------------------------------*/ 02818 02819 #define AREA 0x00 /* The area of bits begins at address 0x10. */ 02820 02821 #define BitClr(BIT) ( *((unsigned char *) (AREA+(BIT)/8)) &= (~(1<<(7-(BIT)%8))) ) 02822 #define BitSet(BIT) ( *((unsigned char *) (AREA+(BIT)/8)) |= (1<<(7-(BIT)%8)) ) 02823 #define BitVal(BIT) ( *((unsigned char *) (AREA+(BIT)/8)) & (1<<(7-(BIT)%8)) ) 02824 02825 /* Exported functions ------------------------------------------------------- */ 02826 02827 #endif /* __STM8S_H */ 02828 02829 /** 02830 * @} 02831 */ 02832 02833 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/