STM8S/A Standard Peripherals Drivers: stm8s_tim1.c Source File

STM8S/A

stm8s_tim1.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_tim1.c
00004   * @author  MCD Application Team
00005   * @version V2.3.0
00006   * @date    16-June-2017
00007   * @brief   This file contains all the functions for the TIM1 peripheral.
00008    ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
00012   *
00013   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00014   * You may not use this file except in compliance with the License.
00015   * You may obtain a copy of the License at:
00016   *
00017   *        http://www.st.com/software_license_agreement_liberty_v2
00018   *
00019   * Unless required by applicable law or agreed to in writing, software 
00020   * distributed under the License is distributed on an "AS IS" BASIS, 
00021   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00022   * See the License for the specific language governing permissions and
00023   * limitations under the License.
00024   *
00025   ******************************************************************************
00026   */
00027 
00028 /* Includes ------------------------------------------------------------------*/
00029 #include "stm8s_tim1.h"
00030 
00031 /** @addtogroup STM8S_StdPeriph_Driver
00032   * @{
00033   */
00034 /* Private typedef -----------------------------------------------------------*/
00035 /* Private define ------------------------------------------------------------*/
00036 /* Private macro -------------------------------------------------------------*/
00037 /* Private variables ---------------------------------------------------------*/
00038 /* Private function prototypes -----------------------------------------------*/
00039 static void TI1_Config(uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection,
00040                        uint8_t TIM1_ICFilter);
00041 static void TI2_Config(uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection,
00042                        uint8_t TIM1_ICFilter);
00043 static void TI3_Config(uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection,
00044                        uint8_t TIM1_ICFilter);
00045 static void TI4_Config(uint8_t TIM1_ICPolarity, uint8_t TIM1_ICSelection,
00046                        uint8_t TIM1_ICFilter);
00047 
00048 /**
00049   * @addtogroup TIM1_Public_Functions
00050   * @{
00051   */
00052 
00053 /**
00054   * @brief  Deinitializes the TIM1 peripheral registers to their default reset values.
00055   * @param  None
00056   * @retval None
00057   */
00058 void TIM1_DeInit(void)
00059 {
00060   TIM1->CR1  = TIM1_CR1_RESET_VALUE;
00061   TIM1->CR2  = TIM1_CR2_RESET_VALUE;
00062   TIM1->SMCR = TIM1_SMCR_RESET_VALUE;
00063   TIM1->ETR  = TIM1_ETR_RESET_VALUE;
00064   TIM1->IER  = TIM1_IER_RESET_VALUE;
00065   TIM1->SR2  = TIM1_SR2_RESET_VALUE;
00066   /* Disable channels */
00067   TIM1->CCER1 = TIM1_CCER1_RESET_VALUE;
00068   TIM1->CCER2 = TIM1_CCER2_RESET_VALUE;
00069   /* Configure channels as inputs: it is necessary if lock level is equal to 2 or 3 */
00070   TIM1->CCMR1 = 0x01;
00071   TIM1->CCMR2 = 0x01;
00072   TIM1->CCMR3 = 0x01;
00073   TIM1->CCMR4 = 0x01;
00074   /* Then reset channel registers: it also works if lock level is equal to 2 or 3 */
00075   TIM1->CCER1 = TIM1_CCER1_RESET_VALUE;
00076   TIM1->CCER2 = TIM1_CCER2_RESET_VALUE;
00077   TIM1->CCMR1 = TIM1_CCMR1_RESET_VALUE;
00078   TIM1->CCMR2 = TIM1_CCMR2_RESET_VALUE;
00079   TIM1->CCMR3 = TIM1_CCMR3_RESET_VALUE;
00080   TIM1->CCMR4 = TIM1_CCMR4_RESET_VALUE;
00081   TIM1->CNTRH = TIM1_CNTRH_RESET_VALUE;
00082   TIM1->CNTRL = TIM1_CNTRL_RESET_VALUE;
00083   TIM1->PSCRH = TIM1_PSCRH_RESET_VALUE;
00084   TIM1->PSCRL = TIM1_PSCRL_RESET_VALUE;
00085   TIM1->ARRH  = TIM1_ARRH_RESET_VALUE;
00086   TIM1->ARRL  = TIM1_ARRL_RESET_VALUE;
00087   TIM1->CCR1H = TIM1_CCR1H_RESET_VALUE;
00088   TIM1->CCR1L = TIM1_CCR1L_RESET_VALUE;
00089   TIM1->CCR2H = TIM1_CCR2H_RESET_VALUE;
00090   TIM1->CCR2L = TIM1_CCR2L_RESET_VALUE;
00091   TIM1->CCR3H = TIM1_CCR3H_RESET_VALUE;
00092   TIM1->CCR3L = TIM1_CCR3L_RESET_VALUE;
00093   TIM1->CCR4H = TIM1_CCR4H_RESET_VALUE;
00094   TIM1->CCR4L = TIM1_CCR4L_RESET_VALUE;
00095   TIM1->OISR  = TIM1_OISR_RESET_VALUE;
00096   TIM1->EGR   = 0x01; /* TIM1_EGR_UG */
00097   TIM1->DTR   = TIM1_DTR_RESET_VALUE;
00098   TIM1->BKR   = TIM1_BKR_RESET_VALUE;
00099   TIM1->RCR   = TIM1_RCR_RESET_VALUE;
00100   TIM1->SR1   = TIM1_SR1_RESET_VALUE;
00101 }
00102 
00103 /**
00104   * @brief  Initializes the TIM1 Time Base Unit according to the specified parameters.
00105   * @param  TIM1_Prescaler specifies the Prescaler value.
00106   * @param  TIM1_CounterMode specifies the counter mode  from @ref TIM1_CounterMode_TypeDef .
00107   * @param  TIM1_Period specifies the Period value.
00108   * @param  TIM1_RepetitionCounter specifies the Repetition counter value
00109   * @retval None
00110   */
00111 void TIM1_TimeBaseInit(uint16_t TIM1_Prescaler,
00112                        TIM1_CounterMode_TypeDef TIM1_CounterMode,
00113                        uint16_t TIM1_Period,
00114                        uint8_t TIM1_RepetitionCounter)
00115 {
00116   /* Check parameters */
00117   assert_param(IS_TIM1_COUNTER_MODE_OK(TIM1_CounterMode));
00118   
00119   /* Set the Autoreload value */
00120   TIM1->ARRH = (uint8_t)(TIM1_Period >> 8);
00121   TIM1->ARRL = (uint8_t)(TIM1_Period);
00122   
00123   /* Set the Prescaler value */
00124   TIM1->PSCRH = (uint8_t)(TIM1_Prescaler >> 8);
00125   TIM1->PSCRL = (uint8_t)(TIM1_Prescaler);
00126   
00127   /* Select the Counter Mode */
00128   TIM1->CR1 = (uint8_t)((uint8_t)(TIM1->CR1 & (uint8_t)(~(TIM1_CR1_CMS | TIM1_CR1_DIR)))
00129                         | (uint8_t)(TIM1_CounterMode));
00130   
00131   /* Set the Repetition Counter value */
00132   TIM1->RCR = TIM1_RepetitionCounter;
00133 }
00134 
00135 /**
00136   * @brief  Initializes the TIM1 Channel1 according to the specified parameters.
00137   * @param  TIM1_OCMode specifies the Output Compare mode from 
00138   *         @ref TIM1_OCMode_TypeDef.
00139   * @param  TIM1_OutputState specifies the Output State from 
00140   *         @ref TIM1_OutputState_TypeDef.
00141   * @param  TIM1_OutputNState specifies the Complementary Output State 
00142   *         from @ref TIM1_OutputNState_TypeDef.
00143   * @param  TIM1_Pulse specifies the Pulse width value.
00144   * @param  TIM1_OCPolarity specifies the Output Compare Polarity from 
00145   *         @ref TIM1_OCPolarity_TypeDef.
00146   * @param  TIM1_OCNPolarity specifies the Complementary Output Compare Polarity
00147   *         from @ref TIM1_OCNPolarity_TypeDef.
00148   * @param  TIM1_OCIdleState specifies the Output Compare Idle State from 
00149   *         @ref TIM1_OCIdleState_TypeDef.
00150   * @param  TIM1_OCNIdleState specifies the Complementary Output Compare Idle 
00151   *         State from @ref TIM1_OCIdleState_TypeDef.
00152   * @retval None
00153   */
00154 void TIM1_OC1Init(TIM1_OCMode_TypeDef TIM1_OCMode,
00155                   TIM1_OutputState_TypeDef TIM1_OutputState,
00156                   TIM1_OutputNState_TypeDef TIM1_OutputNState,
00157                   uint16_t TIM1_Pulse,
00158                   TIM1_OCPolarity_TypeDef TIM1_OCPolarity,
00159                   TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity,
00160                   TIM1_OCIdleState_TypeDef TIM1_OCIdleState,
00161                   TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState)
00162 {
00163   /* Check the parameters */
00164   assert_param(IS_TIM1_OC_MODE_OK(TIM1_OCMode));
00165   assert_param(IS_TIM1_OUTPUT_STATE_OK(TIM1_OutputState));
00166   assert_param(IS_TIM1_OUTPUTN_STATE_OK(TIM1_OutputNState));
00167   assert_param(IS_TIM1_OC_POLARITY_OK(TIM1_OCPolarity));
00168   assert_param(IS_TIM1_OCN_POLARITY_OK(TIM1_OCNPolarity));
00169   assert_param(IS_TIM1_OCIDLE_STATE_OK(TIM1_OCIdleState));
00170   assert_param(IS_TIM1_OCNIDLE_STATE_OK(TIM1_OCNIdleState));
00171   
00172   /* Disable the Channel 1: Reset the CCE Bit, Set the Output State , 
00173   the Output N State, the Output Polarity & the Output N Polarity*/
00174   TIM1->CCER1 &= (uint8_t)(~( TIM1_CCER1_CC1E | TIM1_CCER1_CC1NE 
00175                              | TIM1_CCER1_CC1P | TIM1_CCER1_CC1NP));
00176   /* Set the Output State & Set the Output N State & Set the Output Polarity &
00177   Set the Output N Polarity */
00178   TIM1->CCER1 |= (uint8_t)((uint8_t)((uint8_t)(TIM1_OutputState & TIM1_CCER1_CC1E)
00179                                      | (uint8_t)(TIM1_OutputNState & TIM1_CCER1_CC1NE))
00180                            | (uint8_t)( (uint8_t)(TIM1_OCPolarity  & TIM1_CCER1_CC1P)
00181                                        | (uint8_t)(TIM1_OCNPolarity & TIM1_CCER1_CC1NP)));
00182   
00183   /* Reset the Output Compare Bits & Set the Output Compare Mode */
00184   TIM1->CCMR1 = (uint8_t)((uint8_t)(TIM1->CCMR1 & (uint8_t)(~TIM1_CCMR_OCM)) | 
00185                           (uint8_t)TIM1_OCMode);
00186   
00187   /* Reset the Output Idle state & the Output N Idle state bits */
00188   TIM1->OISR &= (uint8_t)(~(TIM1_OISR_OIS1 | TIM1_OISR_OIS1N));
00189   /* Set the Output Idle state & the Output N Idle state configuration */
00190   TIM1->OISR |= (uint8_t)((uint8_t)( TIM1_OCIdleState & TIM1_OISR_OIS1 ) | 
00191                           (uint8_t)( TIM1_OCNIdleState & TIM1_OISR_OIS1N ));
00192   
00193   /* Set the Pulse value */
00194   TIM1->CCR1H = (uint8_t)(TIM1_Pulse >> 8);
00195   TIM1->CCR1L = (uint8_t)(TIM1_Pulse);
00196 }
00197 
00198 /**
00199   * @brief  Initializes the TIM1 Channel2 according to the specified parameters.
00200   * @param  TIM1_OCMode specifies the Output Compare mode from
00201   *         @ref TIM1_OCMode_TypeDef.
00202   * @param  TIM1_OutputState specifies the Output State from 
00203   *         @ref TIM1_OutputState_TypeDef.
00204   * @param  TIM1_OutputNState specifies the Complementary Output State from 
00205   *         @ref TIM1_OutputNState_TypeDef.
00206   * @param  TIM1_Pulse specifies the Pulse width value.
00207   * @param  TIM1_OCPolarity specifies the Output Compare Polarity from 
00208   *         @ref TIM1_OCPolarity_TypeDef.
00209   * @param  TIM1_OCNPolarity specifies the Complementary Output Compare Polarity
00210   *         from @ref TIM1_OCNPolarity_TypeDef.
00211   * @param  TIM1_OCIdleState specifies the Output Compare Idle State from 
00212   *         @ref TIM1_OCIdleState_TypeDef.
00213   * @param  TIM1_OCNIdleState specifies the Complementary Output Compare Idle 
00214   *         State from @ref TIM1_OCIdleState_TypeDef.
00215   * @retval None
00216   */
00217 void TIM1_OC2Init(TIM1_OCMode_TypeDef TIM1_OCMode,
00218                   TIM1_OutputState_TypeDef TIM1_OutputState,
00219                   TIM1_OutputNState_TypeDef TIM1_OutputNState,
00220                   uint16_t TIM1_Pulse,
00221                   TIM1_OCPolarity_TypeDef TIM1_OCPolarity,
00222                   TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity,
00223                   TIM1_OCIdleState_TypeDef TIM1_OCIdleState,
00224                   TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState)
00225 {
00226   /* Check the parameters */
00227   assert_param(IS_TIM1_OC_MODE_OK(TIM1_OCMode));
00228   assert_param(IS_TIM1_OUTPUT_STATE_OK(TIM1_OutputState));
00229   assert_param(IS_TIM1_OUTPUTN_STATE_OK(TIM1_OutputNState));
00230   assert_param(IS_TIM1_OC_POLARITY_OK(TIM1_OCPolarity));
00231   assert_param(IS_TIM1_OCN_POLARITY_OK(TIM1_OCNPolarity));
00232   assert_param(IS_TIM1_OCIDLE_STATE_OK(TIM1_OCIdleState));
00233   assert_param(IS_TIM1_OCNIDLE_STATE_OK(TIM1_OCNIdleState));
00234   
00235   /* Disable the Channel 1: Reset the CCE Bit, Set the Output State , 
00236   the Output N State, the Output Polarity & the Output N Polarity*/
00237   TIM1->CCER1 &= (uint8_t)(~( TIM1_CCER1_CC2E | TIM1_CCER1_CC2NE | 
00238                              TIM1_CCER1_CC2P | TIM1_CCER1_CC2NP));
00239   
00240   /* Set the Output State & Set the Output N State & Set the Output Polarity &
00241   Set the Output N Polarity */
00242   TIM1->CCER1 |= (uint8_t)((uint8_t)((uint8_t)(TIM1_OutputState & TIM1_CCER1_CC2E  ) | 
00243                                      (uint8_t)(TIM1_OutputNState & TIM1_CCER1_CC2NE )) | 
00244                            (uint8_t)((uint8_t)(TIM1_OCPolarity  & TIM1_CCER1_CC2P  ) | 
00245                                      (uint8_t)(TIM1_OCNPolarity & TIM1_CCER1_CC2NP )));
00246   
00247   /* Reset the Output Compare Bits & Set the Output Compare Mode */
00248   TIM1->CCMR2 = (uint8_t)((uint8_t)(TIM1->CCMR2 & (uint8_t)(~TIM1_CCMR_OCM)) | 
00249                           (uint8_t)TIM1_OCMode);
00250   
00251   /* Reset the Output Idle state & the Output N Idle state bits */
00252   TIM1->OISR &= (uint8_t)(~(TIM1_OISR_OIS2 | TIM1_OISR_OIS2N));
00253   /* Set the Output Idle state & the Output N Idle state configuration */
00254   TIM1->OISR |= (uint8_t)((uint8_t)(TIM1_OISR_OIS2 & TIM1_OCIdleState) | 
00255                           (uint8_t)(TIM1_OISR_OIS2N & TIM1_OCNIdleState));
00256   
00257   /* Set the Pulse value */
00258   TIM1->CCR2H = (uint8_t)(TIM1_Pulse >> 8);
00259   TIM1->CCR2L = (uint8_t)(TIM1_Pulse);
00260 }
00261 
00262 /**
00263   * @brief  Initializes the TIM1 Channel3 according to the specified parameters.
00264   * @param  TIM1_OCMode specifies the Output Compare mode  from 
00265   *         @ref TIM1_OCMode_TypeDef.
00266   * @param  TIM1_OutputState specifies the Output State  
00267   *         from @ref TIM1_OutputState_TypeDef.
00268   * @param  TIM1_OutputNState specifies the Complementary Output State
00269   *         from @ref TIM1_OutputNState_TypeDef.
00270   * @param  TIM1_Pulse specifies the Pulse width value.
00271   * @param  TIM1_OCPolarity specifies the Output Compare Polarity  from 
00272   *         @ref TIM1_OCPolarity_TypeDef.
00273   * @param  TIM1_OCNPolarity specifies the Complementary  Output Compare 
00274   *         Polarity from @ref TIM1_OCNPolarity_TypeDef.
00275   * @param  TIM1_OCIdleState specifies the Output Compare Idle State
00276   *         from @ref TIM1_OCIdleState_TypeDef.
00277   * @param  TIM1_OCNIdleState specifies the Complementary Output Compare 
00278   *         Idle State  from @ref TIM1_OCIdleState_TypeDef.
00279   * @retval None
00280   */
00281 void TIM1_OC3Init(TIM1_OCMode_TypeDef TIM1_OCMode,
00282                   TIM1_OutputState_TypeDef TIM1_OutputState,
00283                   TIM1_OutputNState_TypeDef TIM1_OutputNState,
00284                   uint16_t TIM1_Pulse,
00285                   TIM1_OCPolarity_TypeDef TIM1_OCPolarity,
00286                   TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity,
00287                   TIM1_OCIdleState_TypeDef TIM1_OCIdleState,
00288                   TIM1_OCNIdleState_TypeDef TIM1_OCNIdleState)
00289 {
00290   /* Check the parameters */
00291   assert_param(IS_TIM1_OC_MODE_OK(TIM1_OCMode));
00292   assert_param(IS_TIM1_OUTPUT_STATE_OK(TIM1_OutputState));
00293   assert_param(IS_TIM1_OUTPUTN_STATE_OK(TIM1_OutputNState));
00294   assert_param(IS_TIM1_OC_POLARITY_OK(TIM1_OCPolarity));
00295   assert_param(IS_TIM1_OCN_POLARITY_OK(TIM1_OCNPolarity));
00296   assert_param(IS_TIM1_OCIDLE_STATE_OK(TIM1_OCIdleState));
00297   assert_param(IS_TIM1_OCNIDLE_STATE_OK(TIM1_OCNIdleState));
00298   
00299   /* Disable the Channel 1: Reset the CCE Bit, Set the Output State , 
00300   the Output N State, the Output Polarity & the Output N Polarity*/
00301   TIM1->CCER2 &= (uint8_t)(~( TIM1_CCER2_CC3E | TIM1_CCER2_CC3NE | 
00302                              TIM1_CCER2_CC3P | TIM1_CCER2_CC3NP));
00303   /* Set the Output State & Set the Output N State & Set the Output Polarity &
00304   Set the Output N Polarity */
00305   TIM1->CCER2 |= (uint8_t)((uint8_t)((uint8_t)(TIM1_OutputState  & TIM1_CCER2_CC3E   ) |
00306                                      (uint8_t)(TIM1_OutputNState & TIM1_CCER2_CC3NE  )) | 
00307                            (uint8_t)((uint8_t)(TIM1_OCPolarity   & TIM1_CCER2_CC3P   ) | 
00308                                      (uint8_t)(TIM1_OCNPolarity  & TIM1_CCER2_CC3NP  )));
00309   
00310   /* Reset the Output Compare Bits & Set the Output Compare Mode */
00311   TIM1->CCMR3 = (uint8_t)((uint8_t)(TIM1->CCMR3 & (uint8_t)(~TIM1_CCMR_OCM)) | 
00312                           (uint8_t)TIM1_OCMode);
00313   
00314   /* Reset the Output Idle state & the Output N Idle state bits */
00315   TIM1->OISR &= (uint8_t)(~(TIM1_OISR_OIS3 | TIM1_OISR_OIS3N));
00316   /* Set the Output Idle state & the Output N Idle state configuration */
00317   TIM1->OISR |= (uint8_t)((uint8_t)(TIM1_OISR_OIS3 & TIM1_OCIdleState) | 
00318                           (uint8_t)(TIM1_OISR_OIS3N & TIM1_OCNIdleState));
00319   
00320   /* Set the Pulse value */
00321   TIM1->CCR3H = (uint8_t)(TIM1_Pulse >> 8);
00322   TIM1->CCR3L = (uint8_t)(TIM1_Pulse);
00323 }
00324 
00325 /**
00326   * @brief  Initializes the TIM1 Channel4 according to the specified parameters.
00327   * @param  TIM1_OCMode specifies the Output Compare mode  from 
00328   *         @ref TIM1_OCMode_TypeDef.
00329   * @param  TIM1_OutputState specifies the Output State
00330   *         from @ref TIM1_OutputState_TypeDef.
00331   * @param  TIM1_Pulse specifies the Pulse width  value.
00332   * @param  TIM1_OCPolarity specifies the Output Compare Polarity
00333   *         from @ref TIM1_OCPolarity_TypeDef.
00334   * @param  TIM1_OCIdleState specifies the Output Compare Idle State
00335   *         from @ref TIM1_OCIdleState_TypeDef.
00336   * @retval None
00337   */
00338 void TIM1_OC4Init(TIM1_OCMode_TypeDef TIM1_OCMode,
00339                   TIM1_OutputState_TypeDef TIM1_OutputState,
00340                   uint16_t TIM1_Pulse,
00341                   TIM1_OCPolarity_TypeDef TIM1_OCPolarity,
00342                   TIM1_OCIdleState_TypeDef TIM1_OCIdleState)
00343 {
00344   /* Check the parameters */
00345   assert_param(IS_TIM1_OC_MODE_OK(TIM1_OCMode));
00346   assert_param(IS_TIM1_OUTPUT_STATE_OK(TIM1_OutputState));
00347   assert_param(IS_TIM1_OC_POLARITY_OK(TIM1_OCPolarity));
00348   assert_param(IS_TIM1_OCIDLE_STATE_OK(TIM1_OCIdleState));
00349   
00350   /* Disable the Channel 4: Reset the CCE Bit */
00351   TIM1->CCER2 &= (uint8_t)(~(TIM1_CCER2_CC4E | TIM1_CCER2_CC4P));
00352   /* Set the Output State  &  the Output Polarity */
00353   TIM1->CCER2 |= (uint8_t)((uint8_t)(TIM1_OutputState & TIM1_CCER2_CC4E ) |  
00354                            (uint8_t)(TIM1_OCPolarity  & TIM1_CCER2_CC4P ));
00355   
00356   /* Reset the Output Compare Bit  and Set the Output Compare Mode */
00357   TIM1->CCMR4 = (uint8_t)((uint8_t)(TIM1->CCMR4 & (uint8_t)(~TIM1_CCMR_OCM)) | 
00358                           TIM1_OCMode);
00359   
00360   /* Set the Output Idle state */
00361   if (TIM1_OCIdleState != TIM1_OCIDLESTATE_RESET)
00362   {
00363     TIM1->OISR |= (uint8_t)(~TIM1_CCER2_CC4P);
00364   }
00365   else
00366   {
00367     TIM1->OISR &= (uint8_t)(~TIM1_OISR_OIS4);
00368   }
00369   
00370   /* Set the Pulse value */
00371   TIM1->CCR4H = (uint8_t)(TIM1_Pulse >> 8);
00372   TIM1->CCR4L = (uint8_t)(TIM1_Pulse);
00373 }
00374 
00375 /**
00376   * @brief  Configures the Break feature, dead time, Lock level, the OSSI,
00377   *         and the AOE(automatic output enable).
00378   * @param  TIM1_OSSIState specifies the OSSIS State from @ref TIM1_OSSIState_TypeDef.
00379   * @param  TIM1_LockLevel specifies the lock level from @ref TIM1_LockLevel_TypeDef.
00380   * @param  TIM1_DeadTime specifies the dead time value.
00381   * @param  TIM1_Break specifies the Break state @ref TIM1_BreakState_TypeDef.
00382   * @param  TIM1_BreakPolarity specifies the Break polarity from 
00383   *         @ref TIM1_BreakPolarity_TypeDef.
00384   * @param  TIM1_AutomaticOutput specifies the Automatic Output configuration 
00385   *         from @ref TIM1_AutomaticOutput_TypeDef.
00386   * @retval None
00387   */
00388 void TIM1_BDTRConfig(TIM1_OSSIState_TypeDef TIM1_OSSIState,
00389                      TIM1_LockLevel_TypeDef TIM1_LockLevel,
00390                      uint8_t TIM1_DeadTime,
00391                      TIM1_BreakState_TypeDef TIM1_Break,
00392                      TIM1_BreakPolarity_TypeDef TIM1_BreakPolarity,
00393                      TIM1_AutomaticOutput_TypeDef TIM1_AutomaticOutput)
00394 {
00395   /* Check the parameters */
00396   assert_param(IS_TIM1_OSSI_STATE_OK(TIM1_OSSIState));
00397   assert_param(IS_TIM1_LOCK_LEVEL_OK(TIM1_LockLevel));
00398   assert_param(IS_TIM1_BREAK_STATE_OK(TIM1_Break));
00399   assert_param(IS_TIM1_BREAK_POLARITY_OK(TIM1_BreakPolarity));
00400   assert_param(IS_TIM1_AUTOMATIC_OUTPUT_STATE_OK(TIM1_AutomaticOutput));
00401   
00402   TIM1->DTR = (uint8_t)(TIM1_DeadTime);
00403   /* Set the Lock level, the Break enable Bit and the Polarity, the OSSI State,
00404   the dead time value  and the Automatic Output Enable Bit */
00405   
00406   TIM1->BKR  =  (uint8_t)((uint8_t)(TIM1_OSSIState | (uint8_t)TIM1_LockLevel)  | 
00407                           (uint8_t)((uint8_t)(TIM1_Break | (uint8_t)TIM1_BreakPolarity)  | 
00408                           (uint8_t)TIM1_AutomaticOutput));
00409 }
00410 
00411 /**
00412   * @brief  Initializes the TIM1 peripheral according to the specified parameters.
00413   * @param  TIM1_Channel specifies the input capture channel from TIM1_Channel_TypeDef.
00414   * @param  TIM1_ICPolarity specifies the Input capture polarity from  
00415   *         TIM1_ICPolarity_TypeDef .
00416   * @param  TIM1_ICSelection specifies the Input capture source selection from 
00417   *         TIM1_ICSelection_TypeDef.
00418   * @param  TIM1_ICPrescaler specifies the Input capture Prescaler from
00419   *         TIM1_ICPSC_TypeDef.
00420   * @param  TIM1_ICFilter specifies the Input capture filter value.
00421   * @retval None
00422   */
00423 void TIM1_ICInit(TIM1_Channel_TypeDef TIM1_Channel,
00424                  TIM1_ICPolarity_TypeDef TIM1_ICPolarity,
00425                  TIM1_ICSelection_TypeDef TIM1_ICSelection,
00426                  TIM1_ICPSC_TypeDef TIM1_ICPrescaler,
00427                  uint8_t TIM1_ICFilter)
00428 {
00429   /* Check the parameters */
00430   assert_param(IS_TIM1_CHANNEL_OK(TIM1_Channel));
00431   assert_param(IS_TIM1_IC_POLARITY_OK(TIM1_ICPolarity));
00432   assert_param(IS_TIM1_IC_SELECTION_OK(TIM1_ICSelection));
00433   assert_param(IS_TIM1_IC_PRESCALER_OK(TIM1_ICPrescaler));
00434   assert_param(IS_TIM1_IC_FILTER_OK(TIM1_ICFilter));
00435   
00436   if (TIM1_Channel == TIM1_CHANNEL_1)
00437   {
00438     /* TI1 Configuration */
00439     TI1_Config((uint8_t)TIM1_ICPolarity,
00440                (uint8_t)TIM1_ICSelection,
00441                (uint8_t)TIM1_ICFilter);
00442     /* Set the Input Capture Prescaler value */
00443     TIM1_SetIC1Prescaler(TIM1_ICPrescaler);
00444   }
00445   else if (TIM1_Channel == TIM1_CHANNEL_2)
00446   {
00447     /* TI2 Configuration */
00448     TI2_Config((uint8_t)TIM1_ICPolarity,
00449                (uint8_t)TIM1_ICSelection,
00450                (uint8_t)TIM1_ICFilter);
00451     /* Set the Input Capture Prescaler value */
00452     TIM1_SetIC2Prescaler(TIM1_ICPrescaler);
00453   }
00454   else if (TIM1_Channel == TIM1_CHANNEL_3)
00455   {
00456     /* TI3 Configuration */
00457     TI3_Config((uint8_t)TIM1_ICPolarity,
00458                (uint8_t)TIM1_ICSelection,
00459                (uint8_t)TIM1_ICFilter);
00460     /* Set the Input Capture Prescaler value */
00461     TIM1_SetIC3Prescaler(TIM1_ICPrescaler);
00462   }
00463   else
00464   {
00465     /* TI4 Configuration */
00466     TI4_Config((uint8_t)TIM1_ICPolarity,
00467                (uint8_t)TIM1_ICSelection,
00468                (uint8_t)TIM1_ICFilter);
00469     /* Set the Input Capture Prescaler value */
00470     TIM1_SetIC4Prescaler(TIM1_ICPrescaler);
00471   }
00472 }
00473 
00474 /**
00475   * @brief  Configures the TIM1 peripheral in PWM Input Mode according to the 
00476   *         specified parameters.
00477   * @param  TIM1_Channel specifies the input capture channel from 
00478   *         @ref TIM1_Channel_TypeDef.
00479   * @param  TIM1_ICPolarity specifies the Input capture polarity from  
00480   *         @ref TIM1_ICPolarity_TypeDef .
00481   * @param  TIM1_ICSelection specifies the Input capture source selection  from
00482   *         @ref TIM1_ICSelection_TypeDef.
00483   * @param  TIM1_ICPrescaler specifies the Input capture Prescaler from  
00484   *         @ref TIM1_ICPSC_TypeDef.
00485   * @param  TIM1_ICFilter specifies the Input capture filter value.
00486   * @retval None
00487   */
00488 void TIM1_PWMIConfig(TIM1_Channel_TypeDef TIM1_Channel,
00489                      TIM1_ICPolarity_TypeDef TIM1_ICPolarity,
00490                      TIM1_ICSelection_TypeDef TIM1_ICSelection,
00491                      TIM1_ICPSC_TypeDef TIM1_ICPrescaler,
00492                      uint8_t TIM1_ICFilter)
00493 {
00494   uint8_t icpolarity = TIM1_ICPOLARITY_RISING;
00495   uint8_t icselection = TIM1_ICSELECTION_DIRECTTI;
00496   
00497   /* Check the parameters */
00498   assert_param(IS_TIM1_PWMI_CHANNEL_OK(TIM1_Channel));
00499   assert_param(IS_TIM1_IC_POLARITY_OK(TIM1_ICPolarity));
00500   assert_param(IS_TIM1_IC_SELECTION_OK(TIM1_ICSelection));
00501   assert_param(IS_TIM1_IC_PRESCALER_OK(TIM1_ICPrescaler));
00502   
00503   /* Select the Opposite Input Polarity */
00504   if (TIM1_ICPolarity != TIM1_ICPOLARITY_FALLING)
00505   {
00506     icpolarity = TIM1_ICPOLARITY_FALLING;
00507   }
00508   else
00509   {
00510     icpolarity = TIM1_ICPOLARITY_RISING;
00511   }
00512   
00513   /* Select the Opposite Input */
00514   if (TIM1_ICSelection == TIM1_ICSELECTION_DIRECTTI)
00515   {
00516     icselection = TIM1_ICSELECTION_INDIRECTTI;
00517   }
00518   else
00519   {
00520     icselection = TIM1_ICSELECTION_DIRECTTI;
00521   }
00522   
00523   if (TIM1_Channel == TIM1_CHANNEL_1)
00524   {
00525     /* TI1 Configuration */
00526     TI1_Config((uint8_t)TIM1_ICPolarity, (uint8_t)TIM1_ICSelection,
00527                (uint8_t)TIM1_ICFilter);
00528     
00529     /* Set the Input Capture Prescaler value */
00530     TIM1_SetIC1Prescaler(TIM1_ICPrescaler);
00531     
00532     /* TI2 Configuration */
00533     TI2_Config(icpolarity, icselection, TIM1_ICFilter);
00534     
00535     /* Set the Input Capture Prescaler value */
00536     TIM1_SetIC2Prescaler(TIM1_ICPrescaler);
00537   }
00538   else
00539   {
00540     /* TI2 Configuration */
00541     TI2_Config((uint8_t)TIM1_ICPolarity, (uint8_t)TIM1_ICSelection,
00542                (uint8_t)TIM1_ICFilter);
00543     
00544     /* Set the Input Capture Prescaler value */
00545     TIM1_SetIC2Prescaler(TIM1_ICPrescaler);
00546     
00547     /* TI1 Configuration */
00548     TI1_Config(icpolarity, icselection, TIM1_ICFilter);
00549     
00550     /* Set the Input Capture Prescaler value */
00551     TIM1_SetIC1Prescaler(TIM1_ICPrescaler);
00552   }
00553 }
00554 
00555 /**
00556   * @brief  Enables or disables the TIM1 peripheral.
00557   * @param  NewState new state of the TIM1 peripheral.
00558   *         This parameter can be ENABLE or DISABLE.
00559   * @retval None
00560   */
00561 void TIM1_Cmd(FunctionalState NewState)
00562 {
00563   /* Check the parameters */
00564   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00565   
00566   /* set or Reset the CEN Bit */
00567   if (NewState != DISABLE)
00568   {
00569     TIM1->CR1 |= TIM1_CR1_CEN;
00570   }
00571   else
00572   {
00573     TIM1->CR1 &= (uint8_t)(~TIM1_CR1_CEN);
00574   }
00575 }
00576 
00577 /**
00578   * @brief  Enables or disables the TIM1 peripheral Main Outputs.
00579   * @param  NewState new state of the TIM1 peripheral.
00580   *         This parameter can be ENABLE or DISABLE.
00581   * @retval None
00582   */
00583 void TIM1_CtrlPWMOutputs(FunctionalState NewState)
00584 {
00585   /* Check the parameters */
00586   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00587   
00588   /* Set or Reset the MOE Bit */
00589   
00590   if (NewState != DISABLE)
00591   {
00592     TIM1->BKR |= TIM1_BKR_MOE;
00593   }
00594   else
00595   {
00596     TIM1->BKR &= (uint8_t)(~TIM1_BKR_MOE);
00597   }
00598 }
00599 
00600 /**
00601   * @brief  Enables or disables the specified TIM1 interrupts.
00602   * @param  NewState new state of the TIM1 peripheral.
00603   *         This parameter can be: ENABLE or DISABLE.
00604   * @param  TIM1_IT specifies the TIM1 interrupts sources to be enabled or disabled.
00605   *         This parameter can be any combination of the following values:
00606   *           - TIM1_IT_UPDATE: TIM1 update Interrupt source
00607   *           - TIM1_IT_CC1: TIM1 Capture Compare 1 Interrupt source
00608   *           - TIM1_IT_CC2: TIM1 Capture Compare 2 Interrupt source
00609   *           - TIM1_IT_CC3: TIM1 Capture Compare 3 Interrupt source
00610   *           - TIM1_IT_CC4: TIM1 Capture Compare 4 Interrupt source
00611   *           - TIM1_IT_CCUpdate: TIM1 Capture Compare Update Interrupt source
00612   *           - TIM1_IT_TRIGGER: TIM1 Trigger Interrupt source
00613   *           - TIM1_IT_BREAK: TIM1 Break Interrupt source
00614   * @param  NewState new state of the TIM1 peripheral.
00615   * @retval None
00616   */
00617 void TIM1_ITConfig(TIM1_IT_TypeDef  TIM1_IT, FunctionalState NewState)
00618 {
00619   /* Check the parameters */
00620   assert_param(IS_TIM1_IT_OK(TIM1_IT));
00621   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00622   
00623   if (NewState != DISABLE)
00624   {
00625     /* Enable the Interrupt sources */
00626     TIM1->IER |= (uint8_t)TIM1_IT;
00627   }
00628   else
00629   {
00630     /* Disable the Interrupt sources */
00631     TIM1->IER &= (uint8_t)(~(uint8_t)TIM1_IT);
00632   }
00633 }
00634 
00635 /**
00636   * @brief  Configures the TIM1 internal Clock.
00637   * @param  None
00638   * @retval None
00639   */
00640 void TIM1_InternalClockConfig(void)
00641 {
00642   /* Disable slave mode to clock the prescaler directly with the internal clock */
00643   TIM1->SMCR &= (uint8_t)(~TIM1_SMCR_SMS);
00644 }
00645 
00646 /**
00647   * @brief  Configures the TIM1 External clock Mode1.
00648   * @param  TIM1_ExtTRGPrescaler specifies the external Trigger Prescaler.
00649   *         This parameter can be one of the following values:
00650   *                       - TIM1_EXTTRGPSC_OFF
00651   *                       - TIM1_EXTTRGPSC_DIV2
00652   *                       - TIM1_EXTTRGPSC_DIV4
00653   *                       - TIM1_EXTTRGPSC_DIV8.
00654   * @param  TIM1_ExtTRGPolarity specifies the external Trigger Polarity.
00655   *         This parameter can be one of the following values:
00656   *                       - TIM1_EXTTRGPOLARITY_INVERTED
00657   *                       - TIM1_EXTTRGPOLARITY_NONINVERTED
00658   * @param  ExtTRGFilter specifies the External Trigger Filter.
00659   *         This parameter must be a value between 0x00 and 0x0F
00660   * @retval None
00661   */
00662 void TIM1_ETRClockMode1Config(TIM1_ExtTRGPSC_TypeDef TIM1_ExtTRGPrescaler,
00663                               TIM1_ExtTRGPolarity_TypeDef TIM1_ExtTRGPolarity,
00664                               uint8_t ExtTRGFilter)
00665 {
00666   /* Check the parameters */
00667   assert_param(IS_TIM1_EXT_PRESCALER_OK(TIM1_ExtTRGPrescaler));
00668   assert_param(IS_TIM1_EXT_POLARITY_OK(TIM1_ExtTRGPolarity));
00669   
00670   /* Configure the ETR Clock source */
00671   TIM1_ETRConfig(TIM1_ExtTRGPrescaler, TIM1_ExtTRGPolarity, ExtTRGFilter);
00672   
00673   /* Select the External clock mode1 & Select the Trigger selection : ETRF */
00674   TIM1->SMCR = (uint8_t)((uint8_t)(TIM1->SMCR & (uint8_t)(~(uint8_t)(TIM1_SMCR_SMS | TIM1_SMCR_TS )))
00675                          | (uint8_t)((uint8_t)TIM1_SLAVEMODE_EXTERNAL1 | TIM1_TS_ETRF ));
00676 }
00677 
00678 /**
00679   * @brief  Configures the TIM1 External clock Mode2.
00680   * @param  TIM1_ExtTRGPrescaler specifies the external Trigger Prescaler.
00681   *         This parameter can be one of the following values:
00682   *                       - TIM1_EXTTRGPSC_OFF
00683   *                       - TIM1_EXTTRGPSC_DIV2
00684   *                       - TIM1_EXTTRGPSC_DIV4
00685   *                       - TIM1_EXTTRGPSC_DIV8.
00686   * @param  TIM1_ExtTRGPolarity specifies the external Trigger Polarity.
00687   *         This parameter can be one of the following values:
00688   *                       - TIM1_EXTTRGPOLARITY_INVERTED
00689   *                       - TIM1_EXTTRGPOLARITY_NONINVERTED
00690   * @param  ExtTRGFilter specifies the External Trigger Filter.
00691   *         This parameter must be a value between 0x00 and 0x0F
00692   * @retval None
00693   */
00694 void TIM1_ETRClockMode2Config(TIM1_ExtTRGPSC_TypeDef TIM1_ExtTRGPrescaler,
00695                               TIM1_ExtTRGPolarity_TypeDef TIM1_ExtTRGPolarity,
00696                               uint8_t ExtTRGFilter)
00697 {
00698   /* Check the parameters */
00699   assert_param(IS_TIM1_EXT_PRESCALER_OK(TIM1_ExtTRGPrescaler));
00700   assert_param(IS_TIM1_EXT_POLARITY_OK(TIM1_ExtTRGPolarity));
00701   
00702   /* Configure the ETR Clock source */
00703   TIM1_ETRConfig(TIM1_ExtTRGPrescaler, TIM1_ExtTRGPolarity, ExtTRGFilter);
00704   
00705   /* Enable the External clock mode2 */
00706   TIM1->ETR |= TIM1_ETR_ECE;
00707 }
00708 
00709 /**
00710   * @brief  Configures the TIM1 External Trigger.
00711   * @param  TIM1_ExtTRGPrescaler specifies the external Trigger Prescaler.
00712   *         This parameter can be one of the following values:
00713   *                       - TIM1_EXTTRGPSC_OFF
00714   *                       - TIM1_EXTTRGPSC_DIV2
00715   *                       - TIM1_EXTTRGPSC_DIV4
00716   *                       - TIM1_EXTTRGPSC_DIV8.
00717   * @param  TIM1_ExtTRGPolarity specifies the external Trigger Polarity.
00718   *         This parameter can be one of the following values:
00719   *                       - TIM1_EXTTRGPOLARITY_INVERTED
00720   *                       - TIM1_EXTTRGPOLARITY_NONINVERTED
00721   * @param  ExtTRGFilter specifies the External Trigger Filter.
00722   *         This parameter must be a value between 0x00 and 0x0F
00723   * @retval None
00724   */
00725 void TIM1_ETRConfig(TIM1_ExtTRGPSC_TypeDef TIM1_ExtTRGPrescaler,
00726                     TIM1_ExtTRGPolarity_TypeDef TIM1_ExtTRGPolarity,
00727                     uint8_t ExtTRGFilter)
00728 {
00729   /* Check the parameters */
00730   assert_param(IS_TIM1_EXT_TRG_FILTER_OK(ExtTRGFilter));
00731   /* Set the Prescaler, the Filter value and the Polarity */
00732   TIM1->ETR |= (uint8_t)((uint8_t)(TIM1_ExtTRGPrescaler | (uint8_t)TIM1_ExtTRGPolarity )|
00733                          (uint8_t)ExtTRGFilter );
00734 }
00735 
00736 /**
00737   * @brief  Configures the TIM1 Trigger as External Clock.
00738   * @param  TIM1_TIxExternalCLKSource specifies Trigger source.
00739   *         This parameter can be one of the following values:
00740   *                     - TIM1_TIXEXTERNALCLK1SOURCE_TI1: TI1 Edge Detector
00741   *                     - TIM1_TIXEXTERNALCLK1SOURCE_TI2: Filtered TIM1 Input 1
00742   *                     - TIM1_TIXEXTERNALCLK1SOURCE_TI1ED: Filtered TIM1 Input 2
00743   * @param  TIM1_ICPolarity specifies the TIx Polarity.
00744   *         This parameter can be:
00745   *                     - TIM1_ICPOLARITY_RISING
00746   *                     - TIM1_ICPOLARITY_FALLING
00747   * @param  ICFilter specifies the filter value.
00748   *         This parameter must be a value between 0x00 and 0x0F
00749   * @retval None
00750   */
00751 void TIM1_TIxExternalClockConfig(TIM1_TIxExternalCLK1Source_TypeDef TIM1_TIxExternalCLKSource,
00752                                  TIM1_ICPolarity_TypeDef TIM1_ICPolarity,
00753                                  uint8_t ICFilter)
00754 {
00755   /* Check the parameters */
00756   assert_param(IS_TIM1_TIXCLK_SOURCE_OK(TIM1_TIxExternalCLKSource));
00757   assert_param(IS_TIM1_IC_POLARITY_OK(TIM1_ICPolarity));
00758   assert_param(IS_TIM1_IC_FILTER_OK(ICFilter));
00759   
00760   /* Configure the TIM1 Input Clock Source */
00761   if (TIM1_TIxExternalCLKSource == TIM1_TIXEXTERNALCLK1SOURCE_TI2)
00762   {
00763     TI2_Config((uint8_t)TIM1_ICPolarity, (uint8_t)TIM1_ICSELECTION_DIRECTTI, (uint8_t)ICFilter);
00764   }
00765   else
00766   {
00767     TI1_Config((uint8_t)TIM1_ICPolarity, (uint8_t)TIM1_ICSELECTION_DIRECTTI, (uint8_t)ICFilter);
00768   }
00769   
00770   /* Select the Trigger source */
00771   TIM1_SelectInputTrigger((TIM1_TS_TypeDef)TIM1_TIxExternalCLKSource);
00772   
00773   /* Select the External clock mode1 */
00774   TIM1->SMCR |= (uint8_t)(TIM1_SLAVEMODE_EXTERNAL1);
00775 }
00776 
00777 /**
00778   * @brief  Selects the TIM1 Input Trigger source.
00779   * @param   TIM1_InputTriggerSource specifies Input Trigger source.
00780   * This parameter can be one of the following values:
00781   *                       - TIM1_TS_TI1F_ED: TI1 Edge Detector
00782   *                       - TIM1_TS_TI1FP1: Filtered Timer Input 1
00783   *                       - TIM1_TS_TI2FP2: Filtered Timer Input 2
00784   *                       - TIM1_TS_ETRF: External Trigger input
00785   * @retval None
00786   */
00787 void TIM1_SelectInputTrigger(TIM1_TS_TypeDef TIM1_InputTriggerSource)
00788 {
00789   /* Check the parameters */
00790   assert_param(IS_TIM1_TRIGGER_SELECTION_OK(TIM1_InputTriggerSource));
00791   
00792   /* Select the Tgigger Source */
00793   TIM1->SMCR = (uint8_t)((uint8_t)(TIM1->SMCR & (uint8_t)(~TIM1_SMCR_TS)) | (uint8_t)TIM1_InputTriggerSource);
00794 }
00795 
00796 /**
00797   * @brief  Enables or Disables the TIM1 Update event.
00798   * @param   NewState new state of the TIM1 peripheral Preload register. This parameter can
00799   * be ENABLE or DISABLE.
00800   * @retval None
00801   */
00802 
00803 void TIM1_UpdateDisableConfig(FunctionalState NewState)
00804 {
00805   /* Check the parameters */
00806   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00807   
00808   /* Set or Reset the UDIS Bit */
00809   if (NewState != DISABLE)
00810   {
00811     TIM1->CR1 |= TIM1_CR1_UDIS;
00812   }
00813   else
00814   {
00815     TIM1->CR1 &= (uint8_t)(~TIM1_CR1_UDIS);
00816   }
00817 }
00818 
00819 /**
00820   * @brief  Selects the TIM1 Update Request Interrupt source.
00821   * @param   TIM1_UpdateSource specifies the Update source.
00822   * This parameter can be one of the following values
00823   *                       - TIM1_UPDATESOURCE_REGULAR
00824   *                       - TIM1_UPDATESOURCE_GLOBAL
00825   * @retval None
00826   */
00827 void TIM1_UpdateRequestConfig(TIM1_UpdateSource_TypeDef TIM1_UpdateSource)
00828 {
00829   /* Check the parameters */
00830   assert_param(IS_TIM1_UPDATE_SOURCE_OK(TIM1_UpdateSource));
00831   
00832   /* Set or Reset the URS Bit */
00833   if (TIM1_UpdateSource != TIM1_UPDATESOURCE_GLOBAL)
00834   {
00835     TIM1->CR1 |= TIM1_CR1_URS;
00836   }
00837   else
00838   {
00839     TIM1->CR1 &= (uint8_t)(~TIM1_CR1_URS);
00840   }
00841 }
00842 
00843 /**
00844   * @brief  Enables or Disables the TIM1�s Hall sensor interface.
00845   * @param   NewState new state of the TIM1 Hall sensor interface.This parameter can
00846   * be ENABLE or DISABLE.
00847   * @retval None
00848   */
00849 void TIM1_SelectHallSensor(FunctionalState NewState)
00850 {
00851   /* Check the parameters */
00852   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00853   
00854   /* Set or Reset the TI1S Bit */
00855   if (NewState != DISABLE)
00856   {
00857     TIM1->CR2 |= TIM1_CR2_TI1S;
00858   }
00859   else
00860   {
00861     TIM1->CR2 &= (uint8_t)(~TIM1_CR2_TI1S);
00862   }
00863 }
00864 
00865 /**
00866   * @brief  Selects the TIM1�s One Pulse Mode.
00867   * @param   TIM1_OPMode specifies the OPM Mode to be used.
00868   * This parameter can be one of the following values
00869   *                    - TIM1_OPMODE_SINGLE
00870   *                    - TIM1_OPMODE_REPETITIVE
00871   * @retval None
00872   */
00873 void TIM1_SelectOnePulseMode(TIM1_OPMode_TypeDef TIM1_OPMode)
00874 {
00875   /* Check the parameters */
00876   assert_param(IS_TIM1_OPM_MODE_OK(TIM1_OPMode));
00877   
00878   /* Set or Reset the OPM Bit */
00879   if (TIM1_OPMode != TIM1_OPMODE_REPETITIVE)
00880   {
00881     TIM1->CR1 |= TIM1_CR1_OPM;
00882   }
00883   else
00884   {
00885     TIM1->CR1 &= (uint8_t)(~TIM1_CR1_OPM);
00886   }
00887   
00888 }
00889 
00890 /**
00891   * @brief  Selects the TIM1 Trigger Output Mode.
00892   * @param   TIM1_TRGOSource specifies the Trigger Output source.
00893   * This parameter can be one of the following values
00894   *                       - TIM1_TRGOSOURCE_RESET
00895   *                       - TIM1_TRGOSOURCE_ENABLE
00896   *                       - TIM1_TRGOSOURCE_UPDATE
00897   *                       - TIM1_TRGOSource_OC1
00898   *                       - TIM1_TRGOSOURCE_OC1REF
00899   *                       - TIM1_TRGOSOURCE_OC2REF
00900   *                       - TIM1_TRGOSOURCE_OC3REF
00901   * @retval None
00902   */
00903 void TIM1_SelectOutputTrigger(TIM1_TRGOSource_TypeDef TIM1_TRGOSource)
00904 {
00905   /* Check the parameters */
00906   assert_param(IS_TIM1_TRGO_SOURCE_OK(TIM1_TRGOSource));
00907   
00908   /* Reset the MMS Bits & Select the TRGO source */
00909   TIM1->CR2 = (uint8_t)((uint8_t)(TIM1->CR2 & (uint8_t)(~TIM1_CR2_MMS)) | 
00910                         (uint8_t) TIM1_TRGOSource);
00911 }
00912 
00913 /**
00914   * @brief  Selects the TIM1 Slave Mode.
00915   * @param   TIM1_SlaveMode specifies the TIM1 Slave Mode.
00916   * This parameter can be one of the following values
00917   *                       - TIM1_SLAVEMODE_RESET
00918   *                       - TIM1_SLAVEMODE_GATED
00919   *                       - TIM1_SLAVEMODE_TRIGGER
00920   *                       - TIM1_SLAVEMODE_EXTERNAL1
00921   * @retval None
00922   */
00923 void TIM1_SelectSlaveMode(TIM1_SlaveMode_TypeDef TIM1_SlaveMode)
00924 {
00925   /* Check the parameters */
00926   assert_param(IS_TIM1_SLAVE_MODE_OK(TIM1_SlaveMode));
00927   
00928   /* Reset the SMS Bits */ /* Select the Slave Mode */
00929   TIM1->SMCR = (uint8_t)((uint8_t)(TIM1->SMCR & (uint8_t)(~TIM1_SMCR_SMS)) |
00930                          (uint8_t)TIM1_SlaveMode);
00931 }
00932 
00933 /**
00934   * @brief  Sets or Resets the TIM1 Master/Slave Mode.
00935   * @param   NewState new state of the synchronization between TIM1 and its slaves
00936   *  (through TRGO). This parameter can be ENABLE or DISABLE.
00937   * @retval None
00938   */
00939 void TIM1_SelectMasterSlaveMode(FunctionalState NewState)
00940 {
00941   /* Check the parameters */
00942   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00943   
00944   /* Set or Reset the MSM Bit */
00945   if (NewState != DISABLE)
00946   {
00947     TIM1->SMCR |= TIM1_SMCR_MSM;
00948   }
00949   else
00950   {
00951     TIM1->SMCR &= (uint8_t)(~TIM1_SMCR_MSM);
00952   }
00953 }
00954 
00955 /**
00956   * @brief  Configures the TIM1 Encoder Interface.
00957   * @param   TIM1_EncoderMode specifies the TIM1 Encoder Mode.
00958   * This parameter can be one of the following values
00959   * - TIM1_ENCODERMODE_TI1: Counter counts on TI1FP1 edge
00960         * depending on TI2FP2 level.
00961   * - TIM1_ENCODERMODE_TI2: Counter counts on TI2FP2 edge
00962   *     depending on TI1FP1 level.
00963   * - TIM1_ENCODERMODE_TI12: Counter counts on both TI1FP1 and
00964   * TI2FP2 edges depending on the level of the other input.
00965   * @param   TIM1_IC1Polarity specifies the IC1 Polarity.
00966   * This parameter can be one of the following values
00967   *                       - TIM1_ICPOLARITY_FALLING
00968   *                       - TIM1_ICPOLARITY_RISING
00969   * @param   TIM1_IC2Polarity specifies the IC2 Polarity.
00970   * This parameter can be one of the following values
00971   *                       - TIM1_ICPOLARITY_FALLING
00972   *                       - TIM1_ICPOLARITY_RISING
00973   * @retval None
00974   */
00975 void TIM1_EncoderInterfaceConfig(TIM1_EncoderMode_TypeDef TIM1_EncoderMode,
00976                                  TIM1_ICPolarity_TypeDef TIM1_IC1Polarity,
00977                                  TIM1_ICPolarity_TypeDef TIM1_IC2Polarity)
00978 {
00979   /* Check the parameters */
00980   assert_param(IS_TIM1_ENCODER_MODE_OK(TIM1_EncoderMode));
00981   assert_param(IS_TIM1_IC_POLARITY_OK(TIM1_IC1Polarity));
00982   assert_param(IS_TIM1_IC_POLARITY_OK(TIM1_IC2Polarity));
00983   
00984   /* Set the TI1 and the TI2 Polarities */
00985   if (TIM1_IC1Polarity != TIM1_ICPOLARITY_RISING)
00986   {
00987     TIM1->CCER1 |= TIM1_CCER1_CC1P;
00988   }
00989   else
00990   {
00991     TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC1P);
00992   }
00993   
00994   if (TIM1_IC2Polarity != TIM1_ICPOLARITY_RISING)
00995   {
00996     TIM1->CCER1 |= TIM1_CCER1_CC2P;
00997   }
00998   else
00999   {
01000     TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC2P);
01001   }
01002   /* Set the encoder Mode */
01003   TIM1->SMCR = (uint8_t)((uint8_t)(TIM1->SMCR & (uint8_t)(TIM1_SMCR_MSM | TIM1_SMCR_TS))
01004                          | (uint8_t) TIM1_EncoderMode);
01005   
01006   /* Select the Capture Compare 1 and the Capture Compare 2 as input */
01007   TIM1->CCMR1 = (uint8_t)((uint8_t)(TIM1->CCMR1 & (uint8_t)(~TIM1_CCMR_CCxS)) 
01008                           | (uint8_t) CCMR_TIxDirect_Set);
01009   TIM1->CCMR2 = (uint8_t)((uint8_t)(TIM1->CCMR2 & (uint8_t)(~TIM1_CCMR_CCxS))
01010                           | (uint8_t) CCMR_TIxDirect_Set);
01011 }
01012 
01013 /**
01014   * @brief  Configures the TIM1 Prescaler.
01015   * @param   Prescaler specifies the Prescaler Register value
01016   * This parameter must be a value between 0x0000 and 0xFFFF
01017   * @param   TIM1_PSCReloadMode specifies the TIM1 Prescaler Reload mode.
01018   * This parameter can be one of the following values
01019   * - TIM1_PSCRELOADMODE_IMMEDIATE: The Prescaler is loaded immediately.
01020   * - TIM1_PSCRELOADMODE_UPDATE: The Prescaler is loaded at the update event.
01021   * @retval None
01022   */
01023 void TIM1_PrescalerConfig(uint16_t Prescaler,
01024                           TIM1_PSCReloadMode_TypeDef TIM1_PSCReloadMode)
01025 {
01026   /* Check the parameters */
01027   assert_param(IS_TIM1_PRESCALER_RELOAD_OK(TIM1_PSCReloadMode));
01028   
01029   /* Set the Prescaler value */
01030   TIM1->PSCRH = (uint8_t)(Prescaler >> 8);
01031   TIM1->PSCRL = (uint8_t)(Prescaler);
01032   
01033   /* Set or reset the UG Bit */
01034   TIM1->EGR = (uint8_t)TIM1_PSCReloadMode;
01035 }
01036 
01037 /**
01038   * @brief  Specifies the TIM1 Counter Mode to be used.
01039   * @param   TIM1_CounterMode specifies the Counter Mode to be used
01040   * This parameter can be one of the following values:
01041   * - TIM1_COUNTERMODE_UP: TIM1 Up Counting Mode
01042   * - TIM1_COUNTERMODE_DOWN: TIM1 Down Counting Mode
01043   * - TIM1_COUNTERMODE_CENTERALIGNED1: TIM1 Center Aligned Mode1
01044   * - TIM1_CounterMode_CenterAligned2: TIM1 Center Aligned Mode2
01045   * - TIM1_COUNTERMODE_CENTERALIGNED3: TIM1 Center Aligned Mode3
01046   * @retval None
01047   */
01048 void TIM1_CounterModeConfig(TIM1_CounterMode_TypeDef TIM1_CounterMode)
01049 {
01050   /* Check the parameters */
01051   assert_param(IS_TIM1_COUNTER_MODE_OK(TIM1_CounterMode));
01052   
01053   
01054   /* Reset the CMS and DIR Bits & Set the Counter Mode */
01055   TIM1->CR1 = (uint8_t)((uint8_t)(TIM1->CR1 & (uint8_t)((uint8_t)(~TIM1_CR1_CMS) & (uint8_t)(~TIM1_CR1_DIR)))
01056                         | (uint8_t)TIM1_CounterMode);
01057 }
01058 
01059 /**
01060   * @brief  Forces the TIM1 Channel1 output waveform to active or inactive level.
01061   * @param   TIM1_ForcedAction specifies the forced Action to be set to the output waveform.
01062   * This parameter can be one of the following values:
01063   * - TIM1_FORCEDACTION_ACTIVE: Force active level on OC1REF
01064   * - TIM1_FORCEDACTION_INACTIVE: Force inactive level on OC1REF.
01065   * @retval None
01066   */
01067 void TIM1_ForcedOC1Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
01068 {
01069   /* Check the parameters */
01070   assert_param(IS_TIM1_FORCED_ACTION_OK(TIM1_ForcedAction));
01071   
01072   /* Reset the OCM Bits & Configure the Forced output Mode */
01073   TIM1->CCMR1 =  (uint8_t)((uint8_t)(TIM1->CCMR1 & (uint8_t)(~TIM1_CCMR_OCM))|
01074                            (uint8_t)TIM1_ForcedAction);
01075 }
01076 
01077 /**
01078   * @brief  Forces the TIM1 Channel2 output waveform to active or inactive level.
01079   * @param   TIM1_ForcedAction specifies the forced Action to be set to the output waveform.
01080   * This parameter can be one of the following values:
01081   * - TIM1_FORCEDACTION_ACTIVE: Force active level on OC2REF
01082   * - TIM1_FORCEDACTION_INACTIVE: Force inactive level on OC2REF.
01083   * @retval None
01084   */
01085 void TIM1_ForcedOC2Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
01086 {
01087   /* Check the parameters */
01088   assert_param(IS_TIM1_FORCED_ACTION_OK(TIM1_ForcedAction));
01089   
01090   /* Reset the OCM Bits & Configure the Forced output Mode */
01091   TIM1->CCMR2  =  (uint8_t)((uint8_t)(TIM1->CCMR2 & (uint8_t)(~TIM1_CCMR_OCM))
01092                             | (uint8_t)TIM1_ForcedAction);
01093 }
01094 
01095 /**
01096   * @brief  Forces the TIM1 Channel3 output waveform to active or inactive level.
01097   * @param   TIM1_ForcedAction specifies the forced Action to be set to the output waveform.
01098   * This parameter can be one of the following values:
01099   *                       - TIM1_FORCEDACTION_ACTIVE: Force active level on OC3REF
01100   *                       - TIM1_FORCEDACTION_INACTIVE: Force inactive level on
01101   *                         OC3REF.
01102   * @retval None
01103   */
01104 void TIM1_ForcedOC3Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
01105 {
01106   /* Check the parameters */
01107   assert_param(IS_TIM1_FORCED_ACTION_OK(TIM1_ForcedAction));
01108   
01109   /* Reset the OCM Bits */ /* Configure The Forced output Mode */
01110   TIM1->CCMR3  =  (uint8_t)((uint8_t)(TIM1->CCMR3 & (uint8_t)(~TIM1_CCMR_OCM))  
01111                             | (uint8_t)TIM1_ForcedAction);
01112 }
01113 
01114 /**
01115   * @brief  Forces the TIM1 Channel4 output waveform to active or inactive level.
01116   * @param   TIM1_ForcedAction specifies the forced Action to be set to the output waveform.
01117   * This parameter can be one of the following values:
01118   *                       - TIM1_FORCEDACTION_ACTIVE: Force active level on OC4REF
01119   *                       - TIM1_FORCEDACTION_INACTIVE: Force inactive level on
01120   *                         OC4REF.
01121   * @retval None
01122   */
01123 void TIM1_ForcedOC4Config(TIM1_ForcedAction_TypeDef TIM1_ForcedAction)
01124 {
01125   /* Check the parameters */
01126   assert_param(IS_TIM1_FORCED_ACTION_OK(TIM1_ForcedAction));
01127   
01128   /* Reset the OCM Bits & Configure the Forced output Mode */
01129   TIM1->CCMR4  =  (uint8_t)((uint8_t)(TIM1->CCMR4 & (uint8_t)(~TIM1_CCMR_OCM)) 
01130                             | (uint8_t)TIM1_ForcedAction);
01131 }
01132 
01133 /**
01134   * @brief  Enables or disables TIM1 peripheral Preload register on ARR.
01135   * @param   NewState new state of the TIM1 peripheral Preload register.
01136   * This parameter can be ENABLE or DISABLE.
01137   * @retval None
01138   */
01139 void TIM1_ARRPreloadConfig(FunctionalState NewState)
01140 {
01141   /* Check the parameters */
01142   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
01143   
01144   /* Set or Reset the ARPE Bit */
01145   if (NewState != DISABLE)
01146   {
01147     TIM1->CR1 |= TIM1_CR1_ARPE;
01148   }
01149   else
01150   {
01151     TIM1->CR1 &= (uint8_t)(~TIM1_CR1_ARPE);
01152   }
01153 }
01154 
01155 /**
01156   * @brief  Selects the TIM1 peripheral Commutation event.
01157   * @param   NewState new state of the Commutation event.
01158   * This parameter can be ENABLE or DISABLE.
01159   * @retval None
01160   */
01161 void TIM1_SelectCOM(FunctionalState NewState)
01162 {
01163   /* Check the parameters */
01164   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
01165   
01166   /* Set or Reset the COMS Bit */
01167   if (NewState != DISABLE)
01168   {
01169     TIM1->CR2 |= TIM1_CR2_COMS;
01170   }
01171   else
01172   {
01173     TIM1->CR2 &= (uint8_t)(~TIM1_CR2_COMS);
01174   }
01175 }
01176 
01177 /**
01178   * @brief  Sets or Resets the TIM1 peripheral Capture Compare Preload Control bit.
01179   * @param   NewState new state of the Capture Compare Preload Control bit.
01180   * This parameter can be ENABLE or DISABLE.
01181   * @retval None
01182   */
01183 void TIM1_CCPreloadControl(FunctionalState NewState)
01184 {
01185   /* Check the parameters */
01186   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
01187   
01188   /* Set or Reset the CCPC Bit */
01189   if (NewState != DISABLE)
01190   {
01191     TIM1->CR2 |= TIM1_CR2_CCPC;
01192   }
01193   else
01194   {
01195     TIM1->CR2 &= (uint8_t)(~TIM1_CR2_CCPC);
01196   }
01197 }
01198 
01199 /**
01200   * @brief  Enables or disables the TIM1 peripheral Preload Register on CCR1.
01201   * @param   NewState new state of the Capture Compare Preload register.
01202   * This parameter can be ENABLE or DISABLE.
01203   * @retval None
01204   */
01205 void TIM1_OC1PreloadConfig(FunctionalState NewState)
01206 {
01207   /* Check the parameters */
01208   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
01209   
01210   /* Set or Reset the OC1PE Bit */
01211   if (NewState != DISABLE)
01212   {
01213     TIM1->CCMR1 |= TIM1_CCMR_OCxPE;
01214   }
01215   else
01216   {
01217     TIM1->CCMR1 &= (uint8_t)(~TIM1_CCMR_OCxPE);
01218   }
01219 }
01220 
01221 /**
01222   * @brief  Enables or disables the TIM1 peripheral Preload Register on CCR2.
01223   * @param   NewState new state of the Capture Compare Preload register.
01224   * This parameter can be ENABLE or DISABLE.
01225   * @retval None
01226   */
01227 void TIM1_OC2PreloadConfig(FunctionalState NewState)
01228 {
01229   /* Check the parameters */
01230   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
01231   
01232   /* Set or Reset the OC2PE Bit */
01233   if (NewState != DISABLE)
01234   {
01235     TIM1->CCMR2 |= TIM1_CCMR_OCxPE;
01236   }
01237   else
01238   {
01239     TIM1->CCMR2 &= (uint8_t)(~TIM1_CCMR_OCxPE);
01240   }
01241 }
01242 
01243 /**
01244   * @brief  Enables or disables the TIM1 peripheral Preload Register on CCR3.
01245   * @param   NewState new state of the Capture Compare Preload register.
01246   * This parameter can be ENABLE or DISABLE.
01247   * @retval None
01248   */
01249 void TIM1_OC3PreloadConfig(FunctionalState NewState)
01250 {
01251   /* Check the parameters */
01252   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
01253   
01254   /* Set or Reset the OC3PE Bit */
01255   if (NewState != DISABLE)
01256   {
01257     TIM1->CCMR3 |= TIM1_CCMR_OCxPE;
01258   }
01259   else
01260   {
01261     TIM1->CCMR3 &= (uint8_t)(~TIM1_CCMR_OCxPE);
01262   }
01263 }
01264 
01265 /**
01266   * @brief  Enables or disables the TIM1 peripheral Preload Register on CCR4.
01267   * @param   NewState new state of the Capture Compare Preload register.
01268   * This parameter can be ENABLE or DISABLE.
01269   * @retval None
01270   */
01271 void TIM1_OC4PreloadConfig(FunctionalState NewState)
01272 {
01273   /* Check the parameters */
01274   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
01275   
01276   /* Set or Reset the OC4PE Bit */
01277   if (NewState != DISABLE)
01278   {
01279     TIM1->CCMR4 |= TIM1_CCMR_OCxPE;
01280   }
01281   else
01282   {
01283     TIM1->CCMR4 &= (uint8_t)(~TIM1_CCMR_OCxPE);
01284   }
01285 }
01286 
01287 /**
01288   * @brief  Configures the TIM1 Capture Compare 1 Fast feature.
01289   * @param   NewState new state of the Output Compare Fast Enable bit.
01290   * This parameter can be ENABLE or DISABLE.
01291   * @retval None
01292   */
01293 void TIM1_OC1FastConfig(FunctionalState NewState)
01294 {
01295   /* Check the parameters */
01296   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
01297   
01298   /* Set or Reset the OC1FE Bit */
01299   if (NewState != DISABLE)
01300   {
01301     TIM1->CCMR1 |= TIM1_CCMR_OCxFE;
01302   }
01303   else
01304   {
01305     TIM1->CCMR1 &= (uint8_t)(~TIM1_CCMR_OCxFE);
01306   }
01307 }
01308 
01309 /**
01310   * @brief  Configures the TIM1 Capture Compare 2 Fast feature.
01311   * @param   NewState new state of the Output Compare Fast Enable bit.
01312   * This parameter can be ENABLE or DISABLE.
01313   * @retval None
01314   */
01315 void TIM1_OC2FastConfig(FunctionalState NewState)
01316 {
01317   /* Check the parameters */
01318   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
01319   
01320   /* Set or Reset the OC2FE Bit */
01321   if (NewState != DISABLE)
01322   {
01323     TIM1->CCMR2 |= TIM1_CCMR_OCxFE;
01324   }
01325   else
01326   {
01327     TIM1->CCMR2 &= (uint8_t)(~TIM1_CCMR_OCxFE);
01328   }
01329 }
01330 
01331 /**
01332   * @brief  Configures the TIM1 Capture Compare 3 Fast feature.
01333   * @param   NewState new state of the Output Compare Fast Enable bit.
01334   * This parameter can be ENABLE or DISABLE.
01335   * @retval None
01336   */
01337 void TIM1_OC3FastConfig(FunctionalState NewState)
01338 {
01339   /* Check the parameters */
01340   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
01341   
01342   /* Set or Reset the OC3FE Bit */
01343   if (NewState != DISABLE)
01344   {
01345     TIM1->CCMR3 |= TIM1_CCMR_OCxFE;
01346   }
01347   else
01348   {
01349     TIM1->CCMR3 &= (uint8_t)(~TIM1_CCMR_OCxFE);
01350   }
01351 }
01352 
01353 /**
01354   * @brief  Configures the TIM1 Capture Compare 4 Fast feature.
01355   * @param   NewState new state of the Output Compare Fast Enable bit.
01356   * This parameter can be ENABLE or DISABLE.
01357   * @retval None
01358   */
01359 void TIM1_OC4FastConfig(FunctionalState NewState)
01360 {
01361   /* Check the parameters */
01362   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
01363   
01364   /* Set or Reset the OC4FE Bit */
01365   if (NewState != DISABLE)
01366   {
01367     TIM1->CCMR4 |= TIM1_CCMR_OCxFE;
01368   }
01369   else
01370   {
01371     TIM1->CCMR4 &= (uint8_t)(~TIM1_CCMR_OCxFE);
01372   }
01373 }
01374 
01375 /**
01376   * @brief  Configures the TIM1 event to be generated by software.
01377   * @param   TIM1_EventSource specifies the event source.
01378   * This parameter can be one of the following values:
01379   *                       - TIM1_EVENTSOURCE_UPDATE: TIM1 update Event source
01380   *                       - TIM1_EVENTSOURCE_CC1: TIM1 Capture Compare 1 Event source
01381   *                       - TIM1_EVENTSOURCE_CC2: TIM1 Capture Compare 2 Event source
01382   *                       - TIM1_EVENTSOURCE_CC3: TIM1 Capture Compare 3 Event source
01383   *                       - TIM1_EVENTSOURCE_CC4: TIM1 Capture Compare 4 Event source
01384   *                       - TIM1_EVENTSOURCE_COM: TIM1 COM Event source
01385   *                       - TIM1_EVENTSOURCE_TRIGGER: TIM1 Trigger Event source
01386   *                       - TIM1_EventSourceBreak: TIM1 Break Event source
01387   * @retval None
01388   */
01389 void TIM1_GenerateEvent(TIM1_EventSource_TypeDef TIM1_EventSource)
01390 {
01391   /* Check the parameters */
01392   assert_param(IS_TIM1_EVENT_SOURCE_OK(TIM1_EventSource));
01393   
01394   /* Set the event sources */
01395   TIM1->EGR = (uint8_t)TIM1_EventSource;
01396 }
01397 
01398 /**
01399   * @brief  Configures the TIM1 Channel 1 polarity.
01400   * @param   TIM1_OCPolarity specifies the OC1 Polarity.
01401   * This parameter can be one of the following values:
01402   *                       - TIM1_OCPOLARITY_LOW: Output Compare active low
01403   *                       - TIM1_OCPOLARITY_HIGH: Output Compare active high
01404   * @retval None
01405   */
01406 void TIM1_OC1PolarityConfig(TIM1_OCPolarity_TypeDef TIM1_OCPolarity)
01407 {
01408   /* Check the parameters */
01409   assert_param(IS_TIM1_OC_POLARITY_OK(TIM1_OCPolarity));
01410   
01411   /* Set or Reset the CC1P Bit */
01412   if (TIM1_OCPolarity != TIM1_OCPOLARITY_HIGH)
01413   {
01414     TIM1->CCER1 |= TIM1_CCER1_CC1P;
01415   }
01416   else
01417   {
01418     TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC1P);
01419   }
01420 }
01421 
01422 /**
01423   * @brief  Configures the TIM1 Channel 1N polarity.
01424   * @param   TIM1_OCNPolarity specifies the OC1N Polarity.
01425   * This parameter can be one of the following values:
01426   *                       - TIM1_OCNPOLARITY_LOW: Output Compare active low
01427   *                       - TIM1_OCNPOLARITY_HIGH: Output Compare active high
01428   * @retval None
01429   */
01430 void TIM1_OC1NPolarityConfig(TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity)
01431 {
01432   /* Check the parameters */
01433   assert_param(IS_TIM1_OCN_POLARITY_OK(TIM1_OCNPolarity));
01434   
01435   /* Set or Reset the CC3P Bit */
01436   if (TIM1_OCNPolarity != TIM1_OCNPOLARITY_HIGH)
01437   {
01438     TIM1->CCER1 |= TIM1_CCER1_CC1NP;
01439   }
01440   else
01441   {
01442     TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC1NP);
01443   }
01444 }
01445 
01446 /**
01447   * @brief  Configures the TIM1 Channel 2 polarity.
01448   * @param   TIM1_OCPolarity specifies the OC2 Polarity.
01449   * This parameter can be one of the following values:
01450   *                       - TIM1_OCPOLARITY_LOW: Output Compare active low
01451   *                       - TIM1_OCPOLARITY_HIGH: Output Compare active high
01452   * @retval None
01453   */
01454 void TIM1_OC2PolarityConfig(TIM1_OCPolarity_TypeDef TIM1_OCPolarity)
01455 {
01456   /* Check the parameters */
01457   assert_param(IS_TIM1_OC_POLARITY_OK(TIM1_OCPolarity));
01458   
01459   /* Set or Reset the CC2P Bit */
01460   if (TIM1_OCPolarity != TIM1_OCPOLARITY_HIGH)
01461   {
01462     TIM1->CCER1 |= TIM1_CCER1_CC2P;
01463   }
01464   else
01465   {
01466     TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC2P);
01467   }
01468 }
01469 
01470 /**
01471   * @brief  Configures the TIM1 Channel 2N polarity.
01472   * @param   TIM1_OCNPolarity specifies the OC2N Polarity.
01473   * This parameter can be one of the following values:
01474   *                       - TIM1_OCNPOLARITY_LOW: Output Compare active low
01475   *                       - TIM1_OCNPOLARITY_HIGH: Output Compare active high
01476   * @retval None
01477   */
01478 void TIM1_OC2NPolarityConfig(TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity)
01479 {
01480   /* Check the parameters */
01481   assert_param(IS_TIM1_OCN_POLARITY_OK(TIM1_OCNPolarity));
01482   
01483   /* Set or Reset the CC3P Bit */
01484   if (TIM1_OCNPolarity != TIM1_OCNPOLARITY_HIGH)
01485   {
01486     TIM1->CCER1 |= TIM1_CCER1_CC2NP;
01487   }
01488   else
01489   {
01490     TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC2NP);
01491   }
01492 }
01493 
01494 /**
01495   * @brief  Configures the TIM1 Channel 3 polarity.
01496   * @param   TIM1_OCPolarity specifies the OC3 Polarity.
01497   * This parameter can be one of the following values:
01498   *                       - TIM1_OCPOLARITY_LOW: Output Compare active low
01499   *                       - TIM1_OCPOLARITY_HIGH: Output Compare active high
01500   * @retval None
01501   */
01502 void TIM1_OC3PolarityConfig(TIM1_OCPolarity_TypeDef TIM1_OCPolarity)
01503 {
01504   /* Check the parameters */
01505   assert_param(IS_TIM1_OC_POLARITY_OK(TIM1_OCPolarity));
01506   
01507   /* Set or Reset the CC3P Bit */
01508   if (TIM1_OCPolarity != TIM1_OCPOLARITY_HIGH)
01509   {
01510     TIM1->CCER2 |= TIM1_CCER2_CC3P;
01511   }
01512   else
01513   {
01514     TIM1->CCER2 &= (uint8_t)(~TIM1_CCER2_CC3P);
01515   }
01516 }
01517 
01518 
01519 /**
01520   * @brief  Configures the TIM1 Channel 3N polarity.
01521   * @param   TIM1_OCNPolarity specifies the OC3N Polarity.
01522   * This parameter can be one of the following values:
01523   *                       - TIM1_OCNPOLARITY_LOW: Output Compare active low
01524   *                       - TIM1_OCNPOLARITY_HIGH: Output Compare active high
01525   * @retval None
01526   */
01527 void TIM1_OC3NPolarityConfig(TIM1_OCNPolarity_TypeDef TIM1_OCNPolarity)
01528 {
01529   /* Check the parameters */
01530   assert_param(IS_TIM1_OCN_POLARITY_OK(TIM1_OCNPolarity));
01531   
01532   /* Set or Reset the CC3P Bit */
01533   if (TIM1_OCNPolarity != TIM1_OCNPOLARITY_HIGH)
01534   {
01535     TIM1->CCER2 |= TIM1_CCER2_CC3NP;
01536   }
01537   else
01538   {
01539     TIM1->CCER2 &= (uint8_t)(~TIM1_CCER2_CC3NP);
01540   }
01541 }
01542 
01543 /**
01544   * @brief  Configures the TIM1 Channel 4 polarity.
01545   * @param   TIM1_OCPolarity specifies the OC4 Polarity.
01546   * This parameter can be one of the following values:
01547   *                       - TIM1_OCPOLARITY_LOW: Output Compare active low
01548   *                       - TIM1_OCPOLARITY_HIGH: Output Compare active high
01549   * @retval None
01550   */
01551 void TIM1_OC4PolarityConfig(TIM1_OCPolarity_TypeDef TIM1_OCPolarity)
01552 {
01553   /* Check the parameters */
01554   assert_param(IS_TIM1_OC_POLARITY_OK(TIM1_OCPolarity));
01555   
01556   /* Set or Reset the CC4P Bit */
01557   if (TIM1_OCPolarity != TIM1_OCPOLARITY_HIGH)
01558   {
01559     TIM1->CCER2 |= TIM1_CCER2_CC4P;
01560   }
01561   else
01562   {
01563     TIM1->CCER2 &= (uint8_t)(~TIM1_CCER2_CC4P);
01564   }
01565 }
01566 
01567 /**
01568   * @brief  Enables or disables the TIM1 Capture Compare Channel x (x=1,..,4).
01569   * @param   TIM1_Channel specifies the TIM1 Channel.
01570   * This parameter can be one of the following values:
01571   *                       - TIM1_CHANNEL_1: TIM1 Channel1
01572   *                       - TIM1_CHANNEL_2: TIM1 Channel2
01573   *                       - TIM1_CHANNEL_3: TIM1 Channel3
01574   *                       - TIM1_CHANNEL_4: TIM1 Channel4
01575   * @param   NewState specifies the TIM1 Channel CCxE bit new state.
01576   * This parameter can be: ENABLE or DISABLE.
01577   * @retval None
01578   */
01579 void TIM1_CCxCmd(TIM1_Channel_TypeDef TIM1_Channel, FunctionalState NewState)
01580 {
01581   /* Check the parameters */
01582   assert_param(IS_TIM1_CHANNEL_OK(TIM1_Channel));
01583   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
01584   
01585   if (TIM1_Channel == TIM1_CHANNEL_1)
01586   {
01587     /* Set or Reset the CC1E Bit */
01588     if (NewState != DISABLE)
01589     {
01590       TIM1->CCER1 |= TIM1_CCER1_CC1E;
01591     }
01592     else
01593     {
01594       TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC1E);
01595     }
01596     
01597   }
01598   else if (TIM1_Channel == TIM1_CHANNEL_2)
01599   {
01600     /* Set or Reset the CC2E Bit */
01601     if (NewState != DISABLE)
01602     {
01603       TIM1->CCER1 |= TIM1_CCER1_CC2E;
01604     }
01605     else
01606     {
01607       TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC2E);
01608     }
01609   }
01610   else if (TIM1_Channel == TIM1_CHANNEL_3)
01611   {
01612     /* Set or Reset the CC3E Bit */
01613     if (NewState != DISABLE)
01614     {
01615       TIM1->CCER2 |= TIM1_CCER2_CC3E;
01616     }
01617     else
01618     {
01619       TIM1->CCER2 &= (uint8_t)(~TIM1_CCER2_CC3E);
01620     }
01621   }
01622   else
01623   {
01624     /* Set or Reset the CC4E Bit */
01625     if (NewState != DISABLE)
01626     {
01627       TIM1->CCER2 |= TIM1_CCER2_CC4E;
01628     }
01629     else
01630     {
01631       TIM1->CCER2 &= (uint8_t)(~TIM1_CCER2_CC4E);
01632     }
01633   }
01634 }
01635 
01636 /**
01637   * @brief  Enables or disables the TIM1 Capture Compare Channel xN (xN=1,..,3).
01638   * @param   TIM1_Channel specifies the TIM1 Channel.
01639   * This parameter can be one of the following values:
01640   *                       - TIM1_CHANNEL_1: TIM1 Channel1
01641   *                       - TIM1_CHANNEL_2: TIM1 Channel2
01642   *                       - TIM1_CHANNEL_3: TIM1 Channel3
01643   * @param   NewState specifies the TIM1 Channel CCxNE bit new state.
01644   * This parameter can be: ENABLE or DISABLE.
01645   * @retval None
01646   */
01647 void TIM1_CCxNCmd(TIM1_Channel_TypeDef TIM1_Channel, FunctionalState NewState)
01648 {
01649   /* Check the parameters */
01650   assert_param(IS_TIM1_COMPLEMENTARY_CHANNEL_OK(TIM1_Channel));
01651   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
01652   
01653   if (TIM1_Channel == TIM1_CHANNEL_1)
01654   {
01655     /* Set or Reset the CC1NE Bit */
01656     if (NewState != DISABLE)
01657     {
01658       TIM1->CCER1 |= TIM1_CCER1_CC1NE;
01659     }
01660     else
01661     {
01662       TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC1NE);
01663     }
01664   }
01665   else if (TIM1_Channel == TIM1_CHANNEL_2)
01666   {
01667     /* Set or Reset the CC2NE Bit */
01668     if (NewState != DISABLE)
01669     {
01670       TIM1->CCER1 |= TIM1_CCER1_CC2NE;
01671     }
01672     else
01673     {
01674       TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC2NE);
01675     }
01676   }
01677   else
01678   {
01679     /* Set or Reset the CC3NE Bit */
01680     if (NewState != DISABLE)
01681     {
01682       TIM1->CCER2 |= TIM1_CCER2_CC3NE;
01683     }
01684     else
01685     {
01686       TIM1->CCER2 &= (uint8_t)(~TIM1_CCER2_CC3NE);
01687     }
01688   }
01689 }
01690 
01691 /**
01692   * @brief  Selects the TIM1 Output Compare Mode. This function disables the
01693   * selected channel before changing the Output Compare Mode. User has to
01694   * enable this channel using TIM1_CCxCmd and TIM1_CCxNCmd functions.
01695   * @param   TIM1_Channel specifies the TIM1 Channel.
01696   * This parameter can be one of the following values:
01697   *                       - TIM1_CHANNEL_1: TIM1 Channel1
01698   *                       - TIM1_CHANNEL_2: TIM1 Channel2
01699   *                       - TIM1_CHANNEL_3: TIM1 Channel3
01700   *                       - TIM1_CHANNEL_4: TIM1 Channel4
01701   * @param   TIM1_OCMode specifies the TIM1 Output Compare Mode.
01702   * This parameter can be one of the following values:
01703   *                       - TIM1_OCMODE_TIMING
01704   *                       - TIM1_OCMODE_ACTIVE
01705   *                       - TIM1_OCMODE_TOGGLE
01706   *                       - TIM1_OCMODE_PWM1
01707   *                       - TIM1_OCMODE_PWM2
01708   *                       - TIM1_FORCEDACTION_ACTIVE
01709   *                       - TIM1_FORCEDACTION_INACTIVE
01710   * @retval None
01711   */
01712 void TIM1_SelectOCxM(TIM1_Channel_TypeDef TIM1_Channel, TIM1_OCMode_TypeDef TIM1_OCMode)
01713 {
01714   /* Check the parameters */
01715   assert_param(IS_TIM1_CHANNEL_OK(TIM1_Channel));
01716   assert_param(IS_TIM1_OCM_OK(TIM1_OCMode));
01717   
01718   if (TIM1_Channel == TIM1_CHANNEL_1)
01719   {
01720     /* Disable the Channel 1: Reset the CCE Bit */
01721     TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC1E);
01722     
01723     /* Reset the Output Compare Bits & Set the Output Compare Mode */
01724     TIM1->CCMR1 = (uint8_t)((uint8_t)(TIM1->CCMR1 & (uint8_t)(~TIM1_CCMR_OCM)) 
01725                             | (uint8_t)TIM1_OCMode);
01726   }
01727   else if (TIM1_Channel == TIM1_CHANNEL_2)
01728   {
01729     /* Disable the Channel 2: Reset the CCE Bit */
01730     TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC2E);
01731     
01732     /* Reset the Output Compare Bits & Set the Output Compare Mode */
01733     TIM1->CCMR2 = (uint8_t)((uint8_t)(TIM1->CCMR2 & (uint8_t)(~TIM1_CCMR_OCM))
01734                             | (uint8_t)TIM1_OCMode);
01735   }
01736   else if (TIM1_Channel == TIM1_CHANNEL_3)
01737   {
01738     /* Disable the Channel 3: Reset the CCE Bit */
01739     TIM1->CCER2 &= (uint8_t)(~TIM1_CCER2_CC3E);
01740     
01741     /* Reset the Output Compare Bits & Set the Output Compare Mode */
01742     TIM1->CCMR3 = (uint8_t)((uint8_t)(TIM1->CCMR3 & (uint8_t)(~TIM1_CCMR_OCM)) 
01743                             | (uint8_t)TIM1_OCMode);
01744   }
01745   else
01746   {
01747     /* Disable the Channel 4: Reset the CCE Bit */
01748     TIM1->CCER2 &= (uint8_t)(~TIM1_CCER2_CC4E);
01749     
01750     /* Reset the Output Compare Bits & Set the Output Compare Mode */
01751     TIM1->CCMR4 = (uint8_t)((uint8_t)(TIM1->CCMR4 & (uint8_t)(~TIM1_CCMR_OCM)) 
01752                             | (uint8_t)TIM1_OCMode);
01753   }
01754 }
01755 
01756 /**
01757   * @brief  Sets the TIM1 Counter Register value.
01758   * @param   Counter specifies the Counter register new value.
01759   * This parameter is between 0x0000 and 0xFFFF.
01760   * @retval None
01761   */
01762 void TIM1_SetCounter(uint16_t Counter)
01763 {
01764   /* Set the Counter Register value */
01765   TIM1->CNTRH = (uint8_t)(Counter >> 8);
01766   TIM1->CNTRL = (uint8_t)(Counter);
01767 }
01768 
01769 /**
01770   * @brief  Sets the TIM1 Autoreload Register value.
01771   * @param   Autoreload specifies the Autoreload register new value.
01772   * This parameter is between 0x0000 and 0xFFFF.
01773   * @retval None
01774   */
01775 void TIM1_SetAutoreload(uint16_t Autoreload)
01776 {
01777   /* Set the Autoreload Register value */
01778   TIM1->ARRH = (uint8_t)(Autoreload >> 8);
01779   TIM1->ARRL = (uint8_t)(Autoreload);
01780  }
01781 
01782 /**
01783   * @brief  Sets the TIM1 Capture Compare1 Register value.
01784   * @param   Compare1 specifies the Capture Compare1 register new value.
01785   * This parameter is between 0x0000 and 0xFFFF.
01786   * @retval None
01787   */
01788 void TIM1_SetCompare1(uint16_t Compare1)
01789 {
01790   /* Set the Capture Compare1 Register value */
01791   TIM1->CCR1H = (uint8_t)(Compare1 >> 8);
01792   TIM1->CCR1L = (uint8_t)(Compare1);
01793 }
01794 
01795 /**
01796   * @brief  Sets the TIM1 Capture Compare2 Register value.
01797   * @param   Compare2 specifies the Capture Compare2 register new value.
01798   * This parameter is between 0x0000 and 0xFFFF.
01799   * @retval None
01800   */
01801 void TIM1_SetCompare2(uint16_t Compare2)
01802 {
01803   /* Set the Capture Compare2 Register value */
01804   TIM1->CCR2H = (uint8_t)(Compare2 >> 8);
01805   TIM1->CCR2L = (uint8_t)(Compare2);
01806 }
01807 
01808 /**
01809   * @brief  Sets the TIM1 Capture Compare3 Register value.
01810   * @param   Compare3 specifies the Capture Compare3 register new value.
01811   * This parameter is between 0x0000 and 0xFFFF.
01812   * @retval None
01813   */
01814 void TIM1_SetCompare3(uint16_t Compare3)
01815 {
01816   /* Set the Capture Compare3 Register value */
01817   TIM1->CCR3H = (uint8_t)(Compare3 >> 8);
01818   TIM1->CCR3L = (uint8_t)(Compare3);
01819 }
01820 
01821 /**
01822   * @brief  Sets the TIM1 Capture Compare4 Register value.
01823   * @param   Compare4 specifies the Capture Compare4 register new value.
01824   * This parameter is between 0x0000 and 0xFFFF.
01825   * @retval None
01826   */
01827 void TIM1_SetCompare4(uint16_t Compare4)
01828 {
01829   /* Set the Capture Compare4 Register value */
01830   TIM1->CCR4H = (uint8_t)(Compare4 >> 8);
01831   TIM1->CCR4L = (uint8_t)(Compare4);
01832 }
01833 
01834 /**
01835   * @brief  Sets the TIM1 Input Capture 1 prescaler.
01836   * @param   TIM1_IC1Prescaler specifies the Input Capture prescaler new value
01837   * This parameter can be one of the following values:
01838   *                       - TIM1_ICPSC_DIV1: no prescaler
01839   *                       - TIM1_ICPSC_DIV2: capture is done once every 2 events
01840   *                       - TIM1_ICPSC_DIV4: capture is done once every 4 events
01841   *                       - TIM1_ICPSC_DIV8: capture is done once every 8 events
01842   * @retval None
01843   */
01844 void TIM1_SetIC1Prescaler(TIM1_ICPSC_TypeDef TIM1_IC1Prescaler)
01845 {
01846   /* Check the parameters */
01847   assert_param(IS_TIM1_IC_PRESCALER_OK(TIM1_IC1Prescaler));
01848   
01849   /* Reset the IC1PSC Bits */ /* Set the IC1PSC value */
01850   TIM1->CCMR1 = (uint8_t)((uint8_t)(TIM1->CCMR1 & (uint8_t)(~TIM1_CCMR_ICxPSC)) 
01851                           | (uint8_t)TIM1_IC1Prescaler);
01852 }
01853 
01854 /**
01855   * @brief  Sets the TIM1 Input Capture 2 prescaler.
01856   * @param   TIM1_IC2Prescaler specifies the Input Capture prescaler new value
01857   * This parameter can be one of the following values:
01858   *                       - TIM1_ICPSC_DIV1: no prescaler
01859   *                       - TIM1_ICPSC_DIV2: capture is done once every 2 events
01860   *                       - TIM1_ICPSC_DIV4: capture is done once every 4 events
01861   *                       - TIM1_ICPSC_DIV8: capture is done once every 8 events
01862   * @retval None
01863   */
01864 void TIM1_SetIC2Prescaler(TIM1_ICPSC_TypeDef TIM1_IC2Prescaler)
01865 {
01866   
01867   /* Check the parameters */
01868   assert_param(IS_TIM1_IC_PRESCALER_OK(TIM1_IC2Prescaler));
01869   
01870   /* Reset the IC1PSC Bits */ /* Set the IC1PSC value */
01871   TIM1->CCMR2 = (uint8_t)((uint8_t)(TIM1->CCMR2 & (uint8_t)(~TIM1_CCMR_ICxPSC))
01872                           | (uint8_t)TIM1_IC2Prescaler);
01873 }
01874 
01875 /**
01876   * @brief  Sets the TIM1 Input Capture 3 prescaler.
01877   * @param   TIM1_IC3Prescaler specifies the Input Capture prescaler new value
01878   * This parameter can be one of the following values:
01879   *                       - TIM1_ICPSC_DIV1: no prescaler
01880   *                       - TIM1_ICPSC_DIV2: capture is done once every 2 events
01881   *                       - TIM1_ICPSC_DIV4: capture is done once every 4 events
01882   *                       - TIM1_ICPSC_DIV8: capture is done once every 8 events
01883   * @retval None
01884   */
01885 void TIM1_SetIC3Prescaler(TIM1_ICPSC_TypeDef TIM1_IC3Prescaler)
01886 {
01887   
01888   /* Check the parameters */
01889   assert_param(IS_TIM1_IC_PRESCALER_OK(TIM1_IC3Prescaler));
01890   
01891   /* Reset the IC1PSC Bits & Set the IC1PSC value */
01892   TIM1->CCMR3 = (uint8_t)((uint8_t)(TIM1->CCMR3 & (uint8_t)(~TIM1_CCMR_ICxPSC)) | 
01893                           (uint8_t)TIM1_IC3Prescaler);
01894 }
01895 
01896 /**
01897   * @brief  Sets the TIM1 Input Capture 4 prescaler.
01898   * @param  TIM1_IC4Prescaler specifies the Input Capture prescaler new value
01899   *         This parameter can be one of the following values:
01900   *                       - TIM1_ICPSC_DIV1: no prescaler
01901   *                       - TIM1_ICPSC_DIV2: capture is done once every 2 events
01902   *                       - TIM1_ICPSC_DIV4: capture is done once every 4 events
01903   *                       - TIM1_ICPSC_DIV8: capture is done once every 8 events
01904   * @retval None
01905   */
01906 void TIM1_SetIC4Prescaler(TIM1_ICPSC_TypeDef TIM1_IC4Prescaler)
01907 {
01908   
01909   /* Check the parameters */
01910   assert_param(IS_TIM1_IC_PRESCALER_OK(TIM1_IC4Prescaler));
01911   
01912   /* Reset the IC1PSC Bits &  Set the IC1PSC value */
01913   TIM1->CCMR4 = (uint8_t)((uint8_t)(TIM1->CCMR4 & (uint8_t)(~TIM1_CCMR_ICxPSC)) |
01914                           (uint8_t)TIM1_IC4Prescaler);
01915 }
01916 
01917 /**
01918   * @brief  Gets the TIM1 Input Capture 1 value.
01919   * @param  None
01920   * @retval Capture Compare 1 Register value.
01921   */
01922 uint16_t TIM1_GetCapture1(void)
01923 {
01924   /* Get the Capture 1 Register value */
01925   
01926   uint16_t tmpccr1 = 0;
01927   uint8_t tmpccr1l=0, tmpccr1h=0;
01928   
01929   tmpccr1h = TIM1->CCR1H;
01930   tmpccr1l = TIM1->CCR1L;
01931   
01932   tmpccr1 = (uint16_t)(tmpccr1l);
01933   tmpccr1 |= (uint16_t)((uint16_t)tmpccr1h << 8);
01934   /* Get the Capture 1 Register value */
01935   return (uint16_t)tmpccr1;
01936 }
01937 
01938 /**
01939   * @brief  Gets the TIM1 Input Capture 2 value.
01940   * @param  None
01941   * @retval Capture Compare 2 Register value.
01942   */
01943 uint16_t TIM1_GetCapture2(void)
01944 {
01945   /* Get the Capture 2 Register value */
01946   
01947   uint16_t tmpccr2 = 0;
01948   uint8_t tmpccr2l=0, tmpccr2h=0;
01949   
01950   tmpccr2h = TIM1->CCR2H;
01951   tmpccr2l = TIM1->CCR2L;
01952   
01953   tmpccr2 = (uint16_t)(tmpccr2l);
01954   tmpccr2 |= (uint16_t)((uint16_t)tmpccr2h << 8);
01955   /* Get the Capture 2 Register value */
01956   return (uint16_t)tmpccr2;
01957 }
01958 
01959 /**
01960   * @brief  Gets the TIM1 Input Capture 3 value.
01961   * @param  None
01962   * @retval Capture Compare 3 Register value.
01963   */
01964 uint16_t TIM1_GetCapture3(void)
01965 {
01966   /* Get the Capture 3 Register value */
01967   uint16_t tmpccr3 = 0;
01968   uint8_t tmpccr3l=0, tmpccr3h=0;
01969   
01970   tmpccr3h = TIM1->CCR3H;
01971   tmpccr3l = TIM1->CCR3L;
01972   
01973   tmpccr3 = (uint16_t)(tmpccr3l);
01974   tmpccr3 |= (uint16_t)((uint16_t)tmpccr3h << 8);
01975   /* Get the Capture 3 Register value */
01976   return (uint16_t)tmpccr3;
01977 }
01978 
01979 /**
01980   * @brief  Gets the TIM1 Input Capture 4 value.
01981   * @param  None
01982   * @retval Capture Compare 4 Register value.
01983   */
01984 uint16_t TIM1_GetCapture4(void)
01985 {
01986   /* Get the Capture 4 Register value */
01987   uint16_t tmpccr4 = 0;
01988   uint8_t tmpccr4l=0, tmpccr4h=0;
01989   
01990   tmpccr4h = TIM1->CCR4H;
01991   tmpccr4l = TIM1->CCR4L;
01992   
01993   tmpccr4 = (uint16_t)(tmpccr4l);
01994   tmpccr4 |= (uint16_t)((uint16_t)tmpccr4h << 8);
01995   /* Get the Capture 4 Register value */
01996   return (uint16_t)tmpccr4;
01997 }
01998 
01999 /**
02000   * @brief  Gets the TIM1 Counter value.
02001   * @param  None
02002   * @retval Counter Register value.
02003   */
02004 uint16_t TIM1_GetCounter(void)
02005 {
02006   uint16_t tmpcntr = 0;
02007   
02008   tmpcntr = ((uint16_t)TIM1->CNTRH << 8);
02009   
02010   /* Get the Counter Register value */
02011   return (uint16_t)(tmpcntr | (uint16_t)(TIM1->CNTRL));
02012 }
02013 
02014 /**
02015   * @brief  Gets the TIM1 Prescaler value.
02016   * @param  None
02017   * @retval Prescaler Register value.
02018   */
02019 uint16_t TIM1_GetPrescaler(void)
02020 {
02021   uint16_t temp = 0;
02022   
02023   temp = ((uint16_t)TIM1->PSCRH << 8);
02024   
02025   /* Get the Prescaler Register value */
02026   return (uint16_t)( temp | (uint16_t)(TIM1->PSCRL));
02027 }
02028 
02029 /**
02030   * @brief  Checks whether the specified TIM1 flag is set or not.
02031   * @param  TIM1_FLAG specifies the flag to check.
02032   *         This parameter can be one of the following values:
02033   *                   - TIM1_FLAG_UPDATE: TIM1 update Flag
02034   *                   - TIM1_FLAG_CC1: TIM1 Capture Compare 1 Flag
02035   *                   - TIM1_FLAG_CC2: TIM1 Capture Compare 2 Flag
02036   *                   - TIM1_FLAG_CC3: TIM1 Capture Compare 3 Flag
02037   *                   - TIM1_FLAG_CC4: TIM1 Capture Compare 4 Flag
02038   *                   - TIM1_FLAG_COM: TIM1 Commutation Flag
02039   *                   - TIM1_FLAG_TRIGGER: TIM1 Trigger Flag
02040   *                   - TIM1_FLAG_BREAK: TIM1 Break Flag
02041   *                   - TIM1_FLAG_CC1OF: TIM1 Capture Compare 1 overcapture Flag
02042   *                   - TIM1_FLAG_CC2OF: TIM1 Capture Compare 2 overcapture Flag
02043   *                   - TIM1_FLAG_CC3OF: TIM1 Capture Compare 3 overcapture Flag
02044   *                   - TIM1_FLAG_CC4OF: TIM1 Capture Compare 4 overcapture Flag
02045   * @retval FlagStatus The new state of TIM1_FLAG (SET or RESET).
02046   */
02047 FlagStatus TIM1_GetFlagStatus(TIM1_FLAG_TypeDef TIM1_FLAG)
02048 {
02049   FlagStatus bitstatus = RESET;
02050   uint8_t tim1_flag_l = 0, tim1_flag_h = 0;
02051   
02052   /* Check the parameters */
02053   assert_param(IS_TIM1_GET_FLAG_OK(TIM1_FLAG));
02054   
02055   tim1_flag_l = (uint8_t)(TIM1->SR1 & (uint8_t)TIM1_FLAG);
02056   tim1_flag_h = (uint8_t)((uint16_t)TIM1_FLAG >> 8);
02057   
02058   if ((tim1_flag_l | (uint8_t)(TIM1->SR2 & tim1_flag_h)) != 0)
02059   {
02060     bitstatus = SET;
02061   }
02062   else
02063   {
02064     bitstatus = RESET;
02065   }
02066   return (FlagStatus)(bitstatus);
02067 }
02068 
02069 /**
02070   * @brief  Clears the TIM1�s pending flags.
02071   * @param  TIM1_FLAG specifies the flag to clear.
02072   *         This parameter can be one of the following values:
02073   *                       - TIM1_FLAG_UPDATE: TIM1 update Flag
02074   *                       - TIM1_FLAG_CC1: TIM1 Capture Compare 1 Flag
02075   *                       - TIM1_FLAG_CC2: TIM1 Capture Compare 2 Flag
02076   *                       - TIM1_FLAG_CC3: TIM1 Capture Compare 3 Flag
02077   *                       - TIM1_FLAG_CC4: TIM1 Capture Compare 4 Flag
02078   *                       - TIM1_FLAG_COM: TIM1 Commutation Flag
02079   *                       - TIM1_FLAG_TRIGGER: TIM1 Trigger Flag
02080   *                       - TIM1_FLAG_BREAK: TIM1 Break Flag
02081   *                       - TIM1_FLAG_CC1OF: TIM1 Capture Compare 1 overcapture Flag
02082   *                       - TIM1_FLAG_CC2OF: TIM1 Capture Compare 2 overcapture Flag
02083   *                       - TIM1_FLAG_CC3OF: TIM1 Capture Compare 3 overcapture Flag
02084   *                       - TIM1_FLAG_CC4OF: TIM1 Capture Compare 4 overcapture Flag
02085   * @retval None.
02086   */
02087 void TIM1_ClearFlag(TIM1_FLAG_TypeDef TIM1_FLAG)
02088 {
02089   /* Check the parameters */
02090   assert_param(IS_TIM1_CLEAR_FLAG_OK(TIM1_FLAG));
02091   
02092   /* Clear the flags (rc_w0) clear this bit by writing 0. Writing �1� has no effect*/
02093   TIM1->SR1 = (uint8_t)(~(uint8_t)(TIM1_FLAG));
02094   TIM1->SR2 = (uint8_t)((uint8_t)(~((uint8_t)((uint16_t)TIM1_FLAG >> 8))) & 
02095                         (uint8_t)0x1E);
02096 }
02097 
02098 /**
02099   * @brief  Checks whether the TIM1 interrupt has occurred or not.
02100   * @param  TIM1_IT specifies the TIM1 interrupt source to check.
02101   *         This parameter can be one of the following values:
02102   *                       - TIM1_IT_UPDATE: TIM1 update Interrupt source
02103   *                       - TIM1_IT_CC1: TIM1 Capture Compare 1 Interrupt source
02104   *                       - TIM1_IT_CC2: TIM1 Capture Compare 2 Interrupt source
02105   *                       - TIM1_IT_CC3: TIM1 Capture Compare 3 Interrupt source
02106   *                       - TIM1_IT_CC4: TIM1 Capture Compare 4 Interrupt source
02107   *                       - TIM1_IT_COM: TIM1 Commutation Interrupt source
02108   *                       - TIM1_IT_TRIGGER: TIM1 Trigger Interrupt source
02109   *                       - TIM1_IT_BREAK: TIM1 Break Interrupt source
02110   * @retval ITStatus The new state of the TIM1_IT(SET or RESET).
02111   */
02112 ITStatus TIM1_GetITStatus(TIM1_IT_TypeDef TIM1_IT)
02113 {
02114   ITStatus bitstatus = RESET;
02115   uint8_t TIM1_itStatus = 0, TIM1_itEnable = 0;
02116   
02117   /* Check the parameters */
02118   assert_param(IS_TIM1_GET_IT_OK(TIM1_IT));
02119   
02120   TIM1_itStatus = (uint8_t)(TIM1->SR1 & (uint8_t)TIM1_IT);
02121   
02122   TIM1_itEnable = (uint8_t)(TIM1->IER & (uint8_t)TIM1_IT);
02123   
02124   if ((TIM1_itStatus != (uint8_t)RESET ) && (TIM1_itEnable != (uint8_t)RESET ))
02125   {
02126     bitstatus = SET;
02127   }
02128   else
02129   {
02130     bitstatus = RESET;
02131   }
02132   return (ITStatus)(bitstatus);
02133 }
02134 
02135 /**
02136   * @brief  Clears the TIM1's interrupt pending bits.
02137   * @param  TIM1_IT specifies the pending bit to clear.
02138   *         This parameter can be one of the following values:
02139   *                       - TIM1_IT_UPDATE: TIM1 update Interrupt source
02140   *                       - TIM1_IT_CC1: TIM1 Capture Compare 1 Interrupt source
02141   *                       - TIM1_IT_CC2: TIM1 Capture Compare 2 Interrupt source
02142   *                       - TIM1_IT_CC3: TIM1 Capture Compare 3 Interrupt source
02143   *                       - TIM1_IT_CC4: TIM1 Capture Compare 4 Interrupt source
02144   *                       - TIM1_IT_COM: TIM1 Commutation Interrupt source
02145   *                       - TIM1_IT_TRIGGER: TIM1 Trigger Interrupt source
02146   *                       - TIM1_IT_BREAK: TIM1 Break Interrupt source
02147   * @retval None.
02148   */
02149 void TIM1_ClearITPendingBit(TIM1_IT_TypeDef TIM1_IT)
02150 {
02151   /* Check the parameters */
02152   assert_param(IS_TIM1_IT_OK(TIM1_IT));
02153   
02154   /* Clear the IT pending Bit */
02155   TIM1->SR1 = (uint8_t)(~(uint8_t)TIM1_IT);
02156 }
02157 
02158 /**
02159   * @brief  Configure the TI1 as Input.
02160   * @param  TIM1_ICPolarity  The Input Polarity.
02161   *         This parameter can be one of the following values:
02162   *                       - TIM1_ICPOLARITY_FALLING
02163   *                       - TIM1_ICPOLARITY_RISING
02164   * @param  TIM1_ICSelection specifies the input to be used.
02165   *         This parameter can be one of the following values:
02166   *                       - TIM1_ICSELECTION_DIRECTTI: TIM1 Input 1 is selected to
02167   *                         be connected to IC1.
02168   *                       - TIM1_ICSELECTION_INDIRECTTI: TIM1 Input 1 is selected to
02169   *                         be connected to IC2.
02170   * @param  TIM1_ICFilter Specifies the Input Capture Filter.
02171   *         This parameter must be a value between 0x00 and 0x0F.
02172   * @retval None
02173   */
02174 static void TI1_Config(uint8_t TIM1_ICPolarity,
02175                        uint8_t TIM1_ICSelection,
02176                        uint8_t TIM1_ICFilter)
02177 {
02178   /* Disable the Channel 1: Reset the CCE Bit */
02179   TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC1E);
02180   
02181   /* Select the Input and set the filter */
02182   TIM1->CCMR1 = (uint8_t)((uint8_t)(TIM1->CCMR1 & (uint8_t)(~(uint8_t)( TIM1_CCMR_CCxS | TIM1_CCMR_ICxF ))) | 
02183                           (uint8_t)(( (TIM1_ICSelection)) | ((uint8_t)( TIM1_ICFilter << 4))));
02184   
02185   /* Select the Polarity */
02186   if (TIM1_ICPolarity != TIM1_ICPOLARITY_RISING)
02187   {
02188     TIM1->CCER1 |= TIM1_CCER1_CC1P;
02189   }
02190   else
02191   {
02192     TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC1P);
02193   }
02194   
02195   /* Set the CCE Bit */
02196   TIM1->CCER1 |=  TIM1_CCER1_CC1E;
02197 }
02198 
02199 /**
02200   * @brief  Configure the TI2 as Input.
02201   * @param  TIM1_ICPolarity  The Input Polarity.
02202   *         This parameter can be one of the following values:
02203   *                       - TIM1_ICPOLARITY_FALLING
02204   *                       - TIM1_ICPOLARITY_RISING
02205   * @param  TIM1_ICSelection specifies the input to be used.
02206   *         This parameter can be one of the following values:
02207   *                       - TIM1_ICSELECTION_DIRECTTI: TIM1 Input 2 is selected to
02208   *                         be connected to IC2.
02209   *                       - TIM1_ICSELECTION_INDIRECTTI: TIM1 Input 2 is selected to
02210   *                         be connected to IC1.
02211   * @param  TIM1_ICFilter Specifies the Input Capture Filter.
02212   *         This parameter must be a value between 0x00 and 0x0F.
02213   * @retval None
02214   */
02215 static void TI2_Config(uint8_t TIM1_ICPolarity,
02216                        uint8_t TIM1_ICSelection,
02217                        uint8_t TIM1_ICFilter)
02218 {
02219   /* Disable the Channel 2: Reset the CCE Bit */
02220   TIM1->CCER1 &=  (uint8_t)(~TIM1_CCER1_CC2E);
02221   
02222   /* Select the Input and set the filter */
02223   TIM1->CCMR2  = (uint8_t)((uint8_t)(TIM1->CCMR2 & (uint8_t)(~(uint8_t)( TIM1_CCMR_CCxS | TIM1_CCMR_ICxF ))) 
02224                            | (uint8_t)(( (TIM1_ICSelection)) | ((uint8_t)( TIM1_ICFilter << 4))));
02225   /* Select the Polarity */
02226   if (TIM1_ICPolarity != TIM1_ICPOLARITY_RISING)
02227   {
02228     TIM1->CCER1 |= TIM1_CCER1_CC2P;
02229   }
02230   else
02231   {
02232     TIM1->CCER1 &= (uint8_t)(~TIM1_CCER1_CC2P);
02233   }
02234   /* Set the CCE Bit */
02235   TIM1->CCER1 |=  TIM1_CCER1_CC2E;
02236 }
02237 
02238 /**
02239   * @brief  Configure the TI3 as Input.
02240   * @param  TIM1_ICPolarity  The Input Polarity.
02241   *         This parameter can be one of the following values:
02242   *                       - TIM1_ICPOLARITY_FALLING
02243   *                       - TIM1_ICPOLARITY_RISING
02244   * @param  TIM1_ICSelection specifies the input to be used.
02245   *         This parameter can be one of the following values:
02246   *                       - TIM1_ICSELECTION_DIRECTTI: TIM1 Input 3 is selected to
02247   *                         be connected to IC3.
02248   *                       - TIM1_ICSELECTION_INDIRECTTI: TIM1 Input 3 is selected to
02249   *                         be connected to IC4.
02250   * @param  TIM1_ICFilter Specifies the Input Capture Filter.
02251   *         This parameter must be a value between 0x00 and 0x0F.
02252   * @retval None
02253   */
02254 static void TI3_Config(uint8_t TIM1_ICPolarity,
02255                        uint8_t TIM1_ICSelection,
02256                        uint8_t TIM1_ICFilter)
02257 {
02258   /* Disable the Channel 3: Reset the CCE Bit */
02259   TIM1->CCER2 &=  (uint8_t)(~TIM1_CCER2_CC3E);
02260   
02261   /* Select the Input and set the filter */
02262   TIM1->CCMR3 = (uint8_t)((uint8_t)(TIM1->CCMR3 & (uint8_t)(~(uint8_t)( TIM1_CCMR_CCxS | TIM1_CCMR_ICxF))) 
02263                           | (uint8_t)(( (TIM1_ICSelection)) | ((uint8_t)( TIM1_ICFilter << 4))));
02264   
02265   /* Select the Polarity */
02266   if (TIM1_ICPolarity != TIM1_ICPOLARITY_RISING)
02267   {
02268     TIM1->CCER2 |= TIM1_CCER2_CC3P;
02269   }
02270   else
02271   {
02272     TIM1->CCER2 &= (uint8_t)(~TIM1_CCER2_CC3P);
02273   }
02274   /* Set the CCE Bit */
02275   TIM1->CCER2 |=  TIM1_CCER2_CC3E;
02276 }
02277 
02278 /**
02279   * @brief  Configure the TI4 as Input.
02280   * @param  TIM1_ICPolarity  The Input Polarity.
02281   *         This parameter can be one of the following values:
02282   *                       - TIM1_ICPOLARITY_FALLING
02283   *                       - TIM1_ICPOLARITY_RISING
02284   * @param  TIM1_ICSelection specifies the input to be used.
02285   *         This parameter can be one of the following values:
02286   *                       - TIM1_ICSELECTION_DIRECTTI: TIM1 Input 4 is selected to
02287   *                         be connected to IC4.
02288   *                       - TIM1_ICSELECTION_INDIRECTTI: TIM1 Input 4 is selected to
02289   *                         be connected to IC3.
02290   * @param  TIM1_ICFilter Specifies the Input Capture Filter.
02291   *         This parameter must be a value between 0x00 and 0x0F.
02292   * @retval None
02293   */
02294 static void TI4_Config(uint8_t TIM1_ICPolarity,
02295                        uint8_t TIM1_ICSelection,
02296                        uint8_t TIM1_ICFilter)
02297 {
02298   /* Disable the Channel 4: Reset the CCE Bit */
02299   TIM1->CCER2 &=  (uint8_t)(~TIM1_CCER2_CC4E);
02300   
02301   /* Select the Input and set the filter */
02302   TIM1->CCMR4 = (uint8_t)((uint8_t)(TIM1->CCMR4 & (uint8_t)(~(uint8_t)( TIM1_CCMR_CCxS | TIM1_CCMR_ICxF )))
02303                           | (uint8_t)(( (TIM1_ICSelection)) | ((uint8_t)( TIM1_ICFilter << 4))));
02304   
02305   /* Select the Polarity */
02306   if (TIM1_ICPolarity != TIM1_ICPOLARITY_RISING)
02307   {
02308     TIM1->CCER2 |= TIM1_CCER2_CC4P;
02309   }
02310   else
02311   {
02312     TIM1->CCER2 &= (uint8_t)(~TIM1_CCER2_CC4P);
02313   }
02314   
02315   /* Set the CCE Bit */
02316   TIM1->CCER2 |=  TIM1_CCER2_CC4E;
02317 }
02318 
02319 
02320 /**
02321   * @}
02322   */
02323   
02324 /**
02325   * @}
02326   */
02327   
02328 
02329 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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