STM8S/A Standard Peripherals Drivers: stm8s_clk.c Source File

STM8S/A

stm8s_clk.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm8s_clk.c
00004   * @author  MCD Application Team
00005   * @version V2.3.0
00006   * @date    16-June-2017
00007   * @brief   This file contains all the functions for the CLK peripheral.
00008    ******************************************************************************
00009   * @attention
00010   *
00011   * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
00012   *
00013   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
00014   * You may not use this file except in compliance with the License.
00015   * You may obtain a copy of the License at:
00016   *
00017   *        http://www.st.com/software_license_agreement_liberty_v2
00018   *
00019   * Unless required by applicable law or agreed to in writing, software 
00020   * distributed under the License is distributed on an "AS IS" BASIS, 
00021   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00022   * See the License for the specific language governing permissions and
00023   * limitations under the License.
00024   *
00025   ******************************************************************************
00026   */
00027 
00028 /* Includes ------------------------------------------------------------------*/
00029 
00030 #include "stm8s_clk.h"
00031 
00032 /** @addtogroup STM8S_StdPeriph_Driver
00033   * @{
00034   */
00035 /* Private typedef -----------------------------------------------------------*/
00036 /* Private define ------------------------------------------------------------*/
00037 /* Private macro -------------------------------------------------------------*/
00038 /* Private variables ---------------------------------------------------------*/
00039 /* Private function prototypes -----------------------------------------------*/
00040 
00041 /* Private Constants ---------------------------------------------------------*/
00042 
00043 /**
00044   * @addtogroup CLK_Private_Constants
00045   * @{
00046   */
00047 
00048 CONST uint8_t HSIDivFactor[4] = {1, 2, 4, 8}; /*!< Holds the different HSI Divider factors */
00049 CONST uint8_t CLKPrescTable[8] = {1, 2, 4, 8, 10, 16, 20, 40}; /*!< Holds the different CLK prescaler values */
00050 
00051 /**
00052   * @}
00053   */
00054 
00055 /* Public functions ----------------------------------------------------------*/
00056 /**
00057   * @addtogroup CLK_Public_Functions
00058   * @{
00059   */
00060 
00061 /**
00062   * @brief  Deinitializes the CLK peripheral registers to their default reset
00063   * values.
00064   * @param  None
00065   * @retval None
00066   * @par Warning:
00067   * Resetting the CCOR register: \n
00068   * When the CCOEN bit is set, the reset of the CCOR register require
00069   * two consecutive write instructions in order to reset first the CCOEN bit
00070   * and the second one is to reset the CCOSEL bits.
00071   */
00072 void CLK_DeInit(void)
00073 {
00074   CLK->ICKR = CLK_ICKR_RESET_VALUE;
00075   CLK->ECKR = CLK_ECKR_RESET_VALUE;
00076   CLK->SWR  = CLK_SWR_RESET_VALUE;
00077   CLK->SWCR = CLK_SWCR_RESET_VALUE;
00078   CLK->CKDIVR = CLK_CKDIVR_RESET_VALUE;
00079   CLK->PCKENR1 = CLK_PCKENR1_RESET_VALUE;
00080   CLK->PCKENR2 = CLK_PCKENR2_RESET_VALUE;
00081   CLK->CSSR = CLK_CSSR_RESET_VALUE;
00082   CLK->CCOR = CLK_CCOR_RESET_VALUE;
00083   while ((CLK->CCOR & CLK_CCOR_CCOEN)!= 0)
00084   {}
00085   CLK->CCOR = CLK_CCOR_RESET_VALUE;
00086   CLK->HSITRIMR = CLK_HSITRIMR_RESET_VALUE;
00087   CLK->SWIMCCR = CLK_SWIMCCR_RESET_VALUE;
00088 }
00089 
00090 /**
00091   * @brief   Configures the High Speed Internal oscillator (HSI).
00092   * @par Full description:
00093   * If CLK_FastHaltWakeup is enabled, HSI oscillator is automatically
00094   * switched-on (HSIEN=1) and selected as next clock master
00095   * (CKM=SWI=HSI) when resuming from HALT/ActiveHalt modes.\n
00096   * @param   NewState this parameter is the Wake-up Mode state.
00097   * @retval None
00098   */
00099 void CLK_FastHaltWakeUpCmd(FunctionalState NewState)
00100 {
00101   /* check the parameters */
00102   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00103   
00104   if (NewState != DISABLE)
00105   {
00106     /* Set FHWU bit (HSI oscillator is automatically switched-on) */
00107     CLK->ICKR |= CLK_ICKR_FHWU;
00108   }
00109   else  /* FastHaltWakeup = DISABLE */
00110   {
00111     /* Reset FHWU bit */
00112     CLK->ICKR &= (uint8_t)(~CLK_ICKR_FHWU);
00113   }
00114 }
00115 
00116 /**
00117   * @brief  Enable or Disable the External High Speed oscillator (HSE).
00118   * @param   NewState new state of HSEEN, value accepted ENABLE, DISABLE.
00119   * @retval None
00120   */
00121 void CLK_HSECmd(FunctionalState NewState)
00122 {
00123   /* Check the parameters */
00124   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00125   
00126   if (NewState != DISABLE)
00127   {
00128     /* Set HSEEN bit */
00129     CLK->ECKR |= CLK_ECKR_HSEEN;
00130   }
00131   else
00132   {
00133     /* Reset HSEEN bit */
00134     CLK->ECKR &= (uint8_t)(~CLK_ECKR_HSEEN);
00135   }
00136 }
00137 
00138 /**
00139   * @brief  Enables or disables the Internal High Speed oscillator (HSI).
00140   * @param   NewState new state of HSIEN, value accepted ENABLE, DISABLE.
00141   * @retval None
00142   */
00143 void CLK_HSICmd(FunctionalState NewState)
00144 {
00145   /* Check the parameters */
00146   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00147   
00148   if (NewState != DISABLE)
00149   {
00150     /* Set HSIEN bit */
00151     CLK->ICKR |= CLK_ICKR_HSIEN;
00152   }
00153   else
00154   {
00155     /* Reset HSIEN bit */
00156     CLK->ICKR &= (uint8_t)(~CLK_ICKR_HSIEN);
00157   }
00158 }
00159 
00160 /**
00161   * @brief  Enables or disables the Internal Low Speed oscillator (LSI).
00162   * @param  NewState new state of LSIEN, value accepted ENABLE, DISABLE.
00163   * @note   Before using the LSI clock you have to enable the option bytes (LSI_EN option bit is set).
00164   * @retval None
00165   */
00166 void CLK_LSICmd(FunctionalState NewState)
00167 {
00168   /* Check the parameters */
00169   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00170   
00171   if (NewState != DISABLE)
00172   {
00173     /* Set LSIEN bit */
00174     CLK->ICKR |= CLK_ICKR_LSIEN;
00175   }
00176   else
00177   {
00178     /* Reset LSIEN bit */
00179     CLK->ICKR &= (uint8_t)(~CLK_ICKR_LSIEN);
00180   }
00181 }
00182 
00183 /**
00184   * @brief  Enables or disablle the Configurable Clock Output (CCO).
00185   * @param   NewState : New state of CCEN bit (CCO register).
00186   * This parameter can be any of the @ref FunctionalState enumeration.
00187   * @retval None
00188   */
00189 void CLK_CCOCmd(FunctionalState NewState)
00190 {
00191   /* Check the parameters */
00192   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00193   
00194   if (NewState != DISABLE)
00195   {
00196     /* Set CCOEN bit */
00197     CLK->CCOR |= CLK_CCOR_CCOEN;
00198   }
00199   else
00200   {
00201     /* Reset CCOEN bit */
00202     CLK->CCOR &= (uint8_t)(~CLK_CCOR_CCOEN);
00203   }
00204 }
00205 
00206 /**
00207   * @brief  Starts or Stops manually the clock switch execution.
00208   * @par Full description:
00209   * NewState parameter set the SWEN.
00210   * @param   NewState new state of SWEN, value accepted ENABLE, DISABLE.
00211   * @retval None
00212   */
00213 void CLK_ClockSwitchCmd(FunctionalState NewState)
00214 {
00215   /* Check the parameters */
00216   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00217   
00218   if (NewState != DISABLE )
00219   {
00220     /* Enable the Clock Switch */
00221     CLK->SWCR |= CLK_SWCR_SWEN;
00222   }
00223   else
00224   {
00225     /* Disable the Clock Switch */
00226     CLK->SWCR &= (uint8_t)(~CLK_SWCR_SWEN);
00227   }
00228 }
00229 
00230 /**
00231   * @brief  Configures the slow active halt wake up
00232   * @param   NewState: specifies the Slow Active Halt wake up state.
00233   * can be set of the following values:
00234   * - DISABLE: Slow Active Halt mode disabled;
00235   * - ENABLE:  Slow Active Halt mode enabled.
00236   * @retval None
00237   */
00238 void CLK_SlowActiveHaltWakeUpCmd(FunctionalState NewState)
00239 {
00240   /* check the parameters */
00241   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00242   
00243   if (NewState != DISABLE)
00244   {
00245     /* Set S_ACTHALT bit */
00246     CLK->ICKR |= CLK_ICKR_SWUAH;
00247   }
00248   else
00249   {
00250     /* Reset S_ACTHALT bit */
00251     CLK->ICKR &= (uint8_t)(~CLK_ICKR_SWUAH);
00252   }
00253 }
00254 
00255 /**
00256   * @brief   Enables or disables the specified peripheral CLK.
00257   * @param   CLK_Peripheral : This parameter specifies the peripheral clock to gate.
00258   * This parameter can be any of the  @ref CLK_Peripheral_TypeDef enumeration.
00259   * @param   NewState : New state of specified peripheral clock.
00260   * This parameter can be any of the @ref FunctionalState enumeration.
00261   * @retval None
00262   */
00263 void CLK_PeripheralClockConfig(CLK_Peripheral_TypeDef CLK_Peripheral, FunctionalState NewState)
00264 {
00265   /* Check the parameters */
00266   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00267   assert_param(IS_CLK_PERIPHERAL_OK(CLK_Peripheral));
00268   
00269   if (((uint8_t)CLK_Peripheral & (uint8_t)0x10) == 0x00)
00270   {
00271     if (NewState != DISABLE)
00272     {
00273       /* Enable the peripheral Clock */
00274       CLK->PCKENR1 |= (uint8_t)((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F));
00275     }
00276     else
00277     {
00278       /* Disable the peripheral Clock */
00279       CLK->PCKENR1 &= (uint8_t)(~(uint8_t)(((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F))));
00280     }
00281   }
00282   else
00283   {
00284     if (NewState != DISABLE)
00285     {
00286       /* Enable the peripheral Clock */
00287       CLK->PCKENR2 |= (uint8_t)((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F));
00288     }
00289     else
00290     {
00291       /* Disable the peripheral Clock */
00292       CLK->PCKENR2 &= (uint8_t)(~(uint8_t)(((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F))));
00293     }
00294   }
00295 }
00296 
00297 /**
00298   * @brief  configures the Switch from one clock to another
00299   * @param   CLK_SwitchMode select the clock switch mode.
00300   * It can be set of the values of @ref CLK_SwitchMode_TypeDef
00301   * @param   CLK_NewClock choice of the future clock.
00302   * It can be set of the values of @ref CLK_Source_TypeDef
00303   * @param   ITState Enable or Disable the Clock Switch interrupt.
00304   * @param   CLK_CurrentClockState current clock to switch OFF or to keep ON.
00305   * It can be set of the values of @ref CLK_CurrentClockState_TypeDef
00306   * @note LSI selected as master clock source only if LSI_EN option bit is set.
00307   * @retval ErrorStatus this shows the clock switch status (ERROR/SUCCESS).
00308   */
00309 ErrorStatus CLK_ClockSwitchConfig(CLK_SwitchMode_TypeDef CLK_SwitchMode, CLK_Source_TypeDef CLK_NewClock, FunctionalState ITState, CLK_CurrentClockState_TypeDef CLK_CurrentClockState)
00310 {
00311   CLK_Source_TypeDef clock_master;
00312   uint16_t DownCounter = CLK_TIMEOUT;
00313   ErrorStatus Swif = ERROR;
00314   
00315   /* Check the parameters */
00316   assert_param(IS_CLK_SOURCE_OK(CLK_NewClock));
00317   assert_param(IS_CLK_SWITCHMODE_OK(CLK_SwitchMode));
00318   assert_param(IS_FUNCTIONALSTATE_OK(ITState));
00319   assert_param(IS_CLK_CURRENTCLOCKSTATE_OK(CLK_CurrentClockState));
00320   
00321   /* Current clock master saving */
00322   clock_master = (CLK_Source_TypeDef)CLK->CMSR;
00323   
00324   /* Automatic switch mode management */
00325   if (CLK_SwitchMode == CLK_SWITCHMODE_AUTO)
00326   {
00327     /* Enables Clock switch */
00328     CLK->SWCR |= CLK_SWCR_SWEN;
00329     
00330     /* Enables or Disables Switch interrupt */
00331     if (ITState != DISABLE)
00332     {
00333       CLK->SWCR |= CLK_SWCR_SWIEN;
00334     }
00335     else
00336     {
00337       CLK->SWCR &= (uint8_t)(~CLK_SWCR_SWIEN);
00338     }
00339     
00340     /* Selection of the target clock source */
00341     CLK->SWR = (uint8_t)CLK_NewClock;
00342     
00343     /* Wait until the target clock source is ready */
00344     while((((CLK->SWCR & CLK_SWCR_SWBSY) != 0 )&& (DownCounter != 0)))
00345     {
00346       DownCounter--;
00347     }
00348     
00349     if(DownCounter != 0)
00350     {
00351       Swif = SUCCESS;
00352     }
00353     else
00354     {
00355       Swif = ERROR;
00356     }
00357   }
00358   else /* CLK_SwitchMode == CLK_SWITCHMODE_MANUAL */
00359   {
00360     /* Enables or Disables Switch interrupt  if required  */
00361     if (ITState != DISABLE)
00362     {
00363       CLK->SWCR |= CLK_SWCR_SWIEN;
00364     }
00365     else
00366     {
00367       CLK->SWCR &= (uint8_t)(~CLK_SWCR_SWIEN);
00368     }
00369     
00370     /* Selection of the target clock source */
00371     CLK->SWR = (uint8_t)CLK_NewClock;
00372     
00373     /* Wait until the target clock source is ready */
00374     while((((CLK->SWCR & CLK_SWCR_SWIF) != 0 ) && (DownCounter != 0)))
00375     {
00376       DownCounter--;
00377     }
00378     
00379     if(DownCounter != 0)
00380     {
00381       /* Enables Clock switch */
00382       CLK->SWCR |= CLK_SWCR_SWEN;
00383       Swif = SUCCESS;
00384     }
00385     else
00386     {
00387       Swif = ERROR;
00388     }
00389   }
00390   if(Swif != ERROR)
00391   {
00392     /* Switch OFF current clock if required */
00393     if((CLK_CurrentClockState == CLK_CURRENTCLOCKSTATE_DISABLE) && ( clock_master == CLK_SOURCE_HSI))
00394     {
00395       CLK->ICKR &= (uint8_t)(~CLK_ICKR_HSIEN);
00396     }
00397     else if((CLK_CurrentClockState == CLK_CURRENTCLOCKSTATE_DISABLE) && ( clock_master == CLK_SOURCE_LSI))
00398     {
00399       CLK->ICKR &= (uint8_t)(~CLK_ICKR_LSIEN);
00400     }
00401     else if ((CLK_CurrentClockState == CLK_CURRENTCLOCKSTATE_DISABLE) && ( clock_master == CLK_SOURCE_HSE))
00402     {
00403       CLK->ECKR &= (uint8_t)(~CLK_ECKR_HSEEN);
00404     }
00405   }
00406   return(Swif);
00407 }
00408 
00409 /**
00410   * @brief  Configures the HSI clock dividers.
00411   * @param   HSIPrescaler : Specifies the HSI clock divider to apply.
00412   * This parameter can be any of the @ref CLK_Prescaler_TypeDef enumeration.
00413   * @retval None
00414   */
00415 void CLK_HSIPrescalerConfig(CLK_Prescaler_TypeDef HSIPrescaler)
00416 {
00417   /* check the parameters */
00418   assert_param(IS_CLK_HSIPRESCALER_OK(HSIPrescaler));
00419   
00420   /* Clear High speed internal clock prescaler */
00421   CLK->CKDIVR &= (uint8_t)(~CLK_CKDIVR_HSIDIV);
00422   
00423   /* Set High speed internal clock prescaler */
00424   CLK->CKDIVR |= (uint8_t)HSIPrescaler;
00425 }
00426 
00427 /**
00428   * @brief  Output the selected clock on a dedicated I/O pin.
00429   * @param   CLK_CCO : Specifies the clock source.
00430   * This parameter can be any of the  @ref CLK_Output_TypeDef enumeration.
00431   * @retval None
00432   * @par Required preconditions:
00433   * The dedicated I/O pin must be set at 1 in the corresponding Px_CR1 register \n
00434   * to be set as input with pull-up or push-pull output.
00435   */
00436 void CLK_CCOConfig(CLK_Output_TypeDef CLK_CCO)
00437 {
00438   /* check the parameters */
00439   assert_param(IS_CLK_OUTPUT_OK(CLK_CCO));
00440   
00441   /* Clears of the CCO type bits part */
00442   CLK->CCOR &= (uint8_t)(~CLK_CCOR_CCOSEL);
00443   
00444   /* Selects the source provided on cco_ck output */
00445   CLK->CCOR |= (uint8_t)CLK_CCO;
00446   
00447   /* Enable the clock output */
00448   CLK->CCOR |= CLK_CCOR_CCOEN;
00449 }
00450 
00451 /**
00452   * @brief   Enables or disables the specified CLK interrupts.
00453   * @param   CLK_IT This parameter specifies the interrupt sources.
00454   * It can be one of the values of @ref CLK_IT_TypeDef.
00455   * @param   NewState New state of the Interrupt.
00456   * Value accepted ENABLE, DISABLE.
00457   * @retval None
00458   */
00459 void CLK_ITConfig(CLK_IT_TypeDef CLK_IT, FunctionalState NewState)
00460 {
00461   /* check the parameters */
00462   assert_param(IS_FUNCTIONALSTATE_OK(NewState));
00463   assert_param(IS_CLK_IT_OK(CLK_IT));
00464   
00465   if (NewState != DISABLE)
00466   {
00467     switch (CLK_IT)
00468     {
00469     case CLK_IT_SWIF: /* Enable the clock switch interrupt */
00470       CLK->SWCR |= CLK_SWCR_SWIEN;
00471       break;
00472     case CLK_IT_CSSD: /* Enable the clock security system detection interrupt */
00473       CLK->CSSR |= CLK_CSSR_CSSDIE;
00474       break;
00475     default:
00476       break;
00477     }
00478   }
00479   else  /*(NewState == DISABLE)*/
00480   {
00481     switch (CLK_IT)
00482     {
00483     case CLK_IT_SWIF: /* Disable the clock switch interrupt */
00484       CLK->SWCR  &= (uint8_t)(~CLK_SWCR_SWIEN);
00485       break;
00486     case CLK_IT_CSSD: /* Disable the clock security system detection interrupt */
00487       CLK->CSSR &= (uint8_t)(~CLK_CSSR_CSSDIE);
00488       break;
00489     default:
00490       break;
00491     }
00492   }
00493 }
00494 
00495 /**
00496   * @brief  Configures the HSI and CPU clock dividers.
00497   * @param  CLK_Prescaler Specifies the HSI or CPU clock divider to apply.
00498   * @retval None
00499   */
00500 void CLK_SYSCLKConfig(CLK_Prescaler_TypeDef CLK_Prescaler)
00501 {
00502   /* check the parameters */
00503   assert_param(IS_CLK_PRESCALER_OK(CLK_Prescaler));
00504   
00505   if (((uint8_t)CLK_Prescaler & (uint8_t)0x80) == 0x00) /* Bit7 = 0 means HSI divider */
00506   {
00507     CLK->CKDIVR &= (uint8_t)(~CLK_CKDIVR_HSIDIV);
00508     CLK->CKDIVR |= (uint8_t)((uint8_t)CLK_Prescaler & (uint8_t)CLK_CKDIVR_HSIDIV);
00509   }
00510   else /* Bit7 = 1 means CPU divider */
00511   {
00512     CLK->CKDIVR &= (uint8_t)(~CLK_CKDIVR_CPUDIV);
00513     CLK->CKDIVR |= (uint8_t)((uint8_t)CLK_Prescaler & (uint8_t)CLK_CKDIVR_CPUDIV);
00514   }
00515 }
00516 
00517 /**
00518   * @brief  Configures the SWIM clock frequency on the fly.
00519   * @param   CLK_SWIMDivider Specifies the SWIM clock divider to apply.
00520   * can be one of the value of @ref CLK_SWIMDivider_TypeDef
00521   * @retval None
00522   */
00523 void CLK_SWIMConfig(CLK_SWIMDivider_TypeDef CLK_SWIMDivider)
00524 {
00525   /* check the parameters */
00526   assert_param(IS_CLK_SWIMDIVIDER_OK(CLK_SWIMDivider));
00527   
00528   if (CLK_SWIMDivider != CLK_SWIMDIVIDER_2)
00529   {
00530     /* SWIM clock is not divided by 2 */
00531     CLK->SWIMCCR |= CLK_SWIMCCR_SWIMDIV;
00532   }
00533   else /* CLK_SWIMDivider == CLK_SWIMDIVIDER_2 */
00534   {
00535     /* SWIM clock is divided by 2 */
00536     CLK->SWIMCCR &= (uint8_t)(~CLK_SWIMCCR_SWIMDIV);
00537   }
00538 }
00539 
00540 /**
00541   * @brief  Enables the Clock Security System.
00542   * @par Full description:
00543   * once CSS is enabled it cannot be disabled until the next reset.
00544   * @param  None
00545   * @retval None
00546   */
00547 void CLK_ClockSecuritySystemEnable(void)
00548 {
00549   /* Set CSSEN bit */
00550   CLK->CSSR |= CLK_CSSR_CSSEN;
00551 }
00552 
00553 /**
00554   * @brief  Returns the clock source used as system clock.
00555   * @param  None
00556   * @retval  Clock source used.
00557   * can be one of the values of @ref CLK_Source_TypeDef
00558   */
00559 CLK_Source_TypeDef CLK_GetSYSCLKSource(void)
00560 {
00561   return((CLK_Source_TypeDef)CLK->CMSR);
00562 }
00563 
00564 /**
00565   * @brief  This function returns the frequencies of different on chip clocks.
00566   * @param  None
00567   * @retval the master clock frequency
00568   */
00569 uint32_t CLK_GetClockFreq(void)
00570 {
00571   uint32_t clockfrequency = 0;
00572   CLK_Source_TypeDef clocksource = CLK_SOURCE_HSI;
00573   uint8_t tmp = 0, presc = 0;
00574   
00575   /* Get CLK source. */
00576   clocksource = (CLK_Source_TypeDef)CLK->CMSR;
00577   
00578   if (clocksource == CLK_SOURCE_HSI)
00579   {
00580     tmp = (uint8_t)(CLK->CKDIVR & CLK_CKDIVR_HSIDIV);
00581     tmp = (uint8_t)(tmp >> 3);
00582     presc = HSIDivFactor[tmp];
00583     clockfrequency = HSI_VALUE / presc;
00584   }
00585   else if ( clocksource == CLK_SOURCE_LSI)
00586   {
00587     clockfrequency = LSI_VALUE;
00588   }
00589   else
00590   {
00591     clockfrequency = HSE_VALUE;
00592   }
00593   
00594   return((uint32_t)clockfrequency);
00595 }
00596 
00597 /**
00598   * @brief  Adjusts the Internal High Speed oscillator (HSI) calibration value.
00599   * @par Full description:
00600   * @param   CLK_HSICalibrationValue calibration trimming value.
00601   * can be one of the values of @ref CLK_HSITrimValue_TypeDef
00602   * @retval None
00603   */
00604 void CLK_AdjustHSICalibrationValue(CLK_HSITrimValue_TypeDef CLK_HSICalibrationValue)
00605 {
00606   /* check the parameters */
00607   assert_param(IS_CLK_HSITRIMVALUE_OK(CLK_HSICalibrationValue));
00608   
00609   /* Store the new value */
00610   CLK->HSITRIMR = (uint8_t)( (uint8_t)(CLK->HSITRIMR & (uint8_t)(~CLK_HSITRIMR_HSITRIM))|((uint8_t)CLK_HSICalibrationValue));
00611 }
00612 
00613 /**
00614   * @brief  Reset the SWBSY flag (SWICR Register)
00615   * @par Full description:
00616   * This function reset SWBSY flag in order to reset clock switch operations (target
00617   * oscillator is broken, stabilization is longing too much, etc.).  If at the same time \n
00618   * software attempts to set SWEN and clear SWBSY, SWBSY action takes precedence.
00619   * @param  None
00620   * @retval None
00621   */
00622 void CLK_SYSCLKEmergencyClear(void)
00623 {
00624   CLK->SWCR &= (uint8_t)(~CLK_SWCR_SWBSY);
00625 }
00626 
00627 /**
00628   * @brief  Checks whether the specified CLK flag is set or not.
00629   * @par Full description:
00630   * @param   CLK_FLAG Flag to check.
00631   * can be one of the values of @ref CLK_Flag_TypeDef
00632   * @retval FlagStatus, status of the checked flag
00633   */
00634 FlagStatus CLK_GetFlagStatus(CLK_Flag_TypeDef CLK_FLAG)
00635 {
00636   uint16_t statusreg = 0;
00637   uint8_t tmpreg = 0;
00638   FlagStatus bitstatus = RESET;
00639   
00640   /* check the parameters */
00641   assert_param(IS_CLK_FLAG_OK(CLK_FLAG));
00642   
00643   /* Get the CLK register index */
00644   statusreg = (uint16_t)((uint16_t)CLK_FLAG & (uint16_t)0xFF00);
00645   
00646   
00647   if (statusreg == 0x0100) /* The flag to check is in ICKRregister */
00648   {
00649     tmpreg = CLK->ICKR;
00650   }
00651   else if (statusreg == 0x0200) /* The flag to check is in ECKRregister */
00652   {
00653     tmpreg = CLK->ECKR;
00654   }
00655   else if (statusreg == 0x0300) /* The flag to check is in SWIC register */
00656   {
00657     tmpreg = CLK->SWCR;
00658   }
00659   else if (statusreg == 0x0400) /* The flag to check is in CSS register */
00660   {
00661     tmpreg = CLK->CSSR;
00662   }
00663   else /* The flag to check is in CCO register */
00664   {
00665     tmpreg = CLK->CCOR;
00666   }
00667   
00668   if ((tmpreg & (uint8_t)CLK_FLAG) != (uint8_t)RESET)
00669   {
00670     bitstatus = SET;
00671   }
00672   else
00673   {
00674     bitstatus = RESET;
00675   }
00676   
00677   /* Return the flag status */
00678   return((FlagStatus)bitstatus);
00679 }
00680 
00681 /**
00682   * @brief  Checks whether the specified CLK interrupt has is enabled or not.
00683   * @param   CLK_IT specifies the CLK interrupt.
00684   * can be one of the values of @ref CLK_IT_TypeDef
00685   * @retval ITStatus, new state of CLK_IT (SET or RESET).
00686   */
00687 ITStatus CLK_GetITStatus(CLK_IT_TypeDef CLK_IT)
00688 {
00689   ITStatus bitstatus = RESET;
00690   
00691   /* check the parameters */
00692   assert_param(IS_CLK_IT_OK(CLK_IT));
00693   
00694   if (CLK_IT == CLK_IT_SWIF)
00695   {
00696     /* Check the status of the clock switch interrupt */
00697     if ((CLK->SWCR & (uint8_t)CLK_IT) == (uint8_t)0x0C)
00698     {
00699       bitstatus = SET;
00700     }
00701     else
00702     {
00703       bitstatus = RESET;
00704     }
00705   }
00706   else /* CLK_IT == CLK_IT_CSSDIE */
00707   {
00708     /* Check the status of the security system detection interrupt */
00709     if ((CLK->CSSR & (uint8_t)CLK_IT) == (uint8_t)0x0C)
00710     {
00711       bitstatus = SET;
00712     }
00713     else
00714     {
00715       bitstatus = RESET;
00716     }
00717   }
00718   
00719   /* Return the CLK_IT status */
00720   return bitstatus;
00721 }
00722 
00723 /**
00724   * @brief  Clears the CLK�s interrupt pending bits.
00725   * @param   CLK_IT specifies the interrupt pending bits.
00726   * can be one of the values of @ref CLK_IT_TypeDef
00727   * @retval None
00728   */
00729 void CLK_ClearITPendingBit(CLK_IT_TypeDef CLK_IT)
00730 {
00731   /* check the parameters */
00732   assert_param(IS_CLK_IT_OK(CLK_IT));
00733   
00734   if (CLK_IT == (uint8_t)CLK_IT_CSSD)
00735   {
00736     /* Clear the status of the security system detection interrupt */
00737     CLK->CSSR &= (uint8_t)(~CLK_CSSR_CSSD);
00738   }
00739   else /* CLK_PendingBit == (uint8_t)CLK_IT_SWIF */
00740   {
00741     /* Clear the status of the clock switch interrupt */
00742     CLK->SWCR &= (uint8_t)(~CLK_SWCR_SWIF);
00743   }
00744   
00745 }
00746 
00747 /**
00748   * @}
00749   */
00750   
00751 /**
00752   * @}
00753   */
00754   
00755 
00756 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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