I2C_Exported_Types

Enumerations
enum	I2C_Ack_TypeDef { I2C_ACK_NONE = (uint8_t)0x00, I2C_ACK_CURR = (uint8_t)0x01, I2C_ACK_NEXT = (uint8_t)0x02 }
	I2C Acknowledgement configuration. More...
enum	I2C_AddMode_TypeDef { I2C_ADDMODE_7BIT = (uint8_t)0x00, I2C_ADDMODE_10BIT = (uint8_t)0x80 }
	I2C Addressing Mode (slave mode only) More...
enum	I2C_Direction_TypeDef { I2C_DIRECTION_TX = (uint8_t)0x00, I2C_DIRECTION_RX = (uint8_t)0x01 }
	I2C transfer direction Warning: the values correspond to the ADD0 bit position in the OARL register. More...
enum	I2C_DutyCycle_TypeDef { I2C_DUTYCYCLE_2 = (uint8_t)0x00, I2C_DUTYCYCLE_16_9 = (uint8_t)0x40 }
	I2C duty cycle (fast mode only) More...
enum	I2C_Event_TypeDef {   I2C_EVENT_MASTER_MODE_SELECT = (uint16_t)0x0301, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED = (uint16_t)0x0782, I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED = (uint16_t)0x0302, I2C_EVENT_MASTER_MODE_ADDRESS10 = (uint16_t)0x0308,   I2C_EVENT_MASTER_BYTE_RECEIVED = (uint16_t)0x0340, I2C_EVENT_MASTER_BYTE_TRANSMITTING = (uint16_t)0x0780, I2C_EVENT_MASTER_BYTE_TRANSMITTED = (uint16_t)0x0784, I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED = (uint16_t)0x0202,   I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED = (uint16_t)0x0682, I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED = (uint16_t)0x1200, I2C_EVENT_SLAVE_BYTE_RECEIVED = (uint16_t)0x0240, I2C_EVENT_SLAVE_STOP_DETECTED = (uint16_t)0x0010,   I2C_EVENT_SLAVE_BYTE_TRANSMITTED = (uint16_t)0x0684, I2C_EVENT_SLAVE_BYTE_TRANSMITTING = (uint16_t)0x0680, I2C_EVENT_SLAVE_ACK_FAILURE = (uint16_t)0x0004 }
	I2C possible events Values convention: 0xXXYY XX = Event SR3 corresponding value YY = Event SR1 corresponding value. More...
enum	I2C_Flag_TypeDef {   I2C_FLAG_TXEMPTY = (uint16_t)0x0180, I2C_FLAG_RXNOTEMPTY = (uint16_t)0x0140, I2C_FLAG_STOPDETECTION = (uint16_t)0x0110, I2C_FLAG_HEADERSENT = (uint16_t)0x0108,   I2C_FLAG_TRANSFERFINISHED = (uint16_t)0x0104, I2C_FLAG_ADDRESSSENTMATCHED = (uint16_t)0x0102, I2C_FLAG_STARTDETECTION = (uint16_t)0x0101, I2C_FLAG_WAKEUPFROMHALT = (uint16_t)0x0220,   I2C_FLAG_OVERRUNUNDERRUN = (uint16_t)0x0208, I2C_FLAG_ACKNOWLEDGEFAILURE = (uint16_t)0x0204, I2C_FLAG_ARBITRATIONLOSS = (uint16_t)0x0202, I2C_FLAG_BUSERROR = (uint16_t)0x0201,   I2C_FLAG_GENERALCALL = (uint16_t)0x0310, I2C_FLAG_TRANSMITTERRECEIVER = (uint16_t)0x0304, I2C_FLAG_BUSBUSY = (uint16_t)0x0302, I2C_FLAG_MASTERSLAVE = (uint16_t)0x0301 }
	I2C Flags. More...
enum	I2C_IT_TypeDef { I2C_IT_ERR = (uint8_t)0x01, I2C_IT_EVT = (uint8_t)0x02, I2C_IT_BUF = (uint8_t)0x04 }
	I2C Interrupt sources Warning: the values correspond to the bit position in the ITR register. More...
enum	I2C_ITPendingBit_TypeDef {   I2C_ITPENDINGBIT_TXEMPTY = (uint16_t)0x1680, I2C_ITPENDINGBIT_RXNOTEMPTY = (uint16_t)0x1640, I2C_ITPENDINGBIT_STOPDETECTION = (uint16_t)0x1210, I2C_ITPENDINGBIT_HEADERSENT = (uint16_t)0x1208,   I2C_ITPENDINGBIT_TRANSFERFINISHED = (uint16_t)0x1204, I2C_ITPENDINGBIT_ADDRESSSENTMATCHED = (uint16_t)0x1202, I2C_ITPENDINGBIT_STARTDETECTION = (uint16_t)0x1201, I2C_ITPENDINGBIT_WAKEUPFROMHALT = (uint16_t)0x2220,   I2C_ITPENDINGBIT_OVERRUNUNDERRUN = (uint16_t)0x2108, I2C_ITPENDINGBIT_ACKNOWLEDGEFAILURE = (uint16_t)0x2104, I2C_ITPENDINGBIT_ARBITRATIONLOSS = (uint16_t)0x2102, I2C_ITPENDINGBIT_BUSERROR = (uint16_t)0x2101 }
	I2C Pending bits Elements values convention: 0xXYZZ X = SRx registers index X = 1 : SR1 X = 2 : SR2 Y = Position of the corresponding Interrupt ZZ = flag mask in the dedicated register(X register) More...

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Enumeration Type Documentation

enum I2C_Ack_TypeDef

I2C Acknowledgement configuration.

Enumerator:

I2C_ACK_NONE	No acknowledge
I2C_ACK_CURR	Acknowledge on the current byte
I2C_ACK_NEXT	Acknowledge on the next byte

Definition at line 53 of file stm8s_i2c.h.

enum I2C_AddMode_TypeDef

I2C Addressing Mode (slave mode only)

Enumerator:

I2C_ADDMODE_7BIT	7-bit slave address (10-bit address not acknowledged)
I2C_ADDMODE_10BIT	10-bit slave address (7-bit address not acknowledged)

Definition at line 63 of file stm8s_i2c.h.

enum I2C_Direction_TypeDef

I2C transfer direction Warning: the values correspond to the ADD0 bit position in the OARL register.

Enumerator:

I2C_DIRECTION_TX	Transmission direction
I2C_DIRECTION_RX	Reception direction

Definition at line 84 of file stm8s_i2c.h.

enum I2C_DutyCycle_TypeDef

I2C duty cycle (fast mode only)

Enumerator:

I2C_DUTYCYCLE_2	Fast mode Tlow/THigh = 2
I2C_DUTYCYCLE_16_9	Fast mode Tlow/Thigh = 16/9

Definition at line 44 of file stm8s_i2c.h.

enum I2C_Event_TypeDef

I2C possible events Values convention: 0xXXYY XX = Event SR3 corresponding value YY = Event SR1 corresponding value.

Note:

if Event = EV3_2 the rule above does not apply YY = Event SR2 corresponding value

Enumerator:

I2C_EVENT_MASTER_MODE_SELECT	Communication start. After sending the START condition (I2C_GenerateSTART() function) the master has to wait for this event. It means that the Start condition has been correctly released on the I2C bus (the bus is free, no other devices is communicating). BUSY, MSL and SB flag
I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED	Address Acknowledge. After checking on EV5 (start condition correctly released on the bus), the master sends the address of the slave(s) with which it will communicate (I2C_Send7bitAddress() function, it also determines the direction of the communication: Master transmitter or Receiver). Then the master has to wait that a slave acknowledges his address. If an acknowledge is sent on the bus, one of the following events will be set: 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED event is set. 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED is set 3) In case of 10-Bit addressing mode, the master (just after generating the START and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData() function). Then master should wait on EV9. It means that the 10-bit addressing header has been correctly sent on the bus. Then master should send the second part of the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master should wait for event EV6. BUSY, MSL, ADDR, TXE and TRA flags
I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED	BUSY, MSL and ADDR flags
I2C_EVENT_MASTER_MODE_ADDRESS10	BUSY, MSL and ADD10 flags
I2C_EVENT_MASTER_BYTE_RECEIVED	Communication events. If a communication is established (START condition generated and slave address acknowledged) then the master has to check on one of the following events for communication procedures: 1) Master Receiver mode: The master has to wait on the event EV7 then to read the data received from the slave (I2C_ReceiveData() function). 2) Master Transmitter mode: The master has to send data (I2C_SendData() function) then to wait on event EV8 or EV8_2. These two events are similar: EV8 means that the data has been written in the data register and is being shifted out. EV8_2 means that the data has been physically shifted out and output on the bus. In most cases, using EV8 is sufficient for the application. Using EV8_2 leads to a slower communication but ensures more reliable test. EV8_2 is also more suitable than EV8 for testing on the last data transmission (before Stop condition generation). Note: In case the user software does not guarantee that this event EV7 is managed before the current byte end of transfer, then user may check on EV7 and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)). In this case the communication may be slower. BUSY, MSL and RXNE flags
I2C_EVENT_MASTER_BYTE_TRANSMITTING	TRA, BUSY, MSL, TXE flags
I2C_EVENT_MASTER_BYTE_TRANSMITTED	EV8_2: TRA, BUSY, MSL, TXE and BTF flags
I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED	Communication start events. Wait on one of these events at the start of the communication. It means that the I2C peripheral detected a Start condition on the bus (generated by master device) followed by the peripheral address. The peripheral generates an ACK condition on the bus (if the acknowledge feature is enabled through function I2C_AcknowledgeConfig()) and the events listed above are set : 1) In normal case (only one address managed by the slave), when the address sent by the master matches the own address of the peripheral (configured by I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set (where XXX could be TRANSMITTER or RECEIVER). 2) In case the address sent by the master is General Call (address 0x00) and if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. BUSY and ADDR flags
I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED	TRA, BUSY, TXE and ADDR flags
I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED	EV2: GENCALL and BUSY flags
I2C_EVENT_SLAVE_BYTE_RECEIVED	Communication events. Wait on one of these events when EV1 has already been checked : Slave RECEIVER mode: EV2: When the application is expecting a data byte to be received. EV4: When the application is expecting the end of the communication: master sends a stop condition and data transmission is stopped. Slave Transmitter mode: EV3: When a byte has been transmitted by the slave and the application is expecting the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be used when the user software doesn't guarantee the EV3 is managed before the current byte end of transfer. EV3_2: When the master sends a NACK in order to tell slave that data transmission shall end (before sending the STOP condition). In this case slave has to stop sending data bytes and expect a Stop condition on the bus. Note: In case the user software does not guarantee that the event EV2 is managed before the current byte end of transfer, then user may check on EV2 and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)). In this case the communication may be slower. BUSY and RXNE flags
I2C_EVENT_SLAVE_STOP_DETECTED	STOPF flag
I2C_EVENT_SLAVE_BYTE_TRANSMITTED	TRA, BUSY, TXE and BTF flags
I2C_EVENT_SLAVE_BYTE_TRANSMITTING	TRA, BUSY and TXE flags
I2C_EVENT_SLAVE_ACK_FAILURE	AF flag

Definition at line 163 of file stm8s_i2c.h.

enum I2C_Flag_TypeDef

I2C Flags.

Elements values convention: 0xXXYY X = SRx registers index X = 1 : SR1 X = 2 : SR2 X = 3 : SR3 Y = Flag mask in the register

Enumerator:

I2C_FLAG_TXEMPTY	Transmit Data Register Empty flag
I2C_FLAG_RXNOTEMPTY	Read Data Register Not Empty flag
I2C_FLAG_STOPDETECTION	Stop detected flag
I2C_FLAG_HEADERSENT	10-bit Header sent flag
I2C_FLAG_TRANSFERFINISHED	Data Byte Transfer Finished flag
I2C_FLAG_ADDRESSSENTMATCHED	Address Sent/Matched (master/slave) flag
I2C_FLAG_STARTDETECTION	Start bit sent flag
I2C_FLAG_WAKEUPFROMHALT	Wake Up From Halt Flag
I2C_FLAG_OVERRUNUNDERRUN	Overrun/Underrun flag
I2C_FLAG_ACKNOWLEDGEFAILURE	Acknowledge Failure Flag
I2C_FLAG_ARBITRATIONLOSS	Arbitration Loss Flag
I2C_FLAG_BUSERROR	Misplaced Start or Stop condition
I2C_FLAG_GENERALCALL	General Call header received Flag
I2C_FLAG_TRANSMITTERRECEIVER	Transmitter Receiver Flag
I2C_FLAG_BUSBUSY	Bus Busy Flag
I2C_FLAG_MASTERSLAVE	Master Slave Flag

Definition at line 100 of file stm8s_i2c.h.

enum I2C_IT_TypeDef

I2C Interrupt sources Warning: the values correspond to the bit position in the ITR register.

Enumerator:

I2C_IT_ERR	Error Interruption
I2C_IT_EVT	Event Interruption
I2C_IT_BUF	Buffer Interruption

Definition at line 73 of file stm8s_i2c.h.

enum I2C_ITPendingBit_TypeDef

I2C Pending bits Elements values convention: 0xXYZZ X = SRx registers index X = 1 : SR1 X = 2 : SR2 Y = Position of the corresponding Interrupt ZZ = flag mask in the dedicated register(X register)

Enumerator:

I2C_ITPENDINGBIT_TXEMPTY	Transmit Data Register Empty
I2C_ITPENDINGBIT_RXNOTEMPTY	Read Data Register Not Empty
I2C_ITPENDINGBIT_STOPDETECTION	Stop detected
I2C_ITPENDINGBIT_HEADERSENT	10-bit Header sent
I2C_ITPENDINGBIT_TRANSFERFINISHED	Data Byte Transfer Finished
I2C_ITPENDINGBIT_ADDRESSSENTMATCHED	Address Sent/Matched (master/slave)
I2C_ITPENDINGBIT_STARTDETECTION	Start bit sent
I2C_ITPENDINGBIT_WAKEUPFROMHALT	Wake Up From Halt
I2C_ITPENDINGBIT_OVERRUNUNDERRUN	Overrun/Underrun
I2C_ITPENDINGBIT_ACKNOWLEDGEFAILURE	Acknowledge Failure
I2C_ITPENDINGBIT_ARBITRATIONLOSS	Arbitration Loss
I2C_ITPENDINGBIT_BUSERROR	Misplaced Start or Stop condition

Definition at line 135 of file stm8s_i2c.h.