STM8S/A Standard Peripherals Drivers: ADC1_Exported_Types

STM8S/A

STM8S/A Standard Peripherals Drivers
ADC1_Exported_Types

Enumerations

enum  ADC1_Align_TypeDef { ADC1_ALIGN_LEFT = (uint8_t)0x00, ADC1_ALIGN_RIGHT = (uint8_t)0x08 }
 ADC1 data alignment. More...
enum  ADC1_Channel_TypeDef {
  ADC1_CHANNEL_0 = (uint8_t)0x00, ADC1_CHANNEL_1 = (uint8_t)0x01, ADC1_CHANNEL_2 = (uint8_t)0x02, ADC1_CHANNEL_3 = (uint8_t)0x03,
  ADC1_CHANNEL_4 = (uint8_t)0x04, ADC1_CHANNEL_5 = (uint8_t)0x05, ADC1_CHANNEL_6 = (uint8_t)0x06, ADC1_CHANNEL_7 = (uint8_t)0x07,
  ADC1_CHANNEL_8 = (uint8_t)0x08, ADC1_CHANNEL_9 = (uint8_t)0x09, ADC1_CHANNEL_12 = (uint8_t)0x0C
}
 ADC1 analog channel selection. More...
enum  ADC1_ConvMode_TypeDef { ADC1_CONVERSIONMODE_SINGLE = (uint8_t)0x00, ADC1_CONVERSIONMODE_CONTINUOUS = (uint8_t)0x01 }
 ADC1 conversion mode selection. More...
enum  ADC1_ExtTrig_TypeDef { ADC1_EXTTRIG_TIM = (uint8_t)0x00, ADC1_EXTTRIG_GPIO = (uint8_t)0x10 }
 ADC1 External conversion trigger event selection. More...
enum  ADC1_Flag_TypeDef {
  ADC1_FLAG_OVR = (uint8_t)0x41, ADC1_FLAG_AWD = (uint8_t)0x40, ADC1_FLAG_AWS0 = (uint8_t)0x10, ADC1_FLAG_AWS1 = (uint8_t)0x11,
  ADC1_FLAG_AWS2 = (uint8_t)0x12, ADC1_FLAG_AWS3 = (uint8_t)0x13, ADC1_FLAG_AWS4 = (uint8_t)0x14, ADC1_FLAG_AWS5 = (uint8_t)0x15,
  ADC1_FLAG_AWS6 = (uint8_t)0x16, ADC1_FLAG_AWS7 = (uint8_t)0x17, ADC1_FLAG_AWS8 = (uint8_t)0x18, ADC1_FLAG_AWS9 = (uint8_t)0x19,
  ADC1_FLAG_AWS12 = (uint8_t)0x1C, ADC1_FLAG_EOC = (uint8_t)0x80
}
 ADC1 Flags. More...
enum  ADC1_IT_TypeDef {
  ADC1_IT_AWDIE = (uint16_t)0x010, ADC1_IT_EOCIE = (uint16_t)0x020, ADC1_IT_AWD = (uint16_t)0x140, ADC1_IT_AWS0 = (uint16_t)0x110,
  ADC1_IT_AWS1 = (uint16_t)0x111, ADC1_IT_AWS2 = (uint16_t)0x112, ADC1_IT_AWS3 = (uint16_t)0x113, ADC1_IT_AWS4 = (uint16_t)0x114,
  ADC1_IT_AWS5 = (uint16_t)0x115, ADC1_IT_AWS6 = (uint16_t)0x116, ADC1_IT_AWS7 = (uint16_t)0x117, ADC1_IT_AWS8 = (uint16_t)0x118,
  ADC1_IT_AWS9 = (uint16_t)0x119, ADC1_IT_AWS12 = (uint16_t)0x11C, ADC1_IT_EOC = (uint16_t)0x080
}
 ADC1 Interrupt source. More...
enum  ADC1_PresSel_TypeDef {
  ADC1_PRESSEL_FCPU_D2 = (uint8_t)0x00, ADC1_PRESSEL_FCPU_D3 = (uint8_t)0x10, ADC1_PRESSEL_FCPU_D4 = (uint8_t)0x20, ADC1_PRESSEL_FCPU_D6 = (uint8_t)0x30,
  ADC1_PRESSEL_FCPU_D8 = (uint8_t)0x40, ADC1_PRESSEL_FCPU_D10 = (uint8_t)0x50, ADC1_PRESSEL_FCPU_D12 = (uint8_t)0x60, ADC1_PRESSEL_FCPU_D18 = (uint8_t)0x70
}
 ADC1 clock prescaler selection. More...
enum  ADC1_SchmittTrigg_TypeDef {
  ADC1_SCHMITTTRIG_CHANNEL0 = (uint8_t)0x00, ADC1_SCHMITTTRIG_CHANNEL1 = (uint8_t)0x01, ADC1_SCHMITTTRIG_CHANNEL2 = (uint8_t)0x02, ADC1_SCHMITTTRIG_CHANNEL3 = (uint8_t)0x03,
  ADC1_SCHMITTTRIG_CHANNEL4 = (uint8_t)0x04, ADC1_SCHMITTTRIG_CHANNEL5 = (uint8_t)0x05, ADC1_SCHMITTTRIG_CHANNEL6 = (uint8_t)0x06, ADC1_SCHMITTTRIG_CHANNEL7 = (uint8_t)0x07,
  ADC1_SCHMITTTRIG_CHANNEL8 = (uint8_t)0x08, ADC1_SCHMITTTRIG_CHANNEL9 = (uint8_t)0x09, ADC1_SCHMITTTRIG_CHANNEL12 = (uint8_t)0x0C, ADC1_SCHMITTTRIG_ALL = (uint8_t)0xFF
}
 ADC1 schmitt Trigger. More...

Enumeration Type Documentation

ADC1 data alignment.

Enumerator:
ADC1_ALIGN_LEFT 

Data alignment left.

ADC1_ALIGN_RIGHT 

Data alignment right.

Definition at line 68 of file stm8s_adc1.h.

ADC1 analog channel selection.

Enumerator:
ADC1_CHANNEL_0 

Analog channel 0.

ADC1_CHANNEL_1 

Analog channel 1.

ADC1_CHANNEL_2 

Analog channel 2.

ADC1_CHANNEL_3 

Analog channel 3.

ADC1_CHANNEL_4 

Analog channel 4.

ADC1_CHANNEL_5 

Analog channel 5.

ADC1_CHANNEL_6 

Analog channel 6.

ADC1_CHANNEL_7 

Analog channel 7.

ADC1_CHANNEL_8 

Analog channel 8.

ADC1_CHANNEL_9 

Analog channel 9.

ADC1_CHANNEL_12 

Analog channel 12.

Definition at line 155 of file stm8s_adc1.h.

ADC1 conversion mode selection.

Enumerator:
ADC1_CONVERSIONMODE_SINGLE 

Single conversion mode.

ADC1_CONVERSIONMODE_CONTINUOUS 

Continuous conversion mode.

Definition at line 145 of file stm8s_adc1.h.

ADC1 External conversion trigger event selection.

Enumerator:
ADC1_EXTTRIG_TIM 

Conversion from Internal TIM1 TRGO event.

ADC1_EXTTRIG_GPIO 

Conversion from External interrupt on ADC_ETR pin.

Definition at line 59 of file stm8s_adc1.h.

ADC1 Flags.

Enumerator:
ADC1_FLAG_OVR 

Overrun status flag.

ADC1_FLAG_AWD 

Analog WDG status.

ADC1_FLAG_AWS0 

Analog channel 0 status.

ADC1_FLAG_AWS1 

Analog channel 1 status.

ADC1_FLAG_AWS2 

Analog channel 2 status.

ADC1_FLAG_AWS3 

Analog channel 3 status.

ADC1_FLAG_AWS4 

Analog channel 4 status.

ADC1_FLAG_AWS5 

Analog channel 5 status.

ADC1_FLAG_AWS6 

Analog channel 6 status.

ADC1_FLAG_AWS7 

Analog channel 7 status.

ADC1_FLAG_AWS8 

Analog channel 8 status.

ADC1_FLAG_AWS9 

Analog channel 9 status.

ADC1_FLAG_AWS12 

Analog channel 12 status.

ADC1_FLAG_EOC 

EOC falg.

Definition at line 101 of file stm8s_adc1.h.

ADC1 Interrupt source.

Enumerator:
ADC1_IT_AWDIE 

Analog WDG interrupt enable.

ADC1_IT_EOCIE 

EOC interrupt enable.

ADC1_IT_AWD 

Analog WDG status.

ADC1_IT_AWS0 

Analog channel 0 status.

ADC1_IT_AWS1 

Analog channel 1 status.

ADC1_IT_AWS2 

Analog channel 2 status.

ADC1_IT_AWS3 

Analog channel 3 status.

ADC1_IT_AWS4 

Analog channel 4 status.

ADC1_IT_AWS5 

Analog channel 5 status.

ADC1_IT_AWS6 

Analog channel 6 status.

ADC1_IT_AWS7 

Analog channel 7 status.

ADC1_IT_AWS8 

Analog channel 8 status.

ADC1_IT_AWS9 

Analog channel 9 status.

ADC1_IT_AWS12 

Analog channel 12 status.

ADC1_IT_EOC 

EOC pending bit.

Definition at line 77 of file stm8s_adc1.h.

ADC1 clock prescaler selection.

Enumerator:
ADC1_PRESSEL_FCPU_D2 

Prescaler selection fADC1 = fcpu/2.

ADC1_PRESSEL_FCPU_D3 

Prescaler selection fADC1 = fcpu/3.

ADC1_PRESSEL_FCPU_D4 

Prescaler selection fADC1 = fcpu/4.

ADC1_PRESSEL_FCPU_D6 

Prescaler selection fADC1 = fcpu/6.

ADC1_PRESSEL_FCPU_D8 

Prescaler selection fADC1 = fcpu/8.

ADC1_PRESSEL_FCPU_D10 

Prescaler selection fADC1 = fcpu/10.

ADC1_PRESSEL_FCPU_D12 

Prescaler selection fADC1 = fcpu/12.

ADC1_PRESSEL_FCPU_D18 

Prescaler selection fADC1 = fcpu/18.

Definition at line 44 of file stm8s_adc1.h.

ADC1 schmitt Trigger.

Enumerator:
ADC1_SCHMITTTRIG_CHANNEL0 

Schmitt trigger disable on AIN0.

ADC1_SCHMITTTRIG_CHANNEL1 

Schmitt trigger disable on AIN1.

ADC1_SCHMITTTRIG_CHANNEL2 

Schmitt trigger disable on AIN2.

ADC1_SCHMITTTRIG_CHANNEL3 

Schmitt trigger disable on AIN3.

ADC1_SCHMITTTRIG_CHANNEL4 

Schmitt trigger disable on AIN4.

ADC1_SCHMITTTRIG_CHANNEL5 

Schmitt trigger disable on AIN5.

ADC1_SCHMITTTRIG_CHANNEL6 

Schmitt trigger disable on AIN6.

ADC1_SCHMITTTRIG_CHANNEL7 

Schmitt trigger disable on AIN7.

ADC1_SCHMITTTRIG_CHANNEL8 

Schmitt trigger disable on AIN8.

ADC1_SCHMITTTRIG_CHANNEL9 

Schmitt trigger disable on AIN9.

ADC1_SCHMITTTRIG_CHANNEL12 

Schmitt trigger disable on AIN12.

ADC1_SCHMITTTRIG_ALL 

Schmitt trigger disable on All channels.

Definition at line 124 of file stm8s_adc1.h.

STM8 Standard Peripherals Library: Footer

 

 

 

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