Socket APIs: Ethernet/W5300/w5300.h Source File

Wiznet Socket API

Socket APIs
 #ifndef _W5300_H_
 #define _W5300_H_
 //*****************************************************************************
 //
 //
 //*****************************************************************************
 
 #include <stdint.h>
 #include "wizchip_conf.h"
 
 #if (_WIZCHIP_ == 5300)
 
 #define _WIZCHIP_SN_BASE_ (0x0200)
 #define _WIZCHIP_SN_SIZE_ (0x0040)
 
 
 #define WIZCHIP_CREG_BLOCK 0x00 
 #define WIZCHIP_SREG_BLOCK(N) (_WIZCHIP_SN_BASE_+ _WIZCHIP_SN_SIZE_*N) 
 
 #define WIZCHIP_OFFSET_INC(ADDR, N) (ADDR + N) 
 
 #if (_WIZCHIP_IO_MODE_ == _WIZCHIP_IO_MODE_BUS_DIR_)
  #define _W5300_IO_BASE_ _WIZCHIP_IO_BASE_
 #elif (_WIZCHIP_IO_MODE_ == _WIZCHIP_IO_MODE_BUS_INDIR_)
  #define IDM_AR ((_WIZCHIP_IO_BASE_ + 0x0002)) 
  #define IDM_DR ((_WIZCHIP_IO_BASE_ + 0x0004)) 
  #define _W5300_IO_BASE_ 0x0000
 #elif (_WIZCHIP_IO_MODE_ & _WIZCHIP_IO_MODE_SPI_)
  #error "Unkonw _WIZCHIP_IO_MODE_"
 #endif
 
 // Definition For Legacy Chip Driver //
 #define IINCHIP_READ(ADDR) WIZCHIP_READ(ADDR) 
 #define IINCHIP_WRITE(ADDR,VAL) WIZCHIP_WRITE(ADDR,VAL) 
 //#define IINCHIP_READ_BUF(ADDR,BUF,LEN) WIZCHIP_READ_BUF(ADDR,BUF,LEN) 
 //#define IINCHIP_WRITE_BUF(ADDR,BUF,LEN) WIZCHIP_WRITE(ADDR,BUF,LEN) 
 
 //-------------------------- defgroup ---------------------------------
 //------------------------------- defgroup end --------------------------------------------
 
 //----------------------------- W5300 Common Registers -----------------------------
 #define MR (_WIZCHIP_IO_BASE_)
 
 #define IR (_W5300_IO_BASE_ + 0x02)
 
 #define _IMR_ (_W5300_IO_BASE_ + 0x04)
 
 
 //#define ICFGR (_W5300_IO_BASE_ + 0x06)
 //#define INTLEVEL ICFGR
 
 #define SHAR (_W5300_IO_BASE_ + 0x08)
 
 
  #define GAR (_W5300_IO_BASE_ + 0x10)
 
 #define SUBR (_W5300_IO_BASE_ + 0x14)
 
 #define SIPR (_W5300_IO_BASE_ + 0x18)
 
  #define _RTR_ (_W5300_IO_BASE_ + 0x1C)
 
 #define _RCR_ (_W5300_IO_BASE_ + 0x1E)
 
 #define TMS01R (_W5300_IO_BASE_ + 0x20)
 
 #define TMS23R (TMS01R + 2) 
 
 #define TMS45R (TMS01R + 4)
 
 #define TMS67R (TMS01R + 6) 
 
 #define TMSR0 TMS01R
 
 #define TMSR1 (TMSR0 + 1)
 
 #define TMSR2 (TMSR0 + 2)
 
 #define TMSR3 (TMSR0 + 3)
 
 #define TMSR4 (TMSR0 + 4)
 
 #define TMSR5 (TMSR0 + 5)
 
 #define TMSR6 (TMSR0 + 6)
 
 #define TMSR7 (TMSR0 + 7)
 
 
 #define RMS01R (_W5300_IO_BASE_ + 0x28)
 
 #define RMS23R (RMS01R + 2) 
 
 #define RMS45R (RMS01R + 4) 
 
 #define RMS67R (RMS01R + 6) 
 
 #define RMSR0 RMS01R
 
 #define RMSR1 (RMSR0 + 1)
 
 #define RMSR2 (RMSR0 + 2)
 
 #define RMSR3 (RMSR0 + 3)
 
 #define RMSR4 (RMSR0 + 4)
 
 #define RMSR5 (RMSR0 + 5)
 
 #define RMSR6 (RMSR0 + 6)
 
 #define RMSR7 (RMSR0 + 7)
 
 
 
 #define MTYPER (_W5300_IO_BASE_ + 0x30)
 
 #define PATR (_W5300_IO_BASE_ + 0x32)
 
 //#define PPPALGOR (_W5300_IO_BASE_ + 0x34)
 
 #define PTIMER (_W5300_IO_BASE_ + 0x36)
 
 #define PMAGICR (_W5300_IO_BASE_ + 0x38)
 
 //#define PSTATER (_W5300_IO_BASE_ + 0x3A)
 
 #define PSIDR (_W5300_IO_BASE_ + 0x3C)
 
 #define PDHAR (_W5300_IO_BASE_ + 0x40)
 
 #define UIPR (_W5300_IO_BASE_ + 0x48)
 
 #define UPORTR (_W5300_IO_BASE_ + 0x4C)
 
 #define FMTUR (_W5300_IO_BASE_ + 0x4E)
 
 //#define Sn_RTCR(n) (_W5300_IO_BASE_ + 0x50 + n*2)
 
 #define Pn_BRDYR(n) (_W5300_IO_BASE_ + 0x60 + n*4)
 
 #define Pn_BDPTHR(n) (_W5300_IO_BASE_ + 0x60 + n*4 + 2)
 
 #define IDR (_W5300_IO_BASE_ + 0xFE)
 #define VERSIONR IDR
 
 
 //----------------------------- W5300 SOCKET Registers -----------------------------
 
 #define Sn_MR(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x00)
 
 #define Sn_CR(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x02)
 
 #define Sn_IMR(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x04)
 
 #define Sn_IR(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x06)
 
 #define Sn_SSR(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x08)
 #define Sn_SR(n) Sn_SSR(n) 
 
 
 #define Sn_PORTR(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x0A)
 #define Sn_PORT(n) Sn_PORTR(n) 
 
 
 #define Sn_DHAR(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x0C)
 
 #define Sn_DPORTR(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x12)
 #define Sn_DPORT(n) Sn_DPORTR(n) 
 
 
  #define Sn_DIPR(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x14)
 
 #define Sn_MSSR(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x18)
 
 #define Sn_KPALVTR(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x1A)
 
 #define Sn_PROTOR(n) Sn_KPALVTR(n)
 
 
 #define Sn_TOSR(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x1C)
 #define Sn_TOS(n) Sn_TOSR(n) 
 
 
 #define Sn_TTLR(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x1E)
 #define Sn_TTL(n) Sn_TTLR(n) 
 
 
 #define Sn_TX_WRSR(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x20)
 
 #define Sn_TX_FSR(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x0024)
 
 #define Sn_RX_RSR(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x0028)
 
 #define Sn_FRAGR(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x002C)
 #define Sn_FRAG(n) Sn_FRAGR(n)
 
 #define Sn_TX_FIFOR(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x2E)
 
 #define Sn_RX_FIFOR(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x30)
 
 //#define Sn_TX_SADR(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x32)
 
 //#define Sn_RX_SADR(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x34)
 
 //#define Sn_TX_RD(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x36)
 
 //#define Sn_TX_WR(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x38)
 
 //#define Sn_TX_ACK(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x3A)
 
 //#define Sn_RX_RD(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x3C)
 
 //#define Sn_RX_WR(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x3E)
 
 
 /************************************/
 /* The bit of MR regsiter defintion */
 /************************************/
 #define MR_DBW (1 << 15) 
 #define MR_MPF (1 << 14) 
 #define MR_WDF(X) ((X & 0x07) << 11) 
 #define MR_RDH (1 << 10) 
 #define MR_FS (1 << 8) 
 #define MR_RST (1 << 7) 
 #define MR_MT (1 << 5) 
 #define MR_PB (1 << 4) 
 #define MR_PPPoE (1 << 3) 
 #define MR_DBS (1 << 2) 
 #define MR_IND (1 << 0) 
 /************************************/ 
 /* The bit of IR regsiter defintion */ 
 /************************************/ 
 #define IR_IPCF (1 << 15) 
 #define IR_DPUR (1 << 14) 
 #define IR_PPPT (1 << 13) 
 #define IR_FMTU (1 << 12) 
 #define IR_SnINT(n) (0x01 << n) 
 /*****************************************/ 
 /* The bit of Pn_BRDYR regsiter defintion*/ 
 /*****************************************/ 
 #define Pn_PEN (1 << 7) 
 #define Pn_MT (1 << 6) 
 #define Pn_PPL (1 << 5) 
 #define Pn_SN(n) ((n & 0x07) << 0) 
 /***************************************/ 
 /* The bit of Sn_MR regsiter defintion */ 
 /***************************************/ 
 #define Sn_MR_ALIGN (1 << 8) 
 
 #define Sn_MR_MULTI (1 << 7) 
 
 #define Sn_MR_MF (1 << 6) 
 
 #define Sn_MR_IGMPv (1 << 5)
 #define Sn_MR_MC Sn_MR_IGMPv 
 
 
 #define Sn_MR_ND (1 << 5) 
 
 #define Sn_MR_CLOSE 0x00 
 
 #define Sn_MR_TCP 0x01 
 
 #define Sn_MR_UDP 0x02 
 #define Sn_MR_IPRAW 0x03 
 #define Sn_MR_MACRAW 0x04 
 
 #define Sn_MR_PPPoE 0x05 
 #define SOCK_STREAM Sn_MR_TCP 
 #define SOCK_DGRAM Sn_MR_UDP 
 /******************************/ 
 /* The values of CR defintion */ 
 /******************************/
 #define Sn_CR_OPEN 0x01 
 
 #define Sn_CR_LISTEN 0x02 
 
 #define Sn_CR_CONNECT 0x04 
 
 #define Sn_CR_DISCON 0x08 
 
 #define Sn_CR_CLOSE 0x10 
 
 #define Sn_CR_SEND 0x20 
 
 #define Sn_CR_SEND_MAC 0x21 
 
 #define Sn_CR_SEND_KEEP 0x22 
 
 #define Sn_CR_RECV 0x40 
 #define Sn_CR_PCON 0x23 
 #define Sn_CR_PDISCON 0x24 
 #define Sn_CR_PCR 0x25 
 #define Sn_CR_PCN 0x26 
 #define Sn_CR_PCJ 0x27 
 /*********************************/ 
 /* The values of Sn_IR defintion */ 
 /*********************************/
 #define Sn_IR_PRECV 0x80 
 #define Sn_IR_PFAIL 0x40 
 #define Sn_IR_PNEXT 0x20 
 #define Sn_IR_SENDOK 0x10 
 #define Sn_IR_TIMEOUT 0x08 
 #define Sn_IR_RECV 0x04 
 #define Sn_IR_DISCON 0x02 
 #define Sn_IR_CON 0x01 
 /**********************************/ 
 /* The values of Sn_SSR defintion */ 
 /**********************************/
 #define SOCK_CLOSED 0x00 
 
 #define SOCK_ARP 0x01 
 #define SOCK_INIT 0x13 
 
 #define SOCK_LISTEN 0x14 
 
 #define SOCK_SYNSENT 0x15 
 
 #define SOCK_SYNRECV 0x16 
 
 #define SOCK_ESTABLISHED 0x17 
 
 #define SOCK_FIN_WAIT 0x18 
 
 #define SOCK_CLOSING 0x1A 
 
 #define SOCK_TIME_WAIT 0x1B 
 
 #define SOCK_CLOSE_WAIT 0x1C 
 
 #define SOCK_LAST_ACK 0x1D 
 
 #define SOCK_UDP 0x22 
 
 #define SOCK_IPRAW 0x32 
 
 #define SOCK_MACRAW 0x42 
 #define SOCK_PPPoE 0x5F 
 /* IP PROTOCOL */
 #define IPPROTO_IP 0 //< Dummy for IP 
 #define IPPROTO_ICMP 1 //< Control message protocol
 #define IPPROTO_IGMP 2 //< Internet group management protocol
 #define IPPROTO_GGP 3 //< Gateway^2 (deprecated)
 #define IPPROTO_TCP 6 //< TCP
 #define IPPROTO_PUP 12 //< PUP
 #define IPPROTO_UDP 17 //< UDP
 #define IPPROTO_IDP 22 //< XNS idp
 #define IPPROTO_ND 77 //< UNOFFICIAL net disk protocol
 #define IPPROTO_RAW 255 //< Raw IP packet
 
 
 #define WIZCHIP_CRITICAL_ENTER() WIZCHIP.CRIS._enter()
 
 #ifdef _exit
 #undef _exit
 #endif
 
 #define WIZCHIP_CRITICAL_EXIT() WIZCHIP.CRIS._exit()
 
 // Basic I/O Function //
 
 uint16_t WIZCHIP_READ (uint32_t AddrSel);
 
 void WIZCHIP_WRITE(uint32_t AddrSel, uint16_t wb );
 
 /***********************************
  * COMMON Register Access Function *
  ***********************************/
 
 #if (_WIZCHIP_IO_MODE_ & _WIZCHIP_IO_MODE_BUS_)
  #if (_WIZCHIP_IO_BUS_WIDTH_ == 8)
  #define setMR(mr) \
  (*((uint8_t*)MR) = (uint8_t)((mr) >> 8)); (*((uint8_t*)WIZCHIP_OFFSET_INC(MR,1)) = (uint8_t)((mr) & 0xFF))
  #elif (_WIZCHIP_IO_BUS_WIDTH_ == 16)
  #define setMR(mr) (*((uint16_t*)MR)) = (uint16_t)((mr) & 0xFFFF))
  #else
  #error "Unknown _WIZCHIP_IO_BUS_WIDTH_. You should be define _WIZCHIP_IO_BUS_WIDTH as 8 or 16." 
  #endif
 #else
  #error "Unknown _WIZCHIP_IO_MODE_" 
 #endif
 
 #if (_WIZCHIP_IO_MODE_ & _WIZCHIP_IO_MODE_BUS_)
  #if (_WIZCHIP_IO_BUS_WIDTH_ == 8)
  #define getMR() (((uint16_t)(*((uint8_t*)MR)) << 8) + (((uint16_t)(*((uint8_t*)WIZCHIP_OFFSET_INC(MR,1)))) & 0x00FF))
  #elif(_WIZCHIP_IO_BUS_WIDTH_ == 16)
  #define getMR() (*((uint16_t*)MR))
  #else
  #error "Unknown _WIZCHIP_IO_BUS_WIDTH_. You should be define _WIZCHIP_IO_BUS_WIDTH as 8 or 16." 
  #endif
 #else
  #error "Unknown _WIZCHIP_IO_MODE_" 
 #endif
 
 #define setIR(ir) \
  WIZCHIP_WRITE(IR, ir & 0xF0FF)
 
 #define getIR() \
  (WIZCHIP_READ(IR) & 0xF0FF)
 
 
 #define setIMR(imr) \
  WIZCHIP_WRITE(_IMR_, imr & 0xF0FF)
 
 #define getIMR() \
  (WIZCHIP_READ(_IMR_) & 0xF0FF)
 
 #define setSHAR(shar) { \
  WIZCHIP_WRITE(SHAR, (((uint16_t)((shar)[0])) << 8) + (((uint16_t)((shar)[1])) & 0x00FF)); \
  WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(SHAR,2), (((uint16_t)((shar)[2])) << 8) + (((uint16_t)((shar)[3])) & 0x00FF)); \
  WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(SHAR,4), (((uint16_t)((shar)[4])) << 8) + (((uint16_t)((shar)[5])) & 0x00FF)); \
  }
 
 #define getSHAR(shar) { \
  (shar)[0] = (uint8_t)(WIZCHIP_READ(SHAR) >> 8); \
  (shar)[1] = (uint8_t)(WIZCHIP_READ(SHAR)); \
  (shar)[2] = (uint8_t)(WIZCHIP_READ(WIZCHIP_OFFSET_INC(SHAR,2)) >> 8); \
  (shar)[3] = (uint8_t)(WIZCHIP_READ(WIZCHIP_OFFSET_INC(SHAR,2))); \
  (shar)[4] = (uint8_t)(WIZCHIP_READ(WIZCHIP_OFFSET_INC(SHAR,4)) >> 8); \
  (shar)[5] = (uint8_t)(WIZCHIP_READ(WIZCHIP_OFFSET_INC(SHAR,4))); \
  } 
 
 #define setGAR(gar) { \
  WIZCHIP_WRITE(GAR, (((uint16_t)((gar)[0])) << 8) + (((uint16_t)((gar)[1])) & 0x00FF)); \
  WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(GAR,2), (((uint16_t)((gar)[2])) << 8) + (((uint16_t)((gar)[3])) & 0x00FF)); \
  }
 
 #define getGAR(gar) { \
  (gar)[0] = (uint8_t)(WIZCHIP_READ(GAR) >> 8); \
  (gar)[1] = (uint8_t)(WIZCHIP_READ(GAR)); \
  (gar)[2] = (uint8_t)(WIZCHIP_READ(WIZCHIP_OFFSET_INC(GAR,2)) >> 8); \
  (gar)[3] = (uint8_t)(WIZCHIP_READ(WIZCHIP_OFFSET_INC(GAR,2))); \
  } 
 
 #define setSUBR(subr) { \
  WIZCHIP_WRITE(SUBR, (((uint16_t)((subr)[0])) << 8) + (((uint16_t)((subr)[1])) & 0x00FF)); \
  WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(SUBR,2), (((uint16_t)((subr)[2])) << 8) + (((uint16_t)((subr)[3])) & 0x00FF)); \
  }
 
 #define getSUBR(subr) { \
  (subr)[0] = (uint8_t)(WIZCHIP_READ(SUBR) >> 8); \
  (subr)[1] = (uint8_t)(WIZCHIP_READ(SUBR)); \
  (subr)[2] = (uint8_t)(WIZCHIP_READ(WIZCHIP_OFFSET_INC(SUBR,2)) >> 8); \
  (subr)[3] = (uint8_t)(WIZCHIP_READ(WIZCHIP_OFFSET_INC(SUBR,2))); \
  }
 
 #define setSIPR(sipr) { \
  WIZCHIP_WRITE(SIPR, (((uint16_t)((sipr)[0])) << 8) + (((uint16_t)((sipr)[1])) & 0x00FF)); \
  WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(SIPR,2), (((uint16_t)((sipr)[2])) << 8) + (((uint16_t)((sipr)[3])) & 0x00FF)); \
  }
 
 #define getSIPR(sipr) { \
  (sipr)[0] = (uint8_t)(WIZCHIP_READ(SIPR) >> 8); \
  (sipr)[1] = (uint8_t)(WIZCHIP_READ(SIPR)); \
  (sipr)[2] = (uint8_t)(WIZCHIP_READ(WIZCHIP_OFFSET_INC(SIPR,2)) >> 8); \
  (sipr)[3] = (uint8_t)(WIZCHIP_READ(WIZCHIP_OFFSET_INC(SIPR,2))); \
  }
 
 
 #define setRTR(rtr) \
  WIZCHIP_WRITE(_RTR_, rtr)
 
 #define getRTR() \
  WIZCHIP_READ(_RTR_)
 
 #define setRCR(rcr) \
  WIZCHIP_WRITE(_RCR_, ((uint16_t)rcr)&0x00FF)
 
 #define getRCR() \
  ((uint8_t)(WIZCHIP_READ(_RCR_) & 0x00FF))
 
 #define setTMS01R(tms01r) \
  WIZCHIP_WRITE(TMS01R,tms01r)
 
 #define getTMS01R() \
  WIZCHIP_READ(TMS01R)
 
 #define setTMS23R(tms23r) \
  WIZCHIP_WRITE(TMS23R,tms23r)
 
 #define getTMS23R() \
  WIZCHIP_READ(TMS23R)
 
 #define setTMS45R(tms45r) \
  WIZCHIP_WRITE(TMS45R,tms45r)
 
 #define getTMS45R() \
  WIZCHIP_READ(TMS45R)
 
 #define setTMS67R(tms67r) \
  WIZCHIP_WRITE(TMS67R,tms67r)
 
 #define getTMS67R() \
  WIZCHIP_READ(TMS67R)
 
 void setTMSR(uint8_t sn,uint8_t tmsr);
 #define setSn_TXBUF_SIZE(sn, tmsr) setTMSR(sn, tmsr) 
 
 
 uint8_t getTMSR(uint8_t sn);
 #define getSn_TXBUF_SIZE(sn) getTMSR(sn) 
 
 
 #define setRMS01R(rms01r) \
  WIZCHIP_WRITE(RMS01R,rms01r)
 
 #define getRMS01R() \
  WIZCHIP_READ(RMS01R)
 
 #define setRMS23R(rms23r) \
  WIZCHIP_WRITE(RMS23R,rms23r)
 
 #define getRMS23R() \
  WIZCHIP_READ(RMS23R)
 
 #define setRMS45R(rms45r) \
  WIZCHIP_WRITE(RMS45R,rms45r)
 
 #define getRMS45R() \
  WIZCHIP_READ(RMS45R)
 
 #define setRMS67R(rms67r) \
  WIZCHIP_WRITE(RMS67R,rms67r)
 
 #define getRMS67R() \
  WIZCHIP_READ(RMS67R)
 
 void setRMSR(uint8_t sn,uint8_t rmsr);
 #define setSn_RXBUF_SIZE(sn,rmsr) setRMSR(sn, rmsr) 
 
 
 uint8_t getRMSR(uint8_t sn);
 #define getSn_RXBUF_SIZE(sn) getRMSR(sn) 
 
 
 #define setMTYPER(mtype) \
  WIZCHIP_WRITE(MTYPER, mtype)
 
 #define getMTYPER() \
  WIZCHIP_READ(MTYPER)
 
 #define getPATR() \
  WIZCHIP_READ(PATR)
 
 #define setPTIMER(ptimer) \
  WIZCHIP_WRITE(PTIMER, ((uint16_t)ptimer) & 0x00FF)
 
 #define getPTIMER() \
  ((uint8_t)(WIZCHIP_READ(PTIMER) & 0x00FF))
 
 #define setPMAGIC(pmagic) \
  WIZCHIP_WRITE(PMAGIC, ((uint16_t)pmagic) & 0x00FF)
 
 #define getPMAGIC() \
  ((uint8_t)(WIZCHIP_READ(PMAGIC) & 0x00FF))
 
 #define getPSIDR() \
  WIZCHIP_READ(PSIDR)
 
 #define getPDHAR(pdhar) { \
  (pdhar)[0] = (uint8_t)(WIZCHIP_READ(PDHAR) >> 8); \
  (pdhar)[1] = (uint8_t)(WIZCHIP_READ(PDHAR)); \
  (pdhar)[2] = (uint8_t)(WIZCHIP_READ(WIZCHIP_OFFSET_INC(PDHAR,2)) >> 8); \
  (pdhar)[3] = (uint8_t)(WIZCHIP_READ(WIZCHIP_OFFSET_INC(PDHAR,2))); \
  (pdhar)[4] = (uint8_t)(WIZCHIP_READ(WIZCHIP_OFFSET_INC(PDHAR,4)) >> 8); \
  (pdhar)[5] = (uint8_t)(WIZCHIP_READ(WIZCHIP_OFFSET_INC(PDHAR,4))); \
  }
 
 #define getUIPR(uipr) { \
  (uipr)[0] = (uint8_t)(WIZCHIP_READ(UIPR) >> 8); \
  (uipr)[1] = (uint8_t)(WIZCHIP_READ(UIPR)); \
  (uipr)[2] = (uint8_t)(WIZCHIP_READ(WIZCHIP_OFFSET_INC(UIPR,2)) >> 8); \
  (uipr)[3] = (uint8_t)(WIZCHIP_READ(WIZCHIP_OFFSET_INC(UIPR,2))); \
  }
 
 #define getUPORTR() \
  WIZCHIP_READ(UPORTR)
 
 #define getFMTUR() \
  WIZCHIP_READ(FMTUR)
 
 
 #define getPn_BRDYR(p) \
  ((uint8_t)(WIZCHIP_READ(Pn_BRDYR(p)) & 0x00FF))
 
 #define setPn_BRDYR(p, brdyr) \
  WIZCHIP_WRITE(Pn_BRDYR(p), brdyr & 0x00E7)
 
 #define getPn_BDPTHR(p) \
  WIZCHIP_READ(Pn_BDPTHR(p))
 
 #define setPn_BDPTHR(p, bdpthr) \
  WIZCHIP_WRITE(Pn_BDPTHR(p),bdpthr)
 
 
 #define getIDR() \
  WIZCHIP_READ(IDR)
 
 
 /***********************************
  * SOCKET Register Access Function *
  ***********************************/
 
 #define setSn_MR(sn, mr) \
  WIZCHIP_WRITE(Sn_MR(sn),mr)
 
 #define getSn_MR(sn) \
  WIZCHIP_READ(Sn_MR(sn))
 
 #define setSn_CR(sn, cr) \
  WIZCHIP_WRITE(Sn_CR(sn), ((uint16_t)cr) & 0x00FF)
 
 #define getSn_CR(sn) \
  ((uint8_t)WIZCHIP_READ(Sn_CR(sn)))
 
 #define setSn_IMR(sn, imr) \
  WIZCHIP_WRITE(Sn_IMR(sn), ((uint16_t)imr) & 0x00FF)
 
 #define getSn_IMR(sn) \
  ((uint8_t)WIZCHIP_READ(Sn_IMR(sn)))
 
 #define setSn_IR(sn, ir) \
  WIZCHIP_WRITE(Sn_IR(sn), ((uint16_t)ir) & 0x00FF)
 
 #define getSn_IR(sn) \
  ((uint8_t)WIZCHIP_READ(Sn_IR(sn)))
 
 #define getSn_SSR(sn) \
  ((uint8_t)WIZCHIP_READ(Sn_SR(sn)))
 #define getSn_SR(sn) getSn_SSR(sn) 
 
 
 #define setSn_PORTR(sn, port) \
  WIZCHIP_WRITE(Sn_PORTR(sn), port)
 #define setSn_PORT(sn, port) setSn_PORTR(sn, port) 
 
 
 #define getSn_PORTR(sn, port) \
  WIZCHIP_READ(Sn_PORTR(sn))
 #define getSn_PORT(sn) getSn_PORTR(sn) 
 
 
 #define setSn_DHAR(sn, dhar) { \
  WIZCHIP_WRITE(Sn_DHAR(sn), (((uint16_t)((dhar)[0])) << 8) + (((uint16_t)((dhar)[1])) & 0x00FF)); \
  WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_DHAR(sn),2), (((uint16_t)((dhar)[0])) << 8) + (((uint16_t)((dhar)[1])) & 0x00FF)); \
  WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_DHAR(sn),4), (((uint16_t)((dhar)[0])) << 8) + (((uint16_t)((dhar)[1])) & 0x00FF)); \
  } 
 
 #define getSn_DHAR(sn, dhar) { \
  (dhar)[0] = (uint8_t)(WIZCHIP_READ(Sn_DHAR(sn)) >> 8); \
  (dhar)[1] = (uint8_t) WIZCHIP_READ(Sn_DHAR(sn)); \
  (dhar)[2] = (uint8_t)(WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_DHAR(sn),2)) >> 8); \
  (dhar)[3] = (uint8_t) WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_DHAR(sn),2)); \
  (dhar)[4] = (uint8_t)(WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_DHAR(sn),4)) >> 8); \
  (dhar)[5] = (uint8_t) WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_DHAR(sn),4)); \
  }
 
 #define setSn_DPORTR(sn, dport) \
  WIZCHIP_WRITE(Sn_DPORTR(sn),dport) 
 #define setSn_DPORT(sn, dport) setSn_DPORTR(sn,dport) 
 
 
 #define getSn_DPORTR(sn) \
  WIZCHIP_READ(Sn_DPORTR(sn))
 #define getSn_DPORT(sn) getSn_DPORTR(sn) 
 
 
 #define setSn_DIPR(sn, dipr) { \
  WIZCHIP_WRITE(Sn_DIPR(sn), (((uint16_t)((dipr)[0])) << 8) + (((uint16_t)((dipr)[1])) & 0x00FF)); \
  WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_DIPR(sn),2), (((uint16_t)((dipr)[2])) << 8) + (((uint16_t)((dipr)[3])) & 0x00FF)); \
  }
  
 #define getSn_DIPR(sn, dipr) { \
  (dipr)[0] = (uint8_t)(WIZCHIP_READ(Sn_DIPR(sn)) >> 8); \
  (dipr)[1] = (uint8_t) WIZCHIP_READ(Sn_DIPR(sn)); \
  (dipr)[2] = (uint8_t)(WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_DIPR(sn),2)) >> 8); \
  (dipr)[3] = (uint8_t) WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_DIPR(sn),2)); \
  }
 
 #define setSn_MSSR(sn, mss) \
  WIZCHIP_WRITE(Sn_MSSR(sn), mss)
 
 #define getSn_MSSR(sn) \
  WIZCHIP_READ(Sn_MSSR(sn))
 
 #define setSn_KPALVTR(sn, kpalvt) \
  WIZCHIP_WRITE(Sn_KPALVTR(sn), (WIZCHIP_READ(Sn_KPALVTR(sn)) & 0x00FF) | (((uint16_t)kpalvt)<<8))
 
 #define getSn_KPALVTR(sn) \
  ((uint8_t)(WIZCHIP_READ(Sn_KPALVTR(sn)) >> 8))
 
 #define setSn_PROTOR(sn, proto) \
  WIZCHIP_WRITE(Sn_PROTOR(sn),(WIZCHIP_READ(Sn_PROTOR(sn) & 0xFF00) | (((uint16_t)proto) & 0x00FF))
 #define setSn_PROTO(sn,proto) setSn_PROTOR(sn,proto) 
 
 
 #define getSn_PROTOR(sn) \
  ((uint8_t)WIZCHIP_READ(Sn_PROTOR(sn)))
 #define getSn_PROTO(sn) getSn_PROTOR(sn) 
 
 
 #define setSn_TX_WRSR(sn, txwrs) { \
  WIZCHIP_WRITE(Sn_TX_WRSR(sn), (uint16_t)(((uint32_t)txwrs) >> 16)); \
  WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_TX_WRSR(sn),2), (uint16_t)txwrs); \
  }
  
 #define getSn_TX_WRSR(sn) \
  ( (((uint32_t)WIZCHIP_READ(Sn_TX_WRSR(sn))) << 16) + (((uint32_t)WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_WRSR(sn),1))) & 0x0000FFFF) )
 
 uint32_t getSn_TX_FSR(uint8_t sn);
 
 uint32_t getSn_RX_RSR(uint8_t sn);
 
 #define setSn_TX_FIFOR(sn, txfifo) \
  WIZCHIP_WRITE(Sn_TX_FIFOR(sn), txfifo);
 
 #define getSn_RX_FIFOR(sn) \
  WIZCHIP_READ(Sn_RX_FIFOR(sn));
 
 #define setSn_TOSR(sn, tos) \
  WIZCHIP_WRITE(Sn_TOS(sn), ((uint16_t)tos) & 0x00FF)
 #define setSn_TOS(sn,tos) setSn_TOSR(sn,tos) 
 
 
 #define getSn_TOSR(sn) \
  ((uint8_t)WIZCHIP_READ(Sn_TOSR(sn)))
 #define getSn_TOS(sn) getSn_TOSR(sn) 
 
 
 #define setSn_TTLR(sn, ttl) \
  WIZCHIP_WRITE(Sn_TTLR(sn), ((uint16_t)ttl) & 0x00FF)
 #define setSn_TTL(sn,ttl) setSn_TTLR(sn,ttl) 
 
 
 #define getSn_TTLR(sn) \
  ((uint8_t)WIZCHIP_READ(Sn_TTL(sn)))
 #define getSn_TTL(sn) getSn_TTLR(sn) 
 
 
 #define setSn_FRAGR(sn, frag) \
  WIZCHIP_WRITE(Sn_FRAGR(sn), (uint16_t)(frag >>8))
 #define setSn_FRAG(sn,frag) setSn_FRAGR(sn,flag)
 
 #define getSn_FRAGR(sn) \
  (WIZCHIP_READ(Sn_FRAG(sn)) << 8)
 #define getSn_FRAG(sn) getSn_FRAGR(sn)
 
 
 // Sn_TXBUF & Sn_RXBUF IO function //
 
 #define getSn_RxMAX(sn) \
  (((uint32_t)getSn_RXBUF_SIZE(sn)) << 10) 
 
 #define getSn_TxMAX(sn) \
  (((uint32_t)getSn_TXBUF_SIZE(sn)) << 10) 
 
 void wiz_send_data(uint8_t sn, uint8_t *wizdata, uint32_t len);
 
 void wiz_recv_data(uint8_t sn, uint8_t *wizdata, uint32_t len);
 
 void wiz_recv_ignore(uint8_t sn, uint32_t len);
 
 #endif
 
 #endif // _W5300_H_
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