Socket APIs: Ethernet/W5300/w5300.h Source File

Wiznet Socket API

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w5300.h
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1 #ifndef _W5300_H_
2 #define _W5300_H_
3 //*****************************************************************************
4 //
43 //
44 //*****************************************************************************
45 
46 #include <stdint.h>
47 #include "wizchip_conf.h"
48 
50 #if (_WIZCHIP_ == 5300)
51 
53 #define _WIZCHIP_SN_BASE_ (0x0200)
54 #define _WIZCHIP_SN_SIZE_ (0x0040)
55 
56 
57 #define WIZCHIP_CREG_BLOCK 0x00
58 #define WIZCHIP_SREG_BLOCK(N) (_WIZCHIP_SN_BASE_+ _WIZCHIP_SN_SIZE_*N)
59 
60 #define WIZCHIP_OFFSET_INC(ADDR, N) (ADDR + N)
61 
62 #if (_WIZCHIP_IO_MODE_ == _WIZCHIP_IO_MODE_BUS_DIR_)
63  #define _W5300_IO_BASE_ _WIZCHIP_IO_BASE_
64 #elif (_WIZCHIP_IO_MODE_ == _WIZCHIP_IO_MODE_BUS_INDIR_)
65  #define IDM_AR ((_WIZCHIP_IO_BASE_ + 0x0002))
66  #define IDM_DR ((_WIZCHIP_IO_BASE_ + 0x0004))
67  #define _W5300_IO_BASE_ 0x0000
68 #elif (_WIZCHIP_IO_MODE_ & _WIZCHIP_IO_MODE_SPI_)
69  #error "Unkonw _WIZCHIP_IO_MODE_"
70 #endif
71 
73 // Definition For Legacy Chip Driver //
75 #define IINCHIP_READ(ADDR) WIZCHIP_READ(ADDR)
76 #define IINCHIP_WRITE(ADDR,VAL) WIZCHIP_WRITE(ADDR,VAL)
77 //#define IINCHIP_READ_BUF(ADDR,BUF,LEN) WIZCHIP_READ_BUF(ADDR,BUF,LEN)
78 //#define IINCHIP_WRITE_BUF(ADDR,BUF,LEN) WIZCHIP_WRITE(ADDR,BUF,LEN)
79 
80 //-------------------------- defgroup ---------------------------------
199 //------------------------------- defgroup end --------------------------------------------
200 
201 //----------------------------- W5300 Common Registers -----------------------------
224 #define MR (_WIZCHIP_IO_BASE_)
225 
246 #define IR (_W5300_IO_BASE_ + 0x02)
247 
256 #define _IMR_ (_W5300_IO_BASE_ + 0x04)
257 
258 
259 //#define ICFGR (_W5300_IO_BASE_ + 0x06)
260 //#define INTLEVEL ICFGR
261 
267 #define SHAR (_W5300_IO_BASE_ + 0x08)
268 
269 
275  #define GAR (_W5300_IO_BASE_ + 0x10)
276 
282 #define SUBR (_W5300_IO_BASE_ + 0x14)
283 
289 #define SIPR (_W5300_IO_BASE_ + 0x18)
290 
299  #define _RTR_ (_W5300_IO_BASE_ + 0x1C)
300 
307 #define _RCR_ (_W5300_IO_BASE_ + 0x1E)
308 
316 #define TMS01R (_W5300_IO_BASE_ + 0x20)
317 
323 #define TMS23R (TMS01R + 2)
324 
330 #define TMS45R (TMS01R + 4)
331 
337 #define TMS67R (TMS01R + 6)
338 
344 #define TMSR0 TMS01R
345 
351 #define TMSR1 (TMSR0 + 1)
352 
358 #define TMSR2 (TMSR0 + 2)
359 
365 #define TMSR3 (TMSR0 + 3)
366 
372 #define TMSR4 (TMSR0 + 4)
373 
379 #define TMSR5 (TMSR0 + 5)
380 
386 #define TMSR6 (TMSR0 + 6)
387 
393 #define TMSR7 (TMSR0 + 7)
394 
395 
403 #define RMS01R (_W5300_IO_BASE_ + 0x28)
404 
410 #define RMS23R (RMS01R + 2)
411 
417 #define RMS45R (RMS01R + 4)
418 
424 #define RMS67R (RMS01R + 6)
425 
431 #define RMSR0 RMS01R
432 
438 #define RMSR1 (RMSR0 + 1)
439 
445 #define RMSR2 (RMSR0 + 2)
446 
452 #define RMSR3 (RMSR0 + 3)
453 
459 #define RMSR4 (RMSR0 + 4)
460 
466 #define RMSR5 (RMSR0 + 5)
467 
473 #define RMSR6 (RMSR0 + 6)
474 
480 #define RMSR7 (RMSR0 + 7)
481 
482 
483 
493 #define MTYPER (_W5300_IO_BASE_ + 0x30)
494 
503 #define PATR (_W5300_IO_BASE_ + 0x32)
504 
505 //#define PPPALGOR (_W5300_IO_BASE_ + 0x34)
506 
512 #define PTIMER (_W5300_IO_BASE_ + 0x36)
513 
519 #define PMAGICR (_W5300_IO_BASE_ + 0x38)
520 
521 //#define PSTATER (_W5300_IO_BASE_ + 0x3A)
522 
528 #define PSIDR (_W5300_IO_BASE_ + 0x3C)
529 
535 #define PDHAR (_W5300_IO_BASE_ + 0x40)
536 
545 #define UIPR (_W5300_IO_BASE_ + 0x48)
546 
552 #define UPORTR (_W5300_IO_BASE_ + 0x4C)
553 
561 #define FMTUR (_W5300_IO_BASE_ + 0x4E)
562 
563 //#define Sn_RTCR(n) (_W5300_IO_BASE_ + 0x50 + n*2)
564 
584 #define Pn_BRDYR(n) (_W5300_IO_BASE_ + 0x60 + n*4)
585 
594 #define Pn_BDPTHR(n) (_W5300_IO_BASE_ + 0x60 + n*4 + 2)
595 
601 #define IDR (_W5300_IO_BASE_ + 0xFE)
602 #define VERSIONR IDR
603 
604 
605 //----------------------------- W5300 SOCKET Registers -----------------------------
606 
642 #define Sn_MR(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x00)
643 
666 #define Sn_CR(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x02)
667 
676 #define Sn_IMR(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x04)
677 
699 #define Sn_IR(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x06)
700 
725 #define Sn_SSR(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x08)
726 #define Sn_SR(n) Sn_SSR(n)
727 
728 
734 #define Sn_PORTR(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x0A)
735 #define Sn_PORT(n) Sn_PORTR(n)
736 
737 
743 #define Sn_DHAR(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x0C)
744 
753 #define Sn_DPORTR(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x12)
754 #define Sn_DPORT(n) Sn_DPORTR(n)
755 
756 
765  #define Sn_DIPR(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x14)
766 
772 #define Sn_MSSR(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x18)
773 
785 #define Sn_KPALVTR(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x1A)
786 
793 #define Sn_PROTOR(n) Sn_KPALVTR(n)
794 
795 
802 #define Sn_TOSR(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x1C)
803 #define Sn_TOS(n) Sn_TOSR(n)
804 
805 
811 #define Sn_TTLR(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x1E)
812 #define Sn_TTL(n) Sn_TTLR(n)
813 
814 
821 #define Sn_TX_WRSR(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x20)
822 
832 #define Sn_TX_FSR(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x0024)
833 
841 #define Sn_RX_RSR(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x0028)
842 
848 #define Sn_FRAGR(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x002C)
849 #define Sn_FRAG(n) Sn_FRAGR(n)
850 
859 #define Sn_TX_FIFOR(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x2E)
860 
869 #define Sn_RX_FIFOR(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x30)
870 
871 //#define Sn_TX_SADR(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x32)
872 
873 //#define Sn_RX_SADR(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x34)
874 
875 //#define Sn_TX_RD(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x36)
876 
877 //#define Sn_TX_WR(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x38)
878 
879 //#define Sn_TX_ACK(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x3A)
880 
881 //#define Sn_RX_RD(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x3C)
882 
883 //#define Sn_RX_WR(n) (_W5300_IO_BASE_ + WIZCHIP_SREG_BLOCK(n) + 0x3E)
884 
885 
886 /************************************/
887 /* The bit of MR regsiter defintion */
888 /************************************/
889 #define MR_DBW (1 << 15)
890 #define MR_MPF (1 << 14)
891 #define MR_WDF(X) ((X & 0x07) << 11)
892 #define MR_RDH (1 << 10)
893 #define MR_FS (1 << 8)
894 #define MR_RST (1 << 7)
895 #define MR_MT (1 << 5)
896 #define MR_PB (1 << 4)
897 #define MR_PPPoE (1 << 3)
898 #define MR_DBS (1 << 2)
899 #define MR_IND (1 << 0)
902 /************************************/
903 /* The bit of IR regsiter defintion */
904 /************************************/
905 #define IR_IPCF (1 << 15)
906 #define IR_DPUR (1 << 14)
907 #define IR_PPPT (1 << 13)
908 #define IR_FMTU (1 << 12)
909 #define IR_SnINT(n) (0x01 << n)
911 /*****************************************/
912 /* The bit of Pn_BRDYR regsiter defintion*/
913 /*****************************************/
914 #define Pn_PEN (1 << 7)
915 #define Pn_MT (1 << 6)
916 #define Pn_PPL (1 << 5)
917 #define Pn_SN(n) ((n & 0x07) << 0)
920 /***************************************/
921 /* The bit of Sn_MR regsiter defintion */
922 /***************************************/
929 #define Sn_MR_ALIGN (1 << 8)
930 
937 #define Sn_MR_MULTI (1 << 7)
938 
947 #define Sn_MR_MF (1 << 6)
948 
955 #define Sn_MR_IGMPv (1 << 5)
956 #define Sn_MR_MC Sn_MR_IGMPv
957 
958 
966 #define Sn_MR_ND (1 << 5)
967 
973 #define Sn_MR_CLOSE 0x00
974 
980 #define Sn_MR_TCP 0x01
981 
987 #define Sn_MR_UDP 0x02
994 #define Sn_MR_IPRAW 0x03
1002 #define Sn_MR_MACRAW 0x04
1003 
1010 #define Sn_MR_PPPoE 0x05
1012 #define SOCK_STREAM Sn_MR_TCP
1013 #define SOCK_DGRAM Sn_MR_UDP
1017 /******************************/
1018 /* The values of CR defintion */
1019 /******************************/
1034 #define Sn_CR_OPEN 0x01
1035 
1045 #define Sn_CR_LISTEN 0x02
1046 
1057 #define Sn_CR_CONNECT 0x04
1058 
1070 #define Sn_CR_DISCON 0x08
1071 
1076 #define Sn_CR_CLOSE 0x10
1077 
1083 #define Sn_CR_SEND 0x20
1084 
1093 #define Sn_CR_SEND_MAC 0x21
1094 
1101 #define Sn_CR_SEND_KEEP 0x22
1102 
1108 #define Sn_CR_RECV 0x40
1110 #define Sn_CR_PCON 0x23
1111 #define Sn_CR_PDISCON 0x24
1112 #define Sn_CR_PCR 0x25
1113 #define Sn_CR_PCN 0x26
1114 #define Sn_CR_PCJ 0x27
1117 /*********************************/
1118 /* The values of Sn_IR defintion */
1119 /*********************************/
1120 #define Sn_IR_PRECV 0x80
1121 #define Sn_IR_PFAIL 0x40
1122 #define Sn_IR_PNEXT 0x20
1123 #define Sn_IR_SENDOK 0x10
1124 #define Sn_IR_TIMEOUT 0x08
1125 #define Sn_IR_RECV 0x04
1126 #define Sn_IR_DISCON 0x02
1127 #define Sn_IR_CON 0x01
1129 /**********************************/
1130 /* The values of Sn_SSR defintion */
1131 /**********************************/
1137 #define SOCK_CLOSED 0x00
1138 
1144 #define SOCK_ARP 0x01
1152 #define SOCK_INIT 0x13
1153 
1160 #define SOCK_LISTEN 0x14
1161 
1169 #define SOCK_SYNSENT 0x15
1170 
1177 #define SOCK_SYNRECV 0x16
1178 
1186 #define SOCK_ESTABLISHED 0x17
1187 
1194 #define SOCK_FIN_WAIT 0x18
1195 
1202 #define SOCK_CLOSING 0x1A
1203 
1210 #define SOCK_TIME_WAIT 0x1B
1211 
1218 #define SOCK_CLOSE_WAIT 0x1C
1219 
1225 #define SOCK_LAST_ACK 0x1D
1226 
1233 #define SOCK_UDP 0x22
1234 
1241 #define SOCK_IPRAW 0x32
1242 
1249 #define SOCK_MACRAW 0x42
1257 #define SOCK_PPPoE 0x5F
1259 /* IP PROTOCOL */
1260 #define IPPROTO_IP 0 //< Dummy for IP
1261 #define IPPROTO_ICMP 1 //< Control message protocol
1262 #define IPPROTO_IGMP 2 //< Internet group management protocol
1263 #define IPPROTO_GGP 3 //< Gateway^2 (deprecated)
1264 #define IPPROTO_TCP 6 //< TCP
1265 #define IPPROTO_PUP 12 //< PUP
1266 #define IPPROTO_UDP 17 //< UDP
1267 #define IPPROTO_IDP 22 //< XNS idp
1268 #define IPPROTO_ND 77 //< UNOFFICIAL net disk protocol
1269 #define IPPROTO_RAW 255 //< Raw IP packet
1270 
1271 
1283 #define WIZCHIP_CRITICAL_ENTER() WIZCHIP.CRIS._enter()
1284 
1285 #ifdef _exit
1286 #undef _exit
1287 #endif
1288 
1300 #define WIZCHIP_CRITICAL_EXIT() WIZCHIP.CRIS._exit()
1301 
1303 // Basic I/O Function //
1305 
1312 uint16_t WIZCHIP_READ (uint32_t AddrSel);
1313 
1321 void WIZCHIP_WRITE(uint32_t AddrSel, uint16_t wb );
1322 
1323 /***********************************
1324  * COMMON Register Access Function *
1325  ***********************************/
1326 
1333 #if (_WIZCHIP_IO_MODE_ & _WIZCHIP_IO_MODE_BUS_)
1334  #if (_WIZCHIP_IO_BUS_WIDTH_ == 8)
1335  #define setMR(mr) \
1336  (*((uint8_t*)MR) = (uint8_t)((mr) >> 8)); (*((uint8_t*)WIZCHIP_OFFSET_INC(MR,1)) = (uint8_t)((mr) & 0xFF))
1337  #elif (_WIZCHIP_IO_BUS_WIDTH_ == 16)
1338  #define setMR(mr) (*((uint16_t*)MR)) = (uint16_t)((mr) & 0xFFFF))
1339  #else
1340  #error "Unknown _WIZCHIP_IO_BUS_WIDTH_. You should be define _WIZCHIP_IO_BUS_WIDTH as 8 or 16."
1341  #endif
1342 #else
1343  #error "Unknown _WIZCHIP_IO_MODE_"
1344 #endif
1345 
1352 #if (_WIZCHIP_IO_MODE_ & _WIZCHIP_IO_MODE_BUS_)
1353  #if (_WIZCHIP_IO_BUS_WIDTH_ == 8)
1354  #define getMR() (((uint16_t)(*((uint8_t*)MR)) << 8) + (((uint16_t)(*((uint8_t*)WIZCHIP_OFFSET_INC(MR,1)))) & 0x00FF))
1355  #elif(_WIZCHIP_IO_BUS_WIDTH_ == 16)
1356  #define getMR() (*((uint16_t*)MR))
1357  #else
1358  #error "Unknown _WIZCHIP_IO_BUS_WIDTH_. You should be define _WIZCHIP_IO_BUS_WIDTH as 8 or 16."
1359  #endif
1360 #else
1361  #error "Unknown _WIZCHIP_IO_MODE_"
1362 #endif
1363 
1370 #define setIR(ir) \
1371  WIZCHIP_WRITE(IR, ir & 0xF0FF)
1372 
1379 #define getIR() \
1380  (WIZCHIP_READ(IR) & 0xF0FF)
1381 
1382 
1389 #define setIMR(imr) \
1390  WIZCHIP_WRITE(_IMR_, imr & 0xF0FF)
1391 
1398 #define getIMR() \
1399  (WIZCHIP_READ(_IMR_) & 0xF0FF)
1400 
1407 #define setSHAR(shar) { \
1408  WIZCHIP_WRITE(SHAR, (((uint16_t)((shar)[0])) << 8) + (((uint16_t)((shar)[1])) & 0x00FF)); \
1409  WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(SHAR,2), (((uint16_t)((shar)[2])) << 8) + (((uint16_t)((shar)[3])) & 0x00FF)); \
1410  WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(SHAR,4), (((uint16_t)((shar)[4])) << 8) + (((uint16_t)((shar)[5])) & 0x00FF)); \
1411  }
1412 
1419 #define getSHAR(shar) { \
1420  (shar)[0] = (uint8_t)(WIZCHIP_READ(SHAR) >> 8); \
1421  (shar)[1] = (uint8_t)(WIZCHIP_READ(SHAR)); \
1422  (shar)[2] = (uint8_t)(WIZCHIP_READ(WIZCHIP_OFFSET_INC(SHAR,2)) >> 8); \
1423  (shar)[3] = (uint8_t)(WIZCHIP_READ(WIZCHIP_OFFSET_INC(SHAR,2))); \
1424  (shar)[4] = (uint8_t)(WIZCHIP_READ(WIZCHIP_OFFSET_INC(SHAR,4)) >> 8); \
1425  (shar)[5] = (uint8_t)(WIZCHIP_READ(WIZCHIP_OFFSET_INC(SHAR,4))); \
1426  }
1427 
1434 #define setGAR(gar) { \
1435  WIZCHIP_WRITE(GAR, (((uint16_t)((gar)[0])) << 8) + (((uint16_t)((gar)[1])) & 0x00FF)); \
1436  WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(GAR,2), (((uint16_t)((gar)[2])) << 8) + (((uint16_t)((gar)[3])) & 0x00FF)); \
1437  }
1438 
1445 #define getGAR(gar) { \
1446  (gar)[0] = (uint8_t)(WIZCHIP_READ(GAR) >> 8); \
1447  (gar)[1] = (uint8_t)(WIZCHIP_READ(GAR)); \
1448  (gar)[2] = (uint8_t)(WIZCHIP_READ(WIZCHIP_OFFSET_INC(GAR,2)) >> 8); \
1449  (gar)[3] = (uint8_t)(WIZCHIP_READ(WIZCHIP_OFFSET_INC(GAR,2))); \
1450  }
1451 
1458 #define setSUBR(subr) { \
1459  WIZCHIP_WRITE(SUBR, (((uint16_t)((subr)[0])) << 8) + (((uint16_t)((subr)[1])) & 0x00FF)); \
1460  WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(SUBR,2), (((uint16_t)((subr)[2])) << 8) + (((uint16_t)((subr)[3])) & 0x00FF)); \
1461  }
1462 
1469 #define getSUBR(subr) { \
1470  (subr)[0] = (uint8_t)(WIZCHIP_READ(SUBR) >> 8); \
1471  (subr)[1] = (uint8_t)(WIZCHIP_READ(SUBR)); \
1472  (subr)[2] = (uint8_t)(WIZCHIP_READ(WIZCHIP_OFFSET_INC(SUBR,2)) >> 8); \
1473  (subr)[3] = (uint8_t)(WIZCHIP_READ(WIZCHIP_OFFSET_INC(SUBR,2))); \
1474  }
1475 
1482 #define setSIPR(sipr) { \
1483  WIZCHIP_WRITE(SIPR, (((uint16_t)((sipr)[0])) << 8) + (((uint16_t)((sipr)[1])) & 0x00FF)); \
1484  WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(SIPR,2), (((uint16_t)((sipr)[2])) << 8) + (((uint16_t)((sipr)[3])) & 0x00FF)); \
1485  }
1486 
1493 #define getSIPR(sipr) { \
1494  (sipr)[0] = (uint8_t)(WIZCHIP_READ(SIPR) >> 8); \
1495  (sipr)[1] = (uint8_t)(WIZCHIP_READ(SIPR)); \
1496  (sipr)[2] = (uint8_t)(WIZCHIP_READ(WIZCHIP_OFFSET_INC(SIPR,2)) >> 8); \
1497  (sipr)[3] = (uint8_t)(WIZCHIP_READ(WIZCHIP_OFFSET_INC(SIPR,2))); \
1498  }
1499 
1500 
1507 #define setRTR(rtr) \
1508  WIZCHIP_WRITE(_RTR_, rtr)
1509 
1516 #define getRTR() \
1517  WIZCHIP_READ(_RTR_)
1518 
1525 #define setRCR(rcr) \
1526  WIZCHIP_WRITE(_RCR_, ((uint16_t)rcr)&0x00FF)
1527 
1534 #define getRCR() \
1535  ((uint8_t)(WIZCHIP_READ(_RCR_) & 0x00FF))
1536 
1543 #define setTMS01R(tms01r) \
1544  WIZCHIP_WRITE(TMS01R,tms01r)
1545 
1552 #define getTMS01R() \
1553  WIZCHIP_READ(TMS01R)
1554 
1561 #define setTMS23R(tms23r) \
1562  WIZCHIP_WRITE(TMS23R,tms23r)
1563 
1570 #define getTMS23R() \
1571  WIZCHIP_READ(TMS23R)
1572 
1579 #define setTMS45R(tms45r) \
1580  WIZCHIP_WRITE(TMS45R,tms45r)
1581 
1588 #define getTMS45R() \
1589  WIZCHIP_READ(TMS45R)
1590 
1597 #define setTMS67R(tms67r) \
1598  WIZCHIP_WRITE(TMS67R,tms67r)
1599 
1606 #define getTMS67R() \
1607  WIZCHIP_READ(TMS67R)
1608 
1616 void setTMSR(uint8_t sn,uint8_t tmsr);
1617 #define setSn_TXBUF_SIZE(sn, tmsr) setTMSR(sn, tmsr)
1618 
1619 
1626 uint8_t getTMSR(uint8_t sn);
1627 #define getSn_TXBUF_SIZE(sn) getTMSR(sn)
1628 
1629 
1635 #define setRMS01R(rms01r) \
1636  WIZCHIP_WRITE(RMS01R,rms01r)
1637 
1644 #define getRMS01R() \
1645  WIZCHIP_READ(RMS01R)
1646 
1653 #define setRMS23R(rms23r) \
1654  WIZCHIP_WRITE(RMS23R,rms23r)
1655 
1662 #define getRMS23R() \
1663  WIZCHIP_READ(RMS23R)
1664 
1671 #define setRMS45R(rms45r) \
1672  WIZCHIP_WRITE(RMS45R,rms45r)
1673 
1680 #define getRMS45R() \
1681  WIZCHIP_READ(RMS45R)
1682 
1689 #define setRMS67R(rms67r) \
1690  WIZCHIP_WRITE(RMS67R,rms67r)
1691 
1698 #define getRMS67R() \
1699  WIZCHIP_READ(RMS67R)
1700 
1708 void setRMSR(uint8_t sn,uint8_t rmsr);
1709 #define setSn_RXBUF_SIZE(sn,rmsr) setRMSR(sn, rmsr)
1710 
1711 
1718 uint8_t getRMSR(uint8_t sn);
1719 #define getSn_RXBUF_SIZE(sn) getRMSR(sn)
1720 
1721 
1727 #define setMTYPER(mtype) \
1728  WIZCHIP_WRITE(MTYPER, mtype)
1729 
1736 #define getMTYPER() \
1737  WIZCHIP_READ(MTYPER)
1738 
1744 #define getPATR() \
1745  WIZCHIP_READ(PATR)
1746 
1753 #define setPTIMER(ptimer) \
1754  WIZCHIP_WRITE(PTIMER, ((uint16_t)ptimer) & 0x00FF)
1755 
1762 #define getPTIMER() \
1763  ((uint8_t)(WIZCHIP_READ(PTIMER) & 0x00FF))
1764 
1771 #define setPMAGIC(pmagic) \
1772  WIZCHIP_WRITE(PMAGIC, ((uint16_t)pmagic) & 0x00FF)
1773 
1780 #define getPMAGIC() \
1781  ((uint8_t)(WIZCHIP_READ(PMAGIC) & 0x00FF))
1782 
1788 #define getPSIDR() \
1789  WIZCHIP_READ(PSIDR)
1790 
1796 #define getPDHAR(pdhar) { \
1797  (pdhar)[0] = (uint8_t)(WIZCHIP_READ(PDHAR) >> 8); \
1798  (pdhar)[1] = (uint8_t)(WIZCHIP_READ(PDHAR)); \
1799  (pdhar)[2] = (uint8_t)(WIZCHIP_READ(WIZCHIP_OFFSET_INC(PDHAR,2)) >> 8); \
1800  (pdhar)[3] = (uint8_t)(WIZCHIP_READ(WIZCHIP_OFFSET_INC(PDHAR,2))); \
1801  (pdhar)[4] = (uint8_t)(WIZCHIP_READ(WIZCHIP_OFFSET_INC(PDHAR,4)) >> 8); \
1802  (pdhar)[5] = (uint8_t)(WIZCHIP_READ(WIZCHIP_OFFSET_INC(PDHAR,4))); \
1803  }
1804 
1810 #define getUIPR(uipr) { \
1811  (uipr)[0] = (uint8_t)(WIZCHIP_READ(UIPR) >> 8); \
1812  (uipr)[1] = (uint8_t)(WIZCHIP_READ(UIPR)); \
1813  (uipr)[2] = (uint8_t)(WIZCHIP_READ(WIZCHIP_OFFSET_INC(UIPR,2)) >> 8); \
1814  (uipr)[3] = (uint8_t)(WIZCHIP_READ(WIZCHIP_OFFSET_INC(UIPR,2))); \
1815  }
1816 
1822 #define getUPORTR() \
1823  WIZCHIP_READ(UPORTR)
1824 
1830 #define getFMTUR() \
1831  WIZCHIP_READ(FMTUR)
1832 
1833 
1839 #define getPn_BRDYR(p) \
1840  ((uint8_t)(WIZCHIP_READ(Pn_BRDYR(p)) & 0x00FF))
1841 
1848 #define setPn_BRDYR(p, brdyr) \
1849  WIZCHIP_WRITE(Pn_BRDYR(p), brdyr & 0x00E7)
1850 
1857 #define getPn_BDPTHR(p) \
1858  WIZCHIP_READ(Pn_BDPTHR(p))
1859 
1866 #define setPn_BDPTHR(p, bdpthr) \
1867  WIZCHIP_WRITE(Pn_BDPTHR(p),bdpthr)
1868 
1869 
1875 #define getIDR() \
1876  WIZCHIP_READ(IDR)
1877 
1878 
1879 /***********************************
1880  * SOCKET Register Access Function *
1881  ***********************************/
1882 
1890 #define setSn_MR(sn, mr) \
1891  WIZCHIP_WRITE(Sn_MR(sn),mr)
1892 
1900 #define getSn_MR(sn) \
1901  WIZCHIP_READ(Sn_MR(sn))
1902 
1910 #define setSn_CR(sn, cr) \
1911  WIZCHIP_WRITE(Sn_CR(sn), ((uint16_t)cr) & 0x00FF)
1912 
1920 #define getSn_CR(sn) \
1921  ((uint8_t)WIZCHIP_READ(Sn_CR(sn)))
1922 
1930 #define setSn_IMR(sn, imr) \
1931  WIZCHIP_WRITE(Sn_IMR(sn), ((uint16_t)imr) & 0x00FF)
1932 
1940 #define getSn_IMR(sn) \
1941  ((uint8_t)WIZCHIP_READ(Sn_IMR(sn)))
1942 
1950 #define setSn_IR(sn, ir) \
1951  WIZCHIP_WRITE(Sn_IR(sn), ((uint16_t)ir) & 0x00FF)
1952 
1960 #define getSn_IR(sn) \
1961  ((uint8_t)WIZCHIP_READ(Sn_IR(sn)))
1962 
1969 #define getSn_SSR(sn) \
1970  ((uint8_t)WIZCHIP_READ(Sn_SR(sn)))
1971 #define getSn_SR(sn) getSn_SSR(sn)
1972 
1973 
1980 #define setSn_PORTR(sn, port) \
1981  WIZCHIP_WRITE(Sn_PORTR(sn), port)
1982 #define setSn_PORT(sn, port) setSn_PORTR(sn, port)
1983 
1984 
1991 #define getSn_PORTR(sn, port) \
1992  WIZCHIP_READ(Sn_PORTR(sn))
1993 #define getSn_PORT(sn) getSn_PORTR(sn)
1994 
1995 
2002 #define setSn_DHAR(sn, dhar) { \
2003  WIZCHIP_WRITE(Sn_DHAR(sn), (((uint16_t)((dhar)[0])) << 8) + (((uint16_t)((dhar)[1])) & 0x00FF)); \
2004  WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_DHAR(sn),2), (((uint16_t)((dhar)[0])) << 8) + (((uint16_t)((dhar)[1])) & 0x00FF)); \
2005  WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_DHAR(sn),4), (((uint16_t)((dhar)[0])) << 8) + (((uint16_t)((dhar)[1])) & 0x00FF)); \
2006  }
2007 
2015 #define getSn_DHAR(sn, dhar) { \
2016  (dhar)[0] = (uint8_t)(WIZCHIP_READ(Sn_DHAR(sn)) >> 8); \
2017  (dhar)[1] = (uint8_t) WIZCHIP_READ(Sn_DHAR(sn)); \
2018  (dhar)[2] = (uint8_t)(WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_DHAR(sn),2)) >> 8); \
2019  (dhar)[3] = (uint8_t) WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_DHAR(sn),2)); \
2020  (dhar)[4] = (uint8_t)(WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_DHAR(sn),4)) >> 8); \
2021  (dhar)[5] = (uint8_t) WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_DHAR(sn),4)); \
2022  }
2023 
2031 #define setSn_DPORTR(sn, dport) \
2032  WIZCHIP_WRITE(Sn_DPORTR(sn),dport)
2033 #define setSn_DPORT(sn, dport) setSn_DPORTR(sn,dport)
2034 
2035 
2045 #define getSn_DPORTR(sn) \
2046  WIZCHIP_READ(Sn_DPORTR(sn))
2047 #define getSn_DPORT(sn) getSn_DPORTR(sn)
2048 
2049 
2056 #define setSn_DIPR(sn, dipr) { \
2057  WIZCHIP_WRITE(Sn_DIPR(sn), (((uint16_t)((dipr)[0])) << 8) + (((uint16_t)((dipr)[1])) & 0x00FF)); \
2058  WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_DIPR(sn),2), (((uint16_t)((dipr)[2])) << 8) + (((uint16_t)((dipr)[3])) & 0x00FF)); \
2059  }
2060 
2068 #define getSn_DIPR(sn, dipr) { \
2069  (dipr)[0] = (uint8_t)(WIZCHIP_READ(Sn_DIPR(sn)) >> 8); \
2070  (dipr)[1] = (uint8_t) WIZCHIP_READ(Sn_DIPR(sn)); \
2071  (dipr)[2] = (uint8_t)(WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_DIPR(sn),2)) >> 8); \
2072  (dipr)[3] = (uint8_t) WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_DIPR(sn),2)); \
2073  }
2074 
2082 #define setSn_MSSR(sn, mss) \
2083  WIZCHIP_WRITE(Sn_MSSR(sn), mss)
2084 
2092 #define getSn_MSSR(sn) \
2093  WIZCHIP_READ(Sn_MSSR(sn))
2094 
2102 #define setSn_KPALVTR(sn, kpalvt) \
2103  WIZCHIP_WRITE(Sn_KPALVTR(sn), (WIZCHIP_READ(Sn_KPALVTR(sn)) & 0x00FF) | (((uint16_t)kpalvt)<<8))
2104 
2112 #define getSn_KPALVTR(sn) \
2113  ((uint8_t)(WIZCHIP_READ(Sn_KPALVTR(sn)) >> 8))
2114 
2122 #define setSn_PROTOR(sn, proto) \
2123  WIZCHIP_WRITE(Sn_PROTOR(sn),(WIZCHIP_READ(Sn_PROTOR(sn) & 0xFF00) | (((uint16_t)proto) & 0x00FF))
2124 #define setSn_PROTO(sn,proto) setSn_PROTOR(sn,proto)
2125 
2126 
2133 #define getSn_PROTOR(sn) \
2134  ((uint8_t)WIZCHIP_READ(Sn_PROTOR(sn)))
2135 #define getSn_PROTO(sn) getSn_PROTOR(sn)
2136 
2137 
2144 #define setSn_TX_WRSR(sn, txwrs) { \
2145  WIZCHIP_WRITE(Sn_TX_WRSR(sn), (uint16_t)(((uint32_t)txwrs) >> 16)); \
2146  WIZCHIP_WRITE(WIZCHIP_OFFSET_INC(Sn_TX_WRSR(sn),2), (uint16_t)txwrs); \
2147  }
2148 
2156 #define getSn_TX_WRSR(sn) \
2157  ( (((uint32_t)WIZCHIP_READ(Sn_TX_WRSR(sn))) << 16) + (((uint32_t)WIZCHIP_READ(WIZCHIP_OFFSET_INC(Sn_TX_WRSR(sn),1))) & 0x0000FFFF) )
2158 
2165 uint32_t getSn_TX_FSR(uint8_t sn);
2166 
2173 uint32_t getSn_RX_RSR(uint8_t sn);
2174 
2181 #define setSn_TX_FIFOR(sn, txfifo) \
2182  WIZCHIP_WRITE(Sn_TX_FIFOR(sn), txfifo);
2183 
2190 #define getSn_RX_FIFOR(sn) \
2191  WIZCHIP_READ(Sn_RX_FIFOR(sn));
2192 
2200 #define setSn_TOSR(sn, tos) \
2201  WIZCHIP_WRITE(Sn_TOS(sn), ((uint16_t)tos) & 0x00FF)
2202 #define setSn_TOS(sn,tos) setSn_TOSR(sn,tos)
2203 
2204 
2211 #define getSn_TOSR(sn) \
2212  ((uint8_t)WIZCHIP_READ(Sn_TOSR(sn)))
2213 #define getSn_TOS(sn) getSn_TOSR(sn)
2214 
2215 
2222 #define setSn_TTLR(sn, ttl) \
2223  WIZCHIP_WRITE(Sn_TTLR(sn), ((uint16_t)ttl) & 0x00FF)
2224 #define setSn_TTL(sn,ttl) setSn_TTLR(sn,ttl)
2225 
2226 
2233 #define getSn_TTLR(sn) \
2234  ((uint8_t)WIZCHIP_READ(Sn_TTL(sn)))
2235 #define getSn_TTL(sn) getSn_TTLR(sn)
2236 
2237 
2244 #define setSn_FRAGR(sn, frag) \
2245  WIZCHIP_WRITE(Sn_FRAGR(sn), (uint16_t)(frag >>8))
2246 #define setSn_FRAG(sn,frag) setSn_FRAGR(sn,flag)
2247 
2255 #define getSn_FRAGR(sn) \
2256  (WIZCHIP_READ(Sn_FRAG(sn)) << 8)
2257 #define getSn_FRAG(sn) getSn_FRAGR(sn)
2258 
2259 
2261 // Sn_TXBUF & Sn_RXBUF IO function //
2263 
2270 #define getSn_RxMAX(sn) \
2271  (((uint32_t)getSn_RXBUF_SIZE(sn)) << 10)
2272 
2279 #define getSn_TxMAX(sn) \
2280  (((uint32_t)getSn_TXBUF_SIZE(sn)) << 10)
2281 
2296 void wiz_send_data(uint8_t sn, uint8_t *wizdata, uint32_t len);
2297 
2312 void wiz_recv_data(uint8_t sn, uint8_t *wizdata, uint32_t len);
2313 
2321 void wiz_recv_ignore(uint8_t sn, uint32_t len);
2322 
2324 #endif
2325 
2327 #endif // _W5300_H_
wiz_recv_data
void wiz_recv_data(uint8_t sn, uint8_t *wizdata, uint32_t len)
It copies data to your buffer from internal RX memory.
WIZCHIP_READ
uint16_t WIZCHIP_READ(uint32_t AddrSel)
It reads 1 byte value from a register.
setTMSR
void setTMSR(uint8_t sn, uint8_t tmsr)
Set TMSR0 ~ TMSR7 register.
getSn_TX_FSR
uint32_t getSn_TX_FSR(uint8_t sn)
Get Sn_TX_FSR register.
getTMSR
uint8_t getTMSR(uint8_t sn)
Get TMSR0 ~ TMSR7 register.
WIZCHIP_WRITE
void WIZCHIP_WRITE(uint32_t AddrSel, uint16_t wb)
It writes 1 byte value to a register.
wiz_recv_ignore
void wiz_recv_ignore(uint8_t sn, uint32_t len)
It discard the received data in RX memory.
wiz_send_data
void wiz_send_data(uint8_t sn, uint8_t *wizdata, uint32_t len)
It copies data to internal TX memory.
getSn_RX_RSR
uint32_t getSn_RX_RSR(uint8_t sn)
Get Sn_RX_RSR register.
getRMSR
uint8_t getRMSR(uint8_t sn)
Get RMS01R ~ RMS67R register.
setRMSR
void setRMSR(uint8_t sn, uint8_t rmsr)
Set RMS01R ~ RMS67R register.
wizchip_conf.h
WIZCHIP Config Header File.
Generated on Wed May 4 2016 16:43:58 for Socket APIs by   doxygen 1.8.9.1
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