39 #ifndef __STM32_BLUENRG_BLE_H 40 #define __STM32_BLUENRG_BLE_H 47 #include "stm32l4xx_hal.h" 48 #define SYSCLK_FREQ 80000000 67 #define BNRG_SPI_INSTANCE SPI1 68 #define BNRG_SPI_CLK_ENABLE() __SPI1_CLK_ENABLE() 71 #define BNRG_SPI_MODE SPI_MODE_MASTER 72 #define BNRG_SPI_DIRECTION SPI_DIRECTION_2LINES 73 #define BNRG_SPI_DATASIZE SPI_DATASIZE_8BIT 74 #define BNRG_SPI_CLKPOLARITY SPI_POLARITY_LOW 75 #define BNRG_SPI_CLKPHASE SPI_PHASE_1EDGE 76 #define BNRG_SPI_NSS SPI_NSS_SOFT 77 #define BNRG_SPI_FIRSTBIT SPI_FIRSTBIT_MSB 78 #define BNRG_SPI_TIMODE SPI_TIMODE_DISABLED 79 #define BNRG_SPI_CRCPOLYNOMIAL 7 80 #define BNRG_SPI_BAUDRATEPRESCALER SPI_BAUDRATEPRESCALER_16 81 #define BNRG_SPI_CRCCALCULATION SPI_CRCCALCULATION_DISABLED 84 #define BNRG_SPI_RESET_PIN GPIO_PIN_0 85 #define BNRG_SPI_RESET_MODE GPIO_MODE_OUTPUT_PP 86 #define BNRG_SPI_RESET_PULL GPIO_PULLUP 87 #define BNRG_SPI_RESET_SPEED GPIO_SPEED_LOW 88 #define BNRG_SPI_RESET_ALTERNATE 0 89 #define BNRG_SPI_RESET_PORT GPIOH 90 #define BNRG_SPI_RESET_CLK_ENABLE() __GPIOH_CLK_ENABLE() 93 #define BNRG_SPI_SCLK_PIN GPIO_PIN_5 94 #define BNRG_SPI_SCLK_MODE GPIO_MODE_AF_PP 95 #define BNRG_SPI_SCLK_PULL GPIO_PULLDOWN 96 #define BNRG_SPI_SCLK_SPEED GPIO_SPEED_HIGH 97 #define BNRG_SPI_SCLK_ALTERNATE GPIO_AF5_SPI1 98 #define BNRG_SPI_SCLK_PORT GPIOA 99 #define BNRG_SPI_SCLK_CLK_ENABLE() __GPIOA_CLK_ENABLE() 102 #define BNRG_SPI_MISO_PIN GPIO_PIN_6 103 #define BNRG_SPI_MISO_MODE GPIO_MODE_AF_PP 104 #define BNRG_SPI_MISO_PULL GPIO_NOPULL 105 #define BNRG_SPI_MISO_SPEED GPIO_SPEED_HIGH 106 #define BNRG_SPI_MISO_ALTERNATE GPIO_AF5_SPI1 107 #define BNRG_SPI_MISO_PORT GPIOA 108 #define BNRG_SPI_MISO_CLK_ENABLE() __GPIOA_CLK_ENABLE() 111 #define BNRG_SPI_MOSI_PIN GPIO_PIN_7 112 #define BNRG_SPI_MOSI_MODE GPIO_MODE_AF_PP 113 #define BNRG_SPI_MOSI_PULL GPIO_NOPULL 114 #define BNRG_SPI_MOSI_SPEED GPIO_SPEED_HIGH 115 #define BNRG_SPI_MOSI_ALTERNATE GPIO_AF5_SPI1 116 #define BNRG_SPI_MOSI_PORT GPIOA 117 #define BNRG_SPI_MOSI_CLK_ENABLE() __GPIOA_CLK_ENABLE() 120 #define BNRG_SPI_CS_PIN GPIO_PIN_2 121 #define BNRG_SPI_CS_MODE GPIO_MODE_OUTPUT_PP 122 #define BNRG_SPI_CS_PULL GPIO_PULLUP 123 #define BNRG_SPI_CS_SPEED GPIO_SPEED_HIGH 124 #define BNRG_SPI_CS_ALTERNATE 0 125 #define BNRG_SPI_CS_PORT GPIOB 126 #define BNRG_SPI_CS_CLK_ENABLE() __GPIOB_CLK_ENABLE() 129 #define BNRG_SPI_IRQ_PIN GPIO_PIN_5 130 #define BNRG_SPI_IRQ_MODE GPIO_MODE_IT_RISING 131 #define BNRG_SPI_IRQ_PULL GPIO_NOPULL 132 #define BNRG_SPI_IRQ_SPEED GPIO_SPEED_HIGH 133 #define BNRG_SPI_IRQ_ALTERNATE 0 134 #define BNRG_SPI_IRQ_PORT GPIOC 135 #define BNRG_SPI_IRQ_CLK_ENABLE() __GPIOC_CLK_ENABLE() 140 #define BNRG_SPI_EXTI_IRQn EXTI9_5_IRQn 141 #define BNRG_SPI_EXTI_IRQHandler EXTI9_5_IRQHandler 142 #define BNRG_SPI_EXTI_PIN BNRG_SPI_IRQ_PIN 143 #define BNRG_SPI_EXTI_PORT BNRG_SPI_IRQ_PORT 173 extern void Hal_Write_Serial(
const void* data1,
const void* data2, int32_t n_bytes1,
void Disable_SPI_IRQ(void)
Disable SPI IRQ.
int32_t BlueNRG_SPI_Write(SPI_HandleTypeDef *hspi, uint8_t *data1, uint8_t *data2, uint8_t Nb_bytes1, uint8_t Nb_bytes2)
Writes data from local buffer to SPI.
void Clear_SPI_IRQ(void)
Clear Pending SPI IRQ.
void Clear_SPI_EXTI_Flag(void)
Clear EXTI (External Interrupt) line for SPI IRQ.
void Enable_SPI_IRQ(void)
Enable SPI IRQ.
uint8_t BlueNRG_DataPresent(void)
Reports if the BlueNRG has data for the host micro.
void BlueNRG_HW_Bootloader(void)
Activate internal bootloader using pin.
void BNRG_SPI_Init(void)
Initializes the SPI communication with the BlueNRG Expansion Board.
int32_t BlueNRG_SPI_Read_All(SPI_HandleTypeDef *hspi, uint8_t *buffer, uint8_t buff_size)
Reads from BlueNRG SPI buffer and store data into local buffer.
void Hal_Write_Serial(const void *data1, const void *data2, int32_t n_bytes1, int32_t n_bytes2)
Writes data to a serial interface.
void BlueNRG_RST(void)
Resets the BlueNRG.
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