STSW-STLKT01: Projects/SensorTile/Applications/AudioLoop/Src/system_stm32l4xx.c Source File

STSW-STLKT01

 
 #include "stm32l4xx.h"
 
 #if !defined (HSE_VALUE)
  #define HSE_VALUE ((uint32_t)8000000) 
 #endif /* HSE_VALUE */
 
 #if !defined (MSI_VALUE)
  #define MSI_VALUE ((uint32_t)4000000) 
 #endif /* MSI_VALUE */
 
 #if !defined (HSI_VALUE)
  #define HSI_VALUE ((uint32_t)16000000) 
 #endif /* HSI_VALUE */
 
 /************************* Miscellaneous Configuration ************************/
 /* #define VECT_TAB_SRAM */
 #define VECT_TAB_OFFSET 0x000 
 /******************************************************************************/
 
  /* The SystemCoreClock variable is updated in three ways:
  1) by calling CMSIS function SystemCoreClockUpdate()
  2) by calling HAL API function HAL_RCC_GetHCLKFreq()
  3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
  Note: If you use this function to configure the system clock; then there
  is no need to call the 2 first functions listed above, since SystemCoreClock
  variable is updated automatically.
  */
  uint32_t SystemCoreClock = 4000000;
 
  const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
  const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
  const uint32_t MSIRangeTable[12] = {100000, 200000, 400000, 800000, 1000000, 2000000, \
  4000000, 8000000, 16000000, 24000000, 32000000, 48000000};
 void SystemInit(void)
 {
  /* FPU settings ------------------------------------------------------------*/
  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
  SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
  #endif
  /* Reset the RCC clock configuration to the default reset state ------------*/
  /* Set MSION bit */
  RCC->CR |= RCC_CR_MSION;
 
  /* Reset CFGR register */
  RCC->CFGR = 0x00000000;
 
  /* Reset HSEON, CSSON , HSION, and PLLON bits */
  RCC->CR &= (uint32_t)0xEAF6FFFF;
 
  /* Reset PLLCFGR register */
  RCC->PLLCFGR = 0x00001000;
 
  /* Reset HSEBYP bit */
  RCC->CR &= (uint32_t)0xFFFBFFFF;
 
  /* Disable all interrupts */
  RCC->CIER = 0x00000000;
 
  /* Configure the Vector Table location add offset address ------------------*/
 #ifdef VECT_TAB_SRAM
  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
 #else
  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
 #endif
 }
 
 void SystemCoreClockUpdate(void)
 {
  uint32_t tmp = 0, msirange = 0, pllvco = 0, pllr = 2, pllsource = 0, pllm = 2;
 
  /* Get MSI Range frequency--------------------------------------------------*/
  if((RCC->CR & RCC_CR_MSIRGSEL) == RESET)
  { /* MSISRANGE from RCC_CSR applies */
  msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8;
  }
  else
  { /* MSIRANGE from RCC_CR applies */
  msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4;
  }
  /*MSI frequency range in HZ*/
  msirange = MSIRangeTable[msirange];
 
  /* Get SYSCLK source -------------------------------------------------------*/
  switch (RCC->CFGR & RCC_CFGR_SWS)
  {
  case 0x00: /* MSI used as system clock source */
  SystemCoreClock = msirange;
  break;
 
  case 0x04: /* HSI used as system clock source */
  SystemCoreClock = HSI_VALUE;
  break;
 
  case 0x08: /* HSE used as system clock source */
  SystemCoreClock = HSE_VALUE;
  break;
 
  case 0x0C: /* PLL used as system clock source */
  /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
  SYSCLK = PLL_VCO / PLLR
  */
  pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
  pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4) + 1 ;
 
  switch (pllsource)
  {
  case 0x02: /* HSI used as PLL clock source */
  pllvco = (HSI_VALUE / pllm);
  break;
 
  case 0x03: /* HSE used as PLL clock source */
  pllvco = (HSE_VALUE / pllm);
  break;
 
  default: /* MSI used as PLL clock source */
  pllvco = (msirange / pllm);
  break;
  }
  pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8);
  pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1) * 2;
  SystemCoreClock = pllvco/pllr;
  break;
 
  default:
  SystemCoreClock = msirange;
  break;
  }
  /* Compute HCLK clock frequency --------------------------------------------*/
  /* Get HCLK prescaler */
  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
  /* HCLK clock frequency */
  SystemCoreClock >>= tmp;
 }
 
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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