User-Level Functionality

An INSTR session to a PCI or PXI device provides the same register-level programming functionality as in VXI. NI-VISA supports both high-level and low-level accesses, as discussed in Register-Based Communication. The valid address spaces for a PXI device are the configuration registers (VI_PXI_CFG_SPACE) and the six Base Address Registers (VI_PXI_BAR0_SPACE–VI_PXI_BAR5_SPACE). A device may support any or all of the BARs. This information is device dependent but can be queried through the attributes VI_ATTR_PXI_MEM_TYPE_BAR0–VI_ATTR_PXI_MEM_TYPE_BAR5. The values for this attribute are none (0), memory mapped (1), or I/O (2). If the value is memory mapped or I/O, you can also query the appropriate attributes for the base and size of each supported region.

In addition to register accesses, NI-VISA supports the event VI_EVENT_PXI_INTR to provide notification to an application that the specified device has generated a PCI interrupt. This event allows a user to write an entire device driver or instrument driver at the user level, without having to write any kernel code.