NI sbRIO-9642 (FPGA Interface)
Single-Board Reconfigurable I/O (AI, AO, DI, DO, DIO)
32 AI channels, 4 AO channels, 110 3.3 V DIO channels, 32 24 V DI channels, 32 24 V DO channels, 2 million gate FPGA
FPGA I/O Node
You can use an FPGA I/O Node, configured for reading and writing, with this device.
Terminals in Software
Use the FPGA I/O Node to access the following terminals for this device.
| Terminal | Description |
|---|---|
| Portx/DIOy | Digital input/output channel y on port x, where y is the channel number and x is the port number. The NI sbRIO-9642 has ports 0 to 9. Use the FPGA I/O Node or the Set Data Output or Set Data Enable method to access this channel. |
| Portx/DIOCTL | Digital control channel on port x. Do not use DIOCTL for high-speed digital communication. |
| Portx/DIO9:0 | Digital input/output channels 0 to 9 on port x. Use the FPGA I/O Node or the Set Data Output or Set Data Enable method to access all channels on the port. |
Arbitration
You can configure the arbitration settings for the DIO channels of this device in the Advanced Code Generation page of the FPGA I/O Properties dialog box. The default arbitration setting is Never Arbitrate. For information about arbitration on channels of an onboard or installed C Series module, refer to the help topic for the module. You can find the help topic for the module you are using by navigating on the Contents tab to FPGA Module»CompactRIO Reference and Procedures»Module Type»NI 9xxx.
Onboard C Series Module I/O
This device contains onboard NI 9205, NI 9263, NI 9425, and NI 9476 modules.
I/O Methods
Use the FPGA I/O Method Node to access the following methods for this device. This device does not support any module methods.
| Method | Description |
|---|---|
| Set Output Data | Refer to the FPGA I/O Method Node topic for a description of this method. |
| Set Output Enable | Refer to the FPGA I/O Method Node topic for a description of this method. |
Properties
This device does not support any properties.
Single-Cycle Timed Loop
This device supports the single-cycle Timed Loop for digital I/O only. Configure the number of output synchronizing registers for the channels of this device in the Advanced Code Generation page of the FPGA I/O Properties dialog box. Configure the number of input synchronizing registers for the channels of this device in the Advanced Code Generation page of the FPGA I/O Node Properties dialog box.