Set Triggers Method (FPGA Interface)

This module method controls the data returned by the trigger digital input line. You use this module method by selecting it in an FPGA I/O Method Node that is configured for the appropriate device and/or channel. Details Examples

	Trigger Mode is an enumeration of the following trigger mode options: None disables the trigger function. AI Below Low detects when the analog signal is below the low threshold you specify. AI Above High detects when the analog signal is above the high threshold you specify. AI Inside Region detects when the analog signal is between the high and low thresholds you specify. AI Below Low with Hysteresis asserts the trigger when the signal starts above the high threshold you specify and then crosses below the low threshold you specify. The trigger deasserts when the signal crosses above the high threshold you specify. AI Above High with Hysteresis asserts the trigger when the signal starts below the low threshold you specify and then crosses above the high threshold you specify. The trigger deasserts when the signal crosses below the low threshold you specify. DI Trigger detects when the digital signal on PFI0 is logic high. Note  The onboard NI 9205 on Single-Board RIO (sbRIO) devices does not support DI triggering.
	AI High Threshold defines the upper threshold for the analog trigger circuit.
	AI Low Threshold defines the lower threshold for the analog trigger circuit.

error in describes error conditions that occur before this VI or function runs. The default is no error. If an error occurred before this VI or function runs, the VI or function passes the error in value to error out. This VI or function runs normally only if no error occurred before this VI or function runs. If an error occurs while this VI or function runs, it runs normally and sets its own error status in error out. Use error in and error out to check errors and to specify execution order by wiring error out from one node to error in of the next node. status is TRUE if an error occurred. If status is TRUE, the VI does not perform any operations. code is the error code number identifying an error. The default is 0. If status is TRUE, code is a nonzero error code. If status is FALSE, code is 0 or a warning code. source always contains an empty string because strings are not supported in LabVIEW FPGA.

error out contains error information. If error in indicates that an error occurred before this VI or function ran, error out contains the same error information. Otherwise, it describes the error status that this VI or function produces. Right-click the error out indicator on the front panel and select Explain Error from the shortcut menu for more information about the error. status is TRUE if an error occurred. If status is TRUE, the VI does not perform any operations. code is the error code number identifying an error. The default is 0. If status is TRUE, code is a nonzero error code. If status is FALSE, code is 0 or a warning code. source always contains an empty string because strings are not supported in LabVIEW FPGA.

Using This Method

Use the Set Triggers Method to configure the trigger circuit on the module. Once the trigger circuit is configured, use an FPGA I/O Node configured to access the Trig channel to monitor the output of the trigger circuit. The trigger circuit does not automatically initiate any conversions on the module. It is up to the FPGA VI to monitor the Trig line, and then initiate a conversion using an FPGA I/O Node or the IO Sample method when the appropriate trigger event occurs.

Perform the following steps to trigger an acquisition using the Set Triggers Method:

1. Ensure that the module pipeline is primed with the next two channels that you want to sample after the trigger event. This step will minimize the delay between the trigger event and the AI channels getting sampled. For analog triggering modes, this step also configures the analog trigger circuitry to monitor the desired channel. The AI trigger circuit monitors the channel waiting in the module pipeline for the next conversion.
   
   If you are using FPGA I/O Nodes to perform the acquisition, this step can be accomplished by executing an FPGA I/O Node configured to match the FPGA I/O Node that you will be executing after the trigger event. If you are using one of the analog triggering modes along with the FPGA I/O Nodes, the AI trigger circuit will operate on the lowest numbered channel present in the FPGA I/O Node.
   
   Refer to the IO Sample method and Conversion Timing topics for more information on managing the module pipeline using the IO Sample method. If you are using one of the analog trigger modes along with the IO Sample method, the AI trigger circuit will operate on the channel waiting in the pipeline to be converted by the next IO Sample method.
2. Execute the Set Triggers method with the appropriate trigger mode selected. The trigger mode circuitry is implemented in the hardware as you specify in this method. Refer to the NI 9205 Operating Instructions and Specifications or NI 9206 Operating Instructions and Specifications for more information about the trigger modes.
3. Monitor the Trig channel in a loop until you see the appropriate trigger condition occur.
4. Execute an FPGA I/O Node or IO Sample method function to acquire data in response to the trigger event.

Examples

Refer to the 9205 Basic Triggering VI and the 9205 Advanced Triggering VI in the labview\examples\CompactRIO\Module Specific\NI 9205\NI 9205 Basic Triggering and labview\examples\CompactRIO\Module Specific\NI 9205\NI 9205 Advanced Triggering directories for examples of the triggering concepts discussed above.

• Basic Triggering
  
   Open example
• Advanced Triggering
  
   Open example