NI sbRIO-9602 (FPGA Interface)
Single-Board Reconfigurable I/O (DIO)
110 3.3 V DIO channels, 2 million gate FPGA
FPGA I/O Node
You can use an FPGA I/O Node, configured for reading and writing, with this device.
Terminals in Software
Use the FPGA I/O Node to access the following terminals for this device.
| Terminal | Description |
|---|---|
| Portx/DIOy | Digital input/output channel y on port x, where y is the channel number and x is the port number. The NI sbRIO-9602 has ports 0 to 9. Use the FPGA I/O Node or the Set Data Output or Set Data Enable method to access this channel. |
| Portx/DIOCTL | Digital control channel on port x. Do not use DIOCTL for high-speed digital communication. |
| Portx/DIO9:0 | Digital input/output channels 0 to 9 on port x. Use the FPGA I/O Node or the Set Data Output or Set Data Enable method to access all channels on the port. |
Arbitration
You can configure the arbitration settings for the DIO channels of this device in the Advanced Code Generation page of the FPGA I/O Properties dialog box. The default arbitration setting is Never Arbitrate.
I/O Methods
Use the FPGA I/O Method Node to access the following methods for this device. This device does not support any module methods.
| Method | Description |
|---|---|
| Set Output Data | Refer to the FPGA I/O Method Node topic for a description of this method. |
| Set Output Enable | Refer to the FPGA I/O Method Node topic for a description of this method. |
Properties
This device does not support any properties.
Single-Cycle Timed Loop
This device supports the single-cycle Timed Loop. Configure the number of output synchronizing registers for the channels of this device in the Advanced Code Generation page of the FPGA I/O Properties dialog box. Configure the number of input synchronizing registers for the channels of this device in the Advanced Code Generation page of the FPGA I/O Node Properties dialog box.