Synchronizing Multiple NI 9225/9229/923x Modules (FPGA Interface)
You can synchronize multiple NI 9225/9229/923x modules that are connected to the same FPGA device. To synchronize multiple NI 9225/9229/923x modules, the modules must use the same master timebase source, the modules must start acquisition mode at the same time, and a single FPGA I/O Node function must read the synchronous data. You must create FPGA I/O items for the NI 9225/9229/923x before you can configure the items using the FPGA I/O Node. Develop the FPGA VI to meet the following guidelines.
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Note Synchronizing the NI 9234 module with NI 9225/9229/9233/9235/9236/9237/9239 modules depends on the frequency of the shared master timebase. |
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Note The cRIO-9151 R Series Expansion chassis does not support synchronizing multiple NI 9225/9229/923x modules. |
Sharing a Master Timebase Source
Configure the modules to share the same master timebase source.
Starting the Synchronized Acquisition
Configure an FPGA I/O Node with Start channels for the NI 9225/9229/923x modules you want to synchronize and wire a Boolean constant set to TRUE to each Start channel.
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Note Ensure that all I/O channels are in the same FPGA I/O Node. Otherwise, the FPGA I/O Node will not return synchronized data. |
Acquiring Data from Synchronized NI 9225/9229/923x Modules with the Same Data Rate
Configure an FPGA I/O Node with all of the channels from which you want to synchronously sample.
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Note Ensure that all I/O channels are in the same FPGA I/O Node. Otherwise, the FPGA I/O Node will not return synchronized data. |
Refer to the Synchronizing NI 923x Modules (FPGA) VI in the labview\examples\CompactRIO\Module Specific\NI 923x\Synchronizing NI 923x Modules directory for an example of synchronizing multiple modules with the same data rate.
Open example
Acquiring Data from Synchronized NI 9225/9229/923x Modules with Different Data Rates
If you synchronize NI 9225/9229/923x modules that are configured for different data rates, create a separate loop for each data rate in the FPGA VI. In each loop, configure an FPGA I/O Node with all of the channels that are configured for the data rate of that loop. If you place NI 9225/9229/923x channels that are configured for different data rates in the same loop, LabVIEW returns an overrun warning from the FPGA I/O Node (error 65539) when you run the VI. There is a delay before the FPGA I/O Node returns the first data point. The length of the delay depends on the data rate of the NI 9225/9229/923x.