Advanced Configuration Dialog Box (FPGA Interface)

Click the Advanced button on the C Series Module Properties dialog box for the NI 9401, NI 9472, NI 9474, NI 9475, NI 9481, or NI 9485 to display this dialog box.

Use this dialog box to configure the number of output synchronizing registers for each DO channel in a single-cycle Timed Loop.

This dialog box includes the following components:

• Channels—Select the channel for which you want to configure the number of output synchronizing registers.
• Channel Configuration—Specifies the number of synchronizing registers between the DO channel executing on the FPGA target and the FPGA target hardware interface. The FPGA target hardware interface might be a physical I/O connector on the device or a connection to a section of the FPGA that contains circuitry designed by National Instruments. Each synchronizing register executes in one clock cycle.

  Caution  Select 0 only if you also use the HDL Interface Node and the HDL code contains its own synchronization registers.

  • 0—Specifies that the FPGA VI uses no synchronizing registers. Do not select this option for most FPGA Module applications.
    
    

    Note  If you select 0 for digital output resources in a single-cycle Timed Loop, you create a combinatorial circuit between the two resources. The combinatorial circuit might cause glitches on the output signal.

  • 1—Specifies that the FPGA VI uses one synchronizing register between the DO channel and the FPGA target hardware interface.