NI 9481 (FPGA Interface)
CompactRIO 4-Channel, Form A Electromechanical Relay Module
FPGA I/O Node
You can use an FPGA I/O Node, configured for writing, with this device.
Terminals in Software
Use the FPGA I/O Node to access the following terminals for this device.
| Terminal | Description |
|---|---|
| CHx | Channel x, where x is the number of the channel. The NI 9481 has channels 0 to 3. |
| CH3:0 | Digital port consisting of channels 0 through 3. Channel 3 is returned in bit 3, and channel 0 is returned in bit 0. |
Arbitration
You can configure the arbitration settings for the channels of this device in the Advanced Code Generation page of the FPGA I/O Properties dialog box. The default arbitration setting is Never Arbitrate.
Module Methods
Use the FPGA I/O Method Node to access the following method for this device. This device does not support any I/O methods.
| Method | Description | ||
|---|---|---|---|
| Check Status | Returns a Boolean value that indicates whether the module is ready.
|
Module Properties
Use the FPGA I/O Property Node to access the following properties for this device. This device does not support any I/O properties.
| Property | Description |
|---|---|
| Module ID | Returns the module ID. |
| Serial Number | Returns the unique serial number of the module. |
| Vendor ID | Returns the National Instruments vendor ID, 0x1093. |
Single-Cycle Timed Loop
This device supports the single-cycle Timed Loop. Configure the number of output synchronizing registers for the channels of this device in the Advanced Configuration dialog box.
When the module is within a single-cycle Timed Loop, it must be ready to perform digital output before a loop containing digital output starts. Poll the Ready output of the Check Status method to determine whether the module is ready. The module might ignore or delay digital output operations if it is not ready.
While the module is performing digital output within a single-cycle Timed Loop, do not perform property reads or remove the module from the chassis. Doing either of these actions causes the module to be unable to perform digital output and the Ready output of the Check Status method to return FALSE.
FPGA Target Clock Support
This device supports only top-level FPGA target clock rates and single-cycle Timed Loop clock rates that are multiples of 40 MHz, such as 40 MHz, 80 Mhz, 120 MHz, and so on.
Hardware Documentation
Refer to the NI 9481 Operating Instructions and Specifications to learn about module specifications and how to use the module. Refer to the CompactRIO Related Documentation for further information about CompactRIO documentation.