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STM8S/A Standard Peripherals Drivers
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stm8s_tim5.c
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00001 /** 00002 ****************************************************************************** 00003 * @file stm8s_tim5.c 00004 * @author MCD Application Team 00005 * @version V2.3.0 00006 * @date 16-June-2017 00007 * @brief This file contains all the functions for the TIM5 peripheral. 00008 ****************************************************************************** 00009 * @attention 00010 * 00011 * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> 00012 * 00013 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 00014 * You may not use this file except in compliance with the License. 00015 * You may obtain a copy of the License at: 00016 * 00017 * http://www.st.com/software_license_agreement_liberty_v2 00018 * 00019 * Unless required by applicable law or agreed to in writing, software 00020 * distributed under the License is distributed on an "AS IS" BASIS, 00021 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 00022 * See the License for the specific language governing permissions and 00023 * limitations under the License. 00024 * 00025 ****************************************************************************** 00026 */ 00027 00028 /* Includes ------------------------------------------------------------------*/ 00029 #include "stm8s_tim5.h" 00030 00031 /** @addtogroup STM8S_StdPeriph_Driver 00032 * @{ 00033 */ 00034 /* Private typedef -----------------------------------------------------------*/ 00035 /* Private define ------------------------------------------------------------*/ 00036 /* Private macro -------------------------------------------------------------*/ 00037 /* Private variables ---------------------------------------------------------*/ 00038 /* Private function prototypes -----------------------------------------------*/ 00039 static void TI1_Config(uint8_t TIM5_ICPolarity, uint8_t TIM5_ICSelection, uint8_t TIM5_ICFilter); 00040 static void TI2_Config(uint8_t TIM5_ICPolarity, uint8_t TIM5_ICSelection, uint8_t TIM5_ICFilter); 00041 static void TI3_Config(uint8_t TIM5_ICPolarity, uint8_t TIM5_ICSelection, uint8_t TIM5_ICFilter); 00042 /** 00043 * @addtogroup TIM5_Public_Functions 00044 * @{ 00045 */ 00046 00047 /** 00048 * @brief Deinitializes the TIM5 peripheral registers to their default reset values. 00049 * @param None 00050 * @retval None 00051 */ 00052 void TIM5_DeInit(void) 00053 { 00054 TIM5->CR1 = (uint8_t)TIM5_CR1_RESET_VALUE; 00055 TIM5->CR2 = TIM5_CR2_RESET_VALUE; 00056 TIM5->SMCR = TIM5_SMCR_RESET_VALUE; 00057 TIM5->IER = (uint8_t)TIM5_IER_RESET_VALUE; 00058 TIM5->SR2 = (uint8_t)TIM5_SR2_RESET_VALUE; 00059 00060 /* Disable channels */ 00061 TIM5->CCER1 = (uint8_t)TIM5_CCER1_RESET_VALUE; 00062 TIM5->CCER2 = (uint8_t)TIM5_CCER2_RESET_VALUE; 00063 00064 /* Then reset channel registers: it also works if lock level is equal to 2 or 3 */ 00065 TIM5->CCER1 = (uint8_t)TIM5_CCER1_RESET_VALUE; 00066 TIM5->CCER2 = (uint8_t)TIM5_CCER2_RESET_VALUE; 00067 TIM5->CCMR1 = (uint8_t)TIM5_CCMR1_RESET_VALUE; 00068 TIM5->CCMR2 = (uint8_t)TIM5_CCMR2_RESET_VALUE; 00069 TIM5->CCMR3 = (uint8_t)TIM5_CCMR3_RESET_VALUE; 00070 TIM5->CNTRH = (uint8_t)TIM5_CNTRH_RESET_VALUE; 00071 TIM5->CNTRL = (uint8_t)TIM5_CNTRL_RESET_VALUE; 00072 TIM5->PSCR = (uint8_t)TIM5_PSCR_RESET_VALUE; 00073 TIM5->ARRH = (uint8_t)TIM5_ARRH_RESET_VALUE; 00074 TIM5->ARRL = (uint8_t)TIM5_ARRL_RESET_VALUE; 00075 TIM5->CCR1H = (uint8_t)TIM5_CCR1H_RESET_VALUE; 00076 TIM5->CCR1L = (uint8_t)TIM5_CCR1L_RESET_VALUE; 00077 TIM5->CCR2H = (uint8_t)TIM5_CCR2H_RESET_VALUE; 00078 TIM5->CCR2L = (uint8_t)TIM5_CCR2L_RESET_VALUE; 00079 TIM5->CCR3H = (uint8_t)TIM5_CCR3H_RESET_VALUE; 00080 TIM5->CCR3L = (uint8_t)TIM5_CCR3L_RESET_VALUE; 00081 TIM5->SR1 = (uint8_t)TIM5_SR1_RESET_VALUE; 00082 } 00083 00084 /** 00085 * @brief Initializes the TIM5 Time Base Unit according to the specified parameters. 00086 * @param TIM5_Prescaler specifies the Prescaler from TIM5_Prescaler_TypeDef. 00087 * @param TIM5_Period specifies the Period value. 00088 * @retval None 00089 */ 00090 void TIM5_TimeBaseInit( TIM5_Prescaler_TypeDef TIM5_Prescaler, 00091 uint16_t TIM5_Period) 00092 { 00093 /* Set the Prescaler value */ 00094 TIM5->PSCR = (uint8_t)(TIM5_Prescaler); 00095 /* Set the Autoreload value */ 00096 TIM5->ARRH = (uint8_t)(TIM5_Period >> 8) ; 00097 TIM5->ARRL = (uint8_t)(TIM5_Period); 00098 } 00099 00100 /** 00101 * @brief Initializes the TIM5 Channel1 according to the specified parameters. 00102 * @param TIM5_OCMode specifies the Output Compare mode from @ref TIM5_OCMode_TypeDef. 00103 * @param TIM5_OutputState specifies the Output State from @ref TIM5_OutputState_TypeDef. 00104 * @param TIM5_Pulse specifies the Pulse width value. 00105 * @param TIM5_OCPolarity specifies the Output Compare Polarity from @ref TIM5_OCPolarity_TypeDef. 00106 * @retval None 00107 */ 00108 void TIM5_OC1Init(TIM5_OCMode_TypeDef TIM5_OCMode, 00109 TIM5_OutputState_TypeDef TIM5_OutputState, 00110 uint16_t TIM5_Pulse, 00111 TIM5_OCPolarity_TypeDef TIM5_OCPolarity) 00112 { 00113 /* Check the parameters */ 00114 assert_param(IS_TIM5_OC_MODE_OK(TIM5_OCMode)); 00115 assert_param(IS_TIM5_OUTPUT_STATE_OK(TIM5_OutputState)); 00116 assert_param(IS_TIM5_OC_POLARITY_OK(TIM5_OCPolarity)); 00117 00118 /* Disable the Channel 1: Reset the CCE Bit, Set the Output State , the Output Polarity */ 00119 TIM5->CCER1 &= (uint8_t)(~( TIM5_CCER1_CC1E | TIM5_CCER1_CC1P)); 00120 /* Set the Output State & Set the Output Polarity */ 00121 TIM5->CCER1 |= (uint8_t)((uint8_t)(TIM5_OutputState & TIM5_CCER1_CC1E )| 00122 (uint8_t)(TIM5_OCPolarity & TIM5_CCER1_CC1P)); 00123 00124 /* Reset the Output Compare Bits & Set the Output Compare Mode */ 00125 TIM5->CCMR1 = (uint8_t)((uint8_t)(TIM5->CCMR1 & (uint8_t)(~TIM5_CCMR_OCM)) | 00126 (uint8_t)TIM5_OCMode); 00127 00128 /* Set the Pulse value */ 00129 TIM5->CCR1H = (uint8_t)(TIM5_Pulse >> 8); 00130 TIM5->CCR1L = (uint8_t)(TIM5_Pulse); 00131 } 00132 00133 /** 00134 * @brief Initializes the TIM5 Channel2 according to the specified parameters. 00135 * @param TIM5_OCMode specifies the Output Compare mode from @ref TIM5_OCMode_TypeDef. 00136 * @param TIM5_OutputState specifies the Output State from @ref TIM5_OutputState_TypeDef. 00137 * @param TIM5_Pulse specifies the Pulse width value. 00138 * @param TIM5_OCPolarity specifies the Output Compare Polarity from @ref TIM5_OCPolarity_TypeDef. 00139 * @retval None 00140 */ 00141 void TIM5_OC2Init(TIM5_OCMode_TypeDef TIM5_OCMode, 00142 TIM5_OutputState_TypeDef TIM5_OutputState, 00143 uint16_t TIM5_Pulse, 00144 TIM5_OCPolarity_TypeDef TIM5_OCPolarity) 00145 { 00146 /* Check the parameters */ 00147 assert_param(IS_TIM5_OC_MODE_OK(TIM5_OCMode)); 00148 assert_param(IS_TIM5_OUTPUT_STATE_OK(TIM5_OutputState)); 00149 assert_param(IS_TIM5_OC_POLARITY_OK(TIM5_OCPolarity)); 00150 00151 /* Disable the Channel 1: Reset the CCE Bit, Set the Output State , the Output Polarity */ 00152 TIM5->CCER1 &= (uint8_t)(~( TIM5_CCER1_CC2E | TIM5_CCER1_CC2P )); 00153 /* Set the Output State & Set the Output Polarity */ 00154 TIM5->CCER1 |= (uint8_t)((uint8_t)(TIM5_OutputState & TIM5_CCER1_CC2E )| \ 00155 (uint8_t)(TIM5_OCPolarity & TIM5_CCER1_CC2P)); 00156 00157 00158 /* Reset the Output Compare Bits & Set the Output Compare Mode */ 00159 TIM5->CCMR2 = (uint8_t)((uint8_t)(TIM5->CCMR2 & (uint8_t)(~TIM5_CCMR_OCM)) | 00160 (uint8_t)TIM5_OCMode); 00161 00162 /* Set the Pulse value */ 00163 TIM5->CCR2H = (uint8_t)(TIM5_Pulse >> 8); 00164 TIM5->CCR2L = (uint8_t)(TIM5_Pulse); 00165 } 00166 00167 /** 00168 * @brief Initializes the TIM5 Channel3 according to the specified parameters. 00169 * @param TIM5_OCMode specifies the Output Compare mode from @ref TIM5_OCMode_TypeDef. 00170 * @param TIM5_OutputState specifies the Output State from @ref TIM5_OutputState_TypeDef. 00171 * @param TIM5_Pulse specifies the Pulse width value. 00172 * @param TIM5_OCPolarity specifies the Output Compare Polarity from @ref TIM5_OCPolarity_TypeDef. 00173 * @retval None 00174 */ 00175 void TIM5_OC3Init(TIM5_OCMode_TypeDef TIM5_OCMode, 00176 TIM5_OutputState_TypeDef TIM5_OutputState, 00177 uint16_t TIM5_Pulse, 00178 TIM5_OCPolarity_TypeDef TIM5_OCPolarity) 00179 { 00180 /* Check the parameters */ 00181 assert_param(IS_TIM5_OC_MODE_OK(TIM5_OCMode)); 00182 assert_param(IS_TIM5_OUTPUT_STATE_OK(TIM5_OutputState)); 00183 assert_param(IS_TIM5_OC_POLARITY_OK(TIM5_OCPolarity)); 00184 /* Disable the Channel 1: Reset the CCE Bit, Set the Output State, the Output Polarity */ 00185 TIM5->CCER2 &= (uint8_t)(~( TIM5_CCER2_CC3E | TIM5_CCER2_CC3P)); 00186 /* Set the Output State & Set the Output Polarity */ 00187 TIM5->CCER2 |= (uint8_t)((uint8_t)(TIM5_OutputState & TIM5_CCER2_CC3E )| 00188 (uint8_t)(TIM5_OCPolarity & TIM5_CCER2_CC3P )); 00189 00190 /* Reset the Output Compare Bits & Set the Output Compare Mode */ 00191 TIM5->CCMR3 = (uint8_t)((uint8_t)(TIM5->CCMR3 & (uint8_t)(~TIM5_CCMR_OCM)) | (uint8_t)TIM5_OCMode); 00192 00193 /* Set the Pulse value */ 00194 TIM5->CCR3H = (uint8_t)(TIM5_Pulse >> 8); 00195 TIM5->CCR3L = (uint8_t)(TIM5_Pulse); 00196 } 00197 00198 /** 00199 * @brief Initializes the TIM5 peripheral according to the specified parameters. 00200 * @param TIM5_Channel specifies the Input Capture Channel from @ref TIM5_Channel_TypeDef. 00201 * @param TIM5_ICPolarity specifies the Input Capture Polarity from @ref TIM5_ICPolarity_TypeDef. 00202 * @param TIM5_ICSelection specifies theInput Capture Selection from @ref TIM5_ICSelection_TypeDef. 00203 * @param TIM5_ICPrescaler specifies the Input Capture Prescaler from @ref TIM5_ICPSC_TypeDef. 00204 * @param TIM5_ICFilter specifies the Input Capture Filter value (value can be an integer from 0x00 to 0x0F). 00205 * @retval None 00206 */ 00207 void TIM5_ICInit(TIM5_Channel_TypeDef TIM5_Channel, 00208 TIM5_ICPolarity_TypeDef TIM5_ICPolarity, 00209 TIM5_ICSelection_TypeDef TIM5_ICSelection, 00210 TIM5_ICPSC_TypeDef TIM5_ICPrescaler, 00211 uint8_t TIM5_ICFilter) 00212 { 00213 /* Check the parameters */ 00214 assert_param(IS_TIM5_CHANNEL_OK(TIM5_Channel)); 00215 assert_param(IS_TIM5_IC_POLARITY_OK(TIM5_ICPolarity)); 00216 assert_param(IS_TIM5_IC_SELECTION_OK(TIM5_ICSelection)); 00217 assert_param(IS_TIM5_IC_PRESCALER_OK(TIM5_ICPrescaler)); 00218 assert_param(IS_TIM5_IC_FILTER_OK(TIM5_ICFilter)); 00219 00220 if (TIM5_Channel == TIM5_CHANNEL_1) 00221 { 00222 /* TI1 Configuration */ 00223 TI1_Config((uint8_t)TIM5_ICPolarity, 00224 (uint8_t)TIM5_ICSelection, 00225 (uint8_t)TIM5_ICFilter); 00226 00227 /* Set the Input Capture Prescaler value */ 00228 TIM5_SetIC1Prescaler(TIM5_ICPrescaler); 00229 } 00230 else if (TIM5_Channel == TIM5_CHANNEL_2) 00231 { 00232 /* TI2 Configuration */ 00233 TI2_Config((uint8_t)TIM5_ICPolarity, 00234 (uint8_t)TIM5_ICSelection, 00235 (uint8_t)TIM5_ICFilter); 00236 00237 /* Set the Input Capture Prescaler value */ 00238 TIM5_SetIC2Prescaler(TIM5_ICPrescaler); 00239 } 00240 else 00241 { 00242 /* TI3 Configuration */ 00243 TI3_Config((uint8_t)TIM5_ICPolarity, 00244 (uint8_t)TIM5_ICSelection, 00245 (uint8_t)TIM5_ICFilter); 00246 00247 /* Set the Input Capture Prescaler value */ 00248 TIM5_SetIC3Prescaler(TIM5_ICPrescaler); 00249 } 00250 } 00251 00252 /** 00253 * @brief Configures the TIM5 peripheral in PWM Input Mode according to the specified parameters. 00254 * @param TIM5_Channel specifies the Input Capture Channel from @ref TIM5_Channel_TypeDef. 00255 * @param TIM5_ICPolarity specifies the Input Capture Polarity from @ref TIM5_ICPolarity_TypeDef. 00256 * @param TIM5_ICSelection specifies theInput Capture Selection from @ref TIM5_ICSelection_TypeDef. 00257 * @param TIM5_ICPrescaler specifies the Input Capture Prescaler from @ref TIM5_ICPSC_TypeDef. 00258 * @param TIM5_ICFilter specifies the Input Capture Filter value (value can be an integer from 0x00 to 0x0F). 00259 * @retval None 00260 */ 00261 void TIM5_PWMIConfig(TIM5_Channel_TypeDef TIM5_Channel, 00262 TIM5_ICPolarity_TypeDef TIM5_ICPolarity, 00263 TIM5_ICSelection_TypeDef TIM5_ICSelection, 00264 TIM5_ICPSC_TypeDef TIM5_ICPrescaler, 00265 uint8_t TIM5_ICFilter) 00266 { 00267 uint8_t icpolarity = (uint8_t)TIM5_ICPOLARITY_RISING; 00268 uint8_t icselection = (uint8_t)TIM5_ICSELECTION_DIRECTTI; 00269 00270 /* Check the parameters */ 00271 assert_param(IS_TIM5_PWMI_CHANNEL_OK(TIM5_Channel)); 00272 assert_param(IS_TIM5_IC_POLARITY_OK(TIM5_ICPolarity)); 00273 assert_param(IS_TIM5_IC_SELECTION_OK(TIM5_ICSelection)); 00274 assert_param(IS_TIM5_IC_PRESCALER_OK(TIM5_ICPrescaler)); 00275 00276 /* Select the Opposite Input Polarity */ 00277 if (TIM5_ICPolarity != TIM5_ICPOLARITY_FALLING) 00278 { 00279 icpolarity = (uint8_t)TIM5_ICPOLARITY_FALLING; 00280 } 00281 else 00282 { 00283 icpolarity = (uint8_t)TIM5_ICPOLARITY_RISING; 00284 } 00285 00286 /* Select the Opposite Input */ 00287 if (TIM5_ICSelection == TIM5_ICSELECTION_DIRECTTI) 00288 { 00289 icselection = (uint8_t)TIM5_ICSELECTION_INDIRECTTI; 00290 } 00291 else 00292 { 00293 icselection = (uint8_t)TIM5_ICSELECTION_DIRECTTI; 00294 } 00295 00296 if (TIM5_Channel == TIM5_CHANNEL_1) 00297 { 00298 /* TI1 Configuration */ 00299 TI1_Config((uint8_t)TIM5_ICPolarity, (uint8_t)TIM5_ICSelection, 00300 (uint8_t)TIM5_ICFilter); 00301 00302 /* Set the Input Capture Prescaler value */ 00303 TIM5_SetIC1Prescaler(TIM5_ICPrescaler); 00304 00305 /* TI2 Configuration */ 00306 TI2_Config((uint8_t)icpolarity, (uint8_t)icselection, (uint8_t)TIM5_ICFilter); 00307 00308 /* Set the Input Capture Prescaler value */ 00309 TIM5_SetIC2Prescaler(TIM5_ICPrescaler); 00310 } 00311 else 00312 { 00313 /* TI2 Configuration */ 00314 TI2_Config((uint8_t)TIM5_ICPolarity, (uint8_t)TIM5_ICSelection, 00315 (uint8_t)TIM5_ICFilter); 00316 00317 /* Set the Input Capture Prescaler value */ 00318 TIM5_SetIC2Prescaler(TIM5_ICPrescaler); 00319 00320 /* TI1 Configuration */ 00321 TI1_Config((uint8_t)icpolarity, (uint8_t)icselection, (uint8_t)TIM5_ICFilter); 00322 00323 /* Set the Input Capture Prescaler value */ 00324 TIM5_SetIC1Prescaler(TIM5_ICPrescaler); 00325 } 00326 } 00327 00328 /** 00329 * @brief Enables or disables the TIM5 peripheral. 00330 * @param NewState new state of the TIM5 peripheral.This parameter can 00331 * be ENABLE or DISABLE. 00332 * @retval None 00333 */ 00334 void TIM5_Cmd(FunctionalState NewState) 00335 { 00336 /* Check the parameters */ 00337 assert_param(IS_FUNCTIONALSTATE_OK(NewState)); 00338 00339 /* set or Reset the CEN Bit */ 00340 if (NewState != DISABLE) 00341 { 00342 TIM5->CR1 |= TIM5_CR1_CEN ; 00343 } 00344 else 00345 { 00346 TIM5->CR1 &= (uint8_t)(~TIM5_CR1_CEN) ; 00347 } 00348 } 00349 00350 /** 00351 * @brief Enables or disables the specified TIM5 interrupts. 00352 * @param NewState new state of the TIM5 peripheral. 00353 * This parameter can be: ENABLE or DISABLE. 00354 * @param TIM5_IT specifies the TIM5 interrupts sources to be enabled or disabled. 00355 * This parameter can be any combination of the following values: 00356 * - TIM5_IT_UPDATE: TIM5 update Interrupt source 00357 * - TIM5_IT_CC1: TIM5 Capture Compare 1 Interrupt source 00358 * - TIM5_IT_CC2: TIM5 Capture Compare 2 Interrupt source 00359 * - TIM5_IT_CC3: TIM5 Capture Compare 3 Interrupt source 00360 * @param NewState new state of the TIM5 peripheral. 00361 * @retval None 00362 */ 00363 void TIM5_ITConfig(TIM5_IT_TypeDef TIM5_IT, FunctionalState NewState) 00364 { 00365 /* Check the parameters */ 00366 assert_param(IS_TIM5_IT_OK(TIM5_IT)); 00367 assert_param(IS_FUNCTIONALSTATE_OK(NewState)); 00368 00369 if (NewState != DISABLE) 00370 { 00371 /* Enable the Interrupt sources */ 00372 TIM5->IER |= (uint8_t)TIM5_IT; 00373 } 00374 else 00375 { 00376 /* Disable the Interrupt sources */ 00377 TIM5->IER &= (uint8_t)(~TIM5_IT); 00378 } 00379 } 00380 00381 /** 00382 * @brief Enables or Disables the TIM5 Update event. 00383 * @param NewState new state of the TIM5 peripheral Preload register.This parameter can 00384 * be ENABLE or DISABLE. 00385 * @retval None 00386 */ 00387 void TIM5_UpdateDisableConfig(FunctionalState NewState) 00388 { 00389 /* Check the parameters */ 00390 assert_param(IS_FUNCTIONALSTATE_OK(NewState)); 00391 00392 /* Set or Reset the UDIS Bit */ 00393 if (NewState != DISABLE) 00394 { 00395 TIM5->CR1 |= TIM5_CR1_UDIS ; 00396 } 00397 else 00398 { 00399 TIM5->CR1 &= (uint8_t)(~TIM5_CR1_UDIS) ; 00400 } 00401 } 00402 00403 /** 00404 * @brief Selects the TIM5 Update Request Interrupt source. 00405 * @param TIM5_UpdateSource specifies the Update source. 00406 * This parameter can be one of the following values 00407 * - TIM5_UPDATESOURCE_REGULAR 00408 * - TIM5_UPDATESOURCE_GLOBAL 00409 * @retval None 00410 */ 00411 void TIM5_UpdateRequestConfig(TIM5_UpdateSource_TypeDef TIM5_UpdateSource) 00412 { 00413 /* Check the parameters */ 00414 assert_param(IS_TIM5_UPDATE_SOURCE_OK(TIM5_UpdateSource)); 00415 00416 /* Set or Reset the URS Bit */ 00417 if (TIM5_UpdateSource != TIM5_UPDATESOURCE_GLOBAL) 00418 { 00419 TIM5->CR1 |= TIM5_CR1_URS ; 00420 } 00421 else 00422 { 00423 TIM5->CR1 &= (uint8_t)(~TIM5_CR1_URS) ; 00424 } 00425 } 00426 00427 /** 00428 * @brief Selects the TIM5�s One Pulse Mode. 00429 * @param TIM5_OPMode specifies the OPM Mode to be used. 00430 * This parameter can be one of the following values 00431 * - TIM5_OPMODE_SINGLE 00432 * - TIM5_OPMODE_REPETITIVE 00433 * @retval None 00434 */ 00435 void TIM5_SelectOnePulseMode(TIM5_OPMode_TypeDef TIM5_OPMode) 00436 { 00437 /* Check the parameters */ 00438 assert_param(IS_TIM5_OPM_MODE_OK(TIM5_OPMode)); 00439 00440 /* Set or Reset the OPM Bit */ 00441 if (TIM5_OPMode != TIM5_OPMODE_REPETITIVE) 00442 { 00443 TIM5->CR1 |= TIM5_CR1_OPM ; 00444 } 00445 else 00446 { 00447 TIM5->CR1 &= (uint8_t)(~TIM5_CR1_OPM) ; 00448 } 00449 } 00450 00451 /** 00452 * @brief Configures the TIM5 Prescaler. 00453 * @param Prescaler specifies the Prescaler Register value 00454 * This parameter can be one of the following values 00455 * - TIM5_PRESCALER_1 00456 * - TIM5_PRESCALER_2 00457 * - TIM5_PRESCALER_4 00458 * - TIM5_PRESCALER_8 00459 * - TIM5_PRESCALER_16 00460 * - TIM5_PRESCALER_32 00461 * - TIM5_PRESCALER_64 00462 * - TIM5_PRESCALER_128 00463 * - TIM5_PRESCALER_256 00464 * - TIM5_PRESCALER_512 00465 * - TIM5_PRESCALER_1024 00466 * - TIM5_PRESCALER_2048 00467 * - TIM5_PRESCALER_4096 00468 * - TIM5_PRESCALER_8192 00469 * - TIM5_PRESCALER_16384 00470 * - TIM5_PRESCALER_32768 00471 * @param TIM5_PSCReloadMode specifies the TIM5 Prescaler Reload mode. 00472 * This parameter can be one of the following values 00473 * - TIM5_PSCRELOADMODE_IMMEDIATE: The Prescaler is loaded 00474 * immediately. 00475 * - TIM5_PSCRELOADMODE_UPDATE: The Prescaler is loaded at 00476 * the update event. 00477 * @retval None 00478 */ 00479 void TIM5_PrescalerConfig(TIM5_Prescaler_TypeDef Prescaler, 00480 TIM5_PSCReloadMode_TypeDef TIM5_PSCReloadMode) 00481 { 00482 /* Check the parameters */ 00483 assert_param(IS_TIM5_PRESCALER_RELOAD_OK(TIM5_PSCReloadMode)); 00484 assert_param(IS_TIM5_PRESCALER_OK(Prescaler)); 00485 00486 /* Set the Prescaler value */ 00487 TIM5->PSCR = (uint8_t)Prescaler; 00488 00489 /* Set or reset the UG Bit */ 00490 TIM5->EGR = (uint8_t)TIM5_PSCReloadMode ; 00491 } 00492 00493 /** 00494 * @brief Forces the TIM5 Channel1 output waveform to active or inactive level. 00495 * @param TIM5_ForcedAction specifies the forced Action to be set to the output waveform. 00496 * This parameter can be one of the following values: 00497 * - TIM5_FORCEDACTION_ACTIVE: Force active level on OC1REF 00498 * - TIM5_FORCEDACTION_INACTIVE: Force inactive level on 00499 * OC1REF. 00500 * @retval None 00501 */ 00502 void TIM5_ForcedOC1Config(TIM5_ForcedAction_TypeDef TIM5_ForcedAction) 00503 { 00504 /* Check the parameters */ 00505 assert_param(IS_TIM5_FORCED_ACTION_OK(TIM5_ForcedAction)); 00506 00507 /* Reset the OCM Bits */ /* Configure The Forced output Mode */ 00508 TIM5->CCMR1 = (uint8_t)((uint8_t)(TIM5->CCMR1 & (uint8_t)(~TIM5_CCMR_OCM)) 00509 | (uint8_t)TIM5_ForcedAction); 00510 } 00511 00512 /** 00513 * @brief Forces the TIM5 Channel2 output waveform to active or inactive level. 00514 * @param TIM5_ForcedAction specifies the forced Action to be set to the output waveform. 00515 * This parameter can be one of the following values: 00516 * - TIM5_FORCEDACTION_ACTIVE: Force active level on OC2REF 00517 * - TIM5_FORCEDACTION_INACTIVE: Force inactive level on 00518 * OC2REF. 00519 * @retval None 00520 */ 00521 void TIM5_ForcedOC2Config(TIM5_ForcedAction_TypeDef TIM5_ForcedAction) 00522 { 00523 /* Check the parameters */ 00524 assert_param(IS_TIM5_FORCED_ACTION_OK(TIM5_ForcedAction)); 00525 00526 /* Reset the OCM Bits */ /* Configure The Forced output Mode */ 00527 TIM5->CCMR2 = (uint8_t)((uint8_t)(TIM5->CCMR2 & (uint8_t)(~TIM5_CCMR_OCM)) 00528 | (uint8_t)TIM5_ForcedAction); 00529 } 00530 00531 /** 00532 * @brief Forces the TIM5 Channel3 output waveform to active or inactive level. 00533 * @param TIM5_ForcedAction specifies the forced Action to be set to the output waveform. 00534 * This parameter can be one of the following values: 00535 * - TIM5_FORCEDACTION_ACTIVE: Force active level on OC3REF 00536 * - TIM5_FORCEDACTION_INACTIVE: Force inactive level on 00537 * OC3REF. 00538 * @retval None 00539 */ 00540 void TIM5_ForcedOC3Config(TIM5_ForcedAction_TypeDef TIM5_ForcedAction) 00541 { 00542 /* Check the parameters */ 00543 assert_param(IS_TIM5_FORCED_ACTION_OK(TIM5_ForcedAction)); 00544 00545 /* Reset the OCM Bits */ /* Configure The Forced output Mode */ 00546 TIM5->CCMR3 = (uint8_t)((uint8_t)(TIM5->CCMR3 & (uint8_t)(~TIM5_CCMR_OCM)) 00547 | (uint8_t)TIM5_ForcedAction); 00548 } 00549 00550 /** 00551 * @brief Enables or disables TIM5 peripheral Preload register on ARR. 00552 * @param NewState new state of the TIM5 peripheral Preload register. 00553 * This parameter can be ENABLE or DISABLE. 00554 * @retval None 00555 */ 00556 void TIM5_ARRPreloadConfig(FunctionalState NewState) 00557 { 00558 /* Check the parameters */ 00559 assert_param(IS_FUNCTIONALSTATE_OK(NewState)); 00560 00561 /* Set or Reset the ARPE Bit */ 00562 if (NewState != DISABLE) 00563 { 00564 TIM5->CR1 |= TIM5_CR1_ARPE ; 00565 } 00566 else 00567 { 00568 TIM5->CR1 &= (uint8_t)(~TIM5_CR1_ARPE) ; 00569 } 00570 } 00571 00572 /** 00573 * @brief Enables or disables the TIM5 peripheral Preload Register on CCR1. 00574 * @param NewState new state of the Capture Compare Preload register. 00575 * This parameter can be ENABLE or DISABLE. 00576 * @retval None 00577 */ 00578 void TIM5_OC1PreloadConfig(FunctionalState NewState) 00579 { 00580 /* Check the parameters */ 00581 assert_param(IS_FUNCTIONALSTATE_OK(NewState)); 00582 00583 /* Set or Reset the OC1PE Bit */ 00584 if (NewState != DISABLE) 00585 { 00586 TIM5->CCMR1 |= TIM5_CCMR_OCxPE ; 00587 } 00588 else 00589 { 00590 TIM5->CCMR1 &= (uint8_t)(~TIM5_CCMR_OCxPE) ; 00591 } 00592 } 00593 00594 /** 00595 * @brief Enables or disables the TIM5 peripheral Preload Register on CCR2. 00596 * @param NewState new state of the Capture Compare Preload register. 00597 * This parameter can be ENABLE or DISABLE. 00598 * @retval None 00599 */ 00600 void TIM5_OC2PreloadConfig(FunctionalState NewState) 00601 { 00602 /* Check the parameters */ 00603 assert_param(IS_FUNCTIONALSTATE_OK(NewState)); 00604 00605 /* Set or Reset the OC2PE Bit */ 00606 if (NewState != DISABLE) 00607 { 00608 TIM5->CCMR2 |= TIM5_CCMR_OCxPE ; 00609 } 00610 else 00611 { 00612 TIM5->CCMR2 &= (uint8_t)(~TIM5_CCMR_OCxPE) ; 00613 } 00614 } 00615 00616 /** 00617 * @brief Enables or disables the TIM5 peripheral Preload Register on CCR3. 00618 * @param NewState new state of the Capture Compare Preload register. 00619 * This parameter can be ENABLE or DISABLE. 00620 * @retval None 00621 */ 00622 void TIM5_OC3PreloadConfig(FunctionalState NewState) 00623 { 00624 /* Check the parameters */ 00625 assert_param(IS_FUNCTIONALSTATE_OK(NewState)); 00626 00627 /* Set or Reset the OC3PE Bit */ 00628 if (NewState != DISABLE) 00629 { 00630 TIM5->CCMR3 |= TIM5_CCMR_OCxPE ; 00631 } 00632 else 00633 { 00634 TIM5->CCMR3 &= (uint8_t)(~TIM5_CCMR_OCxPE) ; 00635 } 00636 } 00637 00638 /** 00639 * @brief Configures the TIM5 event to be generated by software. 00640 * @param TIM5_EventSource specifies the event source. 00641 * This parameter can be one of the following values: 00642 * - TIM5_EVENTSOURCE_UPDATE: TIM5 update Event source 00643 * - TIM5_EVENTSOURCE_CC1: TIM5 Capture Compare 1 Event source 00644 * - TIM5_EVENTSOURCE_CC2: TIM5 Capture Compare 2 Event source 00645 * - TIM5_EVENTSOURCE_CC3: TIM5 Capture Compare 3 Event source 00646 * @retval None 00647 */ 00648 void TIM5_GenerateEvent(TIM5_EventSource_TypeDef TIM5_EventSource) 00649 { 00650 /* Check the parameters */ 00651 assert_param(IS_TIM5_EVENT_SOURCE_OK(TIM5_EventSource)); 00652 00653 /* Set the event sources */ 00654 TIM5->EGR = (uint8_t)TIM5_EventSource; 00655 } 00656 00657 /** 00658 * @brief Configures the TIM5 Channel 1 polarity. 00659 * @param TIM5_OCPolarity specifies the OC1 Polarity. 00660 * This parameter can be one of the following values: 00661 * - TIM5_OCPOLARITY_LOW: Output Compare active low 00662 * - TIM5_OCPOLARITY_HIGH: Output Compare active high 00663 * @retval None 00664 */ 00665 void TIM5_OC1PolarityConfig(TIM5_OCPolarity_TypeDef TIM5_OCPolarity) 00666 { 00667 /* Check the parameters */ 00668 assert_param(IS_TIM5_OC_POLARITY_OK(TIM5_OCPolarity)); 00669 00670 /* Set or Reset the CC1P Bit */ 00671 if (TIM5_OCPolarity != TIM5_OCPOLARITY_HIGH) 00672 { 00673 TIM5->CCER1 |= TIM5_CCER1_CC1P ; 00674 } 00675 else 00676 { 00677 TIM5->CCER1 &= (uint8_t)(~TIM5_CCER1_CC1P) ; 00678 } 00679 } 00680 00681 00682 /** 00683 * @brief Configures the TIM5 Channel 2 polarity. 00684 * @param TIM5_OCPolarity specifies the OC2 Polarity. 00685 * This parameter can be one of the following values: 00686 * - TIM5_OCPOLARITY_LOW: Output Compare active low 00687 * - TIM5_OCPOLARITY_HIGH: Output Compare active high 00688 * @retval None 00689 */ 00690 void TIM5_OC2PolarityConfig(TIM5_OCPolarity_TypeDef TIM5_OCPolarity) 00691 { 00692 /* Check the parameters */ 00693 assert_param(IS_TIM5_OC_POLARITY_OK(TIM5_OCPolarity)); 00694 00695 /* Set or Reset the CC2P Bit */ 00696 if (TIM5_OCPolarity != TIM5_OCPOLARITY_HIGH) 00697 { 00698 TIM5->CCER1 |= TIM5_CCER1_CC2P ; 00699 } 00700 else 00701 { 00702 TIM5->CCER1 &= (uint8_t)(~TIM5_CCER1_CC2P) ; 00703 } 00704 } 00705 00706 /** 00707 * @brief Configures the TIM5 Channel 3 polarity. 00708 * @param TIM5_OCPolarity specifies the OC3 Polarity. 00709 * This parameter can be one of the following values: 00710 * - TIM5_OCPOLARITY_LOW: Output Compare active low 00711 * - TIM5_OCPOLARITY_HIGH: Output Compare active high 00712 * @retval None 00713 */ 00714 void TIM5_OC3PolarityConfig(TIM5_OCPolarity_TypeDef TIM5_OCPolarity) 00715 { 00716 /* Check the parameters */ 00717 assert_param(IS_TIM5_OC_POLARITY_OK(TIM5_OCPolarity)); 00718 00719 /* Set or Reset the CC3P Bit */ 00720 if (TIM5_OCPolarity != TIM5_OCPOLARITY_HIGH) 00721 { 00722 TIM5->CCER2 |= TIM5_CCER2_CC3P ; 00723 } 00724 else 00725 { 00726 TIM5->CCER2 &= (uint8_t)(~TIM5_CCER2_CC3P) ; 00727 } 00728 } 00729 00730 /** 00731 * @brief Enables or disables the TIM5 Capture Compare Channel x. 00732 * @param TIM5_Channel specifies the TIM5 Channel. 00733 * This parameter can be one of the following values: 00734 * - TIM5_Channel1: TIM5 Channel1 00735 * - TIM5_Channel2: TIM5 Channel2 00736 * - TIM5_Channel3: TIM5 Channel3 00737 * @param NewState specifies the TIM5 Channel CCxE bit new state. 00738 * This parameter can be: ENABLE or DISABLE. 00739 * @retval None 00740 */ 00741 void TIM5_CCxCmd(TIM5_Channel_TypeDef TIM5_Channel, FunctionalState NewState) 00742 { 00743 /* Check the parameters */ 00744 assert_param(IS_TIM5_CHANNEL_OK(TIM5_Channel)); 00745 assert_param(IS_FUNCTIONALSTATE_OK(NewState)); 00746 00747 if (TIM5_Channel == TIM5_CHANNEL_1) 00748 { 00749 /* Set or Reset the CC1E Bit */ 00750 if (NewState != DISABLE) 00751 { 00752 TIM5->CCER1 |= TIM5_CCER1_CC1E ; 00753 } 00754 else 00755 { 00756 TIM5->CCER1 &= (uint8_t)(~TIM5_CCER1_CC1E) ; 00757 } 00758 00759 } 00760 else if (TIM5_Channel == TIM5_CHANNEL_2) 00761 { 00762 /* Set or Reset the CC2E Bit */ 00763 if (NewState != DISABLE) 00764 { 00765 TIM5->CCER1 |= TIM5_CCER1_CC2E; 00766 } 00767 else 00768 { 00769 TIM5->CCER1 &= (uint8_t)(~TIM5_CCER1_CC2E) ; 00770 } 00771 } 00772 else 00773 { 00774 /* Set or Reset the CC3E Bit */ 00775 if (NewState != DISABLE) 00776 { 00777 TIM5->CCER2 |= TIM5_CCER2_CC3E; 00778 } 00779 else 00780 { 00781 TIM5->CCER2 &= (uint8_t)(~TIM5_CCER2_CC3E) ; 00782 } 00783 } 00784 } 00785 00786 /** 00787 * @brief Selects the TIM5 Output Compare Mode. This function disables the 00788 * selected channel before changing the Output Compare Mode. User has to 00789 * enable this channel using TIM5_CCxCmd and TIM5_CCxNCmd functions. 00790 * @param TIM5_Channel specifies the TIM5 Channel. 00791 * This parameter can be one of the following values: 00792 * - TIM5_Channel1: TIM5 Channel1 00793 * - TIM5_Channel2: TIM5 Channel2 00794 * - TIM5_Channel3: TIM5 Channel3 00795 * @param TIM5_OCMode specifies the TIM5 Output Compare Mode. 00796 * This parameter can be one of the following values: 00797 * - TIM5_OCMODE_TIMING 00798 * - TIM5_OCMODE_ACTIVE 00799 * - TIM5_OCMODE_TOGGLE 00800 * - TIM5_OCMODE_PWM1 00801 * - TIM5_OCMODE_PWM2 00802 * - TIM5_FORCEDACTION_ACTIVE 00803 * - TIM5_FORCEDACTION_INACTIVE 00804 * @retval None 00805 */ 00806 void TIM5_SelectOCxM(TIM5_Channel_TypeDef TIM5_Channel, TIM5_OCMode_TypeDef TIM5_OCMode) 00807 { 00808 /* Check the parameters */ 00809 assert_param(IS_TIM5_CHANNEL_OK(TIM5_Channel)); 00810 assert_param(IS_TIM5_OCM_OK(TIM5_OCMode)); 00811 00812 if (TIM5_Channel == TIM5_CHANNEL_1) 00813 { 00814 /* Disable the Channel 1: Reset the CCE Bit */ 00815 TIM5->CCER1 &= (uint8_t)(~TIM5_CCER1_CC1E); 00816 00817 /* Reset the Output Compare Bits Set the Output Compare Mode */ 00818 TIM5->CCMR1 = (uint8_t)((uint8_t)(TIM5->CCMR1 & (uint8_t)(~TIM5_CCMR_OCM)) 00819 | (uint8_t)TIM5_OCMode); 00820 } 00821 else if (TIM5_Channel == TIM5_CHANNEL_2) 00822 { 00823 /* Disable the Channel 2: Reset the CCE Bit */ 00824 TIM5->CCER1 &= (uint8_t)(~TIM5_CCER1_CC2E); 00825 00826 /* Reset the Output Compare Bits ** Set the Output Compare Mode */ 00827 TIM5->CCMR2 = (uint8_t)((uint8_t)(TIM5->CCMR2 & (uint8_t)(~TIM5_CCMR_OCM)) 00828 | (uint8_t)TIM5_OCMode); 00829 } 00830 else 00831 { 00832 /* Disable the Channel 3: Reset the CCE Bit */ 00833 TIM5->CCER2 &= (uint8_t)(~TIM5_CCER2_CC3E); 00834 00835 /* Reset the Output Compare Bits ** Set the Output Compare Mode */ 00836 TIM5->CCMR3 = (uint8_t)((uint8_t)(TIM5->CCMR3 & (uint8_t)(~TIM5_CCMR_OCM)) 00837 | (uint8_t)TIM5_OCMode); 00838 } 00839 } 00840 00841 /** 00842 * @brief Sets the TIM5 Counter Register value. 00843 * @param Counter specifies the Counter register new value. 00844 * This parameter is between 0x0000 and 0xFFFF. 00845 * @retval None 00846 */ 00847 void TIM5_SetCounter(uint16_t Counter) 00848 { 00849 /* Set the Counter Register value */ 00850 TIM5->CNTRH = (uint8_t)(Counter >> 8); 00851 TIM5->CNTRL = (uint8_t)(Counter); 00852 } 00853 00854 /** 00855 * @brief Sets the TIM5 Autoreload Register value. 00856 * @param Autoreload specifies the Autoreload register new value. 00857 * This parameter is between 0x0000 and 0xFFFF. 00858 * @retval None 00859 */ 00860 void TIM5_SetAutoreload(uint16_t Autoreload) 00861 { 00862 /* Set the Autoreload Register value */ 00863 TIM5->ARRH = (uint8_t)(Autoreload >> 8); 00864 TIM5->ARRL = (uint8_t)(Autoreload); 00865 } 00866 00867 /** 00868 * @brief Sets the TIM5 Capture Compare1 Register value. 00869 * @param Compare1 specifies the Capture Compare1 register new value. 00870 * This parameter is between 0x0000 and 0xFFFF. 00871 * @retval None 00872 */ 00873 void TIM5_SetCompare1(uint16_t Compare1) 00874 { 00875 /* Set the Capture Compare1 Register value */ 00876 TIM5->CCR1H = (uint8_t)(Compare1 >> 8); 00877 TIM5->CCR1L = (uint8_t)(Compare1); 00878 } 00879 00880 /** 00881 * @brief Sets the TIM5 Capture Compare2 Register value. 00882 * @param Compare2 specifies the Capture Compare2 register new value. 00883 * This parameter is between 0x0000 and 0xFFFF. 00884 * @retval None 00885 */ 00886 void TIM5_SetCompare2(uint16_t Compare2) 00887 { 00888 /* Set the Capture Compare2 Register value */ 00889 TIM5->CCR2H = (uint8_t)(Compare2 >> 8); 00890 TIM5->CCR2L = (uint8_t)(Compare2); 00891 } 00892 00893 /** 00894 * @brief Sets the TIM5 Capture Compare3 Register value. 00895 * @param Compare3 specifies the Capture Compare3 register new value. 00896 * This parameter is between 0x0000 and 0xFFFF. 00897 * @retval None 00898 */ 00899 void TIM5_SetCompare3(uint16_t Compare3) 00900 { 00901 /* Set the Capture Compare3 Register value */ 00902 TIM5->CCR3H = (uint8_t)(Compare3 >> 8); 00903 TIM5->CCR3L = (uint8_t)(Compare3); 00904 } 00905 00906 /** 00907 * @brief Sets the TIM5 Input Capture 1 prescaler. 00908 * @param TIM5_IC1Prescaler specifies the Input Capture prescaler new value 00909 * This parameter can be one of the following values: 00910 * - TIM5_ICPSC_DIV1: no prescaler 00911 * - TIM5_ICPSC_DIV2: capture is done once every 2 events 00912 * - TIM5_ICPSC_DIV4: capture is done once every 4 events 00913 * - TIM5_ICPSC_DIV8: capture is done once every 8 events 00914 * @retval None 00915 */ 00916 void TIM5_SetIC1Prescaler(TIM5_ICPSC_TypeDef TIM5_IC1Prescaler) 00917 { 00918 /* Check the parameters */ 00919 assert_param(IS_TIM5_IC_PRESCALER_OK(TIM5_IC1Prescaler)); 00920 00921 /* Reset the IC1PSC Bits */ /* Set the IC1PSC value */ 00922 TIM5->CCMR1 = (uint8_t)((uint8_t)(TIM5->CCMR1 & (uint8_t)(~TIM5_CCMR_ICxPSC))| 00923 (uint8_t)TIM5_IC1Prescaler); 00924 } 00925 00926 /** 00927 * @brief Sets the TIM5 Input Capture 2 prescaler. 00928 * @param TIM5_IC2Prescaler specifies the Input Capture prescaler new value 00929 * This parameter can be one of the following values: 00930 * - TIM5_ICPSC_DIV1: no prescaler 00931 * - TIM5_ICPSC_DIV2: capture is done once every 2 events 00932 * - TIM5_ICPSC_DIV4: capture is done once every 4 events 00933 * - TIM5_ICPSC_DIV8: capture is done once every 8 events 00934 * @retval None 00935 */ 00936 void TIM5_SetIC2Prescaler(TIM5_ICPSC_TypeDef TIM5_IC2Prescaler) 00937 { 00938 /* Check the parameters */ 00939 assert_param(IS_TIM5_IC_PRESCALER_OK(TIM5_IC2Prescaler)); 00940 00941 /* Reset the IC1PSC Bits */ /* Set the IC1PSC value */ 00942 TIM5->CCMR2 = (uint8_t)((uint8_t)(TIM5->CCMR2 & (uint8_t)(~TIM5_CCMR_ICxPSC)) 00943 | (uint8_t)TIM5_IC2Prescaler); 00944 } 00945 00946 /** 00947 * @brief Sets the TIM5 Input Capture 3 prescaler. 00948 * @param TIM5_IC3Prescaler specifies the Input Capture prescaler new value 00949 * This parameter can be one of the following values: 00950 * - TIM5_ICPSC_DIV1: no prescaler 00951 * - TIM5_ICPSC_DIV2: capture is done once every 2 events 00952 * - TIM5_ICPSC_DIV4: capture is done once every 4 events 00953 * - TIM5_ICPSC_DIV8: capture is done once every 8 events 00954 * @retval None 00955 */ 00956 void TIM5_SetIC3Prescaler(TIM5_ICPSC_TypeDef TIM5_IC3Prescaler) 00957 { 00958 /* Check the parameters */ 00959 assert_param(IS_TIM5_IC_PRESCALER_OK(TIM5_IC3Prescaler)); 00960 /* Reset the IC1PSC Bits */ /* Set the IC1PSC value */ 00961 TIM5->CCMR3 = (uint8_t)((uint8_t)(TIM5->CCMR3 & (uint8_t)(~TIM5_CCMR_ICxPSC)) | 00962 (uint8_t)TIM5_IC3Prescaler); 00963 } 00964 00965 /** 00966 * @brief Gets the TIM5 Input Capture 1 value. 00967 * @param None 00968 * @retval Capture Compare 1 Register value. 00969 */ 00970 uint16_t TIM5_GetCapture1(void) 00971 { 00972 uint16_t temp = 0; 00973 00974 temp = ((uint16_t)TIM5->CCR1H << 8); 00975 00976 /* Get the Capture 1 Register value */ 00977 return (uint16_t)(temp | (uint16_t)(TIM5->CCR1L)); 00978 } 00979 00980 /** 00981 * @brief Gets the TIM5 Input Capture 2 value. 00982 * @param None 00983 * @retval Capture Compare 2 Register value. 00984 */ 00985 uint16_t TIM5_GetCapture2(void) 00986 { 00987 uint16_t temp = 0; 00988 00989 temp = ((uint16_t)TIM5->CCR2H << 8); 00990 00991 /* Get the Capture 2 Register value */ 00992 return (uint16_t)(temp | (uint16_t)(TIM5->CCR2L)); 00993 } 00994 00995 /** 00996 * @brief Gets the TIM5 Input Capture 3 value. 00997 * @param None 00998 * @retval Capture Compare 3 Register value. 00999 */ 01000 uint16_t TIM5_GetCapture3(void) 01001 { 01002 uint16_t temp = 0; 01003 01004 temp = ((uint16_t)TIM5->CCR3H << 8); 01005 /* Get the Capture 1 Register value */ 01006 return (uint16_t)(temp | (uint16_t)(TIM5->CCR3L)); 01007 } 01008 01009 /** 01010 * @brief Gets the TIM5 Counter value. 01011 * @param None 01012 * @retval Counter Register value. 01013 */ 01014 uint16_t TIM5_GetCounter(void) 01015 { 01016 uint16_t tmpcntr = 0; 01017 01018 tmpcntr = ((uint16_t)TIM5->CNTRH << 8); 01019 /* Get the Counter Register value */ 01020 return (uint16_t)(tmpcntr | (uint16_t)(TIM5->CNTRL)); 01021 } 01022 01023 /** 01024 * @brief Gets the TIM5 Prescaler value. 01025 * @param None 01026 * @retval Prescaler Register configuration value @ref TIM5_Prescaler_TypeDef . 01027 */ 01028 TIM5_Prescaler_TypeDef TIM5_GetPrescaler(void) 01029 { 01030 /* Get the Prescaler Register value */ 01031 return (TIM5_Prescaler_TypeDef)(TIM5->PSCR); 01032 } 01033 01034 /** 01035 * @brief Checks whether the specified TIM5 flag is set or not. 01036 * @param TIM5_FLAG specifies the flag to check. 01037 * This parameter can be one of the following values: 01038 * - TIM5_FLAG_UPDATE: TIM5 update Flag 01039 * - TIM5_FLAG_CC1: TIM5 Capture Compare 1 Flag 01040 * - TIM5_FLAG_CC2: TIM5 Capture Compare 2 Flag 01041 * - TIM5_FLAG_CC3: TIM5 Capture Compare 3 Flag 01042 * - TIM5_FLAG_CC1OF: TIM5 Capture Compare 1 overcapture Flag 01043 * - TIM5_FLAG_CC2OF: TIM5 Capture Compare 2 overcapture Flag 01044 * - TIM5_FLAG_CC3OF: TIM5 Capture Compare 3 overcapture Flag 01045 * @retval FlagStatus The new state of TIM5_FLAG (SET or RESET). 01046 */ 01047 FlagStatus TIM5_GetFlagStatus(TIM5_FLAG_TypeDef TIM5_FLAG) 01048 { 01049 FlagStatus bitstatus = RESET; 01050 uint8_t tim5_flag_l, tim5_flag_h; 01051 01052 /* Check the parameters */ 01053 assert_param(IS_TIM5_GET_FLAG_OK(TIM5_FLAG)); 01054 01055 tim5_flag_l= (uint8_t)(TIM5->SR1 & (uint8_t)TIM5_FLAG); 01056 tim5_flag_h= (uint8_t)((uint16_t)TIM5_FLAG >> 8); 01057 01058 if (((tim5_flag_l)|(uint8_t)(TIM5->SR2 & tim5_flag_h)) != RESET ) 01059 { 01060 bitstatus = SET; 01061 } 01062 else 01063 { 01064 bitstatus = RESET; 01065 } 01066 return (FlagStatus)bitstatus; 01067 } 01068 01069 /** 01070 * @brief Clears the TIM5�s pending flags. 01071 * @param TIM5_FLAG specifies the flag to clear. 01072 * This parameter can be one of the following values: 01073 * - TIM5_FLAG_UPDATE: TIM5 update Flag 01074 * - TIM5_FLAG_CC1: TIM5 Capture Compare 1 Flag 01075 * - TIM5_FLAG_CC2: TIM5 Capture Compare 2 Flag 01076 * - TIM5_FLAG_CC3: TIM5 Capture Compare 3 Flag 01077 * - TIM5_FLAG_CC1OF: TIM5 Capture Compare 1 overcapture Flag 01078 * - TIM5_FLAG_CC2OF: TIM5 Capture Compare 2 overcapture Flag 01079 * - TIM5_FLAG_CC3OF: TIM5 Capture Compare 3 overcapture Flag 01080 * @retval None. 01081 */ 01082 void TIM5_ClearFlag(TIM5_FLAG_TypeDef TIM5_FLAG) 01083 { 01084 /* Check the parameters */ 01085 assert_param(IS_TIM5_CLEAR_FLAG_OK(TIM5_FLAG)); 01086 01087 /* Clear the flags (rc_w0) clear this bit by writing 0. Writing �1� has no effect*/ 01088 TIM5->SR1 = (uint8_t)(~((uint8_t)(TIM5_FLAG))); 01089 TIM5->SR2 &= (uint8_t)(~((uint8_t)((uint16_t)TIM5_FLAG >> 8))); 01090 } 01091 01092 /** 01093 * @brief Checks whether the TIM5 interrupt has occurred or not. 01094 * @param TIM5_IT specifies the TIM5 interrupt source to check. 01095 * This parameter can be one of the following values: 01096 * - TIM5_IT_UPDATE: TIM5 update Interrupt source 01097 * - TIM5_IT_CC1: TIM5 Capture Compare 1 Interrupt source 01098 * - TIM5_IT_CC2: TIM5 Capture Compare 2 Interrupt source 01099 * - TIM5_IT_CC3: TIM5 Capture Compare 3 Interrupt source 01100 * @retval ITStatus The new state of the TIM5_IT(SET or RESET). 01101 */ 01102 01103 ITStatus TIM5_GetITStatus(TIM5_IT_TypeDef TIM5_IT) 01104 { 01105 ITStatus bitstatus = RESET; 01106 uint8_t TIM5_itStatus = 0, TIM5_itEnable = 0; 01107 01108 /* Check the parameters */ 01109 assert_param(IS_TIM5_GET_IT_OK(TIM5_IT)); 01110 01111 TIM5_itStatus = (uint8_t)(TIM5->SR1 & TIM5_IT); 01112 01113 TIM5_itEnable = (uint8_t)(TIM5->IER & TIM5_IT); 01114 01115 if ((TIM5_itStatus != (uint8_t)RESET ) && (TIM5_itEnable != (uint8_t)RESET )) 01116 { 01117 bitstatus = SET; 01118 } 01119 else 01120 { 01121 bitstatus = RESET; 01122 } 01123 return (ITStatus)(bitstatus); 01124 } 01125 01126 /** 01127 * @brief Clears the TIM5's interrupt pending bits. 01128 * @param TIM5_IT specifies the pending bit to clear. 01129 * This parameter can be one of the following values: 01130 * - TIM5_IT_UPDATE: TIM5 update Interrupt source 01131 * - TIM5_IT_CC1: TIM5 Capture Compare 1 Interrupt source 01132 * - TIM5_IT_CC2: TIM5 Capture Compare 2 Interrupt source 01133 * - TIM5_IT_CC3: TIM5 Capture Compare 3 Interrupt source 01134 * @retval None. 01135 */ 01136 void TIM5_ClearITPendingBit(TIM5_IT_TypeDef TIM5_IT) 01137 { 01138 /* Check the parameters */ 01139 assert_param(IS_TIM5_IT_OK(TIM5_IT)); 01140 01141 /* Clear the IT pending Bit */ 01142 TIM5->SR1 = (uint8_t)(~TIM5_IT); 01143 } 01144 01145 /** 01146 * @brief Configure the TI1 as Input. 01147 * @param TIM5_ICPolarity The Input Polarity. 01148 * This parameter can be one of the following values: 01149 * - TIM5_ICPOLARITY_FALLING 01150 * - TIM5_ICPOLARITY_RISING 01151 * @param TIM5_ICSelection specifies the input to be used. 01152 * This parameter can be one of the following values: 01153 * - TIM5_ICSELECTION_DIRECTTI: TIM5 Input 1 is selected to 01154 * be connected to IC1. 01155 * - TIM5_ICSELECTION_INDIRECTTI: TIM5 Input 1 is selected to 01156 * be connected to IC2. 01157 * @param TIM5_ICFilter Specifies the Input Capture Filter. 01158 * This parameter must be a value between 0x00 and 0x0F. 01159 * @retval None 01160 */ 01161 static void TI1_Config(uint8_t TIM5_ICPolarity, 01162 uint8_t TIM5_ICSelection, 01163 uint8_t TIM5_ICFilter) 01164 { 01165 /* Disable the Channel 1: Reset the CCE Bit */ 01166 TIM5->CCER1 &= (uint8_t)(~TIM5_CCER1_CC1E); 01167 01168 /* Select the Input and set the filter */ 01169 TIM5->CCMR1 = (uint8_t)((uint8_t)(TIM5->CCMR1 & (uint8_t)(~( TIM5_CCMR_CCxS | TIM5_CCMR_ICxF ))) 01170 | (uint8_t)(( (TIM5_ICSelection)) | ((uint8_t)( TIM5_ICFilter << 4)))); 01171 01172 /* Select the Polarity */ 01173 if (TIM5_ICPolarity != TIM5_ICPOLARITY_RISING) 01174 { 01175 TIM5->CCER1 |= TIM5_CCER1_CC1P ; 01176 } 01177 else 01178 { 01179 TIM5->CCER1 &= (uint8_t)(~TIM5_CCER1_CC1P) ; 01180 } 01181 /* Set the CCE Bit */ 01182 TIM5->CCER1 |= TIM5_CCER1_CC1E; 01183 } 01184 01185 /** 01186 * @brief Configure the TI2 as Input. 01187 * @param TIM5_ICPolarity The Input Polarity. 01188 * This parameter can be one of the following values: 01189 * - TIM5_ICPOLARITY_FALLING 01190 * - TIM5_ICPOLARITY_RISING 01191 * @param TIM5_ICSelection specifies the input to be used. 01192 * This parameter can be one of the following values: 01193 * - TIM5_ICSELECTION_DIRECTTI: TIM5 Input 2 is selected to 01194 * be connected to IC2. 01195 * - TIM5_ICSELECTION_INDIRECTTI: TIM5 Input 2 is selected to 01196 * be connected to IC1. 01197 * @param TIM5_ICFilter Specifies the Input Capture Filter. 01198 * This parameter must be a value between 0x00 and 0x0F. 01199 * @retval None 01200 */ 01201 static void TI2_Config(uint8_t TIM5_ICPolarity, 01202 uint8_t TIM5_ICSelection, 01203 uint8_t TIM5_ICFilter) 01204 { 01205 /* Disable the Channel 2: Reset the CCE Bit */ 01206 TIM5->CCER1 &= (uint8_t)(~TIM5_CCER1_CC2E); 01207 01208 /* Select the Input and set the filter */ 01209 TIM5->CCMR2 = (uint8_t)((uint8_t)(TIM5->CCMR2 & (uint8_t)(~( TIM5_CCMR_CCxS | TIM5_CCMR_ICxF))) 01210 | (uint8_t)(( (TIM5_ICSelection)) | ((uint8_t)( TIM5_ICFilter << 4)))); 01211 01212 01213 /* Select the Polarity */ 01214 if (TIM5_ICPolarity != TIM5_ICPOLARITY_RISING) 01215 { 01216 TIM5->CCER1 |= TIM5_CCER1_CC2P ; 01217 } 01218 else 01219 { 01220 TIM5->CCER1 &= (uint8_t)(~TIM5_CCER1_CC2P) ; 01221 } 01222 01223 /* Set the CCE Bit */ 01224 TIM5->CCER1 |= TIM5_CCER1_CC2E; 01225 } 01226 01227 /** 01228 * @brief Configure the TI3 as Input. 01229 * @param TIM5_ICPolarity The Input Polarity. 01230 * This parameter can be one of the following values: 01231 * - TIM5_ICPOLARITY_FALLING 01232 * - TIM5_ICPOLARITY_RISING 01233 * @param TIM5_ICSelection specifies the input to be used. 01234 * This parameter can be one of the following values: 01235 * - TIM5_ICSELECTION_DIRECTTI: TIM5 Input 3 is selected to 01236 * be connected to IC3. 01237 * @param TIM5_ICFilter Specifies the Input Capture Filter. 01238 * This parameter must be a value between 0x00 and 0x0F. 01239 * @retval None 01240 */ 01241 static void TI3_Config(uint8_t TIM5_ICPolarity, uint8_t TIM5_ICSelection, 01242 uint8_t TIM5_ICFilter) 01243 { 01244 /* Disable the Channel 3: Reset the CCE Bit */ 01245 TIM5->CCER2 &= (uint8_t)(~TIM5_CCER2_CC3E); 01246 01247 /* Select the Input and set the filter */ 01248 TIM5->CCMR3 = (uint8_t)((uint8_t)(TIM5->CCMR3 & (uint8_t)(~( TIM5_CCMR_CCxS | TIM5_CCMR_ICxF))) 01249 | (uint8_t)(( (TIM5_ICSelection)) | ((uint8_t)( TIM5_ICFilter << 4)))); 01250 01251 01252 /* Select the Polarity */ 01253 if (TIM5_ICPolarity != TIM5_ICPOLARITY_RISING) 01254 { 01255 TIM5->CCER2 |= TIM5_CCER2_CC3P ; 01256 } 01257 else 01258 { 01259 TIM5->CCER2 &= (uint8_t)(~TIM5_CCER2_CC3P) ; 01260 } 01261 /* Set the CCE Bit */ 01262 TIM5->CCER2 |= TIM5_CCER2_CC3E; 01263 } 01264 01265 /** 01266 * @brief Enables the TIM5 internal Clock. 01267 * @par Parameters: 01268 * None 01269 * @retval None 01270 */ 01271 void TIM5_InternalClockConfig(void) 01272 { 01273 /* Disable slave mode to clock the prescaler directly with the internal clock */ 01274 TIM5->SMCR &= (uint8_t)(~TIM5_SMCR_SMS); 01275 } 01276 01277 /** 01278 * @brief Selects the TIM5 Trigger Output Mode. 01279 * @param TIM5_TRGOSource : Specifies the Trigger Output source. 01280 * This parameter can be one of the @ref TIM5_TRGOSource_TypeDef enumeration. 01281 * @retval None 01282 */ 01283 void TIM5_SelectOutputTrigger(TIM5_TRGOSource_TypeDef TIM5_TRGOSource) 01284 { 01285 uint8_t tmpcr2 = 0; 01286 01287 /* Check the parameters */ 01288 assert_param(IS_TIM5_TRGO_SOURCE_OK(TIM5_TRGOSource)); 01289 01290 tmpcr2 = TIM5->CR2; 01291 01292 /* Reset the MMS Bits */ 01293 tmpcr2 &= (uint8_t)(~TIM5_CR2_MMS); 01294 01295 /* Select the TRGO source */ 01296 tmpcr2 |= (uint8_t)TIM5_TRGOSource; 01297 01298 TIM5->CR2 = tmpcr2; 01299 } 01300 01301 /** 01302 * @brief Selects the TIM5 Slave Mode. 01303 * @param TIM5_SlaveMode : Specifies the TIM5 Slave Mode. 01304 * This parameter can be one of the @ref TIM5_SlaveMode_TypeDef enumeration. 01305 * @retval None 01306 */ 01307 void TIM5_SelectSlaveMode(TIM5_SlaveMode_TypeDef TIM5_SlaveMode) 01308 { 01309 uint8_t tmpsmcr = 0; 01310 01311 /* Check the parameters */ 01312 assert_param(IS_TIM5_SLAVE_MODE_OK(TIM5_SlaveMode)); 01313 01314 tmpsmcr = TIM5->SMCR; 01315 01316 /* Reset the SMS Bits */ 01317 tmpsmcr &= (uint8_t)(~TIM5_SMCR_SMS); 01318 01319 /* Select the Slave Mode */ 01320 tmpsmcr |= (uint8_t)TIM5_SlaveMode; 01321 01322 TIM5->SMCR = tmpsmcr; 01323 } 01324 01325 /** 01326 * @brief Selects the TIM5 Input Trigger source. 01327 * @param TIM5_InputTriggerSource : Specifies Input Trigger source. 01328 * This parameter can be one of the @ref TIM5_TS_TypeDef enumeration. 01329 * @retval None 01330 */ 01331 void TIM5_SelectInputTrigger(TIM5_TS_TypeDef TIM5_InputTriggerSource) 01332 { 01333 uint8_t tmpsmcr = 0; 01334 01335 /* Check the parameters */ 01336 assert_param(IS_TIM5_TRIGGER_SELECTION_OK(TIM5_InputTriggerSource)); 01337 01338 tmpsmcr = TIM5->SMCR; 01339 01340 /* Select the Trigger Source */ 01341 tmpsmcr &= (uint8_t)(~TIM5_SMCR_TS); 01342 tmpsmcr |= (uint8_t)TIM5_InputTriggerSource; 01343 01344 TIM5->SMCR = (uint8_t)tmpsmcr; 01345 } 01346 01347 /** 01348 * @brief Configures the TIM5 Encoder Interface. 01349 * @param TIM5_EncoderMode : Specifies the TIM5 Encoder Mode. 01350 * This parameter can be one of the @ref TIM5_EncoderMode_TypeDef enumeration. 01351 * @param TIM5_IC1Polarity : Specifies the IC1 Polarity. 01352 * This parameter can be one of the @ref TIM5_ICPolarity_TypeDef enumeration. 01353 * @param TIM5_IC2Polarity : Specifies the IC2 Polarity. 01354 * This parameter can be one of the @ref TIM5_ICPolarity_TypeDef enumeration. 01355 * @retval None 01356 */ 01357 void TIM5_EncoderInterfaceConfig(TIM5_EncoderMode_TypeDef TIM5_EncoderMode, 01358 TIM5_ICPolarity_TypeDef TIM5_IC1Polarity, 01359 TIM5_ICPolarity_TypeDef TIM5_IC2Polarity) 01360 { 01361 uint8_t tmpsmcr = 0; 01362 uint8_t tmpccmr1 = 0; 01363 uint8_t tmpccmr2 = 0; 01364 01365 /* Check the parameters */ 01366 assert_param(IS_TIM5_ENCODER_MODE_OK(TIM5_EncoderMode)); 01367 assert_param(IS_TIM5_IC_POLARITY_OK(TIM5_IC1Polarity)); 01368 assert_param(IS_TIM5_IC_POLARITY_OK(TIM5_IC2Polarity)); 01369 01370 tmpsmcr = TIM5->SMCR; 01371 tmpccmr1 = TIM5->CCMR1; 01372 tmpccmr2 = TIM5->CCMR2; 01373 01374 /* Set the encoder Mode */ 01375 tmpsmcr &= (uint8_t)(TIM5_SMCR_MSM | TIM5_SMCR_TS) ; 01376 tmpsmcr |= (uint8_t)TIM5_EncoderMode; 01377 01378 /* Select the Capture Compare 1 and the Capture Compare 2 as input */ 01379 tmpccmr1 &= (uint8_t)(~TIM5_CCMR_CCxS); 01380 tmpccmr2 &= (uint8_t)(~TIM5_CCMR_CCxS); 01381 tmpccmr1 |= TIM5_CCMR_TIxDirect_Set; 01382 tmpccmr2 |= TIM5_CCMR_TIxDirect_Set; 01383 01384 /* Set the TI1 and the TI2 Polarities */ 01385 if (TIM5_IC1Polarity == TIM5_ICPOLARITY_FALLING) 01386 { 01387 TIM5->CCER1 |= TIM5_CCER1_CC1P ; 01388 } 01389 else 01390 { 01391 TIM5->CCER1 &= (uint8_t)(~TIM5_CCER1_CC1P) ; 01392 } 01393 01394 if (TIM5_IC2Polarity == TIM5_ICPOLARITY_FALLING) 01395 { 01396 TIM5->CCER1 |= TIM5_CCER1_CC2P ; 01397 } 01398 else 01399 { 01400 TIM5->CCER1 &= (uint8_t)(~TIM5_CCER1_CC2P) ; 01401 } 01402 01403 TIM5->SMCR = tmpsmcr; 01404 TIM5->CCMR1 = tmpccmr1; 01405 TIM5->CCMR2 = tmpccmr2; 01406 } 01407 01408 /** 01409 * @} 01410 */ 01411 01412 /** 01413 * @} 01414 */ 01415 01416 01417 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/