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STM8S/A Standard Peripherals Drivers
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stm8s_adc1.h
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00001 /** 00002 ****************************************************************************** 00003 * @file stm8s_adc1.h 00004 * @author MCD Application Team 00005 * @version V2.3.0 00006 * @date 16-June-2017 00007 * @brief This file contains all the prototypes/macros for the ADC1 peripheral. 00008 ****************************************************************************** 00009 * @attention 00010 * 00011 * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2> 00012 * 00013 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 00014 * You may not use this file except in compliance with the License. 00015 * You may obtain a copy of the License at: 00016 * 00017 * http://www.st.com/software_license_agreement_liberty_v2 00018 * 00019 * Unless required by applicable law or agreed to in writing, software 00020 * distributed under the License is distributed on an "AS IS" BASIS, 00021 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 00022 * See the License for the specific language governing permissions and 00023 * limitations under the License. 00024 * 00025 ****************************************************************************** 00026 */ 00027 /* Define to prevent recursive inclusion -------------------------------------*/ 00028 #ifndef __STM8S_ADC1_H 00029 #define __STM8S_ADC1_H 00030 00031 /* Includes ------------------------------------------------------------------*/ 00032 #include "stm8s.h" 00033 00034 /* Exported types ------------------------------------------------------------*/ 00035 00036 /** @addtogroup ADC1_Exported_Types 00037 * @{ 00038 */ 00039 00040 /** 00041 * @brief ADC1 clock prescaler selection 00042 */ 00043 00044 typedef enum 00045 { 00046 ADC1_PRESSEL_FCPU_D2 = (uint8_t)0x00, /**< Prescaler selection fADC1 = fcpu/2 */ 00047 ADC1_PRESSEL_FCPU_D3 = (uint8_t)0x10, /**< Prescaler selection fADC1 = fcpu/3 */ 00048 ADC1_PRESSEL_FCPU_D4 = (uint8_t)0x20, /**< Prescaler selection fADC1 = fcpu/4 */ 00049 ADC1_PRESSEL_FCPU_D6 = (uint8_t)0x30, /**< Prescaler selection fADC1 = fcpu/6 */ 00050 ADC1_PRESSEL_FCPU_D8 = (uint8_t)0x40, /**< Prescaler selection fADC1 = fcpu/8 */ 00051 ADC1_PRESSEL_FCPU_D10 = (uint8_t)0x50, /**< Prescaler selection fADC1 = fcpu/10 */ 00052 ADC1_PRESSEL_FCPU_D12 = (uint8_t)0x60, /**< Prescaler selection fADC1 = fcpu/12 */ 00053 ADC1_PRESSEL_FCPU_D18 = (uint8_t)0x70 /**< Prescaler selection fADC1 = fcpu/18 */ 00054 } ADC1_PresSel_TypeDef; 00055 00056 /** 00057 * @brief ADC1 External conversion trigger event selection 00058 */ 00059 typedef enum 00060 { 00061 ADC1_EXTTRIG_TIM = (uint8_t)0x00, /**< Conversion from Internal TIM1 TRGO event */ 00062 ADC1_EXTTRIG_GPIO = (uint8_t)0x10 /**< Conversion from External interrupt on ADC_ETR pin*/ 00063 } ADC1_ExtTrig_TypeDef; 00064 00065 /** 00066 * @brief ADC1 data alignment 00067 */ 00068 typedef enum 00069 { 00070 ADC1_ALIGN_LEFT = (uint8_t)0x00, /**< Data alignment left */ 00071 ADC1_ALIGN_RIGHT = (uint8_t)0x08 /**< Data alignment right */ 00072 } ADC1_Align_TypeDef; 00073 00074 /** 00075 * @brief ADC1 Interrupt source 00076 */ 00077 typedef enum 00078 { 00079 ADC1_IT_AWDIE = (uint16_t)0x010, /**< Analog WDG interrupt enable */ 00080 ADC1_IT_EOCIE = (uint16_t)0x020, /**< EOC interrupt enable */ 00081 ADC1_IT_AWD = (uint16_t)0x140, /**< Analog WDG status */ 00082 ADC1_IT_AWS0 = (uint16_t)0x110, /**< Analog channel 0 status */ 00083 ADC1_IT_AWS1 = (uint16_t)0x111, /**< Analog channel 1 status */ 00084 ADC1_IT_AWS2 = (uint16_t)0x112, /**< Analog channel 2 status */ 00085 ADC1_IT_AWS3 = (uint16_t)0x113, /**< Analog channel 3 status */ 00086 ADC1_IT_AWS4 = (uint16_t)0x114, /**< Analog channel 4 status */ 00087 ADC1_IT_AWS5 = (uint16_t)0x115, /**< Analog channel 5 status */ 00088 ADC1_IT_AWS6 = (uint16_t)0x116, /**< Analog channel 6 status */ 00089 ADC1_IT_AWS7 = (uint16_t)0x117, /**< Analog channel 7 status */ 00090 ADC1_IT_AWS8 = (uint16_t)0x118, /**< Analog channel 8 status */ 00091 ADC1_IT_AWS9 = (uint16_t)0x119, /**< Analog channel 9 status */ 00092 ADC1_IT_AWS12 = (uint16_t)0x11C, /**< Analog channel 12 status */ 00093 /* refer to product datasheet for channel 12 availability */ 00094 ADC1_IT_EOC = (uint16_t)0x080 /**< EOC pending bit */ 00095 00096 } ADC1_IT_TypeDef; 00097 00098 /** 00099 * @brief ADC1 Flags 00100 */ 00101 typedef enum 00102 { 00103 ADC1_FLAG_OVR = (uint8_t)0x41, /**< Overrun status flag */ 00104 ADC1_FLAG_AWD = (uint8_t)0x40, /**< Analog WDG status */ 00105 ADC1_FLAG_AWS0 = (uint8_t)0x10, /**< Analog channel 0 status */ 00106 ADC1_FLAG_AWS1 = (uint8_t)0x11, /**< Analog channel 1 status */ 00107 ADC1_FLAG_AWS2 = (uint8_t)0x12, /**< Analog channel 2 status */ 00108 ADC1_FLAG_AWS3 = (uint8_t)0x13, /**< Analog channel 3 status */ 00109 ADC1_FLAG_AWS4 = (uint8_t)0x14, /**< Analog channel 4 status */ 00110 ADC1_FLAG_AWS5 = (uint8_t)0x15, /**< Analog channel 5 status */ 00111 ADC1_FLAG_AWS6 = (uint8_t)0x16, /**< Analog channel 6 status */ 00112 ADC1_FLAG_AWS7 = (uint8_t)0x17, /**< Analog channel 7 status */ 00113 ADC1_FLAG_AWS8 = (uint8_t)0x18, /**< Analog channel 8 status*/ 00114 ADC1_FLAG_AWS9 = (uint8_t)0x19, /**< Analog channel 9 status */ 00115 ADC1_FLAG_AWS12 = (uint8_t)0x1C, /**< Analog channel 12 status */ 00116 /* refer to product datasheet for channel 12 availability */ 00117 ADC1_FLAG_EOC = (uint8_t)0x80 /**< EOC falg */ 00118 }ADC1_Flag_TypeDef; 00119 00120 00121 /** 00122 * @brief ADC1 schmitt Trigger 00123 */ 00124 typedef enum 00125 { 00126 ADC1_SCHMITTTRIG_CHANNEL0 = (uint8_t)0x00, /**< Schmitt trigger disable on AIN0 */ 00127 ADC1_SCHMITTTRIG_CHANNEL1 = (uint8_t)0x01, /**< Schmitt trigger disable on AIN1 */ 00128 ADC1_SCHMITTTRIG_CHANNEL2 = (uint8_t)0x02, /**< Schmitt trigger disable on AIN2 */ 00129 ADC1_SCHMITTTRIG_CHANNEL3 = (uint8_t)0x03, /**< Schmitt trigger disable on AIN3 */ 00130 ADC1_SCHMITTTRIG_CHANNEL4 = (uint8_t)0x04, /**< Schmitt trigger disable on AIN4 */ 00131 ADC1_SCHMITTTRIG_CHANNEL5 = (uint8_t)0x05, /**< Schmitt trigger disable on AIN5 */ 00132 ADC1_SCHMITTTRIG_CHANNEL6 = (uint8_t)0x06, /**< Schmitt trigger disable on AIN6 */ 00133 ADC1_SCHMITTTRIG_CHANNEL7 = (uint8_t)0x07, /**< Schmitt trigger disable on AIN7 */ 00134 ADC1_SCHMITTTRIG_CHANNEL8 = (uint8_t)0x08, /**< Schmitt trigger disable on AIN8 */ 00135 ADC1_SCHMITTTRIG_CHANNEL9 = (uint8_t)0x09, /**< Schmitt trigger disable on AIN9 */ 00136 ADC1_SCHMITTTRIG_CHANNEL12 = (uint8_t)0x0C, /**< Schmitt trigger disable on AIN12 */ 00137 /* refer to product datasheet for channel 12 availability */ 00138 ADC1_SCHMITTTRIG_ALL = (uint8_t)0xFF /**< Schmitt trigger disable on All channels */ 00139 } ADC1_SchmittTrigg_TypeDef; 00140 00141 /** 00142 * @brief ADC1 conversion mode selection 00143 */ 00144 00145 typedef enum 00146 { 00147 ADC1_CONVERSIONMODE_SINGLE = (uint8_t)0x00, /**< Single conversion mode */ 00148 ADC1_CONVERSIONMODE_CONTINUOUS = (uint8_t)0x01 /**< Continuous conversion mode */ 00149 } ADC1_ConvMode_TypeDef; 00150 00151 /** 00152 * @brief ADC1 analog channel selection 00153 */ 00154 00155 typedef enum 00156 { 00157 ADC1_CHANNEL_0 = (uint8_t)0x00, /**< Analog channel 0 */ 00158 ADC1_CHANNEL_1 = (uint8_t)0x01, /**< Analog channel 1 */ 00159 ADC1_CHANNEL_2 = (uint8_t)0x02, /**< Analog channel 2 */ 00160 ADC1_CHANNEL_3 = (uint8_t)0x03, /**< Analog channel 3 */ 00161 ADC1_CHANNEL_4 = (uint8_t)0x04, /**< Analog channel 4 */ 00162 ADC1_CHANNEL_5 = (uint8_t)0x05, /**< Analog channel 5 */ 00163 ADC1_CHANNEL_6 = (uint8_t)0x06, /**< Analog channel 6 */ 00164 ADC1_CHANNEL_7 = (uint8_t)0x07, /**< Analog channel 7 */ 00165 ADC1_CHANNEL_8 = (uint8_t)0x08, /**< Analog channel 8 */ 00166 ADC1_CHANNEL_9 = (uint8_t)0x09, /**< Analog channel 9 */ 00167 ADC1_CHANNEL_12 = (uint8_t)0x0C /**< Analog channel 12 */ 00168 /* refer to product datasheet for channel 12 availability */ 00169 } ADC1_Channel_TypeDef; 00170 00171 /** 00172 * @} 00173 */ 00174 00175 /* Exported constants --------------------------------------------------------*/ 00176 00177 /* Exported macros ------------------------------------------------------------*/ 00178 00179 /* Private macros ------------------------------------------------------------*/ 00180 00181 /** @addtogroup ADC1_Private_Macros 00182 * @brief Macros used by the assert function to check the different functions parameters. 00183 * @{ 00184 */ 00185 00186 /** 00187 * @brief Macro used by the assert function to check the different prescaler's values. 00188 */ 00189 #define IS_ADC1_PRESSEL_OK(PRESCALER) (((PRESCALER) == ADC1_PRESSEL_FCPU_D2) || \ 00190 ((PRESCALER) == ADC1_PRESSEL_FCPU_D3) || \ 00191 ((PRESCALER) == ADC1_PRESSEL_FCPU_D4) || \ 00192 ((PRESCALER) == ADC1_PRESSEL_FCPU_D6) || \ 00193 ((PRESCALER) == ADC1_PRESSEL_FCPU_D8) || \ 00194 ((PRESCALER) == ADC1_PRESSEL_FCPU_D10) || \ 00195 ((PRESCALER) == ADC1_PRESSEL_FCPU_D12) || \ 00196 ((PRESCALER) == ADC1_PRESSEL_FCPU_D18)) 00197 00198 /** 00199 * @brief Macro used by the assert function to check the different external trigger values. 00200 */ 00201 #define IS_ADC1_EXTTRIG_OK(EXTRIG) (((EXTRIG) == ADC1_EXTTRIG_TIM) || \ 00202 ((EXTRIG) == ADC1_EXTTRIG_GPIO)) 00203 00204 /** 00205 * @brief Macro used by the assert function to check the different alignment modes. 00206 */ 00207 #define IS_ADC1_ALIGN_OK(ALIGN) (((ALIGN) == ADC1_ALIGN_LEFT) || \ 00208 ((ALIGN) == ADC1_ALIGN_RIGHT)) 00209 00210 /** 00211 * @brief Macro used by the assert function to check the Interrupt source. 00212 */ 00213 #define IS_ADC1_IT_OK(IT) (((IT) == ADC1_IT_EOCIE) || \ 00214 ((IT) == ADC1_IT_AWDIE)) 00215 00216 /** 00217 * @brief Macro used by the assert function to check the ADC1 Flag. 00218 */ 00219 #define IS_ADC1_FLAG_OK(FLAG) (((FLAG) == ADC1_FLAG_EOC)|| \ 00220 ((FLAG) == ADC1_FLAG_OVR) || \ 00221 ((FLAG) == ADC1_FLAG_AWD) || \ 00222 ((FLAG) == ADC1_FLAG_AWS0) || \ 00223 ((FLAG) == ADC1_FLAG_AWS1) || \ 00224 ((FLAG) == ADC1_FLAG_AWS2) || \ 00225 ((FLAG) == ADC1_FLAG_AWS3) || \ 00226 ((FLAG) == ADC1_FLAG_AWS4) || \ 00227 ((FLAG) == ADC1_FLAG_AWS5) || \ 00228 ((FLAG) == ADC1_FLAG_AWS6) || \ 00229 ((FLAG) == ADC1_FLAG_AWS7) || \ 00230 ((FLAG) == ADC1_FLAG_AWS8) || \ 00231 ((FLAG) == ADC1_FLAG_AWS9)) 00232 00233 /** 00234 * @brief Macro used by the assert function to check the ADC1 pending bits. 00235 */ 00236 #define IS_ADC1_ITPENDINGBIT_OK(ITPENDINGBIT) (((ITPENDINGBIT) == ADC1_IT_EOC) || \ 00237 ((ITPENDINGBIT) == ADC1_IT_AWD) || \ 00238 ((ITPENDINGBIT) == ADC1_IT_AWS0) || \ 00239 ((ITPENDINGBIT) == ADC1_IT_AWS1) || \ 00240 ((ITPENDINGBIT) == ADC1_IT_AWS2) || \ 00241 ((ITPENDINGBIT) == ADC1_IT_AWS3) || \ 00242 ((ITPENDINGBIT) == ADC1_IT_AWS4) || \ 00243 ((ITPENDINGBIT) == ADC1_IT_AWS5) || \ 00244 ((ITPENDINGBIT) == ADC1_IT_AWS6) || \ 00245 ((ITPENDINGBIT) == ADC1_IT_AWS7) || \ 00246 ((ITPENDINGBIT) == ADC1_IT_AWS8) || \ 00247 ((ITPENDINGBIT) == ADC1_IT_AWS12) || \ 00248 ((ITPENDINGBIT) == ADC1_IT_AWS9)) 00249 00250 /** 00251 * @brief Macro used by the assert function to check the different schmitt trigger values. 00252 */ 00253 #define IS_ADC1_SCHMITTTRIG_OK(SCHMITTTRIG) (((SCHMITTTRIG) == ADC1_SCHMITTTRIG_CHANNEL0) || \ 00254 ((SCHMITTTRIG) == ADC1_SCHMITTTRIG_CHANNEL1) || \ 00255 ((SCHMITTTRIG) == ADC1_SCHMITTTRIG_CHANNEL2) || \ 00256 ((SCHMITTTRIG) == ADC1_SCHMITTTRIG_CHANNEL3) || \ 00257 ((SCHMITTTRIG) == ADC1_SCHMITTTRIG_CHANNEL4) || \ 00258 ((SCHMITTTRIG) == ADC1_SCHMITTTRIG_CHANNEL5) || \ 00259 ((SCHMITTTRIG) == ADC1_SCHMITTTRIG_CHANNEL6) || \ 00260 ((SCHMITTTRIG) == ADC1_SCHMITTTRIG_CHANNEL7) || \ 00261 ((SCHMITTTRIG) == ADC1_SCHMITTTRIG_CHANNEL8) || \ 00262 ((SCHMITTTRIG) == ADC1_SCHMITTTRIG_CHANNEL12) || \ 00263 ((SCHMITTTRIG) == ADC1_SCHMITTTRIG_ALL) || \ 00264 ((SCHMITTTRIG) == ADC1_SCHMITTTRIG_CHANNEL9)) 00265 00266 /** 00267 * @brief Macro used by the assert function to check the different conversion modes. 00268 */ 00269 #define IS_ADC1_CONVERSIONMODE_OK(MODE) (((MODE) == ADC1_CONVERSIONMODE_SINGLE) || \ 00270 ((MODE) == ADC1_CONVERSIONMODE_CONTINUOUS)) 00271 00272 /** 00273 * @brief Macro used by the assert function to check the different channels values. 00274 */ 00275 #define IS_ADC1_CHANNEL_OK(CHANNEL) (((CHANNEL) == ADC1_CHANNEL_0) || \ 00276 ((CHANNEL) == ADC1_CHANNEL_1) || \ 00277 ((CHANNEL) == ADC1_CHANNEL_2) || \ 00278 ((CHANNEL) == ADC1_CHANNEL_3) || \ 00279 ((CHANNEL) == ADC1_CHANNEL_4) || \ 00280 ((CHANNEL) == ADC1_CHANNEL_5) || \ 00281 ((CHANNEL) == ADC1_CHANNEL_6) || \ 00282 ((CHANNEL) == ADC1_CHANNEL_7) || \ 00283 ((CHANNEL) == ADC1_CHANNEL_8) || \ 00284 ((CHANNEL) == ADC1_CHANNEL_12) || \ 00285 ((CHANNEL) == ADC1_CHANNEL_9)) 00286 00287 /** 00288 * @brief Macro used by the assert function to check the possible buffer values. 00289 */ 00290 #define IS_ADC1_BUFFER_OK(BUFFER) ((BUFFER) <= (uint8_t)0x09) 00291 00292 /** 00293 * @} 00294 */ 00295 00296 /* Exported functions ------------------------------------------------------- */ 00297 00298 /** @addtogroup ADC1_Exported_Functions 00299 * @{ 00300 */ 00301 void ADC1_DeInit(void); 00302 void ADC1_Init(ADC1_ConvMode_TypeDef ADC1_ConversionMode, 00303 ADC1_Channel_TypeDef ADC1_Channel, 00304 ADC1_PresSel_TypeDef ADC1_PrescalerSelection, 00305 ADC1_ExtTrig_TypeDef ADC1_ExtTrigger, 00306 FunctionalState ADC1_ExtTriggerState, ADC1_Align_TypeDef ADC1_Align, 00307 ADC1_SchmittTrigg_TypeDef ADC1_SchmittTriggerChannel, 00308 FunctionalState ADC1_SchmittTriggerState); 00309 void ADC1_Cmd(FunctionalState NewState); 00310 void ADC1_ScanModeCmd(FunctionalState NewState); 00311 void ADC1_DataBufferCmd(FunctionalState NewState); 00312 void ADC1_ITConfig(ADC1_IT_TypeDef ADC1_IT, FunctionalState NewState); 00313 void ADC1_PrescalerConfig(ADC1_PresSel_TypeDef ADC1_Prescaler); 00314 void ADC1_SchmittTriggerConfig(ADC1_SchmittTrigg_TypeDef ADC1_SchmittTriggerChannel, 00315 FunctionalState NewState); 00316 void ADC1_ConversionConfig(ADC1_ConvMode_TypeDef ADC1_ConversionMode, 00317 ADC1_Channel_TypeDef ADC1_Channel, 00318 ADC1_Align_TypeDef ADC1_Align); 00319 void ADC1_ExternalTriggerConfig(ADC1_ExtTrig_TypeDef ADC1_ExtTrigger, FunctionalState NewState); 00320 void ADC1_AWDChannelConfig(ADC1_Channel_TypeDef Channel, FunctionalState NewState); 00321 void ADC1_StartConversion(void); 00322 uint16_t ADC1_GetConversionValue(void); 00323 void ADC1_SetHighThreshold(uint16_t Threshold); 00324 void ADC1_SetLowThreshold(uint16_t Threshold); 00325 uint16_t ADC1_GetBufferValue(uint8_t Buffer); 00326 FlagStatus ADC1_GetAWDChannelStatus(ADC1_Channel_TypeDef Channel); 00327 FlagStatus ADC1_GetFlagStatus(ADC1_Flag_TypeDef Flag); 00328 void ADC1_ClearFlag(ADC1_Flag_TypeDef Flag); 00329 ITStatus ADC1_GetITStatus(ADC1_IT_TypeDef ITPendingBit); 00330 void ADC1_ClearITPendingBit(ADC1_IT_TypeDef ITPendingBit); 00331 /** 00332 * @} 00333 */ 00334 00335 #endif /* __STM8S_ADC1_H */ 00336 00337 00338 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/