Adjusts the Internal High Speed oscillator (HSI) calibration value.

Note:

The calibration is used to compensate for the variations in voltage and temperature that influence the frequency of the internal HSI RC.

Parameters:

CLK_HSICalibrationValue

: calibration trimming value. This parameter must be a number between [(HSICALR regiter value) -12] and [(HSICALR regiter value) + 8 ]

Note:

Once HSITRIMR register configured, its value is used instead of the HSICALR register values.

Return values:

None

Definition at line 182 of file stm8l15x_clk.c.

References CLK.

Configures the BEEP clock (BEEPCLK).

Parameters:

CLK_BEEPCLKSource,:

specifies the BEEP clock source. This parameter can be one of the following values: CLK_BEEPCLKSource_Off: BEEP clock Off CLK_BEEPCLKSource_LSE: LSE selected as BEEP clock CLK_BEEPCLKSource_LSI: LSI selected as BEEP clock

Return values:

None

Definition at line 629 of file stm8l15x_clk.c.

References CLK, and IS_CLK_CLOCK_BEEP.

Selects the clock source to output on CCO pin(PC4).

Note:

PC4 should be configured output push-pull with the speed that matches maximum output speed of the desired clock.

Parameters:

CLK_CCOSource,:

specifies the clock source to output. This parameter can be one of the following values: CLK_CCOSource_Off: No clock selected as CCO source CLK_CCOSource_HSI: HSI clock selected as CCO source CLK_CCOSource_LSI: LSI clock selected as CCO source CLK_CCOSource_LSE: LSE clock selected as CCO source CLK_CCOSource_HSE: HSE clock selected as CCO source

CLK_CCODiv,:

specifies the CCO prescaler. This parameter can be one of the following values: CLK_CCODiv_1: no division applied to CCO clock CLK_CCODiv_2: division by 2 applied to CCO clock CLK_CCODiv_4: division by 4 applied to CCO clock CLK_CCODiv_8: division by 8 applied to CCO clock CLK_CCODiv_16: division by 16 applied to CCO clock CLK_CCODiv_32: division by 32 applied to CCO clock CLK_CCODiv_64: division by 64 applied to CCO clock

Return values:

None

Definition at line 350 of file stm8l15x_clk.c.

References CLK, IS_CLK_OUTPUT, and IS_CLK_OUTPUT_DIVIDER.

Clears the CSS LSE Flag.

Parameters:

None

Return values:

None

Definition at line 1010 of file stm8l15x_clk.c.

References CSSLSE, and CSSLSE_CSR_CSSF.

Clears the CLK's interrupt pending bits.

Parameters:

CLK_IT,:

specifies the interrupt pending bit to clear. This parameter can be any combination of the following values: CLK_IT_SWIF: Clock switch interrupt CLK_IT_LSECSSF: LSE Clock security system detection interrupt

Return values:

None

Definition at line 1083 of file stm8l15x_clk.c.

References CLK, CLK_SWCR_SWIF, CSSLSE, CSSLSE_CSR_CSSF, and IS_CLK_CLEAR_IT.

Enables the Clock Security System.

Note:

If a failure is detected on the HSE oscillator clock, this oscillator is automatically disabled and an interrupt is generated to inform the software about the failure allowing the MCU to perform rescue operations.

Once CSS is enabled it cannot be disabled until the next reset.

Parameters:

None

Return values:

None

Definition at line 300 of file stm8l15x_clk.c.

References CLK, and CLK_CSSR_CSSEN.

Enables the Clock Security System deglitcher system.

Parameters:

None

Return values:

None

Definition at line 311 of file stm8l15x_clk.c.

References CLK, CLK_CSSR_CSSDGON, DISABLE, and IS_FUNCTIONAL_STATE.

Deinitializes the CLK peripheral registers to their default reset values.

Parameters:

None

Return values:

None

Definition at line 114 of file stm8l15x_clk.c.

References CLK, CLK_CBEEPR_RESET_VALUE, CLK_CCOR_RESET_VALUE, CLK_CKDIVR_RESET_VALUE, CLK_CRTCR_RESET_VALUE, CLK_CSSR_RESET_VALUE, CLK_ECKCR_RESET_VALUE, CLK_HSICALR_RESET_VALUE, CLK_HSITRIMR_RESET_VALUE, CLK_HSIUNLCKR_RESET_VALUE, CLK_ICKCR_RESET_VALUE, CLK_PCKENR1_RESET_VALUE, CLK_PCKENR2_RESET_VALUE, CLK_PCKENR3_RESET_VALUE, CLK_REGCSR_RESET_VALUE, CLK_SWCR_RESET_VALUE, and CLK_SWR_RESET_VALUE.

Returns the frequencies of different the SYSCLK.

Note:

The system frequency computed by this function is not the real frequency in the chip. It is calculated based on the predefined constant and the selected clock source:

If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)

If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)

If SYSCLK source is LSE, function returns values based on LSE_VALUE(***)

If SYSCLK source is LSI, function returns values based on LSI_VALUE(****)

(*) HSI_VALUE is a constant defined in stm8l15x.h file (default value 16 MHz) but the real value may vary depending on the variations in voltage and temperature.

(**) HSE_VALUE is a constant defined in stm8l15x.h file (default value 16 MHz), user has to ensure that HSE_VALUE is same as the real frequency of the crystal used. Otherwise, this function may have wrong result.

(***) LSI_VALUE is a constant defined in stm8l15x.h file (default value 38 KHz) but the real value may vary depending on the variations in voltage and temperature.

(****) LSE_VALUE is a constant defined in stm8l15x.h file (default value 32,768 KHz), user has to ensure that LSE_VALUE is same as the real frequency of the crystal used. Otherwise, this function may have wrong result.

The result of this function could be not correct when using fractional value for HSE crystal.

Parameters:

None

Note:

This function can be used by the user application to compute the baudrate for the communication peripherals or configure other parameters.

Each time SYSCLK clock changes, this function must be called to update the returned value. Otherwise, any configuration based on this function will be incorrect.

Return values:

System

Clock frequency value

Definition at line 472 of file stm8l15x_clk.c.

References CLK, CLK_CKDIVR_CKM, CLK_SYSCLKSource_HSE, CLK_SYSCLKSource_HSI, CLK_SYSCLKSource_LSI, HSE_VALUE, HSI_VALUE, LSE_VALUE, LSI_VALUE, and SYSDivFactor.

Referenced by I2C_Init(), and USART_Init().

Checks whether the specified CLK flag is set or not.

Parameters:

CLK_FLAG,:

specifies the flag to check. This parameter can be one of the following values: CLK_FLAG_LSIRDY: LSI oscillator clock ready CLK_FLAG_HSIRDY: HSI oscillator clock ready CLK_FLAG_HSERDY: HSE oscillator clock ready CLK_FLAG_SWBSY: Switch busy CLK_FLAG_CSSD: Clock security system detection CLK_FLAG_AUX: Auxiliary oscillator connected to master clock CLK_FLAG_LSERDY: LSE oscillator clock ready CLK_FLAG_CCOBSY: Configurable clock output busy CLK_FLAG_RTCSWBSY: RTC clock busy in switch CLK_FLAG_EEREADY: Flash program memory and Data EEPROM ready CLK_FLAG_EEBUSY: Flash program memory and Data EEPROM busy CLK_FLAG_LSEPD: LSE power-down CLK_FLAG_LSIPD: LSI power-down CLK_FLAG_HSEPD: HSE power-down CLK_FLAG_HSIPD: HSI power-down CLK_FLAG_REGREADY: REGREADY CLK_FLAG_BEEPSWBSY: BEEP clock busy in switch CLK_FLAG_LSECSSF: CSS on LSE detection CLK_FLAG_RTCCLKSWF: RTCCLK switch completed on LSE failure

Return values:

The	new state of CLK_FLAG (SET or RESET).

Definition at line 939 of file stm8l15x_clk.c.

References CLK, CSSLSE, IS_CLK_FLAGS, RESET, and SET.

Checks whether the specified CLK interrupt has occurred or not.

Parameters:

CLK_IT,:

specifies the CLK interrupt source to check. This parameter can be one of the following values: CLK_IT_SWIF: LSI ready interrupt CLK_IT_LSECSSF: LSE ready interrupt CLK_IT_CSSD: HSI ready interrupt

Return values:

The	new state of CLK_IT (SET or RESET).

Definition at line 1026 of file stm8l15x_clk.c.

References CLK, CLK_IT_LSECSSF, CLK_IT_SWIF, CSSLSE, IS_CLK_IT, RESET, and SET.

Returns the clock source used as system clock.

Parameters:

None

Return values:

Clock

used as System clock (SYSCLK) source. The returned value can be one of the following: CLK_SYSCLKSource_HSI: HSI used as system clock CLK_SYSCLKSource_LSI: LSI used as system clock CLK_SYSCLKSource_HSE: HSE used as system clock CLK_SYSCLKSource_LSE: LSE used as system clock

Definition at line 429 of file stm8l15x_clk.c.

References CLK.

Configures clock during halt and active halt modes.

Parameters:

CLK_Halt	: Specifies the clock state and wake-up mode from halt way. This parameter can be a value of CLK_Halt_TypeDef.
NewState	: Specifies the System clock (SYSCLK) state in active halt mode. This parameter can be ENABLE or DISABLE.

Return values:

None

Definition at line 801 of file stm8l15x_clk.c.

References CLK, DISABLE, IS_CLK_HALT, and IS_FUNCTIONAL_STATE.

Configures the External High Speed oscillator (HSE).

Note:

After enabling the HSE (CLK_HSE_ON or CLK_HSE_Bypass), the application software should wait on HSERDY flag to be set indicating that HSE clock is stable and can be used to clock the system.

HSE state can not be changed if it is used as system clock. In this case, you have to select another source of the system clock then change the HSE state (ex. disable it).

The HSE is stopped by hardware when entering HALT and active HALT modes.

Parameters:

CLK_HSE,:

specifies the new state of the HSE. This parameter can be one of the following values: CLK_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after 6 HSE oscillator clock cycles. CLK_HSE_ON: turn ON the HSE oscillator CLK_HSE_Bypass: HSE oscillator bypassed with external clock

Note:

In case of Enabling HSE Bypass make sure that the HSE clock source is not used by the RTC, output or involved in a switching operation.

Return values:

None

Definition at line 243 of file stm8l15x_clk.c.

References CLK, CLK_ECKCR_HSEBYP, CLK_ECKCR_HSEON, and IS_CLK_HSE.

Enables or disables the Internal High Speed oscillator (HSI).

Note:

The HSI is stopped by hardware when entering Halt and active Halt modes. It is used (enabled by hardware) as system clock source after startup from Reset, wakeup from Halt and active Halt mode when the FHWU bit is set in the ICKCR register, or in case of HSE failure used as system clock (if the Clock Security System CSS is enabled).

HSI can not be stopped if it is used as active CCO source, as active RTC clock, if the safe oscillator (AUX) is enabled or as system clock source, In this case, you have to select another source of the system clock then stop the HSI.

After enabling the HSI, the application software should wait on HSIRDY flag to be set indicating that HSI clock is stable and can be used as system clock source.

Parameters:

NewState,:

new state of the HSI. This parameter can be: ENABLE or DISABLE.

Note:

When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator clock cycles.

Return values:

None

Definition at line 154 of file stm8l15x_clk.c.

References CLK, CLK_ICKCR_HSION, DISABLE, and IS_FUNCTIONAL_STATE.

Enables or disables the specified CLK interrupts.

Parameters:

CLK_IT,:	specifies the CLK interrupt sources to be enabled or disabled. This parameter can be any combination of the following values: CLK_IT_CSSD: Clock security system detection interrupt CLK_IT_SWIF: Clock switch interrupt CLK_IT_LSECSSF: LSE Clock security system detection interrupt
NewState,:	new state of the specified CLK interrupts. This parameter can be: ENABLE or DISABLE.

Return values:

None

Definition at line 869 of file stm8l15x_clk.c.

References CLK, CLK_CSSR_CSSDIE, CLK_IT_LSECSSF, CLK_IT_SWIF, CLK_SWCR_SWIEN, CSSLSE, CSSLSE_CSR_CSSIE, DISABLE, IS_CLK_IT, and IS_FUNCTIONAL_STATE.

Enables the clock CSS on LSE.

Note:

Once Enabled, only POR can Disable it.

Parameters:

None

Return values:

None

Definition at line 759 of file stm8l15x_clk.c.

References CSSLSE, and CSSLSE_CSR_CSSEN.

Configures the External Low Speed oscillator (LSE).

Note:

After enabling the LSE (CLK_LSE_ON or CLK_LSE_Bypass), the application software should wait on LSERDY flag to be set indicating that LSE clock is stable and can be used to clock the RTC.

Parameters:

CLK_LSE,:

specifies the new state of the LSE. This parameter can be one of the following values: CLK_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after 6 LSE oscillator clock cycles. CLK_LSE_ON: turn ON the LSE oscillator CLK_LSE_Bypass: LSE oscillator bypassed with external clock

Note:

In case of Enabling LSE Bypass make sure that the LSE clock source is not used by the RTC, output or involved in a switching operation.

Return values:

None

Definition at line 274 of file stm8l15x_clk.c.

References CLK, CLK_ECKCR_LSEBYP, CLK_ECKCR_LSEON, and IS_CLK_LSE.

Enables or disables the Internal Low Speed oscillator (LSI).

Note:

After enabling the LSI, the application software should wait on LSIRDY flag to be set indicating that LSI clock is stable and can be used to clock the IWDG and/or the RTC.

LSI can not be disabled if used as system clock source, as active CCO source, as BEEP clock source while BEEPAHALT bit is set or, as RTC active clock source.

Parameters:

NewState,:

new state of the LSI. This parameter can be: ENABLE or DISABLE.

Note:

When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator clock cycles.

Return values:

None

Definition at line 206 of file stm8l15x_clk.c.

References CLK, CLK_ICKCR_LSION, DISABLE, and IS_FUNCTIONAL_STATE.

Configures the main voltage regulator.

Parameters:

NewState,:

specifies the MVR state. This parameter can be one of the following values: DISABLE: MVR disabled; ENABLE: MVR enabled.

Return values:

None

Definition at line 825 of file stm8l15x_clk.c.

References CLK, CLK_REGCSR_REGOFF, DISABLE, and IS_FUNCTIONAL_STATE.

Enables or disables the specified peripheral clock.

Note:

After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.

Parameters:

CLK_Peripheral,:

specifies the peripheral to gate its clock. This parameter can be any combination of the following values: CLK_Peripheral_TIM2: TIM2 clock CLK_Peripheral_TIM3: TIM3 clock CLK_Peripheral_TIM4: TIM4 clock CLK_Peripheral_I2C1: I2C1 clock CLK_Peripheral_SPI1: SPI1 clock CLK_Peripheral_USART1: USART1 clock CLK_Peripheral_BEEP: BEEP clock CLK_Peripheral_DAC: DAC clock CLK_Peripheral_ADC1: ADC1 clock CLK_Peripheral_TIM1: TIM1 clock CLK_Peripheral_RTC: RTC clock CLK_Peripheral_LCD: LCD clock CLK_Peripheral_DMA1: DMA1 clock CLK_Peripheral_COMP: COMP clock CLK_Peripheral_BOOTROM: BOOTROM clock CLK_Peripheral_AES: AES clock CLK_Peripheral_TIM5: TIM5 clock CLK_Peripheral_SPI2: SPI2 clock CLK_Peripheral_USART2: USART2 clock CLK_Peripheral_USART3: USART3 clock CLK_Peripheral_CSSLSE: CSS on LSE clock

NewState,:

new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.

Return values:

None

Definition at line 671 of file stm8l15x_clk.c.

References CLK, DISABLE, IS_CLK_PERIPHERAL, and IS_FUNCTIONAL_STATE.

Enables RTC clock switch to LSI in case of LSE failure.

Note:

Once Enabled, only POR can Disable it.

Parameters:

None

Return values:

None

Definition at line 771 of file stm8l15x_clk.c.

References CSSLSE, and CSSLSE_CSR_SWITCHEN.

Configures the RTC clock (RTCCLK).

Parameters:

CLK_RTCCLKSource,:	specifies the RTC clock source. This parameter can be one of the following values: CLK_RTCCLKSource_Off: RTC clock Off CLK_RTCCLKSource_LSE: LSE selected as RTC clock CLK_RTCCLKSource_LSI: LSI selected as RTC clock CLK_RTCCLKSource_HSE: HSE selected as RTC clock CLK_RTCCLKSource_HSI: HSI selected as RTC clock
CLK_RTCCLKDiv,:	specifies the RTC clock source divider. This parameter can be one of the following values: CLK_RTCCLKDiv_1: Clock RTC Div 1 CLK_RTCCLKDiv_2: Clock RTC Div 2 CLK_RTCCLKDiv_4: Clock RTC Div 4 CLK_RTCCLKDiv_8: Clock RTC Div 8 CLK_RTCCLKDiv_16: Clock RTC Div 16 CLK_RTCCLKDiv_32: Clock RTC Div 32 CLK_RTCCLKDiv_64: Clock RTC Div 64

Note:

If the LSE or LSI is used as RTC clock source, the RTC continues to work in HALT and Active HALT modes, and can be used as wakeup source. However, when the HSE clock is used as RTC clock source.

The maximum input clock frequency for RTC is 1MHz (when using HSE/HSI as RTC clock source).

Return values:

None

Definition at line 610 of file stm8l15x_clk.c.

References CLK, IS_CLK_CLOCK_RTC, and IS_CLK_CLOCK_RTC_DIV.

Configures the System clock (SYSCLK) dividers.

Parameters:

CLK_SYSCLKDiv

: Specifies the system clock divider to apply. This parameter can be one of the following values: CLK_SYSCLKDiv_1 CLK_SYSCLKDiv_2 CLK_SYSCLKDiv_4 CLK_SYSCLKDiv_8 CLK_SYSCLKDiv_16 CLK_SYSCLKDiv_64 CLK_SYSCLKDiv_128

Return values:

None

Definition at line 522 of file stm8l15x_clk.c.

References CLK, and IS_CLK_SYSTEM_DIVIDER.

Configures the system clock (SYSCLK).

Note:

The HSI is used (enabled by hardware) as system clock source after startup from Reset, wake-up from Halt and active Halt modes, or in case of failure of the HSE used as system clock (if the Clock Security System CSS is enabled).

A switch from one clock source to another occurs only if the target clock source is ready (clock stable after startup delay or PLL locked). You can use CLK_GetSYSCLKSource() function to know which clock is currently used as system clock source.

Parameters:

CLK_SYSCLKSource,:

specifies the clock source used as system clock. This parameter can be one of the following values: CLK_SYSCLKSource_HSI: HSI selected as system clock source CLK_SYSCLKSource_HSE: HSE selected as system clock source CLK_SYSCLKSource_LSI: LSI selected as system clock source CLK_SYSCLKSource_LSE: LSE selected as system clock source

Return values:

None

Definition at line 410 of file stm8l15x_clk.c.

References CLK, and IS_CLK_SOURCE.

Enables or disables the clock switch execution.

Parameters:

NewState

: new state of clock switch, value accepted ENABLE, DISABLE.

Return values:

None

Definition at line 535 of file stm8l15x_clk.c.

References CLK, CLK_SWCR_SWEN, DISABLE, and IS_FUNCTIONAL_STATE.

Holds the different Master clock Divider factors

Definition at line 68 of file stm8l15x_clk.c.

Referenced by CLK_GetClockFreq().