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STM8L15x Standard Peripherals Drivers
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stm8l15x_clk.c
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00001 /** 00002 ****************************************************************************** 00003 * @file stm8l15x_clk.c 00004 * @author MCD Application Team 00005 * @version V1.5.0 00006 * @date 13-May-2011 00007 * @brief This file provides firmware functions to manage the following 00008 * functionalities of the clock controler (CLK) peripheral: 00009 * - Internal/external clocks, CSS and CCO configuration 00010 * - System clocks configuration 00011 * - Peripheral clocks configuration 00012 * - CSS on LSE configuration 00013 * - Low power clock configuration 00014 * - Interrupts and flags management 00015 * 00016 * @verbatim 00017 * 00018 * =================================================================== 00019 * CLK specific features 00020 * =================================================================== 00021 * 00022 * After reset the device is running from Internal High Speed oscillator 00023 * divided by 8 (HSI/8 = 2MHz) with all peripherals off. 00024 * - The clock for all peripherals is switched off, except for the BootROM 00025 * clock used for bootloader, in which case, the software should be properly 00026 * written to switch off that clock after the bootloader execution. 00027 * 00028 * Once the device starts from reset, the user application has to: 00029 * - Configure the clock source to be used to drive the System clock 00030 * (if the application needs higher frequency/performance) 00031 * - Configure the System clock frequency 00032 * - Enable the clock for the peripheral(s) to be used 00033 * - Configure the clock source(s) for peripherals which clocks are not 00034 * derived from the System clock (RTC/LCD, BEEP) 00035 * 00036 * @endverbatim 00037 * 00038 ****************************************************************************** 00039 * @attention 00040 * 00041 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 00042 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 00043 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 00044 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 00045 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 00046 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 00047 * 00048 * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> 00049 ****************************************************************************** 00050 */ 00051 00052 /* Includes ------------------------------------------------------------------*/ 00053 00054 #include "stm8l15x_clk.h" 00055 00056 /** @addtogroup STM8L15x_StdPeriph_Driver 00057 * @{ 00058 */ 00059 00060 /** @defgroup CLK 00061 * @brief CLK driver modules 00062 * @{ 00063 */ 00064 /* Private typedef -----------------------------------------------------------*/ 00065 /* Private macro -------------------------------------------------------------*/ 00066 /* Private Variables ---------------------------------------------------------*/ 00067 /* Private Constant ---------------------------------------------------------*/ 00068 CONST uint8_t SYSDivFactor[5] = {1, 2, 4, 8, 16}; /*!< Holds the different Master clock Divider factors */ 00069 /* Private function prototypes -----------------------------------------------*/ 00070 /* Private functions ---------------------------------------------------------*/ 00071 00072 /** @defgroup CLK_Private_Functions 00073 * @{ 00074 */ 00075 00076 /** @defgroup CLK_Group1 Internal and external clocks, CSS and CCO configuration functions 00077 * @brief Internal and external clocks, CSS and CCO configuration functions 00078 * 00079 @verbatim 00080 =============================================================================== 00081 Internal/external clocks, CSS and CCO configuration functions 00082 =============================================================================== 00083 00084 This section provides functions allowing to configure the internal/external clocks, 00085 CSS and CCO pins. 00086 00087 1. HSI (high-speed internal), 16 MHz factory-trimmed RC used directly as System 00088 clock source. 00089 00090 2. LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC 00091 and/or BEEP clock source. 00092 00093 3. HSE (high-speed external), 1 to 16 MHz crystal oscillator used directly as 00094 System clock source. Can be used also as RTC/LCD clock source. 00095 00096 4. LSE (low-speed external), 32 KHz oscillator used as RTC/LCD and/or BEEP clock source. 00097 00098 5. CSS (Clock security system), once enabled and if a HSE clock failure occurs 00099 (HSE used as System clock source), the System clock is automatically switched 00100 to HSI and an interrupt is generated if enabled. 00101 00102 6. CCO (configurable clock output), used to output HSI, LSE, HSE, HSI, LSI 00103 clock (through a configurable prescaler) on PC4 pin. 00104 00105 @endverbatim 00106 * @{ 00107 */ 00108 00109 /** 00110 * @brief Deinitializes the CLK peripheral registers to their default reset values. 00111 * @param None 00112 * @retval None 00113 */ 00114 void CLK_DeInit(void) 00115 { 00116 CLK->ICKCR = CLK_ICKCR_RESET_VALUE; 00117 CLK->ECKCR = CLK_ECKCR_RESET_VALUE; 00118 CLK->CRTCR = CLK_CRTCR_RESET_VALUE; 00119 CLK->CBEEPR = CLK_CBEEPR_RESET_VALUE; 00120 CLK->SWR = CLK_SWR_RESET_VALUE; 00121 CLK->SWCR = CLK_SWCR_RESET_VALUE; 00122 CLK->CKDIVR = CLK_CKDIVR_RESET_VALUE; 00123 CLK->PCKENR1 = CLK_PCKENR1_RESET_VALUE; 00124 CLK->PCKENR2 = CLK_PCKENR2_RESET_VALUE; 00125 CLK->PCKENR3 = CLK_PCKENR3_RESET_VALUE; 00126 CLK->CSSR = CLK_CSSR_RESET_VALUE; 00127 CLK->CCOR = CLK_CCOR_RESET_VALUE; 00128 CLK->HSITRIMR = CLK_HSITRIMR_RESET_VALUE; 00129 CLK->HSICALR = CLK_HSICALR_RESET_VALUE; 00130 CLK->HSIUNLCKR = CLK_HSIUNLCKR_RESET_VALUE; 00131 CLK->REGCSR = CLK_REGCSR_RESET_VALUE; 00132 } 00133 00134 /** 00135 * @brief Enables or disables the Internal High Speed oscillator (HSI). 00136 * @note The HSI is stopped by hardware when entering Halt and active Halt modes. 00137 * It is used (enabled by hardware) as system clock source after startup 00138 * from Reset, wakeup from Halt and active Halt mode when the FHWU bit is 00139 * set in the ICKCR register, or in case of HSE failure used as system clock 00140 * (if the Clock Security System CSS is enabled). 00141 * @note HSI can not be stopped if it is used as active CCO source, as active 00142 * RTC clock, if the safe oscillator (AUX) is enabled or as system clock source, 00143 * In this case, you have to select another source of the system clock 00144 * then stop the HSI. 00145 * @note After enabling the HSI, the application software should wait on HSIRDY 00146 * flag to be set indicating that HSI clock is stable and can be used as 00147 * system clock source. 00148 * @param NewState: new state of the HSI. 00149 * This parameter can be: ENABLE or DISABLE. 00150 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator 00151 * clock cycles. 00152 * @retval None 00153 */ 00154 void CLK_HSICmd(FunctionalState NewState) 00155 { 00156 /* Check the parameters */ 00157 assert_param(IS_FUNCTIONAL_STATE(NewState)); 00158 00159 if (NewState != DISABLE) 00160 { 00161 /* Set HSION bit */ 00162 CLK->ICKCR |= CLK_ICKCR_HSION; 00163 } 00164 else 00165 { 00166 /* Reset HSION bit */ 00167 CLK->ICKCR &= (uint8_t)(~CLK_ICKCR_HSION); 00168 } 00169 } 00170 00171 /** 00172 * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. 00173 * @note The calibration is used to compensate for the variations in voltage 00174 * and temperature that influence the frequency of the internal HSI RC. 00175 * @param CLK_HSICalibrationValue : calibration trimming value. 00176 * This parameter must be a number between [(HSICALR regiter value) -12] 00177 * and [(HSICALR regiter value) + 8 ] 00178 * @note Once HSITRIMR register configured, its value is used instead of the HSICALR 00179 * register values. 00180 * @retval None 00181 */ 00182 void CLK_AdjustHSICalibrationValue(uint8_t CLK_HSICalibrationValue) 00183 { 00184 /* two consecutive write access to HSIUNLCKR register to unlock HSITRIMR */ 00185 CLK->HSIUNLCKR = 0xAC; 00186 CLK->HSIUNLCKR = 0x35; 00187 00188 /* Store the new value */ 00189 CLK->HSITRIMR = (uint8_t)CLK_HSICalibrationValue; 00190 } 00191 00192 /** 00193 * @brief Enables or disables the Internal Low Speed oscillator (LSI). 00194 * @note After enabling the LSI, the application software should wait on 00195 * LSIRDY flag to be set indicating that LSI clock is stable and can 00196 * be used to clock the IWDG and/or the RTC. 00197 * @note LSI can not be disabled if used as system clock source, as active CCO 00198 * source, as BEEP clock source while BEEPAHALT bit is set or, as RTC active 00199 * clock source. 00200 * @param NewState: new state of the LSI. 00201 * This parameter can be: ENABLE or DISABLE. 00202 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator 00203 * clock cycles. 00204 * @retval None 00205 */ 00206 void CLK_LSICmd(FunctionalState NewState) 00207 { 00208 00209 /* Check the parameters */ 00210 assert_param(IS_FUNCTIONAL_STATE(NewState)); 00211 00212 if (NewState != DISABLE) 00213 { 00214 /* Set LSION bit */ 00215 CLK->ICKCR |= CLK_ICKCR_LSION; 00216 } 00217 else 00218 { 00219 /* Reset LSION bit */ 00220 CLK->ICKCR &= (uint8_t)(~CLK_ICKCR_LSION); 00221 } 00222 } 00223 00224 /** 00225 * @brief Configures the External High Speed oscillator (HSE). 00226 * @note After enabling the HSE (CLK_HSE_ON or CLK_HSE_Bypass), the application 00227 * software should wait on HSERDY flag to be set indicating that HSE clock 00228 * is stable and can be used to clock the system. 00229 * @note HSE state can not be changed if it is used as system clock. In this case, 00230 * you have to select another source of the system clock then change 00231 * the HSE state (ex. disable it). 00232 * @note The HSE is stopped by hardware when entering HALT and active HALT modes. 00233 * @param CLK_HSE: specifies the new state of the HSE. 00234 * This parameter can be one of the following values: 00235 * @arg CLK_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after 00236 * 6 HSE oscillator clock cycles. 00237 * @arg CLK_HSE_ON: turn ON the HSE oscillator 00238 * @arg CLK_HSE_Bypass: HSE oscillator bypassed with external clock 00239 * @note In case of Enabling HSE Bypass make sure that the HSE clock source is 00240 * not used by the RTC, output or involved in a switching operation. 00241 * @retval None 00242 */ 00243 void CLK_HSEConfig(CLK_HSE_TypeDef CLK_HSE) 00244 { 00245 /* Check the parameters */ 00246 assert_param(IS_CLK_HSE(CLK_HSE)); 00247 00248 /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/ 00249 /* Reset HSEON bit */ 00250 CLK->ECKCR &= (uint8_t)~CLK_ECKCR_HSEON; 00251 00252 /* Reset HSEBYP bit */ 00253 CLK->ECKCR &= (uint8_t)~CLK_ECKCR_HSEBYP; 00254 00255 /* Configure HSE */ 00256 CLK->ECKCR |= (uint8_t)CLK_HSE; 00257 } 00258 00259 /** 00260 * @brief Configures the External Low Speed oscillator (LSE). 00261 * @note After enabling the LSE (CLK_LSE_ON or CLK_LSE_Bypass), the application 00262 * software should wait on LSERDY flag to be set indicating that LSE clock 00263 * is stable and can be used to clock the RTC. 00264 * @param CLK_LSE: specifies the new state of the LSE. 00265 * This parameter can be one of the following values: 00266 * @arg CLK_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after 00267 * 6 LSE oscillator clock cycles. 00268 * @arg CLK_LSE_ON: turn ON the LSE oscillator 00269 * @arg CLK_LSE_Bypass: LSE oscillator bypassed with external clock 00270 * @note In case of Enabling LSE Bypass make sure that the LSE clock source is 00271 * not used by the RTC, output or involved in a switching operation. 00272 * @retval None 00273 */ 00274 void CLK_LSEConfig(CLK_LSE_TypeDef CLK_LSE) 00275 { 00276 /* Check the parameters */ 00277 assert_param(IS_CLK_LSE(CLK_LSE)); 00278 00279 /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/ 00280 /* Reset LSEON bit */ 00281 CLK->ECKCR &= (uint8_t)~CLK_ECKCR_LSEON; 00282 00283 /* Reset LSEBYP bit */ 00284 CLK->ECKCR &= (uint8_t)~CLK_ECKCR_LSEBYP; 00285 00286 /* Configure LSE */ 00287 CLK->ECKCR |= (uint8_t)CLK_LSE; 00288 00289 } 00290 00291 /** 00292 * @brief Enables the Clock Security System. 00293 * @note If a failure is detected on the HSE oscillator clock, this oscillator 00294 * is automatically disabled and an interrupt is generated to inform the 00295 * software about the failure allowing the MCU to perform rescue operations. 00296 * @note Once CSS is enabled it cannot be disabled until the next reset. 00297 * @param None 00298 * @retval None 00299 */ 00300 void CLK_ClockSecuritySystemEnable(void) 00301 { 00302 /* Set CSSEN bit */ 00303 CLK->CSSR |= CLK_CSSR_CSSEN; 00304 } 00305 00306 /** 00307 * @brief Enables the Clock Security System deglitcher system. 00308 * @param None 00309 * @retval None 00310 */ 00311 void CLK_ClockSecuritySytemDeglitchCmd(FunctionalState NewState) 00312 { 00313 /* Check the parameters */ 00314 assert_param(IS_FUNCTIONAL_STATE(NewState)); 00315 00316 if (NewState != DISABLE) 00317 { 00318 /* Set CSSDGON bit */ 00319 CLK->CSSR |= CLK_CSSR_CSSDGON; 00320 } 00321 else 00322 { 00323 /* Reset CSSDGON bit */ 00324 CLK->CSSR &= (uint8_t)(~CLK_CSSR_CSSDGON); 00325 } 00326 } 00327 00328 /** 00329 * @brief Selects the clock source to output on CCO pin(PC4). 00330 * @note PC4 should be configured output push-pull with the speed that matches 00331 * maximum output speed of the desired clock. 00332 * @param CLK_CCOSource: specifies the clock source to output. 00333 * This parameter can be one of the following values: 00334 * @arg CLK_CCOSource_Off: No clock selected as CCO source 00335 * @arg CLK_CCOSource_HSI: HSI clock selected as CCO source 00336 * @arg CLK_CCOSource_LSI: LSI clock selected as CCO source 00337 * @arg CLK_CCOSource_LSE: LSE clock selected as CCO source 00338 * @arg CLK_CCOSource_HSE: HSE clock selected as CCO source 00339 * @param CLK_CCODiv: specifies the CCO prescaler. 00340 * This parameter can be one of the following values: 00341 * @arg CLK_CCODiv_1: no division applied to CCO clock 00342 * @arg CLK_CCODiv_2: division by 2 applied to CCO clock 00343 * @arg CLK_CCODiv_4: division by 4 applied to CCO clock 00344 * @arg CLK_CCODiv_8: division by 8 applied to CCO clock 00345 * @arg CLK_CCODiv_16: division by 16 applied to CCO clock 00346 * @arg CLK_CCODiv_32: division by 32 applied to CCO clock 00347 * @arg CLK_CCODiv_64: division by 64 applied to CCO clock 00348 * @retval None 00349 */ 00350 void CLK_CCOConfig(CLK_CCOSource_TypeDef CLK_CCOSource, CLK_CCODiv_TypeDef CLK_CCODiv) 00351 { 00352 /* check teh parameters */ 00353 assert_param(IS_CLK_OUTPUT(CLK_CCOSource)); 00354 assert_param(IS_CLK_OUTPUT_DIVIDER(CLK_CCODiv)); 00355 00356 /* Selects the source provided on cco_ck output and its divider*/ 00357 CLK->CCOR = (uint8_t)((uint8_t)CLK_CCOSource | (uint8_t)CLK_CCODiv); 00358 } 00359 00360 /** 00361 * @} 00362 */ 00363 00364 /** @defgroup CLK_Group2 System clock configuration functions 00365 * @brief System clock configuration functions 00366 * 00367 @verbatim 00368 =============================================================================== 00369 System clock configuration functions 00370 =============================================================================== 00371 00372 This section provides functions allowing to configure the System clock. 00373 00374 1. Several clock sources can be used to drive the System clock (SYSCLK): HSI, 00375 HSE, LSI and LSE. 00376 You can use "CLK_GetClocksFreq()" function to retrieve the frequencies of these clocks. 00377 00378 @note All the peripheral clocks are derived from the System clock (SYSCLK) except: 00379 - BEEP: the Beeper clock can be derived either from a LSE or LSI clock sources. 00380 You have to use CLK_BEEPClockConfig() function to configure this clock. 00381 - RTC: the RTC clock can be derived either from the LSI, LSE, HSI or HSE clock 00382 divided by 1 to 64. You have to use CLK_RTCClockConfig() functions to 00383 configure this clock. 00384 - LCD : LCD clock is the RTC Clock divided by 2. 00385 - IWDG clock which is always the LSI clock. 00386 00387 2. The maximum frequency of the SYSCLK is 16 MHz. 00388 00389 @endverbatim 00390 * @{ 00391 */ 00392 00393 /** 00394 * @brief Configures the system clock (SYSCLK). 00395 * @note The HSI is used (enabled by hardware) as system clock source after 00396 * startup from Reset, wake-up from Halt and active Halt modes, or in case 00397 * of failure of the HSE used as system clock (if the Clock Security System CSS is enabled). 00398 * @note A switch from one clock source to another occurs only if the target 00399 * clock source is ready (clock stable after startup delay or PLL locked). 00400 * You can use CLK_GetSYSCLKSource() function to know which clock is 00401 * currently used as system clock source. 00402 * @param CLK_SYSCLKSource: specifies the clock source used as system clock. 00403 * This parameter can be one of the following values: 00404 * @arg CLK_SYSCLKSource_HSI: HSI selected as system clock source 00405 * @arg CLK_SYSCLKSource_HSE: HSE selected as system clock source 00406 * @arg CLK_SYSCLKSource_LSI: LSI selected as system clock source 00407 * @arg CLK_SYSCLKSource_LSE: LSE selected as system clock source 00408 * @retval None 00409 */ 00410 void CLK_SYSCLKSourceConfig(CLK_SYSCLKSource_TypeDef CLK_SYSCLKSource) 00411 { 00412 /* check teh parameters */ 00413 assert_param(IS_CLK_SOURCE(CLK_SYSCLKSource)); 00414 00415 /* Selection of the target clock source */ 00416 CLK->SWR = (uint8_t)CLK_SYSCLKSource; 00417 } 00418 00419 /** 00420 * @brief Returns the clock source used as system clock. 00421 * @param None 00422 * @retval Clock used as System clock (SYSCLK) source. 00423 * The returned value can be one of the following: 00424 * - CLK_SYSCLKSource_HSI: HSI used as system clock 00425 * - CLK_SYSCLKSource_LSI: LSI used as system clock 00426 * - CLK_SYSCLKSource_HSE: HSE used as system clock 00427 * - CLK_SYSCLKSource_LSE: LSE used as system clock 00428 */ 00429 CLK_SYSCLKSource_TypeDef CLK_GetSYSCLKSource(void) 00430 { 00431 return ((CLK_SYSCLKSource_TypeDef)(CLK->SCSR)); 00432 } 00433 00434 /** 00435 * @brief Returns the frequencies of different the SYSCLK 00436 * 00437 * @note The system frequency computed by this function is not the real 00438 * frequency in the chip. It is calculated based on the predefined 00439 * constant and the selected clock source: 00440 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) 00441 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**) 00442 * @note If SYSCLK source is LSE, function returns values based on LSE_VALUE(***) 00443 * @note If SYSCLK source is LSI, function returns values based on LSI_VALUE(****) 00444 * @note (*) HSI_VALUE is a constant defined in stm8l15x.h file (default value 00445 * 16 MHz) but the real value may vary depending on the variations 00446 * in voltage and temperature. 00447 * @note (**) HSE_VALUE is a constant defined in stm8l15x.h file (default value 00448 * 16 MHz), user has to ensure that HSE_VALUE is same as the real 00449 * frequency of the crystal used. Otherwise, this function may 00450 * have wrong result. 00451 * @note (***) LSI_VALUE is a constant defined in stm8l15x.h file (default value 00452 * 38 KHz) but the real value may vary depending on the variations 00453 * in voltage and temperature. 00454 * @note (****) LSE_VALUE is a constant defined in stm8l15x.h file (default value 00455 * 32,768 KHz), user has to ensure that LSE_VALUE is same as the real 00456 * frequency of the crystal used. Otherwise, this function may 00457 * have wrong result. 00458 * 00459 * @note The result of this function could be not correct when using fractional 00460 * value for HSE crystal. 00461 * 00462 * @param None 00463 * 00464 * @note This function can be used by the user application to compute the 00465 * baudrate for the communication peripherals or configure other parameters. 00466 * @note Each time SYSCLK clock changes, this function must be called to update 00467 * the returned value. Otherwise, any configuration based on this 00468 * function will be incorrect. 00469 * 00470 * @retval System Clock frequency value 00471 */ 00472 uint32_t CLK_GetClockFreq(void) 00473 { 00474 uint32_t clockfrequency = 0; 00475 uint32_t sourcefrequency = 0; 00476 CLK_SYSCLKSource_TypeDef clocksource = CLK_SYSCLKSource_HSI; 00477 uint8_t tmp = 0, presc = 0; 00478 00479 /* Get SYSCLK source. */ 00480 clocksource = (CLK_SYSCLKSource_TypeDef)CLK->SCSR; 00481 00482 if ( clocksource == CLK_SYSCLKSource_HSI) 00483 { 00484 sourcefrequency = HSI_VALUE; 00485 } 00486 else if ( clocksource == CLK_SYSCLKSource_LSI) 00487 { 00488 sourcefrequency = LSI_VALUE; 00489 } 00490 else if ( clocksource == CLK_SYSCLKSource_HSE) 00491 { 00492 sourcefrequency = HSE_VALUE; 00493 } 00494 else 00495 { 00496 clockfrequency = LSE_VALUE; 00497 } 00498 00499 /* Get System clock divider factor*/ 00500 tmp = (uint8_t)(CLK->CKDIVR & CLK_CKDIVR_CKM); 00501 presc = SYSDivFactor[tmp]; 00502 00503 /* Get System clock clcok frequency */ 00504 clockfrequency = sourcefrequency / presc; 00505 00506 return((uint32_t)clockfrequency); 00507 } 00508 00509 /** 00510 * @brief Configures the System clock (SYSCLK) dividers. 00511 * @param CLK_SYSCLKDiv : Specifies the system clock divider to apply. 00512 * This parameter can be one of the following values: 00513 * @arg CLK_SYSCLKDiv_1 00514 * @arg CLK_SYSCLKDiv_2 00515 * @arg CLK_SYSCLKDiv_4 00516 * @arg CLK_SYSCLKDiv_8 00517 * @arg CLK_SYSCLKDiv_16 00518 * @arg CLK_SYSCLKDiv_64 00519 * @arg CLK_SYSCLKDiv_128 00520 * @retval None 00521 */ 00522 void CLK_SYSCLKDivConfig(CLK_SYSCLKDiv_TypeDef CLK_SYSCLKDiv) 00523 { 00524 /* check the parameters */ 00525 assert_param(IS_CLK_SYSTEM_DIVIDER(CLK_SYSCLKDiv)); 00526 00527 CLK->CKDIVR = (uint8_t)(CLK_SYSCLKDiv); 00528 } 00529 00530 /** 00531 * @brief Enables or disables the clock switch execution. 00532 * @param NewState : new state of clock switch, value accepted ENABLE, DISABLE. 00533 * @retval None 00534 */ 00535 void CLK_SYSCLKSourceSwitchCmd(FunctionalState NewState) 00536 { 00537 /* Check the parameters */ 00538 assert_param(IS_FUNCTIONAL_STATE(NewState)); 00539 00540 if (NewState != DISABLE) 00541 { 00542 /* Set SWEN bit */ 00543 CLK->SWCR |= CLK_SWCR_SWEN; 00544 } 00545 else 00546 { 00547 /* Reset SWEN bit */ 00548 CLK->SWCR &= (uint8_t)(~CLK_SWCR_SWEN); 00549 } 00550 } 00551 00552 /** 00553 * @} 00554 */ 00555 00556 /** @defgroup CLK_Group3 Peripheral clocks configuration functions 00557 * @brief Peripheral clocks configuration functions 00558 * 00559 @verbatim 00560 =============================================================================== 00561 Peripheral clocks configuration functions 00562 =============================================================================== 00563 00564 This section provides functions allowing to configure the Peripheral clocks. 00565 00566 1. The RTC clock which is derived from the LSI, LSE, HSI or HSE clock divided by 1 to 64. 00567 00568 2. The BEEP clock which is derived from the LSI or LSE clocks. 00569 00570 3. After restart from Reset or wakeup from HALT, all peripherals are off 00571 Before to start using a peripheral you have to enable its interface clock. 00572 You can do this using CLK_AHBPeriphClockCmd() 00573 , CLK_APB2PeriphClockCmd() and CLK_APB1PeriphClockCmd() functions. 00574 00575 4. To reset the peripherals configuration (to the default state after device reset) 00576 you can use CLK_PeripheralClockConfig() function. 00577 00578 @endverbatim 00579 * @{ 00580 */ 00581 00582 /** 00583 * @brief Configures the RTC clock (RTCCLK). 00584 * @param CLK_RTCCLKSource: specifies the RTC clock source. 00585 * This parameter can be one of the following values: 00586 * @arg CLK_RTCCLKSource_Off: RTC clock Off 00587 * @arg CLK_RTCCLKSource_LSE: LSE selected as RTC clock 00588 * @arg CLK_RTCCLKSource_LSI: LSI selected as RTC clock 00589 * @arg CLK_RTCCLKSource_HSE: HSE selected as RTC clock 00590 * @arg CLK_RTCCLKSource_HSI: HSI selected as RTC clock 00591 * 00592 * @param CLK_RTCCLKDiv: specifies the RTC clock source divider. 00593 * This parameter can be one of the following values: 00594 * @arg CLK_RTCCLKDiv_1: Clock RTC Div 1 00595 * @arg CLK_RTCCLKDiv_2: Clock RTC Div 2 00596 * @arg CLK_RTCCLKDiv_4: Clock RTC Div 4 00597 * @arg CLK_RTCCLKDiv_8: Clock RTC Div 8 00598 * @arg CLK_RTCCLKDiv_16: Clock RTC Div 16 00599 * @arg CLK_RTCCLKDiv_32: Clock RTC Div 32 00600 * @arg CLK_RTCCLKDiv_64: Clock RTC Div 64 00601 * 00602 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to 00603 * work in HALT and Active HALT modes, and can be used as wakeup source. 00604 * However, when the HSE clock is used as RTC clock source. 00605 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE/HSI as 00606 * RTC clock source). 00607 * 00608 * @retval None 00609 */ 00610 void CLK_RTCClockConfig(CLK_RTCCLKSource_TypeDef CLK_RTCCLKSource, CLK_RTCCLKDiv_TypeDef CLK_RTCCLKDiv) 00611 { 00612 /* check the parameters */ 00613 assert_param(IS_CLK_CLOCK_RTC(CLK_RTCCLKSource)); 00614 assert_param(IS_CLK_CLOCK_RTC_DIV(CLK_RTCCLKDiv)); 00615 00616 /* Selects the source provided on to RTC and its divider*/ 00617 CLK->CRTCR = (uint8_t)((uint8_t)CLK_RTCCLKSource | (uint8_t)CLK_RTCCLKDiv); 00618 } 00619 00620 /** 00621 * @brief Configures the BEEP clock (BEEPCLK). 00622 * @param CLK_BEEPCLKSource: specifies the BEEP clock source. 00623 * This parameter can be one of the following values: 00624 * @arg CLK_BEEPCLKSource_Off: BEEP clock Off 00625 * @arg CLK_BEEPCLKSource_LSE: LSE selected as BEEP clock 00626 * @arg CLK_BEEPCLKSource_LSI: LSI selected as BEEP clock 00627 * @retval None 00628 */ 00629 void CLK_BEEPClockConfig(CLK_BEEPCLKSource_TypeDef CLK_BEEPCLKSource) 00630 { 00631 /* check the parameters */ 00632 assert_param(IS_CLK_CLOCK_BEEP(CLK_BEEPCLKSource)); 00633 00634 /* Selects the source provided to BEEP*/ 00635 CLK->CBEEPR = (uint8_t)(CLK_BEEPCLKSource); 00636 00637 } 00638 00639 /** 00640 * @brief Enables or disables the specified peripheral clock. 00641 * @note After reset, the peripheral clock (used for registers read/write access) 00642 * is disabled and the application software has to enable this clock before 00643 * using it. 00644 * @param CLK_Peripheral: specifies the peripheral to gate its clock. 00645 * This parameter can be any combination of the following values: 00646 * @arg CLK_Peripheral_TIM2: TIM2 clock 00647 * @arg CLK_Peripheral_TIM3: TIM3 clock 00648 * @arg CLK_Peripheral_TIM4: TIM4 clock 00649 * @arg CLK_Peripheral_I2C1: I2C1 clock 00650 * @arg CLK_Peripheral_SPI1: SPI1 clock 00651 * @arg CLK_Peripheral_USART1: USART1 clock 00652 * @arg CLK_Peripheral_BEEP: BEEP clock 00653 * @arg CLK_Peripheral_DAC: DAC clock 00654 * @arg CLK_Peripheral_ADC1: ADC1 clock 00655 * @arg CLK_Peripheral_TIM1: TIM1 clock 00656 * @arg CLK_Peripheral_RTC: RTC clock 00657 * @arg CLK_Peripheral_LCD: LCD clock 00658 * @arg CLK_Peripheral_DMA1: DMA1 clock 00659 * @arg CLK_Peripheral_COMP: COMP clock 00660 * @arg CLK_Peripheral_BOOTROM: BOOTROM clock 00661 * @arg CLK_Peripheral_AES: AES clock 00662 * @arg CLK_Peripheral_TIM5: TIM5 clock 00663 * @arg CLK_Peripheral_SPI2: SPI2 clock 00664 * @arg CLK_Peripheral_USART2: USART2 clock 00665 * @arg CLK_Peripheral_USART3: USART3 clock 00666 * @arg CLK_Peripheral_CSSLSE: CSS on LSE clock 00667 * @param NewState: new state of the specified peripheral clock. 00668 * This parameter can be: ENABLE or DISABLE. 00669 * @retval None 00670 */ 00671 void CLK_PeripheralClockConfig(CLK_Peripheral_TypeDef CLK_Peripheral, FunctionalState NewState) 00672 { 00673 uint8_t reg = 0; 00674 00675 /* Check the parameters */ 00676 assert_param(IS_CLK_PERIPHERAL(CLK_Peripheral)); 00677 assert_param(IS_FUNCTIONAL_STATE(NewState)); 00678 00679 /* get flag register */ 00680 reg = (uint8_t)((uint8_t)CLK_Peripheral & (uint8_t)0xF0); 00681 00682 if ( reg == 0x00) 00683 { 00684 if (NewState != DISABLE) 00685 { 00686 /* Enable the peripheral Clock */ 00687 CLK->PCKENR1 |= (uint8_t)((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F)); 00688 } 00689 else 00690 { 00691 /* Disable the peripheral Clock */ 00692 CLK->PCKENR1 &= (uint8_t)(~(uint8_t)(((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F)))); 00693 } 00694 } 00695 else if (reg == 0x10) 00696 { 00697 if (NewState != DISABLE) 00698 { 00699 /* Enable the peripheral Clock */ 00700 CLK->PCKENR2 |= (uint8_t)((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F)); 00701 } 00702 else 00703 { 00704 /* Disable the peripheral Clock */ 00705 CLK->PCKENR2 &= (uint8_t)(~(uint8_t)(((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F)))); 00706 } 00707 } 00708 else 00709 { 00710 if (NewState != DISABLE) 00711 { 00712 /* Enable the peripheral Clock */ 00713 CLK->PCKENR3 |= (uint8_t)((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F)); 00714 } 00715 else 00716 { 00717 /* Disable the peripheral Clock */ 00718 CLK->PCKENR3 &= (uint8_t)(~(uint8_t)(((uint8_t)1 << ((uint8_t)CLK_Peripheral & (uint8_t)0x0F)))); 00719 } 00720 } 00721 } 00722 00723 /** 00724 * @} 00725 */ 00726 00727 /** @defgroup CLK_Group4 CSS on LSE configuration functions 00728 * @brief CSS on LSE configuration functions 00729 * 00730 @verbatim 00731 =============================================================================== 00732 CSS on LSE configuration functions 00733 =============================================================================== 00734 00735 This section provides functions allowing to configure the CSS on LSE capability. 00736 00737 1. The LSE crystal clock source failures can be monitored when used as RTC clock 00738 by the mean of the LSI oscillator. 00739 00740 2. The CSS on LSE is a feature implemented externally to RTC peripheral and though 00741 has no impact the clock controller registers. 00742 00743 3. To enable the CSS on LSE you can use CLK_LSEClockSecuritySystemEnable() function 00744 00745 4. To configure the action to perform at RTC clock failure you can use 00746 CLK_RTCCLKSwitchOnLSEFailureEnable() function that allows to switch the RTC clock 00747 from LSE to LSI. 00748 00749 @endverbatim 00750 * @{ 00751 */ 00752 00753 /** 00754 * @brief Enables the clock CSS on LSE. 00755 * @note Once Enabled, only POR can Disable it. 00756 * @param None 00757 * @retval None 00758 */ 00759 void CLK_LSEClockSecuritySystemEnable(void) 00760 { 00761 /* Set CSSEN bit */ 00762 CSSLSE->CSR |= CSSLSE_CSR_CSSEN; 00763 } 00764 00765 /** 00766 * @brief Enables RTC clock switch to LSI in case of LSE failure. 00767 * @note Once Enabled, only POR can Disable it. 00768 * @param None 00769 * @retval None 00770 */ 00771 void CLK_RTCCLKSwitchOnLSEFailureEnable(void) 00772 { 00773 /* Set SWITCHEN bit */ 00774 CSSLSE->CSR |= CSSLSE_CSR_SWITCHEN; 00775 } 00776 00777 /** 00778 * @} 00779 */ 00780 00781 /** @defgroup CLK_Group5 Low power clock configuration functions 00782 * @brief Low power clock configuration functions 00783 * 00784 @verbatim 00785 =============================================================================== 00786 Low power clock configuration functions 00787 =============================================================================== 00788 00789 @endverbatim 00790 * @{ 00791 */ 00792 00793 /** 00794 * @brief Configures clock during halt and active halt modes. 00795 * @param CLK_Halt : Specifies the clock state and wake-up mode from halt way. 00796 * This parameter can be a value of @ref CLK_Halt_TypeDef. 00797 * @param NewState : Specifies the System clock (SYSCLK) state in active halt mode. 00798 * This parameter can be ENABLE or DISABLE. 00799 * @retval None 00800 */ 00801 void CLK_HaltConfig(CLK_Halt_TypeDef CLK_Halt, FunctionalState NewState) 00802 { 00803 /* check the parameters */ 00804 assert_param(IS_CLK_HALT(CLK_Halt)); 00805 assert_param(IS_FUNCTIONAL_STATE(NewState)); 00806 00807 if (NewState != DISABLE) 00808 { 00809 CLK->ICKCR |= (uint8_t)(CLK_Halt); 00810 } 00811 else 00812 { 00813 CLK->ICKCR &= (uint8_t)(~CLK_Halt); 00814 } 00815 } 00816 00817 /** 00818 * @brief Configures the main voltage regulator 00819 * @param NewState: specifies the MVR state. 00820 * This parameter can be one of the following values: 00821 * - DISABLE: MVR disabled; 00822 * - ENABLE: MVR enabled. 00823 * @retval None 00824 */ 00825 void CLK_MainRegulatorCmd(FunctionalState NewState) 00826 { 00827 /* check the parameters */ 00828 assert_param(IS_FUNCTIONAL_STATE(NewState)); 00829 00830 if (NewState != DISABLE) 00831 { 00832 /* Reset REGUOFF bit */ 00833 CLK->REGCSR &= (uint8_t)(~CLK_REGCSR_REGOFF); 00834 } 00835 else 00836 { 00837 /* Set REGUOFF bit */ 00838 CLK->REGCSR |= CLK_REGCSR_REGOFF; 00839 } 00840 } 00841 00842 /** 00843 * @} 00844 */ 00845 00846 /** @defgroup CLK_Group6 Interrupts and flags management functions 00847 * @brief Interrupts and flags management functions 00848 * 00849 @verbatim 00850 =============================================================================== 00851 Interrupts and flags management functions 00852 =============================================================================== 00853 00854 @endverbatim 00855 * @{ 00856 */ 00857 00858 /** 00859 * @brief Enables or disables the specified CLK interrupts. 00860 * @param CLK_IT: specifies the CLK interrupt sources to be enabled or disabled. 00861 * This parameter can be any combination of the following values: 00862 * @arg CLK_IT_CSSD: Clock security system detection interrupt 00863 * @arg CLK_IT_SWIF: Clock switch interrupt 00864 * @arg CLK_IT_LSECSSF: LSE Clock security system detection interrupt 00865 * @param NewState: new state of the specified CLK interrupts. 00866 * This parameter can be: ENABLE or DISABLE. 00867 * @retval None 00868 */ 00869 void CLK_ITConfig(CLK_IT_TypeDef CLK_IT, FunctionalState NewState) 00870 { 00871 00872 /* check the parameters */ 00873 assert_param(IS_CLK_IT(CLK_IT)); 00874 assert_param(IS_FUNCTIONAL_STATE(NewState)); 00875 00876 if (NewState != DISABLE) 00877 { 00878 if (CLK_IT == CLK_IT_SWIF) 00879 { 00880 /* Enable the clock switch interrupt */ 00881 CLK->SWCR |= CLK_SWCR_SWIEN; 00882 } 00883 else if (CLK_IT == CLK_IT_LSECSSF) 00884 { 00885 /* Enable the CSS on LSE interrupt */ 00886 CSSLSE->CSR |= CSSLSE_CSR_CSSIE; 00887 } 00888 else 00889 { 00890 /* Enable the clock security system detection interrupt */ 00891 CLK->CSSR |= CLK_CSSR_CSSDIE; 00892 } 00893 } 00894 else /*(NewState == DISABLE)*/ 00895 { 00896 if (CLK_IT == CLK_IT_SWIF) 00897 { 00898 /* Disable the clock switch interrupt */ 00899 CLK->SWCR &= (uint8_t)(~CLK_SWCR_SWIEN); 00900 } 00901 else if (CLK_IT == CLK_IT_LSECSSF) 00902 { 00903 /* Disable the CSS on LSE interrupt */ 00904 CSSLSE->CSR &= (uint8_t)(~CSSLSE_CSR_CSSIE); 00905 } 00906 else 00907 { 00908 /* Disable the clock security system detection interrupt */ 00909 CLK->CSSR &= (uint8_t)(~CLK_CSSR_CSSDIE); 00910 } 00911 } 00912 } 00913 00914 /** 00915 * @brief Checks whether the specified CLK flag is set or not. 00916 * @param CLK_FLAG: specifies the flag to check. 00917 * This parameter can be one of the following values: 00918 * @arg CLK_FLAG_LSIRDY: LSI oscillator clock ready 00919 * @arg CLK_FLAG_HSIRDY: HSI oscillator clock ready 00920 * @arg CLK_FLAG_HSERDY: HSE oscillator clock ready 00921 * @arg CLK_FLAG_SWBSY: Switch busy 00922 * @arg CLK_FLAG_CSSD: Clock security system detection 00923 * @arg CLK_FLAG_AUX: Auxiliary oscillator connected to master clock 00924 * @arg CLK_FLAG_LSERDY: LSE oscillator clock ready 00925 * @arg CLK_FLAG_CCOBSY: Configurable clock output busy 00926 * @arg CLK_FLAG_RTCSWBSY: RTC clock busy in switch 00927 * @arg CLK_FLAG_EEREADY: Flash program memory and Data EEPROM ready 00928 * @arg CLK_FLAG_EEBUSY: Flash program memory and Data EEPROM busy 00929 * @arg CLK_FLAG_LSEPD: LSE power-down 00930 * @arg CLK_FLAG_LSIPD: LSI power-down 00931 * @arg CLK_FLAG_HSEPD: HSE power-down 00932 * @arg CLK_FLAG_HSIPD: HSI power-down 00933 * @arg CLK_FLAG_REGREADY: REGREADY 00934 * @arg CLK_FLAG_BEEPSWBSY: BEEP clock busy in switch 00935 * @arg CLK_FLAG_LSECSSF: CSS on LSE detection 00936 * @arg CLK_FLAG_RTCCLKSWF: RTCCLK switch completed on LSE failure 00937 * @retval The new state of CLK_FLAG (SET or RESET). 00938 */ 00939 FlagStatus CLK_GetFlagStatus(CLK_FLAG_TypeDef CLK_FLAG) 00940 { 00941 uint8_t reg = 0; 00942 uint8_t pos = 0; 00943 FlagStatus bitstatus = RESET; 00944 00945 /* check the parameters */ 00946 assert_param(IS_CLK_FLAGS(CLK_FLAG)); 00947 00948 /* get flag register */ 00949 reg = (uint8_t)((uint8_t)CLK_FLAG & (uint8_t)0xF0); 00950 00951 /* get flag position */ 00952 pos = (uint8_t)((uint8_t)CLK_FLAG & (uint8_t)0x0F); 00953 00954 if (reg == 0x00) /* The flag to check is in CRTC Rregister */ 00955 { 00956 reg = CLK->CRTCR; 00957 } 00958 else if (reg == 0x10) /* The flag to check is in ICKCR register */ 00959 { 00960 reg = CLK->ICKCR; 00961 } 00962 else if (reg == 0x20) /* The flag to check is in CCOR register */ 00963 { 00964 reg = CLK->CCOR; 00965 } 00966 else if (reg == 0x30) /* The flag to check is in ECKCR register */ 00967 { 00968 reg = CLK->ECKCR; 00969 } 00970 else if (reg == 0x40) /* The flag to check is in SWCR register */ 00971 { 00972 reg = CLK->SWCR; 00973 } 00974 else if (reg == 0x50) /* The flag to check is in CSSR register */ 00975 { 00976 reg = CLK->CSSR; 00977 } 00978 else if (reg == 0x70) /* The flag to check is in REGCSR register */ 00979 { 00980 reg = CLK->REGCSR; 00981 } 00982 else if (reg == 0x80) /* The flag to check is in CSSLSE_CSRregister */ 00983 { 00984 reg = CSSLSE->CSR; 00985 } 00986 else /* The flag to check is in CBEEPR register */ 00987 { 00988 reg = CLK->CBEEPR; 00989 } 00990 00991 00992 if ((reg & (uint8_t)((uint8_t)1 << (uint8_t)pos)) != (uint8_t)RESET) 00993 { 00994 bitstatus = SET; 00995 } 00996 else 00997 { 00998 bitstatus = RESET; 00999 } 01000 01001 /* Return the flag status */ 01002 return((FlagStatus)bitstatus); 01003 } 01004 01005 /** 01006 * @brief Clears the CSS LSE Flag. 01007 * @param None 01008 * @retval None 01009 */ 01010 void CLK_ClearFlag(void) 01011 { 01012 01013 /* Clear the clock security system on LSE detection Flag */ 01014 CSSLSE->CSR &= (uint8_t)(~CSSLSE_CSR_CSSF); 01015 } 01016 01017 /** 01018 * @brief Checks whether the specified CLK interrupt has occurred or not. 01019 * @param CLK_IT: specifies the CLK interrupt source to check. 01020 * This parameter can be one of the following values: 01021 * @arg CLK_IT_SWIF: LSI ready interrupt 01022 * @arg CLK_IT_LSECSSF: LSE ready interrupt 01023 * @arg CLK_IT_CSSD: HSI ready interrupt 01024 * @retval The new state of CLK_IT (SET or RESET). 01025 */ 01026 ITStatus CLK_GetITStatus(CLK_IT_TypeDef CLK_IT) 01027 { 01028 01029 ITStatus bitstatus = RESET; 01030 01031 /* check the parameters */ 01032 assert_param(IS_CLK_IT(CLK_IT)); 01033 01034 if (CLK_IT == CLK_IT_SWIF) 01035 { 01036 /* Check the status of the clock switch interrupt */ 01037 if ((CLK->SWCR & (uint8_t)CLK_IT) == (uint8_t)0x0C) 01038 { 01039 bitstatus = SET; 01040 } 01041 else 01042 { 01043 bitstatus = RESET; 01044 } 01045 } 01046 else if (CLK_IT == CLK_IT_LSECSSF) 01047 { 01048 /* Check the status of the clock security system on LSE interrupt */ 01049 if ((CSSLSE->CSR & (uint8_t)CLK_IT) == (uint8_t)0x0C) 01050 { 01051 bitstatus = SET; 01052 } 01053 else 01054 { 01055 bitstatus = RESET; 01056 } 01057 } 01058 else /* CLK_IT == CLK_IT_CSSD */ 01059 { 01060 /* Check the status of the security system detection interrupt */ 01061 if ((CLK->CSSR & (uint8_t)CLK_IT) == (uint8_t)0x0C) 01062 { 01063 bitstatus = SET; 01064 } 01065 else 01066 { 01067 bitstatus = RESET; 01068 } 01069 } 01070 01071 /* Return the CLK_IT status */ 01072 return bitstatus; 01073 } 01074 01075 /** 01076 * @brief Clears the CLK's interrupt pending bits. 01077 * @param CLK_IT: specifies the interrupt pending bit to clear. 01078 * This parameter can be any combination of the following values: 01079 * @arg CLK_IT_SWIF: Clock switch interrupt 01080 * @arg CLK_IT_LSECSSF: LSE Clock security system detection interrupt 01081 * @retval None 01082 */ 01083 void CLK_ClearITPendingBit(CLK_IT_TypeDef CLK_IT) 01084 { 01085 01086 /* check the parameters */ 01087 assert_param(IS_CLK_CLEAR_IT(CLK_IT)); 01088 01089 if ((uint8_t)((uint8_t)CLK_IT & (uint8_t)0xF0) == (uint8_t)0x20) 01090 { 01091 /* Clear the status of the clock security system on LSE interrupt */ 01092 CSSLSE->CSR &= (uint8_t)(~CSSLSE_CSR_CSSF); 01093 } 01094 else 01095 { 01096 /* Clear the status of the clock switch interrupt */ 01097 CLK->SWCR &= (uint8_t)(~CLK_SWCR_SWIF); 01098 } 01099 } 01100 01101 /** 01102 * @} 01103 */ 01104 01105 /** 01106 * @} 01107 */ 01108 01109 /** 01110 * @} 01111 */ 01112 01113 /** 01114 * @} 01115 */ 01116 01117 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/