This file contains all the peripheral register's definitions, bits definitions and memory mapping for STM8L15x devices. More...

#include "stm8l15x_conf.h" #include <intrinsics.h>

Data Structures
struct	ADC_struct
	Analog to Digital Converter (ADC) peripheral. More...
struct	AES_struct
	AES tiny (AES) More...
struct	BEEP_struct
	Beeper (BEEP) peripheral registers. More...
struct	CFG_struct
	Configuration Registers (CFG) More...
struct	CLK_struct
	Clock Controller (CLK) More...
struct	COMP_struct
	Comparator interface (COMP) More...
struct	CSSLSE_struct
	CSS on LSE registers. More...
struct	DAC_struct
	Digital to Analog Converter (DAC) peripheral. More...
struct	DMA_Channel_struct
struct	DMA_struct
	Direct-Memory Access (DMA) More...
struct	EXTI_struct
	External Interrupt Controller (EXTI) More...
struct	FLASH_struct
	FLASH and Data EEPROM. More...
struct	GPIO_struct
	General Purpose I/Os (GPIO) More...
struct	I2C_struct
	Inter-Integrated Circuit (I2C) More...
struct	IRTIM_struct
	IR digital interface (IRTIM) More...
struct	ITC_struct
	Interrupt Controller (ITC) More...
struct	IWDG_struct
	Internal Low Speed Watchdog (IWDG) More...
struct	LCD_struct
	LCD Controller (LCD) More...
struct	OPT_struct
	Option Bytes (OPT) More...
struct	PWR_struct
	Power Control (PWR) More...
struct	RI_struct
	Routing Interface (RI) More...
struct	RST_struct
	Reset Controller (RST) More...
struct	RTC_struct
	Real-Time Clock (RTC) peripheral registers. More...
struct	SPI_struct
	Serial Peripheral Interface (SPI) More...
struct	SYSCFG_struct
	SYSCFG. More...
struct	TIM1_struct
	Advanced 16 bit timer with complementary PWM outputs (TIM1) More...
struct	TIM4_struct
	8-bit system or Low End Small Timer (TIM4) More...
struct	TIM_struct
	16 bit timer :TIM2, TIM3 & TIM5 More...
struct	USART_struct
	USART. More...
struct	WFE_struct
struct	WWDG_struct
	Window Watchdog (WWDG) More...
Defines
#define	__CONST CONST
	Legacy definition.
#define	__I volatile const
	IO definitions.
#define	__IO volatile
#define	__O volatile
#define	__STM8L15X_STDPERIPH_VERSION
#define	__STM8L15X_STDPERIPH_VERSION_MAIN ((uint8_t)0x01)
#define	__STM8L15X_STDPERIPH_VERSION_RC ((uint8_t)0x00)
#define	__STM8L15X_STDPERIPH_VERSION_SUB1 ((uint8_t)0x05)
#define	__STM8L15X_STDPERIPH_VERSION_SUB2 ((uint8_t)0x00)
#define	ADC1 ((ADC_TypeDef *) ADC1_BASE)
#define	ADC1_BASE (uint16_t)0x5340
#define	ADC_CR1_ADON ((uint8_t)0x01)
#define	ADC_CR1_AWDIE ((uint8_t)0x10)
#define	ADC_CR1_CONT ((uint8_t)0x04)
#define	ADC_CR1_EOCIE ((uint8_t)0x08)
#define	ADC_CR1_OVERIE ((uint8_t)0x80)
#define	ADC_CR1_RES ((uint8_t)0x60)
#define	ADC_CR1_RESET_VALUE ((uint8_t) 0x00)
#define	ADC_CR1_START ((uint8_t)0x02)
#define	ADC_CR2_EXTSEL ((uint8_t)0x18)
#define	ADC_CR2_PRESC ((uint8_t)0x80)
#define	ADC_CR2_RESET_VALUE ((uint8_t) 0x00)
#define	ADC_CR2_SMPT1 ((uint8_t)0x07)
#define	ADC_CR2_TRIGEDGE ((uint8_t)0x60)
#define	ADC_CR3_CHSEL ((uint8_t)0x1F)
#define	ADC_CR3_RESET_VALUE ((uint8_t) 0x1F)
#define	ADC_CR3_SMPT2 ((uint8_t)0xE0)
#define	ADC_DRH_CONVDATA ((uint8_t)0x0F)
#define	ADC_DRH_RESET_VALUE ((uint8_t) 0x00)
#define	ADC_DRL_CONVDATA ((uint8_t)0xFF)
#define	ADC_DRL_RESET_VALUE ((uint8_t) 0x00)
#define	ADC_HTRH_HT ((uint8_t)0x0F)
#define	ADC_HTRH_RESET_VALUE ((uint8_t) 0x0F)
#define	ADC_HTRL_HT ((uint8_t)0xFF)
#define	ADC_HTRL_RESET_VALUE ((uint8_t) 0xFF)
#define	ADC_LTRH_LT ((uint8_t)0x0F)
#define	ADC_LTRH_RESET_VALUE ((uint8_t) 0x00)
#define	ADC_LTRL_LT ((uint8_t)0xFF)
#define	ADC_LTRL_RESET_VALUE ((uint8_t) 0x00)
#define	ADC_SQR1_CHSELS ((uint8_t)0x3F)
#define	ADC_SQR1_DMAOFF ((uint8_t)0x80)
#define	ADC_SQR1_RESET_VALUE ((uint8_t) 0x00)
#define	ADC_SQR2_CHSELS ((uint8_t)0xFF)
#define	ADC_SQR2_RESET_VALUE ((uint8_t) 0x00)
#define	ADC_SQR3_CHSELS ((uint8_t)0xFF)
#define	ADC_SQR3_RESET_VALUE ((uint8_t) 0x00)
#define	ADC_SQR4_CHSELS ((uint8_t)0xFF)
#define	ADC_SQR4_RESET_VALUE ((uint8_t) 0x00)
#define	ADC_SR_AWD ((uint8_t)0x02)
#define	ADC_SR_EOC ((uint8_t)0x01)
#define	ADC_SR_OVER ((uint8_t)0x04)
#define	ADC_SR_RESET_VALUE ((uint8_t) 0x00)
#define	ADC_TRIGR1_RESET_VALUE ((uint8_t) 0x00)
#define	ADC_TRIGR1_TRIG ((uint8_t)0x0F)
#define	ADC_TRIGR1_TSON ((uint8_t)0x20)
#define	ADC_TRIGR1_VREFINTON ((uint8_t)0x10)
#define	ADC_TRIGR2_RESET_VALUE ((uint8_t) 0x00)
#define	ADC_TRIGR2_TRIG ((uint8_t)0xFF)
#define	ADC_TRIGR3_RESET_VALUE ((uint8_t) 0x00)
#define	ADC_TRIGR3_TRIG ((uint8_t)0xFF)
#define	ADC_TRIGR4_RESET_VALUE ((uint8_t) 0x00)
#define	ADC_TRIGR4_TRIG ((uint8_t)0xFF)
#define	AES ((AES_TypeDef *) AES_BASE)
#define	AES_BASE (uint16_t)0x53D0
#define	AES_CR_CCFC ((uint8_t)0x08)
#define	AES_CR_CCIE ((uint8_t)0x20)
#define	AES_CR_DMAEN ((uint8_t)0x80)
#define	AES_CR_EN ((uint8_t)0x01)
#define	AES_CR_ERRC ((uint8_t)0x10)
#define	AES_CR_ERRIE ((uint8_t)0x40)
#define	AES_CR_MODE ((uint8_t)0x06)
#define	AES_CR_RESET_VALUE ((uint8_t)0x00)
#define	AES_DINR ((uint8_t)0xFF)
#define	AES_DINR_RESET_VALUE ((uint8_t)0x00)
#define	AES_DOUTR ((uint8_t)0xFF)
#define	AES_DOUTR_RESET_VALUE ((uint8_t)0x00)
#define	AES_SR_CCF ((uint8_t)0x01)
#define	AES_SR_RDERR ((uint8_t)0x02)
#define	AES_SR_RESET_VALUE ((uint8_t)0x00)
#define	AES_SR_WRERR ((uint8_t)0x04)
#define	AffBit(VAR, Place, Value)
#define	AREA 0x00
#define	BEEP ((BEEP_TypeDef *) BEEP_BASE)
#define	BEEP_BASE (uint16_t)0x50F0
#define	BEEP_CSR1_MSR ((uint8_t)0x01)
#define	BEEP_CSR1_RESET_VALUE ((uint8_t)0x00)
#define	BEEP_CSR2_BEEPDIV ((uint8_t)0x1F)
#define	BEEP_CSR2_BEEPEN ((uint8_t)0x20)
#define	BEEP_CSR2_BEEPSEL ((uint8_t)0xC0)
#define	BEEP_CSR2_RESET_VALUE ((uint8_t)0x1F)
#define	BitClr(BIT) ( ((unsigned char ) (AREA+(BIT)/8)) &= (~(1<<(7-(BIT)%8))) )
#define	BitSet(BIT) ( ((unsigned char ) (AREA+(BIT)/8)) \|= (1<<(7-(BIT)%8)) )
#define	BitVal(BIT) ( ((unsigned char ) (AREA+(BIT)/8)) & (1<<(7-(BIT)%8)) )
#define	BYTE_0(n) ((uint8_t)((n) & (uint8_t)0xFF))
#define	BYTE_1(n) ((uint8_t)(BYTE_0((n) >> (uint8_t)8)))
#define	BYTE_2(n) ((uint8_t)(BYTE_0((n) >> (uint8_t)16)))
#define	BYTE_3(n) ((uint8_t)(BYTE_0((n) >> (uint8_t)24)))
#define	CCMR_TIxDirect_Set ((uint8_t)0x01)
#define	CFG ((CFG_TypeDef *) CFG_BASE)
#define	CFG_BASE (uint16_t)0x7F60
#define	CFG_GCR_AL ((uint8_t)0x02)
#define	CFG_GCR_RESET_VALUE ((uint8_t)0x00)
#define	CFG_GCR_SWD ((uint8_t)0x01)
#define	ChgBit(VAR, Place) ( (VAR) ^= (uint8_t)((uint8_t)1<<(uint8_t)(Place)) )
#define	CLK ((CLK_TypeDef *) CLK_BASE)
#define	CLK_BASE (uint16_t)0x50C0
#define	CLK_CBEEPR_BEEPSWBSY ((uint8_t)0x01)
#define	CLK_CBEEPR_CLKBEEPSEL ((uint8_t)0x06)
#define	CLK_CBEEPR_RESET_VALUE ((uint8_t)0x00)
#define	CLK_CCOR_CCODIV ((uint8_t)0xE0)
#define	CLK_CCOR_CCOSEL ((uint8_t)0x1E)
#define	CLK_CCOR_CCOSWBSY ((uint8_t)0x01)
#define	CLK_CCOR_RESET_VALUE ((uint8_t)0x00)
#define	CLK_CKDIVR_CKM ((uint8_t)0x07)
#define	CLK_CKDIVR_RESET_VALUE ((uint8_t)0x03)
#define	CLK_CRTCR_RESET_VALUE ((uint8_t)0x00)
#define	CLK_CRTCR_RTCDIV ((uint8_t)0xE0)
#define	CLK_CRTCR_RTCSEL ((uint8_t)0x1E)
#define	CLK_CRTCR_RTCSWBSY ((uint8_t)0x01)
#define	CLK_CSSR_AUX ((uint8_t)0x02)
#define	CLK_CSSR_CSSD ((uint8_t)0x08)
#define	CLK_CSSR_CSSDGON ((uint8_t)0x10)
#define	CLK_CSSR_CSSDIE ((uint8_t)0x04)
#define	CLK_CSSR_CSSEN ((uint8_t)0x01)
#define	CLK_CSSR_RESET_VALUE ((uint8_t)0x00)
#define	CLK_ECKCR_HSEBYP ((uint8_t)0x10)
#define	CLK_ECKCR_HSEON ((uint8_t)0x01)
#define	CLK_ECKCR_HSERDY ((uint8_t)0x02)
#define	CLK_ECKCR_LSEBYP ((uint8_t)0x20)
#define	CLK_ECKCR_LSEON ((uint8_t)0x04)
#define	CLK_ECKCR_LSERDY ((uint8_t)0x08)
#define	CLK_ECKCR_RESET_VALUE ((uint8_t)0x00)
#define	CLK_HSICALR_HSICAL ((uint8_t)0xFF)
#define	CLK_HSICALR_RESET_VALUE ((uint8_t)0x00)
#define	CLK_HSITRIMR_HSITRIM ((uint8_t)0xFF)
#define	CLK_HSITRIMR_RESET_VALUE ((uint8_t)0x00)
#define	CLK_HSIUNLCKR_HSIUNLCK ((uint8_t)0xFF)
#define	CLK_HSIUNLCKR_RESET_VALUE ((uint8_t)0x00)
#define	CLK_ICKCR_BEEPAHALT ((uint8_t)0x40)
#define	CLK_ICKCR_FHWU ((uint8_t)0x20)
#define	CLK_ICKCR_HSION ((uint8_t)0x01)
#define	CLK_ICKCR_HSIRDY ((uint8_t)0x02)
#define	CLK_ICKCR_LSION ((uint8_t)0x04)
#define	CLK_ICKCR_LSIRDY ((uint8_t)0x08)
#define	CLK_ICKCR_RESET_VALUE ((uint8_t)0x11)
#define	CLK_ICKCR_SAHALT ((uint8_t)0x10)
#define	CLK_PCKENR1_BEEP ((uint8_t)0x40)
#define	CLK_PCKENR1_DAC ((uint8_t)0x80)
#define	CLK_PCKENR1_I2C1 ((uint8_t)0x08)
#define	CLK_PCKENR1_RESET_VALUE ((uint8_t)0x00)
#define	CLK_PCKENR1_SPI1 ((uint8_t)0x10)
#define	CLK_PCKENR1_TIM2 ((uint8_t)0x01)
#define	CLK_PCKENR1_TIM3 ((uint8_t)0x02)
#define	CLK_PCKENR1_TIM4 ((uint8_t)0x04)
#define	CLK_PCKENR1_USART1 ((uint8_t)0x20)
#define	CLK_PCKENR2_ADC1 ((uint8_t)0x01)
#define	CLK_PCKENR2_BOOTROM ((uint8_t)0x80)
#define	CLK_PCKENR2_COMP ((uint8_t)0x20)
#define	CLK_PCKENR2_DMA1 ((uint8_t)0x10)
#define	CLK_PCKENR2_LCD ((uint8_t)0x08)
#define	CLK_PCKENR2_RESET_VALUE ((uint8_t)0x80)
#define	CLK_PCKENR2_RTC ((uint8_t)0x04)
#define	CLK_PCKENR2_TIM1 ((uint8_t)0x02)
#define	CLK_PCKENR3_AES ((uint8_t)0x01)
#define	CLK_PCKENR3_RESET_VALUE ((uint8_t)0x00)
#define	CLK_PCKENR3_SPI2 ((uint8_t)0x04)
#define	CLK_PCKENR3_TIM5 ((uint8_t)0x02)
#define	CLK_PCKENR3_UASRT2 ((uint8_t)0x08)
#define	CLK_PCKENR3_USART3 ((uint8_t)0x10)
#define	CLK_REGCSR_EEBUSY ((uint8_t)0x40)
#define	CLK_REGCSR_EEREADY ((uint8_t)0x80)
#define	CLK_REGCSR_HSEPD ((uint8_t)0x10)
#define	CLK_REGCSR_HSIPD ((uint8_t)0x04)
#define	CLK_REGCSR_LSEPD ((uint8_t)0x20)
#define	CLK_REGCSR_LSIPD ((uint8_t)0x08)
#define	CLK_REGCSR_REGOFF ((uint8_t)0x02)
#define	CLK_REGCSR_REGREADY ((uint8_t)0x01)
#define	CLK_REGCSR_RESET_VALUE ((uint8_t)0xB9)
#define	CLK_SCSR_CKM ((uint8_t)0x0F)
#define	CLK_SCSR_RESET_VALUE ((uint8_t)0x01)
#define	CLK_SWCR_RESET_VALUE ((uint8_t)0x00)
#define	CLK_SWCR_SWBSY ((uint8_t)0x01)
#define	CLK_SWCR_SWEN ((uint8_t)0x02)
#define	CLK_SWCR_SWIEN ((uint8_t)0x04)
#define	CLK_SWCR_SWIF ((uint8_t)0x08)
#define	CLK_SWR_RESET_VALUE ((uint8_t)0x01)
#define	CLK_SWR_SWI ((uint8_t)0x0F)
#define	ClrBit(VAR, Place) ( (VAR) &= (uint8_t)((uint8_t)((uint8_t)1<<(uint8_t)(Place))^(uint8_t)255) )
#define	COMP ((COMP_TypeDef *) COMP_BASE)
#define	COMP_BASE (uint16_t)0x5440
#define	COMP_CSR1_CMP1 ((uint8_t)0x03)
#define	COMP_CSR1_CMP1OUT ((uint8_t)0x08)
#define	COMP_CSR1_EF1 ((uint8_t)0x10)
#define	COMP_CSR1_IE1 ((uint8_t)0x20)
#define	COMP_CSR1_RESET_VALUE ((uint8_t)0x00)
#define	COMP_CSR1_STE ((uint8_t)0x04)
#define	COMP_CSR2_CMP2 ((uint8_t)0x03)
#define	COMP_CSR2_CMP2OUT ((uint8_t)0x08)
#define	COMP_CSR2_EF2 ((uint8_t)0x10)
#define	COMP_CSR2_IE2 ((uint8_t)0x20)
#define	COMP_CSR2_RESET_VALUE ((uint8_t)0x00)
#define	COMP_CSR2_SPEED ((uint8_t)0x04)
#define	COMP_CSR3_INSEL ((uint8_t)0x38)
#define	COMP_CSR3_OUTSEL ((uint8_t)0xC0)
#define	COMP_CSR3_RESET_VALUE ((uint8_t)0xC0)
#define	COMP_CSR3_VREFEN ((uint8_t)0x04)
#define	COMP_CSR3_VREFOUTEN ((uint8_t)0x01)
#define	COMP_CSR3_WNDWE ((uint8_t)0x02)
#define	COMP_CSR4_INVTRIG ((uint8_t)0x07)
#define	COMP_CSR4_NINVTRIG ((uint8_t)0x38)
#define	COMP_CSR4_RESET_VALUE ((uint8_t)0x00)
#define	COMP_CSR5_DACTRIG ((uint8_t)0x38)
#define	COMP_CSR5_RESET_VALUE ((uint8_t)0x00)
#define	COMP_CSR5_VREFTRIG ((uint8_t)0x07)
#define	CONST const
#define	CSSLSE ((CSSLSE_TypeDef *) CSSLSE_BASE)
#define	CSSLSE_BASE (uint16_t)0x5190
#define	CSSLSE_CSR_CSSEN ((uint8_t)0x01)
#define	CSSLSE_CSR_CSSF ((uint8_t)0x08)
#define	CSSLSE_CSR_CSSIE ((uint8_t)0x04)
#define	CSSLSE_CSR_RESET_VALUE ((uint8_t)0x00)
#define	CSSLSE_CSR_SWITCHEN ((uint8_t)0x02)
#define	CSSLSE_CSR_SWITCHF ((uint8_t)0x10)
#define	DAC ((DAC_TypeDef *) DAC_BASE)
#define	DAC_BASE (uint16_t)0x5380
#define	DAC_CR1_BOFF ((uint8_t)0x02)
#define	DAC_CR1_EN ((uint8_t)0x01)
#define	DAC_CR1_RESET_VALUE ((uint8_t)0x00)
#define	DAC_CR1_TEN ((uint8_t)0x04)
#define	DAC_CR1_TSEL ((uint8_t)0x38)
#define	DAC_CR1_WAVEN ((uint8_t)0xC0)
#define	DAC_CR2_DMAEN ((uint8_t)0x10)
#define	DAC_CR2_DMAUDRIE ((uint8_t)0x20)
#define	DAC_CR2_MAMPx ((uint8_t)0x0F)
#define	DAC_CR2_RESET_VALUE ((uint8_t)0x00)
#define	DAC_DHR8_8DHR ((uint8_t)0xFF)
#define	DAC_DHR8_RESET_VALUE ((uint8_t)0x00)
#define	DAC_DORH_DORH ((uint8_t)0x0F)
#define	DAC_DORH_RESET_VALUE ((uint8_t)0x00)
#define	DAC_DORL_DORL ((uint8_t)0xFF)
#define	DAC_DORL_RESET_VALUE ((uint8_t)0x00)
#define	DAC_LDHRH_LDHRH ((uint8_t)0xFF)
#define	DAC_LDHRH_RESET_VALUE ((uint8_t)0x00)
#define	DAC_LDHRL_LDHRL ((uint8_t)0xF0)
#define	DAC_LDHRL_RESET_VALUE ((uint8_t)0x00)
#define	DAC_RDHRH_RDHRH ((uint8_t)0x0F)
#define	DAC_RDHRH_RESET_VALUE ((uint8_t)0x00)
#define	DAC_RDHRL_RDHRL ((uint8_t)0xFF)
#define	DAC_RDHRL_RESET_VALUE ((uint8_t)0x00)
#define	DAC_SR_DMAUDR1 ((uint8_t)0x01)
#define	DAC_SR_DMAUDR2 ((uint8_t)0x02)
#define	DAC_SR_RESET_VALUE ((uint8_t)0x00)
#define	DAC_SWTRIGR_RESET_VALUE ((uint8_t)0x00)
#define	DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01)
#define	DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02)
#define	disableInterrupts() __disable_interrupt()
#define	DM ((DM_TypeDef *) DM_BASE)
#define	DM_BASE (uint16_t)0x7F90
#define	DMA1 ((DMA_TypeDef *) DMA1_BASE)
#define	DMA1_BASE (uint16_t)0x5070
#define	DMA1_Channel0 ((DMA_Channel_TypeDef *) DMA1_Channel0_BASE)
#define	DMA1_Channel0_BASE (uint16_t)0x5075
#define	DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
#define	DMA1_Channel1_BASE (uint16_t)0x507F
#define	DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
#define	DMA1_Channel2_BASE (uint16_t)0x5089
#define	DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
#define	DMA1_Channel3_BASE (uint16_t)0x5093
#define	DMA_C3M0EAR_RESET_VALUE ((uint8_t)0x00)
#define	DMA_C3PARH_RESET_VALUE ((uint8_t)0x40)
#define	DMA_CCR_ARM ((uint8_t)0x10)
#define	DMA_CCR_CE ((uint8_t)0x01)
#define	DMA_CCR_DTD ((uint8_t)0x08)
#define	DMA_CCR_HTIE ((uint8_t)0x04)
#define	DMA_CCR_IDM ((uint8_t)0x20)
#define	DMA_CCR_MEM ((uint8_t)0x40)
#define	DMA_CCR_RESET_VALUE ((uint8_t)0x00)
#define	DMA_CCR_TCIE ((uint8_t)0x02)
#define	DMA_CM0ARH_MA ((uint8_t)0xFF)
#define	DMA_CM0ARH_RESET_VALUE ((uint8_t)0x00)
#define	DMA_CM0ARL_MA ((uint8_t)0xFF)
#define	DMA_CM0ARL_RESET_VALUE ((uint8_t)0x00)
#define	DMA_CM0EAR_MA ((uint8_t)0x01)
#define	DMA_CNBTR_NDT ((uint8_t)0xFF)
#define	DMA_CNBTR_RESET_VALUE ((uint8_t)0x00)
#define	DMA_CPARH_PA ((uint8_t)0xFF)
#define	DMA_CPARH_RESET_VALUE ((uint8_t)0x52)
#define	DMA_CPARL_PA ((uint8_t)0xFF)
#define	DMA_CPARL_RESET_VALUE ((uint8_t)0x00)
#define	DMA_CSPR_16BM ((uint8_t)0x08)
#define	DMA_CSPR_BUSY ((uint8_t)0x80)
#define	DMA_CSPR_HTIF ((uint8_t)0x04)
#define	DMA_CSPR_PEND ((uint8_t)0x40)
#define	DMA_CSPR_PL ((uint8_t)0x30)
#define	DMA_CSPR_RESET_VALUE ((uint8_t)0x00)
#define	DMA_CSPR_TCIF ((uint8_t)0x02)
#define	DMA_GCSR_GB ((uint8_t)0x02)
#define	DMA_GCSR_GE ((uint8_t)0x01)
#define	DMA_GCSR_RESET_VALUE ((uint8_t)0xFC)
#define	DMA_GCSR_TO ((uint8_t)0xFC)
#define	DMA_GIR1_IFC0 ((uint8_t)0x01)
#define	DMA_GIR1_IFC1 ((uint8_t)0x02)
#define	DMA_GIR1_IFC2 ((uint8_t)0x04)
#define	DMA_GIR1_IFC3 ((uint8_t)0x08)
#define	DMA_GIR1_RESET_VALUE ((uint8_t)0x00)
#define	EEPROM __eeprom
#define	enableInterrupts() __enable_interrupt()
#define	EXTI ((EXTI_TypeDef *) EXTI_BASE)
#define	EXTI_BASE (uint16_t)0x50A0
#define	EXTI_CONF1_PBHIS ((uint8_t)0x02)
#define	EXTI_CONF1_PBLIS ((uint8_t)0x01)
#define	EXTI_CONF1_PDHIS ((uint8_t)0x08)
#define	EXTI_CONF1_PDLIS ((uint8_t)0x04)
#define	EXTI_CONF1_PEHIS ((uint8_t)0x20)
#define	EXTI_CONF1_PELIS ((uint8_t)0x10)
#define	EXTI_CONF1_PFES ((uint8_t)0x80)
#define	EXTI_CONF1_PFLIS ((uint8_t)0x40)
#define	EXTI_CONF1_RESET_VALUE ((uint8_t)0x00)
#define	EXTI_CONF2_PFHIS ((uint8_t)0x01)
#define	EXTI_CONF2_PGBS ((uint8_t)0x20)
#define	EXTI_CONF2_PGHIS ((uint8_t)0x04)
#define	EXTI_CONF2_PGLIS ((uint8_t)0x02)
#define	EXTI_CONF2_PHDS ((uint8_t)0x40)
#define	EXTI_CONF2_PHHIS ((uint8_t)0x10)
#define	EXTI_CONF2_PHLIS ((uint8_t)0x08)
#define	EXTI_CONF2_RESET_VALUE ((uint8_t)0x00)
#define	EXTI_CR1_P0IS ((uint8_t)0x03)
#define	EXTI_CR1_P1IS ((uint8_t)0x0C)
#define	EXTI_CR1_P2IS ((uint8_t)0x30)
#define	EXTI_CR1_P3IS ((uint8_t)0xC0)
#define	EXTI_CR1_RESET_VALUE ((uint8_t)0x00)
#define	EXTI_CR2_P4IS ((uint8_t)0x03)
#define	EXTI_CR2_P5IS ((uint8_t)0x0C)
#define	EXTI_CR2_P6IS ((uint8_t)0x30)
#define	EXTI_CR2_P7IS ((uint8_t)0xC0)
#define	EXTI_CR2_RESET_VALUE ((uint8_t)0x00)
#define	EXTI_CR3_PBIS ((uint8_t)0x03)
#define	EXTI_CR3_PDIS ((uint8_t)0x0C)
#define	EXTI_CR3_PEIS ((uint8_t)0x30)
#define	EXTI_CR3_PFIS ((uint8_t)0xC0)
#define	EXTI_CR3_RESET_VALUE ((uint8_t)0x00)
#define	EXTI_CR4_PGIS ((uint8_t)0x03)
#define	EXTI_CR4_PHIS ((uint8_t)0x0C)
#define	EXTI_CR4_RESET_VALUE ((uint8_t)0x00)
#define	EXTI_SR1_RESET_VALUE ((uint8_t)0x00)
#define	EXTI_SR2_RESET_VALUE ((uint8_t)0x00)
#define	FAR __far
#define	FLASH ((FLASH_TypeDef *) FLASH_BASE)
#define	FLASH_BASE (uint16_t)0x5050
#define	FLASH_CR1_EEPM ((uint8_t)0x08)
#define	FLASH_CR1_FIX ((uint8_t)0x01)
#define	FLASH_CR1_IE ((uint8_t)0x02)
#define	FLASH_CR1_RESET_VALUE ((uint8_t)0x00)
#define	FLASH_CR1_WAITM ((uint8_t)0x04)
#define	FLASH_CR2_ERASE ((uint8_t)0x20)
#define	FLASH_CR2_FPRG ((uint8_t)0x10)
#define	FLASH_CR2_OPT ((uint8_t)0x80)
#define	FLASH_CR2_PRG ((uint8_t)0x01)
#define	FLASH_CR2_RESET_VALUE ((uint8_t)0x00)
#define	FLASH_CR2_WPRG ((uint8_t)0x40)
#define	FLASH_DUKR_DUK ((uint8_t)0xFF)
#define	FLASH_DUKR_RESET_VALUE ((uint8_t)0x56)
#define	FLASH_IAPSR_DUL ((uint8_t)0x08)
#define	FLASH_IAPSR_EOP ((uint8_t)0x04)
#define	FLASH_IAPSR_HVOFF ((uint8_t)0x40)
#define	FLASH_IAPSR_PUL ((uint8_t)0x02)
#define	FLASH_IAPSR_RESET_VALUE ((uint8_t)0x40)
#define	FLASH_IAPSR_WR_PG_DIS ((uint8_t)0x01)
#define	FLASH_PUKR_PUK ((uint8_t)0xFF)
#define	FLASH_PUKR_RESET_VALUE ((uint8_t)0xAE)
#define	GPIO_CR1_RESET_VALUE ((uint8_t)0x00)
#define	GPIO_CR2_RESET_VALUE ((uint8_t)0x00)
#define	GPIO_DDR_RESET_VALUE ((uint8_t)0x00)
#define	GPIO_ODR_RESET_VALUE ((uint8_t)0x00)
#define	GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
#define	GPIOA_BASE (uint16_t)0x5000
#define	GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
#define	GPIOB_BASE (uint16_t)0x5005
#define	GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
#define	GPIOC_BASE (uint16_t)0x500A
#define	GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
#define	GPIOD_BASE (uint16_t)0x500F
#define	GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
#define	GPIOE_BASE (uint16_t)0x5014
#define	GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
#define	GPIOF_BASE (uint16_t)0x5019
#define	GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
#define	GPIOG_BASE (uint16_t)0x501E
#define	GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
#define	GPIOH_BASE (uint16_t)0x5023
#define	GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
#define	GPIOI_BASE (uint16_t)0x5028
#define	halt() __halt()
#define	HSE_VALUE ((uint32_t)16000000)
	In the following line adjust the value of External High Speed oscillator (HSE) used in your application.
#define	HSI_VALUE ((uint32_t)16000000)
	Definition of Device on-chip RC oscillator frequencies.
#define	I2C1 ((I2C_TypeDef *) I2C1_BASE)
#define	I2C1_BASE (uint16_t)0x5210
#define	I2C_CCRH_CCR ((uint8_t)0x0F)
#define	I2C_CCRH_DUTY ((uint8_t)0x40)
#define	I2C_CCRH_FS ((uint8_t)0x80)
#define	I2C_CCRH_RESET_VALUE ((uint8_t)0x00)
#define	I2C_CCRL_CCR ((uint8_t)0xFF)
#define	I2C_CCRL_RESET_VALUE ((uint8_t)0x00)
#define	I2C_CR1_ARP ((uint8_t)0x10)
#define	I2C_CR1_ENGC ((uint8_t)0x40)
#define	I2C_CR1_ENPEC ((uint8_t)0x20)
#define	I2C_CR1_NOSTRETCH ((uint8_t)0x80)
#define	I2C_CR1_PE ((uint8_t)0x01)
#define	I2C_CR1_RESET_VALUE ((uint8_t)0x00)
#define	I2C_CR1_SMBTYPE ((uint8_t)0x08)
#define	I2C_CR1_SMBUS ((uint8_t)0x02)
#define	I2C_CR2_ACK ((uint8_t)0x04)
#define	I2C_CR2_ALERT ((uint8_t)0x20)
#define	I2C_CR2_PEC ((uint8_t)0x10)
#define	I2C_CR2_POS ((uint8_t)0x08)
#define	I2C_CR2_RESET_VALUE ((uint8_t)0x00)
#define	I2C_CR2_START ((uint8_t)0x01)
#define	I2C_CR2_STOP ((uint8_t)0x02)
#define	I2C_CR2_SWRST ((uint8_t)0x80)
#define	I2C_DR_DR ((uint8_t)0xFF)
#define	I2C_DR_RESET_VALUE ((uint8_t)0x00)
#define	I2C_FREQR_FREQ ((uint8_t)0x3F)
#define	I2C_FREQR_RESET_VALUE ((uint8_t)0x00)
#define	I2C_ITR_DMAEN ((uint8_t)0x08)
#define	I2C_ITR_ITBUFEN ((uint8_t)0x04)
#define	I2C_ITR_ITERREN ((uint8_t)0x01)
#define	I2C_ITR_ITEVTEN ((uint8_t)0x02)
#define	I2C_ITR_LAST ((uint8_t)0x10)
#define	I2C_ITR_RESET_VALUE ((uint8_t)0x00)
#define	I2C_OAR2_ADD2 ((uint8_t)0xFE)
#define	I2C_OAR2_ENDUAL ((uint8_t)0x01)
#define	I2C_OAR2_RESET_VALUE ((uint8_t)0x00)
#define	I2C_OARH_ADD ((uint8_t)0x06)
#define	I2C_OARH_ADDCONF ((uint8_t)0x40)
#define	I2C_OARH_ADDMODE ((uint8_t)0x80)
#define	I2C_OARH_RESET_VALUE ((uint8_t)0x00)
#define	I2C_OARL_ADD ((uint8_t)0xFE)
#define	I2C_OARL_ADD0 ((uint8_t)0x01)
#define	I2C_OARL_RESET_VALUE ((uint8_t)0x00)
#define	I2C_PECR_PEC ((uint8_t)0xFF)
#define	I2C_PECR_RESET_VALUE ((uint8_t)0x00)
#define	I2C_SR1_ADD10 ((uint8_t)0x08)
#define	I2C_SR1_ADDR ((uint8_t)0x02)
#define	I2C_SR1_BTF ((uint8_t)0x04)
#define	I2C_SR1_RESET_VALUE ((uint8_t)0x00)
#define	I2C_SR1_RXNE ((uint8_t)0x40)
#define	I2C_SR1_SB ((uint8_t)0x01)
#define	I2C_SR1_STOPF ((uint8_t)0x10)
#define	I2C_SR1_TXE ((uint8_t)0x80)
#define	I2C_SR2_AF ((uint8_t)0x04)
#define	I2C_SR2_ARLO ((uint8_t)0x02)
#define	I2C_SR2_BERR ((uint8_t)0x01)
#define	I2C_SR2_OVR ((uint8_t)0x08)
#define	I2C_SR2_PECERR ((uint8_t)0x10)
#define	I2C_SR2_RESET_VALUE ((uint8_t)0x00)
#define	I2C_SR2_SMBALERT ((uint8_t)0x80)
#define	I2C_SR2_TIMEOUT ((uint8_t)0x40)
#define	I2C_SR2_WUFH ((uint8_t)0x20)
#define	I2C_SR3_BUSY ((uint8_t)0x02)
#define	I2C_SR3_DUALF ((uint8_t)0x80)
#define	I2C_SR3_GENCALL ((uint8_t)0x10)
#define	I2C_SR3_MSL ((uint8_t)0x01)
#define	I2C_SR3_RESET_VALUE ((uint8_t)0x00)
#define	I2C_SR3_SMBDEFAULT ((uint8_t)0x20)
#define	I2C_SR3_SMBHOST ((uint8_t)0x40)
#define	I2C_SR3_TRA ((uint8_t)0x04)
#define	I2C_TRISER_RESET_VALUE ((uint8_t)0x02)
#define	I2C_TRISER_TRISE ((uint8_t)0x3F)
#define	IN_RAM(a) a
#define	IRTIM ((IRTIM_TypeDef *) IRTIM_BASE)
#define	IRTIM_BASE (uint16_t)0x52FF
#define	IRTIM_CR_EN ((uint8_t)0x01)
#define	IRTIM_CR_HSEN ((uint8_t)0x02)
#define	IRTIM_CR_RESET_VALUE ((uint8_t)0x00)
#define	IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) \|\| ((STATE) == ENABLE))
#define	IS_STATE_VALUE(STATE)
#define	ITC ((ITC_TypeDef *) ITC_BASE)
#define	ITC_BASE (uint16_t)0x7F70
#define	ITC_SPRX_RESET_VALUE ((uint8_t)0xFF)
#define	IWDG ((IWDG_TypeDef *) IWDG_BASE)
#define	IWDG_BASE (uint16_t)0x50E0
#define	IWDG_PR_RESET_VALUE ((uint8_t)0x00)
#define	IWDG_RLR_RESET_VALUE ((uint8_t)0xFF)
#define	LCD ((LCD_TypeDef *) LCD_BASE)
#define	LCD_BASE (uint16_t)0x5400
#define	LCD_CR1_B2 ((uint8_t)0x01)
#define	LCD_CR1_BLINK ((uint8_t)0xC0)
#define	LCD_CR1_BLINKF ((uint8_t)0x38)
#define	LCD_CR1_DUTY ((uint8_t)0x06)
#define	LCD_CR1_RESET_VALUE ((uint8_t)0x00)
#define	LCD_CR2_CC ((uint8_t)0x0E)
#define	LCD_CR2_HD ((uint8_t)0x10)
#define	LCD_CR2_PON ((uint8_t)0xE0)
#define	LCD_CR2_RESET_VALUE ((uint8_t)0x00)
#define	LCD_CR2_VSEL ((uint8_t)0x01)
#define	LCD_CR3_DEAD ((uint8_t)0x07)
#define	LCD_CR3_LCDEN ((uint8_t)0x40)
#define	LCD_CR3_RESET_VALUE ((uint8_t)0x00)
#define	LCD_CR3_SOF ((uint8_t)0x10)
#define	LCD_CR3_SOFC ((uint8_t)0x08)
#define	LCD_CR3_SOFIE ((uint8_t)0x20)
#define	LCD_CR4_B4 ((uint8_t)0x01)
#define	LCD_CR4_DUTY8 ((uint8_t)0x02)
#define	LCD_CR4_MAPCOM ((uint8_t)0x08)
#define	LCD_CR4_PAGECOM ((uint8_t)0x04)
#define	LCD_CR4_RESET_VALUE ((uint8_t)0x00)
#define	LCD_FRQ_DIV ((uint8_t)0x0F)
#define	LCD_FRQ_PS ((uint8_t)0xF0)
#define	LCD_FRQ_RESET_VALUE ((uint8_t)0x00)
#define	LCD_PM_RESET_VALUE ((uint8_t)0x00)
#define	LCD_RAM_RESET_VALUE ((uint8_t)0x00)
#define	LSE_VALUE ((uint32_t)32768)
	Definition of External Low Speed oscillator (LSE) frequency.
#define	LSI_VALUE ((uint32_t)38000)
#define	MskBit(Dest, Msk, Src) ( (Dest) = ((Msk) & (Src)) \| ((~(Msk)) & (Dest)) )
#define	NEAR __near
#define	nop() __no_operation()
#define	OPT ((OPT_TypeDef *) OPT_BASE)
#define	OPT_BASE (uint16_t)0x4800
#define	PointerAttr FAR
#define	PWR ((PWR_TypeDef *) PWR_BASE)
#define	PWR_BASE (uint16_t)0x50B2
#define	PWR_CR2_VREFINTF ((uint8_t)0x01)
#define	PWR_CSR1_PLS ((uint8_t)0x0E)
#define	PWR_CSR1_PVDE ((uint8_t)0x01)
#define	PWR_CSR1_PVDIEN ((uint8_t)0x10)
#define	PWR_CSR1_PVDIF ((uint8_t)0x20)
#define	PWR_CSR1_PVDOF ((uint8_t)0x40)
#define	PWR_CSR1_RESET_VALUE ((uint8_t)0x00)
#define	PWR_CSR2_FWU ((uint8_t)0x04)
#define	PWR_CSR2_RESET_VALUE ((uint8_t)0x00)
#define	PWR_CSR2_ULP ((uint8_t)0x02)
#define	RI ((RI_TypeDef *) RI_BASE)
#define	RI_ASCR1_AS0 ((uint8_t)0x01)
#define	RI_ASCR1_AS1 ((uint8_t)0x02)
#define	RI_ASCR1_AS2 ((uint8_t)0x04)
#define	RI_ASCR1_AS3 ((uint8_t)0x08)
#define	RI_ASCR1_AS4 ((uint8_t)0x10)
#define	RI_ASCR1_AS5 ((uint8_t)0x20)
#define	RI_ASCR1_AS6 ((uint8_t)0x40)
#define	RI_ASCR1_AS7 ((uint8_t)0x80)
#define	RI_ASCR1_RESET_VALUE ((uint8_t)0x00)
#define	RI_ASCR2_AS10 ((uint8_t)0x04)
#define	RI_ASCR2_AS11 ((uint8_t)0x08)
#define	RI_ASCR2_AS14 ((uint8_t)0x40)
#define	RI_ASCR2_AS8 ((uint8_t)0x01)
#define	RI_ASCR2_AS9 ((uint8_t)0x02)
#define	RI_ASCR2_RESET_VALUE ((uint8_t)0x00)
#define	RI_BASE (uint16_t)0x5430
#define	RI_ICR1_IC2CS ((uint8_t)0x1F)
#define	RI_ICR1_RESET_VALUE ((uint8_t)0x00)
#define	RI_ICR2_IC3CS ((uint8_t)0x1F)
#define	RI_ICR2_RESET_VALUE ((uint8_t)0x00)
#define	RI_IOCMR1_CH10M ((uint8_t)0x08)
#define	RI_IOCMR1_CH13M ((uint8_t)0x10)
#define	RI_IOCMR1_CH16M ((uint8_t)0x20)
#define	RI_IOCMR1_CH19M ((uint8_t)0x40)
#define	RI_IOCMR1_CH1M ((uint8_t)0x01)
#define	RI_IOCMR1_CH22M ((uint8_t)0x80)
#define	RI_IOCMR1_CH4M ((uint8_t)0x02)
#define	RI_IOCMR1_CH7M ((uint8_t)0x04)
#define	RI_IOCMR1_RESET_VALUE ((uint8_t)0x00)
#define	RI_IOCMR2_CH11M ((uint8_t)0x08)
#define	RI_IOCMR2_CH14M ((uint8_t)0x10)
#define	RI_IOCMR2_CH17M ((uint8_t)0x20)
#define	RI_IOCMR2_CH20M ((uint8_t)0x40)
#define	RI_IOCMR2_CH23M ((uint8_t)0x80)
#define	RI_IOCMR2_CH2M ((uint8_t)0x01)
#define	RI_IOCMR2_CH5M ((uint8_t)0x02)
#define	RI_IOCMR2_CH8M ((uint8_t)0x04)
#define	RI_IOCMR2_RESET_VALUE ((uint8_t)0x00)
#define	RI_IOCMR3_CH12M ((uint8_t)0x08)
#define	RI_IOCMR3_CH15M ((uint8_t)0x10)
#define	RI_IOCMR3_CH18M ((uint8_t)0x20)
#define	RI_IOCMR3_CH21M ((uint8_t)0x40)
#define	RI_IOCMR3_CH24M ((uint8_t)0x80)
#define	RI_IOCMR3_CH3M ((uint8_t)0x01)
#define	RI_IOCMR3_CH6M ((uint8_t)0x02)
#define	RI_IOCMR3_CH9M ((uint8_t)0x04)
#define	RI_IOCMR3_RESET_VALUE ((uint8_t)0x00)
#define	RI_IOCMR4_RESET_VALUE ((uint8_t)0x00)
#define	RI_IOGCR_IOM1 ((uint8_t)0x03)
#define	RI_IOGCR_IOM2 ((uint8_t)0x0C)
#define	RI_IOGCR_IOM3 ((uint8_t)0x30)
#define	RI_IOGCR_IOM4 ((uint8_t)0xC0)
#define	RI_IOGCR_RESET_VALUE ((uint8_t)0xFF)
#define	RI_IOIR1_CH10I ((uint8_t)0x08)
#define	RI_IOIR1_CH13I ((uint8_t)0x10)
#define	RI_IOIR1_CH16I ((uint8_t)0x20)
#define	RI_IOIR1_CH19I ((uint8_t)0x40)
#define	RI_IOIR1_CH1I ((uint8_t)0x01)
#define	RI_IOIR1_CH22I ((uint8_t)0x80)
#define	RI_IOIR1_CH4I ((uint8_t)0x02)
#define	RI_IOIR1_CH7I ((uint8_t)0x04)
#define	RI_IOIR2_CH11I ((uint8_t)0x08)
#define	RI_IOIR2_CH14I ((uint8_t)0x10)
#define	RI_IOIR2_CH17I ((uint8_t)0x20)
#define	RI_IOIR2_CH20I ((uint8_t)0x40)
#define	RI_IOIR2_CH23I ((uint8_t)0x80)
#define	RI_IOIR2_CH2I ((uint8_t)0x01)
#define	RI_IOIR2_CH5I ((uint8_t)0x02)
#define	RI_IOIR2_CH8I ((uint8_t)0x04)
#define	RI_IOIR3_CH12I ((uint8_t)0x08)
#define	RI_IOIR3_CH15I ((uint8_t)0x10)
#define	RI_IOIR3_CH18I ((uint8_t)0x20)
#define	RI_IOIR3_CH21I ((uint8_t)0x40)
#define	RI_IOIR3_CH24I ((uint8_t)0x80)
#define	RI_IOIR3_CH3I ((uint8_t)0x01)
#define	RI_IOIR3_CH6I ((uint8_t)0x02)
#define	RI_IOIR3_CH9I ((uint8_t)0x04)
#define	RI_IOSR1_CH10E ((uint8_t)0x08)
#define	RI_IOSR1_CH13E ((uint8_t)0x10)
#define	RI_IOSR1_CH16E ((uint8_t)0x20)
#define	RI_IOSR1_CH19E ((uint8_t)0x40)
#define	RI_IOSR1_CH1E ((uint8_t)0x01)
#define	RI_IOSR1_CH22E ((uint8_t)0x80)
#define	RI_IOSR1_CH4E ((uint8_t)0x02)
#define	RI_IOSR1_CH7E ((uint8_t)0x04)
#define	RI_IOSR1_RESET_VALUE ((uint8_t)0x00)
#define	RI_IOSR2_CH11E ((uint8_t)0x08)
#define	RI_IOSR2_CH14E ((uint8_t)0x10)
#define	RI_IOSR2_CH17E ((uint8_t)0x20)
#define	RI_IOSR2_CH20E ((uint8_t)0x40)
#define	RI_IOSR2_CH23E ((uint8_t)0x80)
#define	RI_IOSR2_CH2E ((uint8_t)0x01)
#define	RI_IOSR2_CH5E ((uint8_t)0x02)
#define	RI_IOSR2_CH8E ((uint8_t)0x04)
#define	RI_IOSR2_RESET_VALUE ((uint8_t)0x00)
#define	RI_IOSR3_CH12E ((uint8_t)0x08)
#define	RI_IOSR3_CH15E ((uint8_t)0x10)
#define	RI_IOSR3_CH18E ((uint8_t)0x20)
#define	RI_IOSR3_CH21E ((uint8_t)0x40)
#define	RI_IOSR3_CH24E ((uint8_t)0x80)
#define	RI_IOSR3_CH3E ((uint8_t)0x01)
#define	RI_IOSR3_CH6E ((uint8_t)0x02)
#define	RI_IOSR3_CH9E ((uint8_t)0x04)
#define	RI_IOSR3_RESET_VALUE ((uint8_t)0x00)
#define	RI_IOSR4_CH26E ((uint8_t)0x02)
#define	RI_IOSR4_CH27E ((uint8_t)0x40)
#define	RI_IOSR4_CH28E ((uint8_t)0x80)
#define	RI_IOSR4_CH29E ((uint8_t)0x01)
#define	RI_IOSR4_RESET_VALUE ((uint8_t)0x00)
#define	RI_RCR_10KPD ((uint8_t)0x04)
#define	RI_RCR_10KPU ((uint8_t)0x01)
#define	RI_RCR_400KPD ((uint8_t)0x08)
#define	RI_RCR_400KPU ((uint8_t)0x02)
#define	RI_RCR_RESET_VALUE ((uint8_t)0x00)
#define	rim() __enable_interrupt()
#define	RST ((RST_TypeDef *) RST_BASE)
#define	RST_BASE (uint16_t)0x50B0
#define	RST_CR_RESET_VALUE ((uint8_t)0x00)
#define	RST_SR_BORF ((uint8_t)0x20)
#define	RST_SR_ILLOPF ((uint8_t)0x04)
#define	RST_SR_IWDGF ((uint8_t)0x02)
#define	RST_SR_PORF ((uint8_t)0x01)
#define	RST_SR_RESET_VALUE ((uint8_t)0x01)
#define	RST_SR_SWIMF ((uint8_t)0x08)
#define	RST_SR_WWDGF ((uint8_t)0x10)
#define	RTC ((RTC_TypeDef *) RTC_BASE)
#define	RTC_ALRMAR1_MSK1 ((uint8_t)0x80)
#define	RTC_ALRMAR1_RESET_VALUE ((uint8_t)0x00)
#define	RTC_ALRMAR1_ST ((uint8_t)0x70)
#define	RTC_ALRMAR1_SU ((uint8_t)0x0F)
#define	RTC_ALRMAR2_MNT ((uint8_t)0x70)
#define	RTC_ALRMAR2_MNU ((uint8_t)0x0F)
#define	RTC_ALRMAR2_MSK2 ((uint8_t)0x80)
#define	RTC_ALRMAR2_RESET_VALUE ((uint8_t)0x00)
#define	RTC_ALRMAR3_HT ((uint8_t)0x30)
#define	RTC_ALRMAR3_HU ((uint8_t)0x0F)
#define	RTC_ALRMAR3_MSK3 ((uint8_t)0x80)
#define	RTC_ALRMAR3_PM ((uint8_t)0x40)
#define	RTC_ALRMAR3_RESET_VALUE ((uint8_t)0x00)
#define	RTC_ALRMAR4_DT ((uint8_t)0x30)
#define	RTC_ALRMAR4_DU ((uint8_t)0x0F)
#define	RTC_ALRMAR4_MSK4 ((uint8_t)0x80)
#define	RTC_ALRMAR4_RESET_VALUE ((uint8_t)0x00)
#define	RTC_ALRMAR4_WDSEL ((uint8_t)0x40)
#define	RTC_ALRMASSMSKR_MASKSS ((uint8_t)0x1F)
#define	RTC_ALRMASSMSKR_RESET_VALUE ((uint8_t)0x00)
#define	RTC_ALRMASSRH_ALSS ((uint8_t)0x7F)
#define	RTC_ALRMASSRH_RESET_VALUE ((uint8_t)0x00)
#define	RTC_ALRMASSRL_ALSS ((uint8_t)0xFF)
#define	RTC_ALRMASSRL_RESET_VALUE ((uint8_t)0x00)
#define	RTC_APRER_RESET_VALUE ((uint8_t)0x7F)
#define	RTC_BASE (uint16_t)0x5140
#define	RTC_CALRH_CALM ((uint8_t)0x01)
#define	RTC_CALRH_CALP ((uint8_t)0x80)
#define	RTC_CALRH_CALW16 ((uint8_t)0x20)
#define	RTC_CALRH_CALW8 ((uint8_t)0x40)
#define	RTC_CALRH_CALWx ((uint8_t)0x60)
#define	RTC_CALRH_RESET_VALUE ((uint8_t)0x00)
#define	RTC_CALRL_CALM ((uint8_t)0xFF)
#define	RTC_CALRL_RESET_VALUE ((uint8_t)0x00)
#define	RTC_CR1_BYPSHAD ((uint8_t)0x10)
#define	RTC_CR1_FMT ((uint8_t)0x40)
#define	RTC_CR1_RATIO ((uint8_t)0x20)
#define	RTC_CR1_RESET_VALUE ((uint8_t)0x00)
#define	RTC_CR1_WUCKSEL ((uint8_t)0x07)
#define	RTC_CR2_ALRAE ((uint8_t)0x01)
#define	RTC_CR2_ALRAIE ((uint8_t)0x10)
#define	RTC_CR2_ALRIE ((uint8_t)0x20)
#define	RTC_CR2_RESET_VALUE ((uint8_t)0x00)
#define	RTC_CR2_WUTE ((uint8_t)0x04)
#define	RTC_CR2_WUTIE ((uint8_t)0x40)
#define	RTC_CR3_ADD1H ((uint8_t)0x01)
#define	RTC_CR3_BCK ((uint8_t)0x04)
#define	RTC_CR3_COE ((uint8_t)0x80)
#define	RTC_CR3_COSEL ((uint8_t)0x08)
#define	RTC_CR3_OSEL ((uint8_t)0x60)
#define	RTC_CR3_POL ((uint8_t)0x10)
#define	RTC_CR3_RESET_VALUE ((uint8_t)0x00)
#define	RTC_CR3_SUB1H ((uint8_t)0x02)
#define	RTC_DR1_DT ((uint8_t)0x30)
#define	RTC_DR1_DU ((uint8_t)0x0F)
#define	RTC_DR1_RESET_VALUE ((uint8_t)0x01)
#define	RTC_DR2_MT ((uint8_t)0x10)
#define	RTC_DR2_MU ((uint8_t)0x0F)
#define	RTC_DR2_RESET_VALUE ((uint8_t)0x21)
#define	RTC_DR2_WDU ((uint8_t)0xE0)
#define	RTC_DR3_RESET_VALUE ((uint8_t)0x00)
#define	RTC_DR3_YT ((uint8_t)0xF0)
#define	RTC_DR3_YU ((uint8_t)0x0F)
#define	RTC_ISR1_ALRAWF ((uint8_t)0x01)
#define	RTC_ISR1_INIT ((uint8_t)0x80)
#define	RTC_ISR1_INITF ((uint8_t)0x40)
#define	RTC_ISR1_INITS ((uint8_t)0x10)
#define	RTC_ISR1_RECALPF ((uint8_t)0x02)
#define	RTC_ISR1_RESET_VALUE ((uint8_t)0x07)
#define	RTC_ISR1_RSF ((uint8_t)0x20)
#define	RTC_ISR1_SHPF ((uint8_t)0x08)
#define	RTC_ISR1_WUTWF ((uint8_t)0x04)
#define	RTC_ISR2_ALRAF ((uint8_t)0x01)
#define	RTC_ISR2_RESET_VALUE ((uint8_t)0x00)
#define	RTC_ISR2_TAMP1F ((uint8_t)0x20)
#define	RTC_ISR2_TAMP2F ((uint8_t)0x40)
#define	RTC_ISR2_TAMP3F ((uint8_t)0x80)
#define	RTC_ISR2_WUTF ((uint8_t)0x04)
#define	RTC_SHIFTRH_ADD1S ((uint8_t)0x80)
#define	RTC_SHIFTRH_RESET_VALUE ((uint8_t)0x00)
#define	RTC_SHIFTRH_SUBFS ((uint8_t)0x7F)
#define	RTC_SHIFTRL_RESET_VALUE ((uint8_t)0x00)
#define	RTC_SHIFTRL_SUBFS ((uint8_t)0xFF)
#define	RTC_SPRERH_RESET_VALUE ((uint8_t)0x00)
#define	RTC_SPRERL_RESET_VALUE ((uint8_t)0xFF)
#define	RTC_TCR1_RESET_VALUE ((uint8_t)0x00)
#define	RTC_TCR1_TAMP1E ((uint8_t)0x02)
#define	RTC_TCR1_TAMP1LEVEL ((uint8_t)0x04)
#define	RTC_TCR1_TAMP2E ((uint8_t)0x08)
#define	RTC_TCR1_TAMP2LEVEL ((uint8_t)0x10)
#define	RTC_TCR1_TAMP3E ((uint8_t)0x20)
#define	RTC_TCR1_TAMP3LEVEL ((uint8_t)0x40)
#define	RTC_TCR1_TAMPIE ((uint8_t)0x01)
#define	RTC_TCR2_RESET_VALUE ((uint8_t)0x00)
#define	RTC_TCR2_TAMPFLT ((uint8_t)0x18)
#define	RTC_TCR2_TAMPFREQ ((uint8_t)0x07)
#define	RTC_TCR2_TAMPPRCH ((uint8_t)0x60)
#define	RTC_TCR2_TAMPPUDIS ((uint8_t)0x80)
#define	RTC_TR1_RESET_VALUE ((uint8_t)0x00)
#define	RTC_TR1_ST ((uint8_t)0x70)
#define	RTC_TR1_SU ((uint8_t)0x0F)
#define	RTC_TR2_MNT ((uint8_t)0x70)
#define	RTC_TR2_MNU ((uint8_t)0x0F)
#define	RTC_TR2_RESET_VALUE ((uint8_t)0x00)
#define	RTC_TR3_HT ((uint8_t)0x30)
#define	RTC_TR3_HU ((uint8_t)0x0F)
#define	RTC_TR3_PM ((uint8_t)0x40)
#define	RTC_TR3_RESET_VALUE ((uint8_t)0x00)
#define	RTC_WPR_DisableKey1 ((uint8_t)0xCA)
#define	RTC_WPR_DisableKey2 ((uint8_t)0x53)
#define	RTC_WPR_EnableKey ((uint8_t)0xFF)
#define	RTC_WPR_RESET_VALUE ((uint8_t)0x00)
#define	RTC_WUTRH_RESET_VALUE ((uint8_t)0xFF)
#define	RTC_WUTRL_RESET_VALUE ((uint8_t)0xFF)
#define	S16_MAX (32767)
#define	S16_MIN (-32768)
#define	S32_MAX (2147483647)
#define	S32_MIN (-2147483648uL)
#define	S8_MAX (127)
#define	S8_MIN (-128)
#define	SetBit(VAR, Place) ( (VAR) \|= (uint8_t)((uint8_t)1<<(uint8_t)(Place)) )
#define	sim() __disable_interrupt()
#define	SPI1 ((SPI_TypeDef *) SPI1_BASE)
#define	SPI1_BASE (uint16_t)0x5200
#define	SPI2 ((SPI_TypeDef *) SPI2_BASE)
#define	SPI2_BASE (uint16_t)0x53C0
#define	SPI_CR1_BR ((uint8_t)0x38)
#define	SPI_CR1_CPHA ((uint8_t)0x01)
#define	SPI_CR1_CPOL ((uint8_t)0x02)
#define	SPI_CR1_LSBFIRST ((uint8_t)0x80)
#define	SPI_CR1_MSTR ((uint8_t)0x04)
#define	SPI_CR1_RESET_VALUE ((uint8_t)0x00)
#define	SPI_CR1_SPE ((uint8_t)0x40)
#define	SPI_CR2_BDM ((uint8_t)0x80)
#define	SPI_CR2_BDOE ((uint8_t)0x40)
#define	SPI_CR2_CRCEN ((uint8_t)0x20)
#define	SPI_CR2_CRCNEXT ((uint8_t)0x10)
#define	SPI_CR2_RESET_VALUE ((uint8_t)0x00)
#define	SPI_CR2_RXONLY ((uint8_t)0x04)
#define	SPI_CR2_SSI ((uint8_t)0x01)
#define	SPI_CR2_SSM ((uint8_t)0x02)
#define	SPI_CR3_ERRIE ((uint8_t)0x20)
#define	SPI_CR3_RESET_VALUE ((uint8_t)0x00)
#define	SPI_CR3_RXDMAEN ((uint8_t)0x01)
#define	SPI_CR3_RXIE ((uint8_t)0x40)
#define	SPI_CR3_TXDMAEN ((uint8_t)0x02)
#define	SPI_CR3_TXIE ((uint8_t)0x80)
#define	SPI_CR3_WKIE ((uint8_t)0x10)
#define	SPI_CRCPR_RESET_VALUE ((uint8_t)0x07)
#define	SPI_DR_RESET_VALUE ((uint8_t)0x00)
#define	SPI_RXCRCR_RESET_VALUE ((uint8_t)0x00)
#define	SPI_SR_BSY ((uint8_t)0x80)
#define	SPI_SR_CRCERR ((uint8_t)0x10)
#define	SPI_SR_MODF ((uint8_t)0x20)
#define	SPI_SR_OVR ((uint8_t)0x40)
#define	SPI_SR_RESET_VALUE ((uint8_t)0x02)
#define	SPI_SR_RXNE ((uint8_t)0x01)
#define	SPI_SR_TXE ((uint8_t)0x02)
#define	SPI_SR_WKUP ((uint8_t)0x08)
#define	SPI_TXCRCR_RESET_VALUE ((uint8_t)0x00)
#define	SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
#define	SYSCFG_BASE (uint16_t)0x509D
#define	SYSCFG_RMPCR1_ADC1DMA_REMAP ((uint8_t)0x03)
#define	SYSCFG_RMPCR1_RESET_VALUE ((uint8_t)0x0C)
#define	SYSCFG_RMPCR1_SPI1_REMAP ((uint8_t)0x80)
#define	SYSCFG_RMPCR1_TIM4DMA_REMAP ((uint8_t)0x0C)
#define	SYSCFG_RMPCR1_USART1CK_REMAP ((uint8_t)0x40)
#define	SYSCFG_RMPCR1_USART1TR_REMAP ((uint8_t)0x30)
#define	SYSCFG_RMPCR2_ADC1TRIG_REMAP ((uint8_t)0x01)
#define	SYSCFG_RMPCR2_RESET_VALUE ((uint8_t)0x00)
#define	SYSCFG_RMPCR2_SPI2_REMAP ((uint8_t)0x20)
#define	SYSCFG_RMPCR2_TIM23BKIN_REMAP ((uint8_t)0x80)
#define	SYSCFG_RMPCR2_TIM2TRIG_LSE ((uint8_t)0x08)
#define	SYSCFG_RMPCR2_TIM2TRIG_REMAP ((uint8_t)0x02)
#define	SYSCFG_RMPCR2_TIM3TRIG_LSE ((uint8_t)0x10)
#define	SYSCFG_RMPCR2_TIM3TRIG_REMAP1 ((uint8_t)0x04)
#define	SYSCFG_RMPCR2_TIM3TRIG_REMAP2 ((uint8_t)0x40)
#define	SYSCFG_RMPCR3_CCO_REMAP ((uint8_t)0x20)
#define	SYSCFG_RMPCR3_RESET_VALUE ((uint8_t)0x00)
#define	SYSCFG_RMPCR3_SPI1_REMAP ((uint8_t)0x01)
#define	SYSCFG_RMPCR3_TIM3CH1_REMAP ((uint8_t)0x08)
#define	SYSCFG_RMPCR3_TIM3CH2_REMAP ((uint8_t)0x10)
#define	SYSCFG_RMPCR3_USART3CK_REMAP ((uint8_t)0x04)
#define	SYSCFG_RMPCR3_USART3TR_REMAP ((uint8_t)0x02)
#define	TIM1 ((TIM1_TypeDef *) TIM1_BASE)
#define	TIM1_ARRH_ARR ((uint8_t)0xFF)
#define	TIM1_ARRH_RESET_VALUE ((uint8_t)0xFF)
#define	TIM1_ARRL_ARR ((uint8_t)0xFF)
#define	TIM1_ARRL_RESET_VALUE ((uint8_t)0xFF)
#define	TIM1_BASE (uint16_t)0x52B0
#define	TIM1_BKR_AOE ((uint8_t)0x40)
#define	TIM1_BKR_BKE ((uint8_t)0x10)
#define	TIM1_BKR_BKP ((uint8_t)0x20)
#define	TIM1_BKR_LOCK ((uint8_t)0x03)
#define	TIM1_BKR_MOE ((uint8_t)0x80)
#define	TIM1_BKR_OSSI ((uint8_t)0x04)
#define	TIM1_BKR_OSSR ((uint8_t)0x08)
#define	TIM1_BKR_RESET_VALUE ((uint8_t)0x00)
#define	TIM1_CCER1_CC1E ((uint8_t)0x01)
#define	TIM1_CCER1_CC1NE ((uint8_t)0x04)
#define	TIM1_CCER1_CC1NP ((uint8_t)0x08)
#define	TIM1_CCER1_CC1P ((uint8_t)0x02)
#define	TIM1_CCER1_CC2E ((uint8_t)0x10)
#define	TIM1_CCER1_CC2NE ((uint8_t)0x40)
#define	TIM1_CCER1_CC2NP ((uint8_t)0x80)
#define	TIM1_CCER1_CC2P ((uint8_t)0x20)
#define	TIM1_CCER1_RESET_VALUE ((uint8_t)0x00)
#define	TIM1_CCER2_CC3E ((uint8_t)0x01)
#define	TIM1_CCER2_CC3NE ((uint8_t)0x04)
#define	TIM1_CCER2_CC3NP ((uint8_t)0x08)
#define	TIM1_CCER2_CC3P ((uint8_t)0x02)
#define	TIM1_CCER2_CC4E ((uint8_t)0x10)
#define	TIM1_CCER2_CC4P ((uint8_t)0x20)
#define	TIM1_CCER2_RESET_VALUE ((uint8_t)0x00)
#define	TIM1_CCMR1_RESET_VALUE ((uint8_t)0x00)
#define	TIM1_CCMR2_RESET_VALUE ((uint8_t)0x00)
#define	TIM1_CCMR3_RESET_VALUE ((uint8_t)0x00)
#define	TIM1_CCMR4_RESET_VALUE ((uint8_t)0x00)
#define	TIM1_CCMR_CCxS ((uint8_t)0x03)
#define	TIM1_CCMR_ICxF ((uint8_t)0xF0)
#define	TIM1_CCMR_ICxPSC ((uint8_t)0x0C)
#define	TIM1_CCMR_OCM ((uint8_t)0x70)
#define	TIM1_CCMR_OCxCE ((uint8_t)0x80)
#define	TIM1_CCMR_OCxFE ((uint8_t)0x04)
#define	TIM1_CCMR_OCxPE ((uint8_t)0x08)
#define	TIM1_CCR1H_CCR1 ((uint8_t)0xFF)
#define	TIM1_CCR1H_RESET_VALUE ((uint8_t)0x00)
#define	TIM1_CCR1L_CCR1 ((uint8_t)0xFF)
#define	TIM1_CCR1L_RESET_VALUE ((uint8_t)0x00)
#define	TIM1_CCR2H_CCR2 ((uint8_t)0xFF)
#define	TIM1_CCR2H_RESET_VALUE ((uint8_t)0x00)
#define	TIM1_CCR2L_CCR2 ((uint8_t)0xFF)
#define	TIM1_CCR2L_RESET_VALUE ((uint8_t)0x00)
#define	TIM1_CCR3H_CCR3 ((uint8_t)0xFF)
#define	TIM1_CCR3H_RESET_VALUE ((uint8_t)0x00)
#define	TIM1_CCR3L_CCR3 ((uint8_t)0xFF)
#define	TIM1_CCR3L_RESET_VALUE ((uint8_t)0x00)
#define	TIM1_CCR4H_CCR4 ((uint8_t)0xFF)
#define	TIM1_CCR4H_RESET_VALUE ((uint8_t)0x00)
#define	TIM1_CCR4L_CCR4 ((uint8_t)0xFF)
#define	TIM1_CCR4L_RESET_VALUE ((uint8_t)0x00)
#define	TIM1_CNTRH_CNT ((uint8_t)0xFF)
#define	TIM1_CNTRH_RESET_VALUE ((uint8_t)0x00)
#define	TIM1_CNTRL_CNT ((uint8_t)0xFF)
#define	TIM1_CNTRL_RESET_VALUE ((uint8_t)0x00)
#define	TIM1_CR1_ARPE ((uint8_t)0x80)
#define	TIM1_CR1_CEN ((uint8_t)0x01)
#define	TIM1_CR1_CMS ((uint8_t)0x60)
#define	TIM1_CR1_DIR ((uint8_t)0x10)
#define	TIM1_CR1_OPM ((uint8_t)0x08)
#define	TIM1_CR1_RESET_VALUE ((uint8_t)0x00)
#define	TIM1_CR1_UDIS ((uint8_t)0x02)
#define	TIM1_CR1_URS ((uint8_t)0x04)
#define	TIM1_CR2_CCDS ((uint8_t)0x08)
#define	TIM1_CR2_CCPC ((uint8_t)0x01)
#define	TIM1_CR2_CCUS ((uint8_t)0x04)
#define	TIM1_CR2_MMS ((uint8_t)0x70)
#define	TIM1_CR2_RESET_VALUE ((uint8_t)0x00)
#define	TIM1_CR2_TI1S ((uint8_t)0x80)
#define	TIM1_DCR1_DBA ((uint8_t)0x1F)
#define	TIM1_DCR1_RESET_VALUE ((uint8_t)0x00)
#define	TIM1_DCR2_DBL ((uint8_t)0x1F)
#define	TIM1_DCR2_RESET_VALUE ((uint8_t)0x00)
#define	TIM1_DER_CC1DE ((uint8_t)0x02)
#define	TIM1_DER_CC2DE ((uint8_t)0x04)
#define	TIM1_DER_CC3DE ((uint8_t)0x08)
#define	TIM1_DER_CC4DE ((uint8_t)0x10)
#define	TIM1_DER_COMDE ((uint8_t)0x20)
#define	TIM1_DER_RESET_VALUE ((uint8_t)0x00)
#define	TIM1_DER_UDE ((uint8_t)0x01)
#define	TIM1_DMAR_RESET_VALUE ((uint8_t)0x00)
#define	TIM1_DMAR_VR ((uint8_t)0xFF)
#define	TIM1_DTR_DTG ((uint8_t)0xFF)
#define	TIM1_DTR_RESET_VALUE ((uint8_t)0x00)
#define	TIM1_EGR_BG ((uint8_t)0x80)
#define	TIM1_EGR_CC1G ((uint8_t)0x02)
#define	TIM1_EGR_CC2G ((uint8_t)0x04)
#define	TIM1_EGR_CC3G ((uint8_t)0x08)
#define	TIM1_EGR_CC4G ((uint8_t)0x10)
#define	TIM1_EGR_COMG ((uint8_t)0x20)
#define	TIM1_EGR_RESET_VALUE ((uint8_t)0x00)
#define	TIM1_EGR_TG ((uint8_t)0x40)
#define	TIM1_EGR_UG ((uint8_t)0x01)
#define	TIM1_ETR_ECE ((uint8_t)0x40)
#define	TIM1_ETR_ETF ((uint8_t)0x0F)
#define	TIM1_ETR_ETP ((uint8_t)0x80)
#define	TIM1_ETR_ETPS ((uint8_t)0x30)
#define	TIM1_ETR_RESET_VALUE ((uint8_t)0x00)
#define	TIM1_IER_BIE ((uint8_t)0x80)
#define	TIM1_IER_CC1IE ((uint8_t)0x02)
#define	TIM1_IER_CC2IE ((uint8_t)0x04)
#define	TIM1_IER_CC3IE ((uint8_t)0x08)
#define	TIM1_IER_CC4IE ((uint8_t)0x10)
#define	TIM1_IER_COMIE ((uint8_t)0x20)
#define	TIM1_IER_RESET_VALUE ((uint8_t)0x00)
#define	TIM1_IER_TIE ((uint8_t)0x40)
#define	TIM1_IER_UIE ((uint8_t)0x01)
#define	TIM1_OISR_OIS1 ((uint8_t)0x01)
#define	TIM1_OISR_OIS1N ((uint8_t)0x02)
#define	TIM1_OISR_OIS2 ((uint8_t)0x04)
#define	TIM1_OISR_OIS2N ((uint8_t)0x08)
#define	TIM1_OISR_OIS3 ((uint8_t)0x10)
#define	TIM1_OISR_OIS3N ((uint8_t)0x20)
#define	TIM1_OISR_RESET_VALUE ((uint8_t)0x00)
#define	TIM1_PSCH_PSC ((uint8_t)0xFF)
#define	TIM1_PSCL_PSC ((uint8_t)0xFF)
#define	TIM1_PSCRH_RESET_VALUE ((uint8_t)0x00)
#define	TIM1_PSCRL_RESET_VALUE ((uint8_t)0x00)
#define	TIM1_RCR_REP ((uint8_t)0xFF)
#define	TIM1_RCR_RESET_VALUE ((uint8_t)0x00)
#define	TIM1_SMCR_MSM ((uint8_t)0x80)
#define	TIM1_SMCR_OCCS ((uint8_t)0x08)
#define	TIM1_SMCR_RESET_VALUE ((uint8_t)0x00)
#define	TIM1_SMCR_SMS ((uint8_t)0x07)
#define	TIM1_SMCR_TS ((uint8_t)0x70)
#define	TIM1_SR1_BIF ((uint8_t)0x80)
#define	TIM1_SR1_CC1IF ((uint8_t)0x02)
#define	TIM1_SR1_CC2IF ((uint8_t)0x04)
#define	TIM1_SR1_CC3IF ((uint8_t)0x08)
#define	TIM1_SR1_CC4IF ((uint8_t)0x10)
#define	TIM1_SR1_COMIF ((uint8_t)0x20)
#define	TIM1_SR1_RESET_VALUE ((uint8_t)0x00)
#define	TIM1_SR1_TIF ((uint8_t)0x40)
#define	TIM1_SR1_UIF ((uint8_t)0x01)
#define	TIM1_SR2_CC1OF ((uint8_t)0x02)
#define	TIM1_SR2_CC2OF ((uint8_t)0x04)
#define	TIM1_SR2_CC3OF ((uint8_t)0x08)
#define	TIM1_SR2_CC4OF ((uint8_t)0x10)
#define	TIM1_SR2_RESET_VALUE ((uint8_t)0x00)
#define	TIM2 ((TIM_TypeDef *) TIM2_BASE)
#define	TIM2_BASE (uint16_t)0x5250
#define	TIM3 ((TIM_TypeDef *) TIM3_BASE)
#define	TIM3_BASE (uint16_t)0x5280
#define	TIM4 ((TIM4_TypeDef *) TIM4_BASE)
#define	TIM4_ARR_ARR ((uint8_t)0xFF)
#define	TIM4_ARR_RESET_VALUE ((uint8_t)0xFF)
#define	TIM4_BASE (uint16_t)0x52E0
#define	TIM4_CNTR_CNT ((uint8_t)0xFF)
#define	TIM4_CNTR_RESET_VALUE ((uint8_t)0x00)
#define	TIM4_CR1_ARPE ((uint8_t)0x80)
#define	TIM4_CR1_CEN ((uint8_t)0x01)
#define	TIM4_CR1_OPM ((uint8_t)0x08)
#define	TIM4_CR1_RESET_VALUE ((uint8_t)0x00)
#define	TIM4_CR1_UDIS ((uint8_t)0x02)
#define	TIM4_CR1_URS ((uint8_t)0x04)
#define	TIM4_CR2_MMS ((uint8_t)0x70)
#define	TIM4_CR2_RESET_VALUE ((uint8_t)0x00)
#define	TIM4_DER_RESET_VALUE ((uint8_t)0x00)
#define	TIM4_DER_UDE ((uint8_t)0x01)
#define	TIM4_EGR_RESET_VALUE ((uint8_t)0x00)
#define	TIM4_EGR_TG ((uint8_t)0x40)
#define	TIM4_EGR_UG ((uint8_t)0x01)
#define	TIM4_IER_RESET_VALUE ((uint8_t)0x00)
#define	TIM4_IER_TIE ((uint8_t)0x40)
#define	TIM4_IER_UIE ((uint8_t)0x01)
#define	TIM4_PSCR_PSC ((uint8_t)0x0F)
#define	TIM4_PSCR_RESET_VALUE ((uint8_t)0x00)
#define	TIM4_SMCR_MSM ((uint8_t)0x80)
#define	TIM4_SMCR_RESET_VALUE ((uint8_t)0x00)
#define	TIM4_SMCR_SMS ((uint8_t)0x07)
#define	TIM4_SMCR_TS ((uint8_t)0x70)
#define	TIM4_SR1_RESET_VALUE ((uint8_t)0x00)
#define	TIM4_SR1_TIF ((uint8_t)0x40)
#define	TIM4_SR1_UIF ((uint8_t)0x01)
#define	TIM5 ((TIM_TypeDef *) TIM5_BASE)
#define	TIM5_BASE (uint16_t)0x5300
#define	TIM_ARRH_ARR ((uint8_t)0xFF)
#define	TIM_ARRH_RESET_VALUE ((uint8_t)0xFF)
#define	TIM_ARRL_ARR ((uint8_t)0xFF)
#define	TIM_ARRL_RESET_VALUE ((uint8_t)0xFF)
#define	TIM_BKR_AOE ((uint8_t)0x40)
#define	TIM_BKR_BKE ((uint8_t)0x10)
#define	TIM_BKR_BKP ((uint8_t)0x20)
#define	TIM_BKR_LOCK ((uint8_t)0x03)
#define	TIM_BKR_MOE ((uint8_t)0x80)
#define	TIM_BKR_OSSI ((uint8_t)0x04)
#define	TIM_BKR_RESET_VALUE ((uint8_t)0x00)
#define	TIM_CCER1_CC1E ((uint8_t)0x01)
#define	TIM_CCER1_CC1P ((uint8_t)0x02)
#define	TIM_CCER1_CC2E ((uint8_t)0x10)
#define	TIM_CCER1_CC2P ((uint8_t)0x20)
#define	TIM_CCER1_RESET_VALUE ((uint8_t)0x00)
#define	TIM_CCMR1_RESET_VALUE ((uint8_t)0x00)
#define	TIM_CCMR2_RESET_VALUE ((uint8_t)0x00)
#define	TIM_CCMR_CCxS ((uint8_t)0x03)
#define	TIM_CCMR_ICxF ((uint8_t)0xF0)
#define	TIM_CCMR_ICxPSC ((uint8_t)0x0C)
#define	TIM_CCMR_OCM ((uint8_t)0x70)
#define	TIM_CCMR_OCxFE ((uint8_t)0x04)
#define	TIM_CCMR_OCxPE ((uint8_t)0x08)
#define	TIM_CCMR_TIxDirect_Set ((uint8_t)0x01)
#define	TIM_CCR1H_CCR1 ((uint8_t)0xFF)
#define	TIM_CCR1H_RESET_VALUE ((uint8_t)0x00)
#define	TIM_CCR1L_CCR1 ((uint8_t)0xFF)
#define	TIM_CCR1L_RESET_VALUE ((uint8_t)0x00)
#define	TIM_CCR2H_CCR2 ((uint8_t)0xFF)
#define	TIM_CCR2H_RESET_VALUE ((uint8_t)0x00)
#define	TIM_CCR2L_CCR2 ((uint8_t)0xFF)
#define	TIM_CCR2L_RESET_VALUE ((uint8_t)0x00)
#define	TIM_CNTRH_CNT ((uint8_t)0xFF)
#define	TIM_CNTRH_RESET_VALUE ((uint8_t)0x00)
#define	TIM_CNTRL_CNT ((uint8_t)0xFF)
#define	TIM_CNTRL_RESET_VALUE ((uint8_t)0x00)
#define	TIM_CR1_ARPE ((uint8_t)0x80)
#define	TIM_CR1_CEN ((uint8_t)0x01)
#define	TIM_CR1_CMS ((uint8_t)0x60)
#define	TIM_CR1_DIR ((uint8_t)0x10)
#define	TIM_CR1_OPM ((uint8_t)0x08)
#define	TIM_CR1_RESET_VALUE ((uint8_t)0x00)
#define	TIM_CR1_UDIS ((uint8_t)0x02)
#define	TIM_CR1_URS ((uint8_t)0x04)
#define	TIM_CR2_CCDS ((uint8_t)0x08)
#define	TIM_CR2_MMS ((uint8_t)0x70)
#define	TIM_CR2_RESET_VALUE ((uint8_t)0x00)
#define	TIM_CR2_TI1S ((uint8_t)0x80)
#define	TIM_DER_CC1DE ((uint8_t)0x02)
#define	TIM_DER_CC2DE ((uint8_t)0x04)
#define	TIM_DER_RESET_VALUE ((uint8_t)0x00)
#define	TIM_DER_UDE ((uint8_t)0x01)
#define	TIM_EGR_BG ((uint8_t)0x80)
#define	TIM_EGR_CC1G ((uint8_t)0x02)
#define	TIM_EGR_CC2G ((uint8_t)0x04)
#define	TIM_EGR_RESET_VALUE ((uint8_t)0x00)
#define	TIM_EGR_TG ((uint8_t)0x40)
#define	TIM_EGR_UG ((uint8_t)0x01)
#define	TIM_ETR_ECE ((uint8_t)0x40)
#define	TIM_ETR_ETF ((uint8_t)0x0F)
#define	TIM_ETR_ETP ((uint8_t)0x80)
#define	TIM_ETR_ETPS ((uint8_t)0x30)
#define	TIM_ETR_RESET_VALUE ((uint8_t)0x00)
#define	TIM_IER_BIE ((uint8_t)0x80)
#define	TIM_IER_CC1IE ((uint8_t)0x02)
#define	TIM_IER_CC2IE ((uint8_t)0x04)
#define	TIM_IER_RESET_VALUE ((uint8_t)0x00)
#define	TIM_IER_TIE ((uint8_t)0x40)
#define	TIM_IER_UIE ((uint8_t)0x01)
#define	TIM_OISR_OIS1 ((uint8_t)0x01)
#define	TIM_OISR_OIS2 ((uint8_t)0x04)
#define	TIM_OISR_RESET_VALUE ((uint8_t)0x00)
#define	TIM_PSCR_PSC ((uint8_t)0x07)
#define	TIM_PSCR_RESET_VALUE ((uint8_t)0x00)
#define	TIM_SMCR_MSM ((uint8_t)0x80)
#define	TIM_SMCR_RESET_VALUE ((uint8_t)0x00)
#define	TIM_SMCR_SMS ((uint8_t)0x07)
#define	TIM_SMCR_TS ((uint8_t)0x70)
#define	TIM_SR1_BIF ((uint8_t)0x80)
#define	TIM_SR1_CC1IF ((uint8_t)0x02)
#define	TIM_SR1_CC2IF ((uint8_t)0x04)
#define	TIM_SR1_RESET_VALUE ((uint8_t)0x00)
#define	TIM_SR1_TIF ((uint8_t)0x40)
#define	TIM_SR1_UIF ((uint8_t)0x01)
#define	TIM_SR2_CC1OF ((uint8_t)0x02)
#define	TIM_SR2_CC2OF ((uint8_t)0x04)
#define	TIM_SR2_RESET_VALUE ((uint8_t)0x00)
#define	TINY __tiny
#define	trap() __trap()
#define	U16_MAX (65535u)
#define	U32_MAX (4294967295uL)
#define	U8_MAX (255)
#define	USART1 ((USART_TypeDef *) USART1_BASE)
#define	USART1_BASE (uint16_t)0x5230
#define	USART2 ((USART_TypeDef *) USART2_BASE)
#define	USART2_BASE (uint16_t)0x53E0
#define	USART3 ((USART_TypeDef *) USART3_BASE)
#define	USART3_BASE (uint16_t)0x53F0
#define	USART_BRR1_DIVM ((uint8_t)0xFF)
#define	USART_BRR1_RESET_VALUE ((uint8_t)0x00)
#define	USART_BRR2_DIVF ((uint8_t)0x0F)
#define	USART_BRR2_DIVM ((uint8_t)0xF0)
#define	USART_BRR2_RESET_VALUE ((uint8_t)0x00)
#define	USART_CR1_M ((uint8_t)0x10)
#define	USART_CR1_PCEN ((uint8_t)0x04)
#define	USART_CR1_PIEN ((uint8_t)0x01)
#define	USART_CR1_PS ((uint8_t)0x02)
#define	USART_CR1_R8 ((uint8_t)0x80)
#define	USART_CR1_RESET_VALUE ((uint8_t)0x00)
#define	USART_CR1_T8 ((uint8_t)0x40)
#define	USART_CR1_USARTD ((uint8_t)0x20)
#define	USART_CR1_WAKE ((uint8_t)0x08)
#define	USART_CR2_ILIEN ((uint8_t)0x10)
#define	USART_CR2_REN ((uint8_t)0x04)
#define	USART_CR2_RESET_VALUE ((uint8_t)0x00)
#define	USART_CR2_RIEN ((uint8_t)0x20)
#define	USART_CR2_RWU ((uint8_t)0x02)
#define	USART_CR2_SBK ((uint8_t)0x01)
#define	USART_CR2_TCIEN ((uint8_t)0x40)
#define	USART_CR2_TEN ((uint8_t)0x08)
#define	USART_CR2_TIEN ((uint8_t)0x80)
#define	USART_CR3_CLKEN ((uint8_t)0x08)
#define	USART_CR3_CPHA ((uint8_t)0x02)
#define	USART_CR3_CPOL ((uint8_t)0x04)
#define	USART_CR3_LBCL ((uint8_t)0x01)
#define	USART_CR3_RESET_VALUE ((uint8_t)0x00)
#define	USART_CR3_STOP ((uint8_t)0x30)
#define	USART_CR4_ADD ((uint8_t)0x0F)
#define	USART_CR4_RESET_VALUE ((uint8_t)0x00)
#define	USART_CR5_DMAR ((uint8_t)0x40)
#define	USART_CR5_DMAT ((uint8_t)0x80)
#define	USART_CR5_EIE ((uint8_t)0x01)
#define	USART_CR5_HDSEL ((uint8_t)0x08)
#define	USART_CR5_IREN ((uint8_t)0x02)
#define	USART_CR5_IRLP ((uint8_t)0x04)
#define	USART_CR5_NACK ((uint8_t)0x10)
#define	USART_CR5_SCEN ((uint8_t)0x20)
#define	USART_SR_FE ((uint8_t)0x02)
#define	USART_SR_IDLE ((uint8_t)0x10)
#define	USART_SR_NF ((uint8_t)0x04)
#define	USART_SR_OR ((uint8_t)0x08)
#define	USART_SR_PE ((uint8_t)0x01)
#define	USART_SR_RESET_VALUE ((uint8_t)0xC0)
#define	USART_SR_RXNE ((uint8_t)0x20)
#define	USART_SR_TC ((uint8_t)0x40)
#define	USART_SR_TXE ((uint8_t)0x80)
#define	USE_STDPERIPH_DRIVER
#define	ValBit(VAR, Place) ((uint8_t)(VAR) & (uint8_t)((uint8_t)1<<(uint8_t)(Place)))
#define	wfe() __wait_for_event();
#define	WFE ((WFE_TypeDef *) WFE_BASE)
#define	WFE_BASE (uint16_t)0x50A6
#define	WFE_CR1_EXTI_EV0 ((uint8_t)0x10)
#define	WFE_CR1_EXTI_EV1 ((uint8_t)0x20)
#define	WFE_CR1_EXTI_EV2 ((uint8_t)0x40)
#define	WFE_CR1_EXTI_EV3 ((uint8_t)0x80)
#define	WFE_CR1_TIM1_EV0 ((uint8_t)0x04)
#define	WFE_CR1_TIM1_EV1 ((uint8_t)0x08)
#define	WFE_CR1_TIM2_EV0 ((uint8_t)0x01)
#define	WFE_CR1_TIM2_EV1 ((uint8_t)0x02)
#define	WFE_CR2_ADC1_COMP_EV ((uint8_t)0x80)
#define	WFE_CR2_EXTI_EV4 ((uint8_t)0x01)
#define	WFE_CR2_EXTI_EV5 ((uint8_t)0x02)
#define	WFE_CR2_EXTI_EV6 ((uint8_t)0x04)
#define	WFE_CR2_EXTI_EV7 ((uint8_t)0x08)
#define	WFE_CR2_EXTI_EVBG ((uint8_t)0x10)
#define	WFE_CR2_EXTI_EVDH ((uint8_t)0x20)
#define	WFE_CR2_EXTI_EVEF ((uint8_t)0x40)
#define	WFE_CR3_DMA1CH01_EV ((uint8_t)0x40)
#define	WFE_CR3_DMA1CH23_EV ((uint8_t)0x80)
#define	WFE_CR3_I2C1_EV ((uint8_t)0x10)
#define	WFE_CR3_SPI1_EV ((uint8_t)0x08)
#define	WFE_CR3_TIM3_EV0 ((uint8_t)0x01)
#define	WFE_CR3_TIM3_EV1 ((uint8_t)0x02)
#define	WFE_CR3_TIM4_EV ((uint8_t)0x04)
#define	WFE_CR3_USART1_EV ((uint8_t)0x20)
#define	WFE_CR4_AES_EV ((uint8_t)0x40)
#define	WFE_CR4_RTC_CSS_EV ((uint8_t)0x01)
#define	WFE_CR4_SPI2_EV ((uint8_t)0x02)
#define	WFE_CR4_TIM5_EV0 ((uint8_t)0x10)
#define	WFE_CR4_TIM5_EV1 ((uint8_t)0x20)
#define	WFE_CR4_USART2_EV ((uint8_t)0x04)
#define	WFE_CR4_USART3_EV ((uint8_t)0x08)
#define	WFE_CRX_RESET_VALUE ((uint8_t)0x00)
#define	wfi() __wait_for_interrupt()
#define	WWDG ((WWDG_TypeDef *) WWDG_BASE)
#define	WWDG_BASE (uint16_t)0x50D3
#define	WWDG_CR_RESET_VALUE ((uint8_t)0x7F)
#define	WWDG_CR_T ((uint8_t)0x7F)
#define	WWDG_CR_T6 ((uint8_t)0x40)
#define	WWDG_CR_WDGA ((uint8_t)0x80)
#define	WWDG_WR_MSB ((uint8_t)0x80)
#define	WWDG_WR_RESET_VALUE ((uint8_t)0x7F)
#define	WWDG_WR_W ((uint8_t)0x7F)
Typedefs
typedef struct ADC_struct	ADC_TypeDef
	Analog to Digital Converter (ADC) peripheral.
typedef struct AES_struct	AES_TypeDef
	AES tiny (AES)
typedef struct BEEP_struct	BEEP_TypeDef
	Beeper (BEEP) peripheral registers.
typedef enum FlagStatus	BitAction
typedef enum FlagStatus	BitStatus
typedef struct CFG_struct	CFG_TypeDef
	Configuration Registers (CFG)
typedef struct CLK_struct	CLK_TypeDef
	Clock Controller (CLK)
typedef struct COMP_struct	COMP_TypeDef
	Comparator interface (COMP)
typedef struct CSSLSE_struct	CSSLSE_TypeDef
	CSS on LSE registers.
typedef struct DAC_struct	DAC_TypeDef
	Digital to Analog Converter (DAC) peripheral.
typedef struct DMA_Channel_struct	DMA_Channel_TypeDef
typedef struct DMA_struct	DMA_TypeDef
	Direct-Memory Access (DMA)
typedef struct EXTI_struct	EXTI_TypeDef
	External Interrupt Controller (EXTI)
typedef struct FLASH_struct	FLASH_TypeDef
	FLASH and Data EEPROM.
typedef struct GPIO_struct	GPIO_TypeDef
	General Purpose I/Os (GPIO)
typedef struct I2C_struct	I2C_TypeDef
	Inter-Integrated Circuit (I2C)
typedef signed short	int16_t
typedef signed long	int32_t
typedef signed char	int8_t
typedef struct IRTIM_struct	IRTIM_TypeDef
	IR digital interface (IRTIM)
typedef struct ITC_struct	ITC_TypeDef
	Interrupt Controller (ITC)
typedef enum FlagStatus	ITStatus
typedef struct IWDG_struct	IWDG_TypeDef
	Internal Low Speed Watchdog (IWDG)
typedef struct LCD_struct	LCD_TypeDef
	LCD Controller (LCD)
typedef struct OPT_struct	OPT_TypeDef
	Option Bytes (OPT)
typedef struct PWR_struct	PWR_TypeDef
	Power Control (PWR)
typedef struct RI_struct	RI_TypeDef
	Routing Interface (RI)
typedef struct RST_struct	RST_TypeDef
	Reset Controller (RST)
typedef struct RTC_struct	RTC_TypeDef
	Real-Time Clock (RTC) peripheral registers.
typedef int16_t	s16
typedef int32_t	s32
typedef int8_t	s8
typedef struct SPI_struct	SPI_TypeDef
	Serial Peripheral Interface (SPI)
typedef struct SYSCFG_struct	SYSCFG_TypeDef
	SYSCFG.
typedef struct TIM1_struct	TIM1_TypeDef
	Advanced 16 bit timer with complementary PWM outputs (TIM1)
typedef struct TIM4_struct	TIM4_TypeDef
	8-bit system or Low End Small Timer (TIM4)
typedef struct TIM_struct	TIM_TypeDef
	16 bit timer :TIM2, TIM3 & TIM5
typedef uint16_t	u16
typedef uint32_t	u32
typedef uint8_t	u8
typedef unsigned short	uint16_t
typedef unsigned long	uint32_t
typedef unsigned char	uint8_t
typedef struct USART_struct	USART_TypeDef
	USART.
typedef struct WFE_struct	WFE_TypeDef
typedef struct WWDG_struct	WWDG_TypeDef
	Window Watchdog (WWDG)
Enumerations
enum	bool { FALSE = 0, TRUE = !FALSE }
enum	ErrorStatus { ERROR = 0, SUCCESS = !ERROR }
enum	FlagStatus { RESET = 0, SET = !RESET }
enum	FunctionalState { DISABLE = 0, ENABLE = !DISABLE }

Detailed Description

This file contains all the peripheral register's definitions, bits definitions and memory mapping for STM8L15x devices.

Author:: MCD Application Team

Version:: V1.5.0

Date:: 13-May-2011

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.