Clears the DMA Channels selected flags.

Parameters:

DMA_FLAG,:

specifies the flag to clear. This parameter can be one or a combination (for the same channel)of the following values: DMA1_FLAG_TC0: Transaction Complete Interrupt Flag Channel 0 DMA1_FLAG_TC1: Transaction Complete Interrupt Flag Channel 1 DMA1_FLAG_TC2: Transaction Complete Interrupt Flag Channel 2 DMA1_FLAG_TC2: Transaction Complete Interrupt Flag Channel 3 DMA1_FLAG_HT0: Half Transaction Interrupt Flag Channel 0 DMA1_FLAG_HT1: Half Transaction Interrupt Flag Channel 1 DMA1_FLAG_HT2: Half Transaction Interrupt Flag Channel 2 DMA1_FLAG_HT3: Half Transaction Interrupt Flag Channel 3

Return values:

None

Definition at line 591 of file stm8l15x_dma.c.

References DMA_Channel_struct::CSPR, DMA1_Channel0, DMA1_Channel1, DMA1_Channel2, DMA1_Channel3, IS_DMA_CLEAR_FLAG, and RESET.

Clears the DMA Channelx�s interrupt pending bits.

Parameters:

DMA_IT,:

specifies the DMA interrupt pending bit to clear. This parameter can be one or a combination(for the same channel)of the following values: DMA1_IT_TC0: Transaction Complete Interrupt Channel 0 DMA1_IT_TC1: Transaction Complete Interrupt Channel 1 DMA1_IT_TC2: Transaction Complete Interrupt Channel 2 DMA1_IT_TC3: Transaction Complete Interrupt Channel 3 DMA1_IT_HT0: Half Transaction Interrupt Channel 0 DMA1_IT_HT1: Half Transaction Interrupt Channel 1 DMA1_IT_HT2: Half Transaction Interrupt Channel 2 DMA1_IT_HT3: Half Transaction Interrupt Channel 3

Return values:

None

Definition at line 698 of file stm8l15x_dma.c.

References DMA_Channel_struct::CSPR, DMA1_Channel0, DMA1_Channel1, DMA1_Channel2, DMA1_Channel3, IS_DMA_CLEAR_IT, and RESET.

Enables or disables the specified DMA Channelx.

Note:

DMA_GlobalCmd function must be called first to enable or disable the global DMA.

Parameters:

DMA_Channelx,:	selects the DMA Channelx where x can be 0 to 3
NewState,:	new state of the DMA Channelx. This parameter can be: ENABLE or DISABLE.

Return values:

None

Definition at line 308 of file stm8l15x_dma.c.

References DMA_Channel_struct::CCR, DISABLE, DMA_CCR_CE, IS_DMA_CHANNEL, and IS_FUNCTIONAL_STATE.

Deinitializes the DMA Channelx registers to their default reset values.

Parameters:

DMA_Channelx,:

selects the DMA Channelx where x can be 0 to 3

Return values:

None

Definition at line 149 of file stm8l15x_dma.c.

References DMA_Channel_struct::CCR, DMA_Channel_struct::CM0ARH, DMA_Channel_struct::CM0ARL, DMA_Channel_struct::CM0EAR, DMA_Channel_struct::CNBTR, DMA_Channel_struct::CPARH, DMA_Channel_struct::CPARL, DMA_Channel_struct::CSPR, DMA1_Channel3, DMA_C3M0EAR_RESET_VALUE, DMA_C3PARH_RESET_VALUE, DMA_CCR_CE, DMA_CCR_RESET_VALUE, DMA_CM0ARH_RESET_VALUE, DMA_CM0ARL_RESET_VALUE, DMA_CNBTR_RESET_VALUE, DMA_CPARH_RESET_VALUE, DMA_CPARL_RESET_VALUE, DMA_CSPR_RESET_VALUE, and IS_DMA_CHANNEL.

Returns the number of remaining data units in the current DMA Channelx transfer.

Parameters:

DMA_Channelx,:

selects the DMA Channelx where x can be 0 to 3

Return values:

The	number of remaining data units in the current DMA Channelx

Definition at line 409 of file stm8l15x_dma.c.

References DMA_Channel_struct::CNBTR, and IS_DMA_CHANNEL.

Checks whether the specified DMA Channelx flag is set or not.

Parameters:

DMA_FLAG,:

specifies the flag to check. This parameter can be one of the following values: DMA1_FLAG_GB: Global Busy Flag DMA1_FLAG_IFC0: Global Interrupt Flag Channel 0 DMA1_FLAG_IFC1: Global Interrupt Flag Channel 1 DMA1_FLAG_IFC2: Global Interrupt Flag Channel 2 DMA1_FLAG_IFC3: Global Interrupt Flag Channel 3 DMA1_FLAG_TC0: Transaction Complete Interrupt Flag Channel 0 DMA1_FLAG_TC1: Transaction Complete Interrupt Flag Channel 1 DMA1_FLAG_TC2: Transaction Complete Interrupt Flag Channel 2 DMA1_FLAG_TC2: Transaction Complete Interrupt Flag Channel 3 DMA1_FLAG_HT0: Half Transaction Interrupt Flag Channel 0 DMA1_FLAG_HT1: Half Transaction Interrupt Flag Channel 1 DMA1_FLAG_HT2: Half Transaction Interrupt Flag Channel 2 DMA1_FLAG_HT3: Half Transaction Interrupt Flag Channel 3 DMA1_FLAG_PEND0: DMA Request pending on Channel 0 DMA1_FLAG_PEND1: DMA Request pending on Channel 1 DMA1_FLAG_PEND2: DMA Request pending on Channel 2 DMA1_FLAG_PEND3: DMA Request pending on Channel 3 DMA1_FLAG_BUSY0: No DMA transfer on going in Channel 0 DMA1_FLAG_BUSY1: No DMA transfer on going in Channel 1 DMA1_FLAG_BUSY2: No DMA transfer on going in Channel 2 DMA1_FLAG_BUSY3: No DMA transfer on going in Channel 3

Return values:

The	status of DMA_FLAG (SET or RESET).

Definition at line 524 of file stm8l15x_dma.c.

References DMA_Channel_struct::CSPR, DMA1, DMA1_Channel0, DMA1_Channel1, DMA1_Channel2, DMA1_Channel3, DMA_GCSR_GB, IS_DMA_GET_FLAG, and RESET.

Checks whether the specified DMA Channelx interrupt has occurred or not.

Parameters:

DMA_IT,:

specifies the DMA interrupt source to check. This parameter can be one or a combination of the following values: DMA1_IT_TC0: Transaction Complete Interrupt Channel 0 DMA1_IT_TC1: Transaction Complete Interrupt Channel 1 DMA1_IT_TC2: Transaction Complete Interrupt Channel 2 DMA1_IT_TC3: Transaction Complete Interrupt Channel 3 DMA1_IT_HT0: Half Transaction Interrupt Channel 0 DMA1_IT_HT1: Half Transaction Interrupt Channel 1 DMA1_IT_HT2: Half Transaction Interrupt Channel 2 DMA1_IT_HT3: Half Transaction Interrupt Channel 3

Return values:

ITStatus,:

The status of DMA_IT (SET or RESET).

Definition at line 640 of file stm8l15x_dma.c.

References DMA_Channel_struct::CCR, DMA_Channel_struct::CSPR, DMA1_Channel0, DMA1_Channel1, DMA1_Channel2, DMA1_Channel3, DMA_CCR_HTIE, DMA_CCR_TCIE, IS_DMA_GET_IT, and RESET.

Enables or disables All the DMA.

Parameters:

NewState,:

new state of the DMA. This parameter can be: ENABLE or DISABLE.

Return values:

None

Definition at line 282 of file stm8l15x_dma.c.

References DISABLE, DMA1, DMA_GCSR_GE, and IS_FUNCTIONAL_STATE.

Deinitializes the DMA Global Status register to its default reset values.

Parameters:

None

Return values:

None

Definition at line 134 of file stm8l15x_dma.c.

References DMA1, DMA_GCSR_GE, and DMA_GCSR_RESET_VALUE.

Initializes the DMA Channelx according to the specified parameters.

Parameters:

DMA_Channelx,:	selects the DMA Channelx where x can be 0 to 3
DMA_Memory0BaseAddr,:	Specifies Memory 0 Base Address
DMA_PeripheralMemory1BaseAddr,:	Specifies DMA channelx Peripheral Base Address (if data is from/to peripheral) or DMA channelx Memory1 Base Address (if data is from Memory0 to Memory1).
DMA_BufferSize,:	Specifies the size of the DMA channelx Buffer. This parameter must be a value greater than 0.
DMA_DIR,:	Specifies the DMA Channelx transfer direction. This parameter can be one of the following values: DMA_DIR_PeripheralToMemory: Data transfer direction is Peripheral To Memory DMA_DIR_MemoryToPeripheral: Data transfer direction is Memory To Peripheral DMA_DIR_Memory0ToMemory1: Data transfer direction is Memory0 To Memory 1
DMA_Mode,:	Specifies the DMA channelx mode. This parameter can be one of the following values: DMA_Mode_Normal: DMA normal buffer mode DMA_Mode_Circular: DMA circular buffer mode
DMA_MemoryIncMode,:	Specifies the DMA channelx memory Incremental/Decremental mode This parameter can be one of the following values: DMA_MemoryIncMode_Dec: DMA memory incremented mode is decremental DMA_MemoryIncMode_Inc: DMA memory incremented mode is incremental
DMA_Priority,:	Specifies the DMA channelx priority. This parameter can be one of the following values: DMA_Priority_Low: Software Priority is Low DMA_Priority_Medium: Software Priority is Medium DMA_Priority_High: Software Priority is High DMA_Priority_VeryHigh: Software Priority is Very High
DMA_MemoryDataSize,:	Specifies the DMA channelx transfer Data size This parameter can be one of the following values: DMA_MemoryDataSize_Byte: Memory Data Size is 1 Byte DMA_MemoryDataSize_HalfWord: Memory Data Size is 2 Bytes

Return values:

None

Definition at line 218 of file stm8l15x_dma.c.

References DMA_Channel_struct::CCR, DMA_Channel_struct::CM0ARH, DMA_Channel_struct::CM0ARL, DMA_Channel_struct::CM0EAR, DMA_Channel_struct::CNBTR, DMA_Channel_struct::CPARH, DMA_Channel_struct::CPARL, DMA_Channel_struct::CSPR, DMA1_Channel3, DMA_CCR_CE, DMA_CCR_RESET_VALUE, DMA_CSPR_16BM, DMA_CSPR_PL, IS_DMA_BUFFER_SIZE, IS_DMA_CHANNEL, IS_DMA_DIR, IS_DMA_MEMORY_INC_MODE, IS_DMA_MODE, and IS_DMA_PRIORITY.

Enables or disables the specified DMA Channelx interrupts.

Parameters:

DMA_Channelx,:	selects the DMA Channelx where x can be 0 to 3
DMA_ITx,:	specifies the DMA interrupts sources to be enabled or disabled. This parameter can be one of the following values: DMA_ITx_TC: Transaction Complete Interrupt DMA_ITx_HT: Half Transaction Interrupt
NewState,:	new state of the specified DMA interrupts. This parameter can be: ENABLE or DISABLE.

Return values:

None

Definition at line 476 of file stm8l15x_dma.c.

References DMA_Channel_struct::CCR, DISABLE, IS_DMA_CHANNEL, IS_DMA_CONFIG_ITX, and IS_FUNCTIONAL_STATE.

Set the number of data units to transfer for DMA Channelx.

Parameters:

DMA_Channelx,:	selects the DMA Channelx where x can be 0 to 3
DataNumber,:	The number of data units to transfer, it can be any value from 0 to 255

Note:

It is advised to use this function rather than DMA_Init() in situations where only the Data buffer needs to be reloaded.

Return values:

None

Definition at line 395 of file stm8l15x_dma.c.

References DMA_Channel_struct::CNBTR, and IS_DMA_CHANNEL.

Sets the Time out Value.

Parameters:

DMA_TimeOut,:

an integer from 0 to 63

Note:

If timeout duration >0 (number of wait cycles starting from the latest request), the DMA waits until this timeout has elapsed before requesting from the core a high priority access to the bus.

If timeout duration =0, there is no timeout and once a request is served, the DMA immediately asks to the CPU a high priority access to the bus.

Return values:

None

Definition at line 336 of file stm8l15x_dma.c.

References DMA1, and IS_DMA_TIMEOUT.