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STM8L15x Standard Peripherals Drivers
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stm8l15x_clk.h
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00001 /** 00002 ****************************************************************************** 00003 * @file stm8l15x_clk.h 00004 * @author MCD Application Team 00005 * @version V1.5.0 00006 * @date 13-May-2011 00007 * @brief This file contains all the functions prototypes for the CLK firmware 00008 * library. 00009 ****************************************************************************** 00010 * @attention 00011 * 00012 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 00013 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 00014 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 00015 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 00016 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 00017 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 00018 * 00019 * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> 00020 ****************************************************************************** 00021 */ 00022 00023 00024 /* Define to prevent recursive inclusion -------------------------------------*/ 00025 #ifndef __STM8L15x_CLK_H 00026 #define __STM8L15x_CLK_H 00027 00028 /* Includes ------------------------------------------------------------------*/ 00029 #include "stm8l15x.h" 00030 00031 /** @addtogroup STM8L15x_StdPeriph_Driver 00032 * @{ 00033 */ 00034 00035 /** @addtogroup CLK 00036 * @{ 00037 */ 00038 /* Exported types ------------------------------------------------------------*/ 00039 00040 /** @defgroup Exported_Types 00041 * @{ 00042 */ 00043 00044 /** @defgroup CLK_HSE_Configuration 00045 * @{ 00046 */ 00047 typedef enum { 00048 CLK_HSE_OFF = (uint8_t)0x00, /*!< HSE Diasble */ 00049 CLK_HSE_ON = (uint8_t)0x01, /*!< HSE Enable */ 00050 CLK_HSE_Bypass = (uint8_t)0x11 /*!< HSE Bypass and enable */ 00051 } CLK_HSE_TypeDef; 00052 00053 #define IS_CLK_HSE(CONFIG) (((CONFIG) == CLK_HSE_ON) ||\ 00054 ((CONFIG) == CLK_HSE_OFF)||\ 00055 ((CONFIG) == CLK_HSE_Bypass)) 00056 /** 00057 * @} 00058 */ 00059 00060 /** @defgroup CLK_LSE_Configuration 00061 * @{ 00062 */ 00063 typedef enum { 00064 CLK_LSE_OFF = (uint8_t)0x00, /*!< LSE Diasble */ 00065 CLK_LSE_ON = (uint8_t)0x04, /*!< LSE Enable */ 00066 CLK_LSE_Bypass = (uint8_t)0x24 /*!< LSE Bypass and enable */ 00067 } CLK_LSE_TypeDef; 00068 00069 #define IS_CLK_LSE(CONFIG) (((CONFIG) == CLK_LSE_OFF) ||\ 00070 ((CONFIG) == CLK_LSE_ON) ||\ 00071 ((CONFIG) == CLK_LSE_Bypass)) 00072 /** 00073 * @} 00074 */ 00075 00076 /** @defgroup CLK_System_Clock_Sources 00077 * @{ 00078 */ 00079 typedef enum { 00080 CLK_SYSCLKSource_HSI = (uint8_t)0x01, /*!< System Clock Source HSI */ 00081 CLK_SYSCLKSource_LSI = (uint8_t)0x02, /*!< System Clock Source LSI */ 00082 CLK_SYSCLKSource_HSE = (uint8_t)0x04, /*!< System Clock Source HSE */ 00083 CLK_SYSCLKSource_LSE = (uint8_t)0x08 /*!< System Clock Source LSE */ 00084 } CLK_SYSCLKSource_TypeDef; 00085 00086 #define IS_CLK_SOURCE(SOURCE) (((SOURCE) == CLK_SYSCLKSource_HSI) ||\ 00087 ((SOURCE) == CLK_SYSCLKSource_LSI) ||\ 00088 ((SOURCE) == CLK_SYSCLKSource_HSE) ||\ 00089 ((SOURCE) == CLK_SYSCLKSource_LSE)) 00090 /** 00091 * @} 00092 */ 00093 00094 /** @defgroup CLK_Clock_Output_Selection 00095 * @{ 00096 */ 00097 typedef enum { 00098 CLK_CCOSource_Off = (uint8_t)0x00, /*!< Clock Output Off */ 00099 CLK_CCOSource_HSI = (uint8_t)0x02, /*!< HSI Clock Output */ 00100 CLK_CCOSource_LSI = (uint8_t)0x04, /*!< LSI Clock Output */ 00101 CLK_CCOSource_HSE = (uint8_t)0x08, /*!< HSE Clock Output */ 00102 CLK_CCOSource_LSE = (uint8_t)0x10 /*!< LSE Clock Output */ 00103 } CLK_CCOSource_TypeDef; 00104 00105 #define IS_CLK_OUTPUT(OUTPUT) (((OUTPUT) == CLK_CCOSource_Off) ||\ 00106 ((OUTPUT) == CLK_CCOSource_HSI) ||\ 00107 ((OUTPUT) == CLK_CCOSource_LSI) ||\ 00108 ((OUTPUT) == CLK_CCOSource_HSE) ||\ 00109 ((OUTPUT) == CLK_CCOSource_LSE)) 00110 /** 00111 * @} 00112 */ 00113 00114 /** @defgroup CLK_Clock_Output_Prescaler 00115 * @{ 00116 */ 00117 typedef enum { 00118 CLK_CCODiv_1 = (uint8_t)0x00, /*!< Clock Output Div 1 */ 00119 CLK_CCODiv_2 = (uint8_t)0x20, /*!< Clock Output Div 2 */ 00120 CLK_CCODiv_4 = (uint8_t)0x40, /*!< Clock Output Div 4 */ 00121 CLK_CCODiv_8 = (uint8_t)0x60, /*!< Clock Output Div 8 */ 00122 CLK_CCODiv_16 = (uint8_t)0x80, /*!< Clock Output Div 16 */ 00123 CLK_CCODiv_32 = (uint8_t)0xA0, /*!< Clock Output Div 32 */ 00124 CLK_CCODiv_64 = (uint8_t)0xC0 /*!< Clock Output Div 64 */ 00125 } CLK_CCODiv_TypeDef; 00126 00127 #define IS_CLK_OUTPUT_DIVIDER(PRESCALER) (((PRESCALER) == CLK_CCODiv_1) ||\ 00128 ((PRESCALER) == CLK_CCODiv_2) ||\ 00129 ((PRESCALER) == CLK_CCODiv_4) ||\ 00130 ((PRESCALER) == CLK_CCODiv_8) ||\ 00131 ((PRESCALER) == CLK_CCODiv_16) ||\ 00132 ((PRESCALER) == CLK_CCODiv_32) ||\ 00133 ((PRESCALER) == CLK_CCODiv_64)) 00134 /** 00135 * @} 00136 */ 00137 00138 /** @defgroup CLK_Beep_Selection 00139 * @{ 00140 */ 00141 typedef enum { 00142 CLK_BEEPCLKSource_Off = (uint8_t)0x00, /*!< Clock BEEP Off */ 00143 CLK_BEEPCLKSource_LSI = (uint8_t)0x02, /*!< Clock BEEP : LSI */ 00144 CLK_BEEPCLKSource_LSE = (uint8_t)0x04 /*!< Clock BEEP : LSE */ 00145 } CLK_BEEPCLKSource_TypeDef; 00146 00147 #define IS_CLK_CLOCK_BEEP(OUTPUT) (((OUTPUT) == CLK_BEEPCLKSource_Off) ||\ 00148 ((OUTPUT) == CLK_BEEPCLKSource_LSI) ||\ 00149 ((OUTPUT) == CLK_BEEPCLKSource_LSE)) 00150 /** 00151 * @} 00152 */ 00153 00154 /** @defgroup CLK_RTC_Selection 00155 * @{ 00156 */ 00157 typedef enum { 00158 CLK_RTCCLKSource_Off = (uint8_t)0x00, /*!< Clock RTC Off */ 00159 CLK_RTCCLKSource_HSI = (uint8_t)0x02, /*!< Clock RTC : HSI */ 00160 CLK_RTCCLKSource_LSI = (uint8_t)0x04, /*!< Clock RTC : LSI */ 00161 CLK_RTCCLKSource_HSE = (uint8_t)0x08, /*!< Clock RTC : HSE */ 00162 CLK_RTCCLKSource_LSE = (uint8_t)0x10 /*!< Clock RTC : LSE */ 00163 } CLK_RTCCLKSource_TypeDef; 00164 00165 #define IS_CLK_CLOCK_RTC(OUTPUT) (((OUTPUT) == CLK_RTCCLKSource_Off) ||\ 00166 ((OUTPUT) == CLK_RTCCLKSource_HSI) ||\ 00167 ((OUTPUT) == CLK_RTCCLKSource_LSI) ||\ 00168 ((OUTPUT) == CLK_RTCCLKSource_HSE) ||\ 00169 ((OUTPUT) == CLK_RTCCLKSource_LSE)) 00170 /** 00171 * @} 00172 */ 00173 00174 /** @defgroup CLK_RTC_Prescaler 00175 * @{ 00176 */ 00177 typedef enum { 00178 CLK_RTCCLKDiv_1 = (uint8_t)0x00, /*!< Clock RTC Div 1 */ 00179 CLK_RTCCLKDiv_2 = (uint8_t)0x20, /*!< Clock RTC Div 2 */ 00180 CLK_RTCCLKDiv_4 = (uint8_t)0x40, /*!< Clock RTC Div 4 */ 00181 CLK_RTCCLKDiv_8 = (uint8_t)0x60, /*!< Clock RTC Div 8 */ 00182 CLK_RTCCLKDiv_16 = (uint8_t)0x80, /*!< Clock RTC Div 16 */ 00183 CLK_RTCCLKDiv_32 = (uint8_t)0xA0, /*!< Clock RTC Div 32 */ 00184 CLK_RTCCLKDiv_64 = (uint8_t)0xC0 /*!< Clock RTC Div 64 */ 00185 } CLK_RTCCLKDiv_TypeDef; 00186 00187 #define IS_CLK_CLOCK_RTC_DIV(DIV) (((DIV) == CLK_RTCCLKDiv_1) ||\ 00188 ((DIV) == CLK_RTCCLKDiv_2) ||\ 00189 ((DIV) == CLK_RTCCLKDiv_4) ||\ 00190 ((DIV) == CLK_RTCCLKDiv_8) ||\ 00191 ((DIV) == CLK_RTCCLKDiv_16) ||\ 00192 ((DIV) == CLK_RTCCLKDiv_32) ||\ 00193 ((DIV) == CLK_RTCCLKDiv_64)) 00194 /** 00195 * @} 00196 */ 00197 00198 /** @defgroup CLK_Peripherals 00199 * @{ 00200 */ 00201 /* Elements values convention: 0xXY 00202 X = choice between the peripheral registers 00203 X = 0 : PCKENR1 00204 X = 1 : PCKENR2 00205 X = 2 : PCKENR3 00206 Y = Peripheral position in the register 00207 */ 00208 typedef enum { 00209 CLK_Peripheral_TIM2 = (uint8_t)0x00, /*!< Peripheral Clock Enable 1, TIM2 */ 00210 CLK_Peripheral_TIM3 = (uint8_t)0x01, /*!< Peripheral Clock Enable 1, TIM3 */ 00211 CLK_Peripheral_TIM4 = (uint8_t)0x02, /*!< Peripheral Clock Enable 1, TIM4 */ 00212 CLK_Peripheral_I2C1 = (uint8_t)0x03, /*!< Peripheral Clock Enable 1, I2C1 */ 00213 CLK_Peripheral_SPI1 = (uint8_t)0x04, /*!< Peripheral Clock Enable 1, SPI1 */ 00214 CLK_Peripheral_USART1 = (uint8_t)0x05, /*!< Peripheral Clock Enable 1, USART1 */ 00215 CLK_Peripheral_BEEP = (uint8_t)0x06, /*!< Peripheral Clock Enable 1, BEEP */ 00216 CLK_Peripheral_DAC = (uint8_t)0x07, /*!< Peripheral Clock Enable 1, DAC */ 00217 CLK_Peripheral_ADC1 = (uint8_t)0x10, /*!< Peripheral Clock Enable 2, ADC1 */ 00218 CLK_Peripheral_TIM1 = (uint8_t)0x11, /*!< Peripheral Clock Enable 2, TIM1 */ 00219 CLK_Peripheral_RTC = (uint8_t)0x12, /*!< Peripheral Clock Enable 2, RTC */ 00220 CLK_Peripheral_LCD = (uint8_t)0x13, /*!< Peripheral Clock Enable 2, LCD */ 00221 CLK_Peripheral_DMA1 = (uint8_t)0x14, /*!< Peripheral Clock Enable 2, DMA1 */ 00222 CLK_Peripheral_COMP = (uint8_t)0x15, /*!< Peripheral Clock Enable 2, COMP1 and COMP2 */ 00223 CLK_Peripheral_BOOTROM = (uint8_t)0x17,/*!< Peripheral Clock Enable 2, Boot ROM */ 00224 CLK_Peripheral_AES = (uint8_t)0x20, /*!< Peripheral Clock Enable 3, AES */ 00225 CLK_Peripheral_TIM5 = (uint8_t)0x21, /*!< Peripheral Clock Enable 3, TIM5 */ 00226 CLK_Peripheral_SPI2 = (uint8_t)0x22, /*!< Peripheral Clock Enable 3, SPI2 */ 00227 CLK_Peripheral_USART2 = (uint8_t)0x23, /*!< Peripheral Clock Enable 3, USART2 */ 00228 CLK_Peripheral_USART3 = (uint8_t)0x24, /*!< Peripheral Clock Enable 3, USART3 */ 00229 CLK_Peripheral_CSSLSE = (uint8_t)0x25 /*!< Peripheral Clock Enable 3, CSS on LSE */ 00230 } CLK_Peripheral_TypeDef; 00231 00232 #define IS_CLK_PERIPHERAL(PERIPHERAL) (((PERIPHERAL) == CLK_Peripheral_DAC) ||\ 00233 ((PERIPHERAL) == CLK_Peripheral_ADC1) ||\ 00234 ((PERIPHERAL) == CLK_Peripheral_DMA1) ||\ 00235 ((PERIPHERAL) == CLK_Peripheral_RTC) ||\ 00236 ((PERIPHERAL) == CLK_Peripheral_LCD) ||\ 00237 ((PERIPHERAL) == CLK_Peripheral_COMP) ||\ 00238 ((PERIPHERAL) == CLK_Peripheral_TIM1) ||\ 00239 ((PERIPHERAL) == CLK_Peripheral_USART1) ||\ 00240 ((PERIPHERAL) == CLK_Peripheral_SPI1) ||\ 00241 ((PERIPHERAL) == CLK_Peripheral_I2C1) ||\ 00242 ((PERIPHERAL) == CLK_Peripheral_TIM4) ||\ 00243 ((PERIPHERAL) == CLK_Peripheral_TIM3) ||\ 00244 ((PERIPHERAL) == CLK_Peripheral_BEEP) ||\ 00245 ((PERIPHERAL) == CLK_Peripheral_BOOTROM) ||\ 00246 ((PERIPHERAL) == CLK_Peripheral_AES) ||\ 00247 ((PERIPHERAL) == CLK_Peripheral_TIM5) ||\ 00248 ((PERIPHERAL) == CLK_Peripheral_SPI2) ||\ 00249 ((PERIPHERAL) == CLK_Peripheral_USART2) ||\ 00250 ((PERIPHERAL) == CLK_Peripheral_USART3) ||\ 00251 ((PERIPHERAL) == CLK_Peripheral_CSSLSE) ||\ 00252 ((PERIPHERAL) == CLK_Peripheral_TIM2)) 00253 /** 00254 * @} 00255 */ 00256 00257 /** @defgroup CLK_System_Clock_Divider 00258 * @{ 00259 */ 00260 typedef enum { 00261 CLK_SYSCLKDiv_1 = (uint8_t)0x00, /*!< System Clock Divider: 1 */ 00262 CLK_SYSCLKDiv_2 = (uint8_t)0x01, /*!< System Clock Divider: 2 */ 00263 CLK_SYSCLKDiv_4 = (uint8_t)0x02, /*!< System Clock Divider: 4 */ 00264 CLK_SYSCLKDiv_8 = (uint8_t)0x03, /*!< System Clock Divider: 8 */ 00265 CLK_SYSCLKDiv_16 = (uint8_t)0x04, /*!< System Clock Divider: 16 */ 00266 CLK_SYSCLKDiv_32 = (uint8_t)0x05, /*!< System Clock Divider: 32 */ 00267 CLK_SYSCLKDiv_64 = (uint8_t)0x06, /*!< System Clock Divider: 64 */ 00268 CLK_SYSCLKDiv_128 = (uint8_t)0x07 /*!< System Clock Divider: 128 */ 00269 } CLK_SYSCLKDiv_TypeDef; 00270 00271 #define IS_CLK_SYSTEM_DIVIDER(DIV) (((DIV) == CLK_SYSCLKDiv_1) ||\ 00272 ((DIV) == CLK_SYSCLKDiv_2) ||\ 00273 ((DIV) == CLK_SYSCLKDiv_4) ||\ 00274 ((DIV) == CLK_SYSCLKDiv_8) ||\ 00275 ((DIV) == CLK_SYSCLKDiv_16) ||\ 00276 ((DIV) == CLK_SYSCLKDiv_32) ||\ 00277 ((DIV) == CLK_SYSCLKDiv_64) ||\ 00278 ((DIV) == CLK_SYSCLKDiv_128)) 00279 /** 00280 * @} 00281 */ 00282 00283 /** @defgroup CLK_Flags 00284 * @{ 00285 */ 00286 /* Elements values convention: 0xXY 00287 X = choice between the register's flags 00288 X = 0 : CLK_CRTCR 00289 X = 1 : CLK_ICKCR 00290 X = 2 : CLK_CCOR 00291 X = 3 : CLK_ECKCR 00292 X = 4 : CLK_SWCR 00293 X = 5 : CLK_CSSR 00294 X = 6 : CLK_CBEEPR 00295 X = 7 : CLK_REGCSRR 00296 X = 8 : CSSLSE_CSR 00297 Y = flag position in the register 00298 */ 00299 typedef enum { 00300 CLK_FLAG_RTCSWBSY = (uint8_t)0x00, /*!< RTC clock busy in switch Flag */ 00301 CLK_FLAG_HSIRDY = (uint8_t)0x11, /*!< High speed internal oscillator ready Flag */ 00302 CLK_FLAG_LSIRDY = (uint8_t)0x13, /*!< Low speed internal oscillator ready Flag */ 00303 CLK_FLAG_CCOBSY = (uint8_t)0x20, /*!< Configurable clock output busy */ 00304 CLK_FLAG_HSERDY = (uint8_t)0x31, /*!< High speed external oscillator ready Flag */ 00305 CLK_FLAG_LSERDY = (uint8_t)0x33, /*!< Low speed external oscillator ready Flag */ 00306 CLK_FLAG_SWBSY = (uint8_t)0x40, /*!< Switch busy Flag */ 00307 CLK_FLAG_AUX = (uint8_t)0x51, /*!< Auxiliary oscillator connected to master clock */ 00308 CLK_FLAG_CSSD = (uint8_t)0x53, /*!< Clock security system detection Flag */ 00309 CLK_FLAG_BEEPSWBSY = (uint8_t)0x60, /*!< BEEP clock busy in switch Flag*/ 00310 CLK_FLAG_EEREADY = (uint8_t)0x77, /*!< Flash program memory and Data EEPROM ready Flag */ 00311 CLK_FLAG_EEBUSY = (uint8_t)0x76, /*!< Flash program memory and Data EEPROM busy Flag */ 00312 CLK_FLAG_LSEPD = (uint8_t)0x75, /*!< LSE power-down Flag */ 00313 CLK_FLAG_HSEPD = (uint8_t)0x74, /*!< HSE power-down Flag */ 00314 CLK_FLAG_LSIPD = (uint8_t)0x73, /*!< LSI power-down Flag */ 00315 CLK_FLAG_HSIPD = (uint8_t)0x72, /*!< HSI power-down Flag */ 00316 CLK_FLAG_REGREADY = (uint8_t)0x70, /*!< REGREADY Flag */ 00317 CLK_FLAG_LSECSSF = (uint8_t)0x83, /*!< CSS on LSE detection Flag */ 00318 CLK_FLAG_RTCCLKSWF = (uint8_t)0x84 /*!< RTCCLK switch completed flag on LSE failure */ 00319 }CLK_FLAG_TypeDef; 00320 00321 #define IS_CLK_FLAGS(FLAG) (((FLAG) == CLK_FLAG_LSIRDY) ||\ 00322 ((FLAG) == CLK_FLAG_HSIRDY) ||\ 00323 ((FLAG) == CLK_FLAG_HSERDY) ||\ 00324 ((FLAG) == CLK_FLAG_SWBSY) ||\ 00325 ((FLAG) == CLK_FLAG_CSSD) ||\ 00326 ((FLAG) == CLK_FLAG_AUX) ||\ 00327 ((FLAG) == CLK_FLAG_LSERDY) ||\ 00328 ((FLAG) == CLK_FLAG_CCOBSY) ||\ 00329 ((FLAG) == CLK_FLAG_RTCSWBSY) ||\ 00330 ((FLAG) == CLK_FLAG_EEREADY) ||\ 00331 ((FLAG) == CLK_FLAG_EEBUSY) ||\ 00332 ((FLAG) == CLK_FLAG_LSEPD) ||\ 00333 ((FLAG) == CLK_FLAG_LSIPD) ||\ 00334 ((FLAG) == CLK_FLAG_HSEPD) ||\ 00335 ((FLAG) == CLK_FLAG_HSIPD) ||\ 00336 ((FLAG) == CLK_FLAG_REGREADY) ||\ 00337 ((FLAG) == CLK_FLAG_BEEPSWBSY)||\ 00338 ((FLAG) == CLK_FLAG_LSECSSF)||\ 00339 ((FLAG) == CLK_FLAG_RTCCLKSWF)) 00340 /** 00341 * @} 00342 */ 00343 00344 /** @defgroup CLK_Interrupts 00345 * @{ 00346 */ 00347 typedef enum { 00348 CLK_IT_CSSD = (uint8_t)0x0C, /*!< Clock security system detection Flag */ 00349 CLK_IT_SWIF = (uint8_t)0x1C, /*!< Clock switch interrupt Flag */ 00350 CLK_IT_LSECSSF = (uint8_t)0x2C /*!< LSE Clock security system detection Interrupt */ 00351 }CLK_IT_TypeDef; 00352 #define IS_CLK_IT(IT) (((IT) == CLK_IT_CSSD) ||\ 00353 ((IT) == CLK_IT_SWIF) ||\ 00354 ((IT) == CLK_IT_LSECSSF)) 00355 00356 #define IS_CLK_CLEAR_IT(IT) (((IT) == CLK_IT_SWIF)||\ 00357 ((IT) == CLK_IT_LSECSSF)) 00358 /** 00359 * @} 00360 */ 00361 00362 /** @defgroup CLK_Halt_Configuration 00363 * @{ 00364 */ 00365 typedef enum { 00366 CLK_Halt_BEEPRunning = (uint8_t)0x40, /*!< BEEP clock Halt/Active-halt mode */ 00367 CLK_Halt_FastWakeup = (uint8_t)0x20, /*!< Fast wakeup from Halt/Active-halt modes */ 00368 CLK_Halt_SlowWakeup = (uint8_t)0x10 /*!< Slow Active-halt mode */ 00369 } 00370 CLK_Halt_TypeDef; 00371 00372 #define IS_CLK_HALT(HALT) (((HALT) == CLK_Halt_BEEPRunning) ||\ 00373 ((HALT) == CLK_Halt_FastWakeup) ||\ 00374 ((HALT) == CLK_Halt_SlowWakeup)) 00375 /** 00376 * @} 00377 */ 00378 00379 /** 00380 * @} 00381 */ 00382 00383 /* Exported constants --------------------------------------------------------*/ 00384 /* Exported macro ------------------------------------------------------------*/ 00385 /* Exported functions ------------------------------------------------------- */ 00386 00387 /* Function used to set the CLK configuration to the default reset state ******/ 00388 void CLK_DeInit(void); 00389 00390 /* Internal/external clocks, CSS and CCO configuration functions **************/ 00391 void CLK_HSICmd(FunctionalState NewState); 00392 void CLK_AdjustHSICalibrationValue(uint8_t CLK_HSICalibrationValue); 00393 void CLK_LSICmd(FunctionalState NewState); 00394 void CLK_HSEConfig(CLK_HSE_TypeDef CLK_HSE); 00395 void CLK_LSEConfig(CLK_LSE_TypeDef CLK_LSE); 00396 void CLK_ClockSecuritySystemEnable(void); 00397 void CLK_ClockSecuritySytemDeglitchCmd(FunctionalState NewState); 00398 void CLK_CCOConfig(CLK_CCOSource_TypeDef CLK_CCOSource, CLK_CCODiv_TypeDef CLK_CCODiv); 00399 00400 /* System clocks configuration functions ******************/ 00401 void CLK_SYSCLKSourceConfig(CLK_SYSCLKSource_TypeDef CLK_SYSCLKSource); 00402 CLK_SYSCLKSource_TypeDef CLK_GetSYSCLKSource(void); 00403 uint32_t CLK_GetClockFreq(void); 00404 void CLK_SYSCLKDivConfig(CLK_SYSCLKDiv_TypeDef CLK_SYSCLKDiv); 00405 void CLK_SYSCLKSourceSwitchCmd(FunctionalState NewState); 00406 00407 /* Peripheral clocks configuration functions **********************************/ 00408 void CLK_RTCClockConfig(CLK_RTCCLKSource_TypeDef CLK_RTCCLKSource, CLK_RTCCLKDiv_TypeDef CLK_RTCCLKDiv); 00409 void CLK_BEEPClockConfig(CLK_BEEPCLKSource_TypeDef CLK_BEEPCLKSource); 00410 void CLK_PeripheralClockConfig(CLK_Peripheral_TypeDef CLK_Peripheral, FunctionalState NewState); 00411 00412 /* CSS on LSE configuration functions *****************************************/ 00413 void CLK_LSEClockSecuritySystemEnable(void); 00414 void CLK_RTCCLKSwitchOnLSEFailureEnable(void); 00415 00416 /* Low power clock configuration functions ************************************/ 00417 void CLK_HaltConfig(CLK_Halt_TypeDef CLK_Halt, FunctionalState NewState); 00418 void CLK_MainRegulatorCmd(FunctionalState NewState); 00419 00420 /* Interrupts and flags management functions **********************************/ 00421 void CLK_ITConfig(CLK_IT_TypeDef CLK_IT, FunctionalState NewState); 00422 FlagStatus CLK_GetFlagStatus(CLK_FLAG_TypeDef CLK_FLAG); 00423 void CLK_ClearFlag(void); 00424 ITStatus CLK_GetITStatus(CLK_IT_TypeDef CLK_IT); 00425 void CLK_ClearITPendingBit(CLK_IT_TypeDef CLK_IT); 00426 00427 00428 #endif /* __STM8L15x_CLK_H */ 00429 00430 /** 00431 * @} 00432 */ 00433 00434 /** 00435 * @} 00436 */ 00437 00438 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/