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STM8L15x Standard Peripherals Drivers
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stm8l15x.h
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00001 /** 00002 ****************************************************************************** 00003 * @file stm8l15x.h 00004 * @author MCD Application Team 00005 * @version V1.5.0 00006 * @date 13-May-2011 00007 * @brief This file contains all the peripheral register's definitions, bits 00008 * definitions and memory mapping for STM8L15x devices. 00009 ****************************************************************************** 00010 * @attention 00011 * 00012 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 00013 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 00014 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 00015 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 00016 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 00017 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 00018 * 00019 * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> 00020 ****************************************************************************** 00021 */ 00022 00023 /* Define to prevent recursive inclusion -------------------------------------*/ 00024 #ifndef __STM8L15x_H 00025 #define __STM8L15x_H 00026 00027 /** @addtogroup STM8L15x_StdPeriph_Driver 00028 * @{ 00029 */ 00030 /* Uncomment the line below according to the target STM8L15x device used in your 00031 application 00032 */ 00033 /* #define STM8L15X_LD */ /*!< STM8L15X_LD: STM8L15x Low density devices */ 00034 /* #define STM8L15X_MD */ /*!< STM8L15X_MD: STM8L15x Medium density devices */ 00035 /* #define STM8L15X_MDP */ /*!< STM8L15X_MDP: STM8L15x Medium density plus devices */ 00036 /* #define STM8L15X_HD */ /*!< STM8L15X_HD: STM8L15x/16x High density devices */ 00037 00038 /* Tip: To avoid modifying this file each time you need to switch between these 00039 devices, you can define the device in your toolchain compiler preprocessor. 00040 00041 - Low density STM8L15x devices are STM8L151C3, STM8L151K3, STM8L151G3, STM8L151F3, 00042 STM8L151C2, STM8L151K2, STM8L151G2 and STM8L151F2 microcontrollers where the 00043 Flash memory density ranges between 4 and 8 Kbytes. 00044 - Medium density STM8L15x devices are STM8L151C4, STM8L151C6, STM8L152C4, 00045 STM8L152C6, STM8L151K4, STM8L151K6, STM8L152K4, STM8L152K6, STM8L151G4, 00046 STM8L151G6, STM8L152G4 and STM8L152G6 microcontrollers where the Flash memory 00047 density ranges between 16 and 32 Kbytes. 00048 - Medium density Plus devices are STM8L151R6, STM8L152R6 microcontrollers where 00049 the Flash memory density is fixed and equal to 32 Kbytes and a wider range of 00050 peripheral than the medium density devices. 00051 - High density STM8L15x devices are STM8L151x8, STM8L152x8, STM8L162R8 and STM8L162M8 00052 microcontrollers where the Flash memory density is fixed and equal to 64 Kbytes with 00053 the same peripheral set than Medium Density Plus devices. 00054 00055 */ 00056 00057 #if !defined (STM8L15X_MD) && !defined (STM8L15X_MDP) && !defined (STM8L15X_HD) && !defined (STM8L15X_LD) 00058 #error "Please select first the target STM8L device used in your application (in stm8l15x.h file)" 00059 #endif 00060 00061 /******************************************************************************/ 00062 /* Library configuration section */ 00063 /******************************************************************************/ 00064 /* Check the used compiler */ 00065 #if defined(__CSMC__) 00066 #define _COSMIC_ 00067 #elif defined(__RCST7__) 00068 #define _RAISONANCE_ 00069 #elif defined(__ICCSTM8__) 00070 #define _IAR_ 00071 #else 00072 #error "Unsupported Compiler!" /* Compiler defines not found */ 00073 #endif 00074 00075 #if !defined USE_STDPERIPH_DRIVER 00076 /* Comment the line below if you will not use the peripherals drivers. 00077 In this case, these drivers will not be included and the application code will be 00078 based on direct access to peripherals registers */ 00079 #define USE_STDPERIPH_DRIVER 00080 #endif 00081 00082 /** 00083 * @brief In the following line adjust the value of External High Speed oscillator (HSE) 00084 used in your application 00085 00086 Tip: To avoid modifying this file each time you need to use different HSE, you 00087 can define the HSE value in your toolchain compiler preprocessor. 00088 */ 00089 #if !defined HSE_Value 00090 #define HSE_VALUE ((uint32_t)16000000) /*!< Typical Value of the HSE in Hz */ 00091 #endif /* HSE_Value */ 00092 00093 /** 00094 * @brief Definition of External Low Speed oscillator (LSE) frequency 00095 */ 00096 #define LSE_VALUE ((uint32_t)32768) /*!< Typical Value of the LSE in Hz */ 00097 00098 /** 00099 * @brief Definition of Device on-chip RC oscillator frequencies 00100 */ 00101 #define HSI_VALUE ((uint32_t)16000000) /*!< Typical Value of the HSI in Hz */ 00102 #define LSI_VALUE ((uint32_t)38000) /*!< Typical Value of the LSI in Hz */ 00103 00104 #ifdef _COSMIC_ 00105 #define FAR @far 00106 #define NEAR @near 00107 #define TINY @tiny 00108 #define EEPROM @eeprom 00109 #define CONST const 00110 #elif defined (_RAISONANCE_) /* __RCST7__ */ 00111 #define FAR far 00112 #define NEAR data 00113 #define TINY page0 00114 #define EEPROM eeprom 00115 #define CONST code 00116 #if defined (STM8L15X_MD) || defined (STM8L15X_MDP) 00117 /*!< Used with memory Models for code less than 64K */ 00118 #define MEMCPY memcpy 00119 #else /* STM8L15X_HD */ 00120 /*!< Used with memory Models for code higher than 64K */ 00121 #define MEMCPY fmemcpy 00122 #endif /* STM8L15X_MD or STM8L15X_MDP */ 00123 #else /*_IAR_*/ 00124 #define FAR __far 00125 #define NEAR __near 00126 #define TINY __tiny 00127 #define EEPROM __eeprom 00128 #define CONST const 00129 #endif /* __CSMC__ */ 00130 00131 /** 00132 * @brief Legacy definition 00133 */ 00134 #define __CONST CONST 00135 00136 #if defined (STM8L15X_MD) || defined (STM8L15X_MDP) || defined (STM8L15X_LD) 00137 /*!< Used with memory Models for code smaller than 64K */ 00138 #define PointerAttr NEAR 00139 #else /* STM8L15X_HD */ 00140 /*!< Used with memory Models for code higher than 64K */ 00141 #define PointerAttr FAR 00142 #endif /* STM8L15X_MD or STM8L15X_MDP or STM8L15X_LD*/ 00143 00144 /* Uncomment the line below to enable the FLASH functions execution from RAM */ 00145 #if !defined (RAM_EXECUTION) 00146 /* #define RAM_EXECUTION (1) */ 00147 #endif /* RAM_EXECUTION */ 00148 00149 #ifdef RAM_EXECUTION 00150 #ifdef _COSMIC_ 00151 #define IN_RAM(a) a 00152 #elif defined (_RAISONANCE_) /* __RCST7__ */ 00153 #define IN_RAM(a) a inram 00154 #else /*_IAR_*/ 00155 #define IN_RAM(a) __ramfunc a 00156 #endif /* _COSMIC_ */ 00157 #else 00158 #define IN_RAM(a) a 00159 #endif /* RAM_EXECUTION */ 00160 00161 /*!< [31:16] STM8L15X Standard Peripheral Library main version */ 00162 #define __STM8L15X_STDPERIPH_VERSION_MAIN ((uint8_t)0x01) /*!< [31:24] main version */ 00163 #define __STM8L15X_STDPERIPH_VERSION_SUB1 ((uint8_t)0x05) /*!< [23:16] sub1 version */ 00164 #define __STM8L15X_STDPERIPH_VERSION_SUB2 ((uint8_t)0x00) /*!< [15:8] sub2 version */ 00165 #define __STM8L15X_STDPERIPH_VERSION_RC ((uint8_t)0x00) /*!< [7:0] release candidate */ 00166 #define __STM8L15X_STDPERIPH_VERSION ( (__STM8L15X_STDPERIPH_VERSION_MAIN << 24)\ 00167 |(__STM8L15X_STDPERIPH_VERSION_SUB1 << 16)\ 00168 |(__STM8L15X_STDPERIPH_VERSION_SUB2 << 8)\ 00169 |(__STM8L15X_STDPERIPH_VERSION_RC)) 00170 00171 /******************************************************************************/ 00172 00173 /* Includes ------------------------------------------------------------------*/ 00174 00175 /* Exported types and constants ----------------------------------------------*/ 00176 00177 /** @addtogroup Exported_types 00178 * @{ 00179 */ 00180 00181 /** 00182 * IO definitions 00183 * 00184 * define access restrictions to peripheral registers 00185 */ 00186 #define __I volatile const /*!< defines 'read only' permissions */ 00187 #define __O volatile /*!< defines 'write only' permissions */ 00188 #define __IO volatile /*!< defines 'read / write' permissions */ 00189 00190 /*!< Signed integer types */ 00191 typedef signed char int8_t; 00192 typedef signed short int16_t; 00193 typedef signed long int32_t; 00194 00195 /*!< Unsigned integer types */ 00196 typedef unsigned char uint8_t; 00197 typedef unsigned short uint16_t; 00198 typedef unsigned long uint32_t; 00199 00200 /*!< STM8Lx Standard Peripheral Library old types (maintained for legacy purpose) */ 00201 00202 typedef int32_t s32; 00203 typedef int16_t s16; 00204 typedef int8_t s8; 00205 00206 typedef uint32_t u32; 00207 typedef uint16_t u16; 00208 typedef uint8_t u8; 00209 00210 00211 typedef enum {FALSE = 0, TRUE = !FALSE} bool; 00212 00213 typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus, BitStatus, BitAction; 00214 00215 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; 00216 #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) 00217 00218 typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; 00219 00220 #define U8_MAX (255) 00221 #define S8_MAX (127) 00222 #define S8_MIN (-128) 00223 #define U16_MAX (65535u) 00224 #define S16_MAX (32767) 00225 #define S16_MIN (-32768) 00226 #define U32_MAX (4294967295uL) 00227 #define S32_MAX (2147483647) 00228 #define S32_MIN (-2147483648uL) 00229 00230 /** 00231 * @} 00232 */ 00233 00234 /** @addtogroup MAP_FILE_Exported_Types_and_Constants 00235 * @{ 00236 */ 00237 00238 /******************************************************************************/ 00239 /* IP registers structures */ 00240 /******************************************************************************/ 00241 00242 /*----------------------------------------------------------------------------*/ 00243 /** 00244 * @brief General Purpose I/Os (GPIO) 00245 */ 00246 typedef struct GPIO_struct 00247 { 00248 __IO uint8_t ODR; /*!< Output Data Register */ 00249 __IO uint8_t IDR; /*!< Input Data Register */ 00250 __IO uint8_t DDR; /*!< Data Direction Register */ 00251 __IO uint8_t CR1; /*!< Configuration Register 1 */ 00252 __IO uint8_t CR2; /*!< Configuration Register 2 */ 00253 } 00254 GPIO_TypeDef; 00255 00256 /** @addtogroup GPIO_Registers_Reset_Value 00257 * @{ 00258 */ 00259 #define GPIO_ODR_RESET_VALUE ((uint8_t)0x00) 00260 #define GPIO_DDR_RESET_VALUE ((uint8_t)0x00) 00261 #define GPIO_CR1_RESET_VALUE ((uint8_t)0x00) 00262 #define GPIO_CR2_RESET_VALUE ((uint8_t)0x00) 00263 /** 00264 * @} 00265 */ 00266 /*----------------------------------------------------------------------------*/ 00267 00268 /** 00269 * @brief Real-Time Clock (RTC) peripheral registers. 00270 */ 00271 typedef struct RTC_struct 00272 { 00273 __IO uint8_t TR1; /*!< Time Register 1*/ 00274 __IO uint8_t TR2; /*!< Time Register 2*/ 00275 __IO uint8_t TR3; /*!< Time Register 3*/ 00276 00277 uint8_t RESERVED0; 00278 00279 __IO uint8_t DR1; /*!< Date Register 1*/ 00280 __IO uint8_t DR2; /*!< Date Register 2*/ 00281 __IO uint8_t DR3; /*!< Date Register 3*/ 00282 00283 uint8_t RESERVED1; 00284 00285 __IO uint8_t CR1; /*!< Control Register 1*/ 00286 __IO uint8_t CR2; /*!< Control Register 2*/ 00287 __IO uint8_t CR3; /*!< Control Register 3*/ 00288 00289 uint8_t RESERVED2; 00290 00291 __IO uint8_t ISR1; /*!< Initialisation and Status Register 1 */ 00292 __IO uint8_t ISR2; /*!< Initialisation and Status Register 2 */ 00293 00294 uint8_t RESERVED3; 00295 uint8_t RESERVED4; 00296 00297 __IO uint8_t SPRERH; /*!< Synchronous Prediv high Register */ 00298 __IO uint8_t SPRERL; /*!< Synchronous Prediv Low Register */ 00299 __IO uint8_t APRER; /*!< Asynchronous Prediv Register */ 00300 00301 uint8_t RESERVED5; 00302 00303 __IO uint8_t WUTRH; /*!< Wake-Up Timer High Register */ 00304 __IO uint8_t WUTRL; /*!< Wake-Up Timer Low Register */ 00305 00306 uint8_t RESERVED6; 00307 00308 __IO uint8_t SSRH; /*!< Sub Second High Register */ 00309 __IO uint8_t SSRL; /*!< Sub Second Low Register */ 00310 00311 __IO uint8_t WPR; /*!< Write Protection Register */ 00312 00313 __IO uint8_t SHIFTRH; /*!< Shift control High Register */ 00314 __IO uint8_t SHIFTRL; /*!< Shift control Low Register */ 00315 00316 __IO uint8_t ALRMAR1; /*!< ALARM A Register 1 */ 00317 __IO uint8_t ALRMAR2; /*!< ALARM A Register 2 */ 00318 __IO uint8_t ALRMAR3; /*!< ALARM A Register 3 */ 00319 __IO uint8_t ALRMAR4; /*!< ALARM A Register 4 */ 00320 00321 uint8_t RESERVED7[4]; 00322 00323 __IO uint8_t ALRMASSRH; /*!< ALARM A Subsecond Register High */ 00324 __IO uint8_t ALRMASSRL; /*!< ALARM A Subsecond Register Low */ 00325 __IO uint8_t ALRMASSMSKR; /*!< ALARM A Subsecond Mask Register */ 00326 00327 uint8_t RESERVED8[3]; 00328 00329 __IO uint8_t CALRH; /*!< Calibration register high */ 00330 __IO uint8_t CALRL; /*!< Calibration register low */ 00331 00332 __IO uint8_t TCR1; /*!< Tamper control register 1 */ 00333 __IO uint8_t TCR2; /*!< Tamper control register 2 */ 00334 } 00335 RTC_TypeDef; 00336 00337 /** @addtogroup RTC_Registers_Reset_Value 00338 * @{ 00339 */ 00340 #define RTC_TR1_RESET_VALUE ((uint8_t)0x00) 00341 #define RTC_TR2_RESET_VALUE ((uint8_t)0x00) 00342 #define RTC_TR3_RESET_VALUE ((uint8_t)0x00) 00343 00344 #define RTC_DR1_RESET_VALUE ((uint8_t)0x01) 00345 #define RTC_DR2_RESET_VALUE ((uint8_t)0x21) 00346 #define RTC_DR3_RESET_VALUE ((uint8_t)0x00) 00347 00348 #define RTC_CR1_RESET_VALUE ((uint8_t)0x00) 00349 #define RTC_CR2_RESET_VALUE ((uint8_t)0x00) 00350 #define RTC_CR3_RESET_VALUE ((uint8_t)0x00) 00351 00352 #define RTC_ISR1_RESET_VALUE ((uint8_t)0x07) 00353 #define RTC_ISR2_RESET_VALUE ((uint8_t)0x00) 00354 00355 #define RTC_SPRERH_RESET_VALUE ((uint8_t)0x00) 00356 #define RTC_SPRERL_RESET_VALUE ((uint8_t)0xFF) 00357 #define RTC_APRER_RESET_VALUE ((uint8_t)0x7F) 00358 00359 #define RTC_WUTRH_RESET_VALUE ((uint8_t)0xFF) 00360 #define RTC_WUTRL_RESET_VALUE ((uint8_t)0xFF) 00361 00362 #define RTC_WPR_RESET_VALUE ((uint8_t)0x00) 00363 00364 #define RTC_ALRMAR1_RESET_VALUE ((uint8_t)0x00) 00365 #define RTC_ALRMAR2_RESET_VALUE ((uint8_t)0x00) 00366 #define RTC_ALRMAR3_RESET_VALUE ((uint8_t)0x00) 00367 #define RTC_ALRMAR4_RESET_VALUE ((uint8_t)0x00) 00368 00369 #define RTC_SHIFTRH_RESET_VALUE ((uint8_t)0x00) 00370 #define RTC_SHIFTRL_RESET_VALUE ((uint8_t)0x00) 00371 00372 #define RTC_ALRMASSRH_RESET_VALUE ((uint8_t)0x00) 00373 #define RTC_ALRMASSRL_RESET_VALUE ((uint8_t)0x00) 00374 #define RTC_ALRMASSMSKR_RESET_VALUE ((uint8_t)0x00) 00375 00376 #define RTC_CALRH_RESET_VALUE ((uint8_t)0x00) 00377 #define RTC_CALRL_RESET_VALUE ((uint8_t)0x00) 00378 00379 #define RTC_TCR1_RESET_VALUE ((uint8_t)0x00) 00380 #define RTC_TCR2_RESET_VALUE ((uint8_t)0x00) 00381 00382 /** 00383 * @} 00384 */ 00385 00386 /** @addtogroup RTC_Registers_Bits_Definition 00387 * @{ 00388 */ 00389 00390 /* Bits definition for RTC_TR1 register*/ 00391 #define RTC_TR1_ST ((uint8_t)0x70) 00392 #define RTC_TR1_SU ((uint8_t)0x0F) 00393 00394 /* Bits definition for RTC_TR2 register*/ 00395 #define RTC_TR2_MNT ((uint8_t)0x70) 00396 #define RTC_TR2_MNU ((uint8_t)0x0F) 00397 00398 /* Bits definition for RTC_TR3 register*/ 00399 #define RTC_TR3_PM ((uint8_t)0x40) 00400 #define RTC_TR3_HT ((uint8_t)0x30) 00401 #define RTC_TR3_HU ((uint8_t)0x0F) 00402 00403 /* Bits definition for RTC_DR1 register*/ 00404 #define RTC_DR1_DT ((uint8_t)0x30) 00405 #define RTC_DR1_DU ((uint8_t)0x0F) 00406 00407 /* Bits definition for RTC_DR2 register*/ 00408 #define RTC_DR2_WDU ((uint8_t)0xE0) 00409 #define RTC_DR2_MT ((uint8_t)0x10) 00410 #define RTC_DR2_MU ((uint8_t)0x0F) 00411 00412 /* Bits definition for RTC_DR3 register*/ 00413 #define RTC_DR3_YT ((uint8_t)0xF0) 00414 #define RTC_DR3_YU ((uint8_t)0x0F) 00415 00416 /* Bits definition for RTC_CR1 register*/ 00417 #define RTC_CR1_FMT ((uint8_t)0x40) 00418 #define RTC_CR1_RATIO ((uint8_t)0x20) 00419 #define RTC_CR1_WUCKSEL ((uint8_t)0x07) 00420 #define RTC_CR1_BYPSHAD ((uint8_t)0x10) 00421 00422 00423 /* Bits definition for RTC_CR2 register*/ 00424 #define RTC_CR2_WUTIE ((uint8_t)0x40) 00425 #define RTC_CR2_ALRAIE ((uint8_t)0x10) 00426 #define RTC_CR2_WUTE ((uint8_t)0x04) 00427 #define RTC_CR2_ALRAE ((uint8_t)0x01) 00428 #define RTC_CR2_ALRIE ((uint8_t)0x20) 00429 00430 00431 00432 /* Bits definition for RTC_CR3 register*/ 00433 #define RTC_CR3_COE ((uint8_t)0x80) 00434 #define RTC_CR3_OSEL ((uint8_t)0x60) 00435 #define RTC_CR3_POL ((uint8_t)0x10) 00436 #define RTC_CR3_COSEL ((uint8_t)0x08) 00437 #define RTC_CR3_BCK ((uint8_t)0x04) 00438 #define RTC_CR3_SUB1H ((uint8_t)0x02) 00439 #define RTC_CR3_ADD1H ((uint8_t)0x01) 00440 00441 00442 /* Bits definition for RTC_ISR1 register*/ 00443 #define RTC_ISR1_INIT ((uint8_t)0x80) 00444 #define RTC_ISR1_INITF ((uint8_t)0x40) 00445 #define RTC_ISR1_RSF ((uint8_t)0x20) 00446 #define RTC_ISR1_INITS ((uint8_t)0x10) 00447 #define RTC_ISR1_SHPF ((uint8_t)0x08) 00448 #define RTC_ISR1_WUTWF ((uint8_t)0x04) 00449 #define RTC_ISR1_RECALPF ((uint8_t)0x02) 00450 #define RTC_ISR1_ALRAWF ((uint8_t)0x01) 00451 00452 00453 /* Bits definition for RTC_ISR2 register*/ 00454 #define RTC_ISR2_WUTF ((uint8_t)0x04) 00455 #define RTC_ISR2_ALRAF ((uint8_t)0x01) 00456 #define RTC_ISR2_TAMP3F ((uint8_t)0x80) 00457 #define RTC_ISR2_TAMP2F ((uint8_t)0x40) 00458 #define RTC_ISR2_TAMP1F ((uint8_t)0x20) 00459 00460 /* Bits definition for RTC_SHIFTRH register*/ 00461 #define RTC_SHIFTRH_ADD1S ((uint8_t)0x80) 00462 #define RTC_SHIFTRH_SUBFS ((uint8_t)0x7F) 00463 00464 /* Bits definition for RTC_SHIFTRL register*/ 00465 #define RTC_SHIFTRL_SUBFS ((uint8_t)0xFF) 00466 00467 00468 /* Bits definition for RTC_ALRMAR1 register*/ 00469 #define RTC_ALRMAR1_MSK1 ((uint8_t)0x80) 00470 #define RTC_ALRMAR1_ST ((uint8_t)0x70) 00471 #define RTC_ALRMAR1_SU ((uint8_t)0x0F) 00472 00473 /* Bits definition for RTC_ALRMAR2 register*/ 00474 #define RTC_ALRMAR2_MSK2 ((uint8_t)0x80) 00475 #define RTC_ALRMAR2_MNT ((uint8_t)0x70) 00476 #define RTC_ALRMAR2_MNU ((uint8_t)0x0F) 00477 00478 /* Bits definition for RTC_ALRMAR3 register*/ 00479 #define RTC_ALRMAR3_MSK3 ((uint8_t)0x80) 00480 #define RTC_ALRMAR3_PM ((uint8_t)0x40) 00481 #define RTC_ALRMAR3_HT ((uint8_t)0x30) 00482 #define RTC_ALRMAR3_HU ((uint8_t)0x0F) 00483 00484 /* Bits definition for RTC_ALRMAR4 register*/ 00485 #define RTC_ALRMAR4_MSK4 ((uint8_t)0x80) 00486 #define RTC_ALRMAR4_WDSEL ((uint8_t)0x40) 00487 #define RTC_ALRMAR4_DT ((uint8_t)0x30) 00488 #define RTC_ALRMAR4_DU ((uint8_t)0x0F) 00489 00490 /* Bits definition for RTC_ALRMASSRH register*/ 00491 #define RTC_ALRMASSRH_ALSS ((uint8_t)0x7F) 00492 00493 /* Bits definition for RTC_ALRMASSRL register*/ 00494 #define RTC_ALRMASSRL_ALSS ((uint8_t)0xFF) 00495 00496 /* Bits definition for RTC_ALRMASSMSKR register*/ 00497 #define RTC_ALRMASSMSKR_MASKSS ((uint8_t)0x1F) 00498 00499 00500 /* Bits definition for RTC_CALRH register*/ 00501 #define RTC_CALRH_CALP ((uint8_t)0x80) 00502 #define RTC_CALRH_CALW8 ((uint8_t)0x40) 00503 #define RTC_CALRH_CALW16 ((uint8_t)0x20) 00504 #define RTC_CALRH_CALWx ((uint8_t)0x60) 00505 #define RTC_CALRH_CALM ((uint8_t)0x01) 00506 00507 /* Bits definition for RTC_CALRL register*/ 00508 #define RTC_CALRL_CALM ((uint8_t)0xFF) 00509 00510 /* Bits definition for RTC_TCR1 register*/ 00511 #define RTC_TCR1_TAMP3LEVEL ((uint8_t)0x40) 00512 #define RTC_TCR1_TAMP3E ((uint8_t)0x20) 00513 #define RTC_TCR1_TAMP2LEVEL ((uint8_t)0x10) 00514 #define RTC_TCR1_TAMP2E ((uint8_t)0x08) 00515 #define RTC_TCR1_TAMP1LEVEL ((uint8_t)0x04) 00516 #define RTC_TCR1_TAMP1E ((uint8_t)0x02) 00517 #define RTC_TCR1_TAMPIE ((uint8_t)0x01) 00518 00519 /* Bits definition for RTC_TCR2 register*/ 00520 #define RTC_TCR2_TAMPPUDIS ((uint8_t)0x80) 00521 #define RTC_TCR2_TAMPPRCH ((uint8_t)0x60) 00522 #define RTC_TCR2_TAMPFLT ((uint8_t)0x18) 00523 #define RTC_TCR2_TAMPFREQ ((uint8_t)0x07) 00524 00525 00526 /*RTC special defines */ 00527 #define RTC_WPR_EnableKey ((uint8_t)0xFF) 00528 #define RTC_WPR_DisableKey1 ((uint8_t)0xCA) 00529 #define RTC_WPR_DisableKey2 ((uint8_t)0x53) 00530 00531 /** 00532 * @} 00533 */ 00534 00535 /** 00536 * @brief CSS on LSE registers. 00537 */ 00538 typedef struct CSSLSE_struct 00539 { 00540 __IO uint8_t CSR; /*!< Control and Status Register*/ 00541 } 00542 CSSLSE_TypeDef; 00543 00544 /** @addtogroup CSSLSE_Registers_Reset_Value 00545 * @{ 00546 */ 00547 #define CSSLSE_CSR_RESET_VALUE ((uint8_t)0x00) 00548 00549 /** 00550 * @} 00551 */ 00552 00553 /** @addtogroup CSSLSE_Registers_Bits_Definition 00554 * @{ 00555 */ 00556 00557 /* Bits definition for CSSLSE_CSR register*/ 00558 #define CSSLSE_CSR_SWITCHF ((uint8_t)0x10) 00559 #define CSSLSE_CSR_CSSF ((uint8_t)0x08) 00560 #define CSSLSE_CSR_CSSIE ((uint8_t)0x04) 00561 #define CSSLSE_CSR_SWITCHEN ((uint8_t)0x02) 00562 #define CSSLSE_CSR_CSSEN ((uint8_t)0x01) 00563 00564 /** 00565 * @} 00566 */ 00567 /*----------------------------------------------------------------------------*/ 00568 /** 00569 * @brief Beeper (BEEP) peripheral registers. 00570 */ 00571 00572 typedef struct BEEP_struct 00573 { 00574 __IO uint8_t CSR1; /*!< BEEP Control status register1 */ 00575 uint8_t RSERVED1; 00576 uint8_t RESERVED2; 00577 __IO uint8_t CSR2; /*!< BEEP Control status register2 */ 00578 } 00579 BEEP_TypeDef; 00580 00581 /** @addtogroup BEEP_Registers_Reset_Value 00582 * @{ 00583 */ 00584 #define BEEP_CSR1_RESET_VALUE ((uint8_t)0x00) 00585 #define BEEP_CSR2_RESET_VALUE ((uint8_t)0x1F) 00586 00587 /** 00588 * @} 00589 */ 00590 00591 /** @addtogroup BEEP_Registers_Bits_Definition 00592 * @{ 00593 */ 00594 00595 #define BEEP_CSR1_MSR ((uint8_t)0x01) /*!< Measurement enable mask */ 00596 00597 #define BEEP_CSR2_BEEPSEL ((uint8_t)0xC0) /*!< Beeper frequency selection mask */ 00598 #define BEEP_CSR2_BEEPEN ((uint8_t)0x20) /*!< Beeper enable mask */ 00599 #define BEEP_CSR2_BEEPDIV ((uint8_t)0x1F) /*!< Beeper Divider prescalar mask */ 00600 00601 /** 00602 * @} 00603 */ 00604 00605 /*----------------------------------------------------------------------------ok*/ 00606 00607 /** 00608 * @brief Configuration Registers (CFG) 00609 */ 00610 00611 typedef struct CFG_struct 00612 { 00613 __IO uint8_t GCR; /*!< Global Configuration register */ 00614 } 00615 CFG_TypeDef; 00616 00617 /** @addtogroup CFG_Registers_Reset_Value 00618 * @{ 00619 */ 00620 00621 #define CFG_GCR_RESET_VALUE ((uint8_t)0x00) 00622 00623 /** 00624 * @} 00625 */ 00626 00627 /** @addtogroup CFG_Registers_Bits_Definition 00628 * @{ 00629 */ 00630 00631 #define CFG_GCR_SWD ((uint8_t)0x01) /*!< Swim disable bit mask */ 00632 #define CFG_GCR_AL ((uint8_t)0x02) /*!< Activation Level bit mask */ 00633 00634 /** 00635 * @} 00636 */ 00637 /*----------------------------------------------------------------------------ok*/ 00638 00639 /** 00640 * @brief SYSCFG 00641 */ 00642 00643 typedef struct SYSCFG_struct 00644 { 00645 __IO uint8_t RMPCR3; /*!< Remap control register 3 */ 00646 __IO uint8_t RMPCR1; /*!< Remap control register 1 */ 00647 __IO uint8_t RMPCR2; /*!< Remap control register 2 */ 00648 } 00649 SYSCFG_TypeDef; 00650 00651 /** @addtogroup SYSCFG_Registers_Reset_Value 00652 * @{ 00653 */ 00654 #define SYSCFG_RMPCR1_RESET_VALUE ((uint8_t)0x0C) 00655 #define SYSCFG_RMPCR2_RESET_VALUE ((uint8_t)0x00) 00656 #define SYSCFG_RMPCR3_RESET_VALUE ((uint8_t)0x00) 00657 00658 /** 00659 * @} 00660 */ 00661 00662 /** @addtogroup SYSCFG_Registers_Bits_Definition 00663 * @{ 00664 */ 00665 00666 /* For DMA Channel Mapping*/ 00667 #define SYSCFG_RMPCR1_ADC1DMA_REMAP ((uint8_t)0x03) /*!< ADC1 DMA channel remapping */ 00668 #define SYSCFG_RMPCR1_TIM4DMA_REMAP ((uint8_t)0x0C) /*!< TIM4 DMA channel remapping */ 00669 00670 00671 /* For GPIO Reapping*/ 00672 #define SYSCFG_RMPCR1_USART1TR_REMAP ((uint8_t)0x30) /*!< USART1_TX and USART1_RX remapping */ 00673 #define SYSCFG_RMPCR1_USART1CK_REMAP ((uint8_t)0x40) /*!< USART1_CK remapping */ 00674 #define SYSCFG_RMPCR1_SPI1_REMAP ((uint8_t)0x80) /*!< SPI1 remapping */ 00675 00676 #define SYSCFG_RMPCR2_ADC1TRIG_REMAP ((uint8_t)0x01) /*!< ADC1 External Trigger remap */ 00677 #define SYSCFG_RMPCR2_TIM2TRIG_REMAP ((uint8_t)0x02) /*!< TIM2 Trigger remap */ 00678 #define SYSCFG_RMPCR2_TIM3TRIG_REMAP1 ((uint8_t)0x04) /*!< TIM3 Trigger remap 1 */ 00679 #define SYSCFG_RMPCR2_TIM2TRIG_LSE ((uint8_t)0x08) /*!< TIM2 Trigger remap to LSE */ 00680 #define SYSCFG_RMPCR2_TIM3TRIG_LSE ((uint8_t)0x10) /*!< TIM3 Trigger remap to LSE */ 00681 #define SYSCFG_RMPCR2_SPI2_REMAP ((uint8_t)0x20) /*!< SPI2 remapping */ 00682 #define SYSCFG_RMPCR2_TIM3TRIG_REMAP2 ((uint8_t)0x40) /*!< TIM3 Trigger remap 2 */ 00683 #define SYSCFG_RMPCR2_TIM23BKIN_REMAP ((uint8_t)0x80) /*!< TIM2 & TIM3 Break input remap */ 00684 00685 #define SYSCFG_RMPCR3_SPI1_REMAP ((uint8_t)0x01) /*!< SPI1 remapping */ 00686 #define SYSCFG_RMPCR3_USART3TR_REMAP ((uint8_t)0x02) /*!< USART3_TX and USART3_RX remapping */ 00687 #define SYSCFG_RMPCR3_USART3CK_REMAP ((uint8_t)0x04) /*!< USART3_CK remapping */ 00688 #define SYSCFG_RMPCR3_TIM3CH1_REMAP ((uint8_t)0x08) /*!< TIM3 channel 1 remapping */ 00689 #define SYSCFG_RMPCR3_TIM3CH2_REMAP ((uint8_t)0x10) /*!< TIM3 channel 2 remapping */ 00690 #define SYSCFG_RMPCR3_CCO_REMAP ((uint8_t)0x20) /*!< CCO remapping */ 00691 00692 /** 00693 * @} 00694 */ 00695 /*----------------------------------------------------------------------------ok*/ 00696 00697 /** 00698 * @brief Clock Controller (CLK) 00699 */ 00700 typedef struct CLK_struct 00701 { 00702 __IO uint8_t CKDIVR; /*!< Clock Master Divider Register */ 00703 __IO uint8_t CRTCR; /*!< RTC Clock selection Register */ 00704 __IO uint8_t ICKCR; /*!< Internal Clocks Control Register */ 00705 __IO uint8_t PCKENR1; /*!< Peripheral Clock Gating Register 1 */ 00706 __IO uint8_t PCKENR2; /*!< Peripheral Clock Gating Register 2 */ 00707 __IO uint8_t CCOR; /*!< Configurable Clock Output Register */ 00708 __IO uint8_t ECKCR; /*!< External Clocks Control Register */ 00709 __IO uint8_t SCSR; /*!< System clock status Register */ 00710 __IO uint8_t SWR; /*!< System clock Switch Register */ 00711 __IO uint8_t SWCR; /*!< Switch Control Register */ 00712 __IO uint8_t CSSR; /*!< Clock Security Sytem Register */ 00713 __IO uint8_t CBEEPR; /*!< Clock BEEP Register */ 00714 __IO uint8_t HSICALR; /*!< HSI Calibration Register */ 00715 __IO uint8_t HSITRIMR; /*!< HSI clock Calibration Trimmer Register */ 00716 __IO uint8_t HSIUNLCKR; /*!< HSI Unlock Register */ 00717 __IO uint8_t REGCSR; /*!< Main regulator control status register */ 00718 __IO uint8_t PCKENR3; /*!< Peripheral Clock Gating Register 3 */ 00719 } 00720 CLK_TypeDef; 00721 00722 /** @addtogroup CLK_Registers_Reset_Value 00723 * @{ 00724 */ 00725 #define CLK_CKDIVR_RESET_VALUE ((uint8_t)0x03) 00726 #define CLK_CRTCR_RESET_VALUE ((uint8_t)0x00) 00727 #define CLK_ICKCR_RESET_VALUE ((uint8_t)0x11) 00728 #define CLK_PCKENR1_RESET_VALUE ((uint8_t)0x00) 00729 #define CLK_PCKENR2_RESET_VALUE ((uint8_t)0x80) 00730 #define CLK_PCKENR3_RESET_VALUE ((uint8_t)0x00) 00731 #define CLK_CCOR_RESET_VALUE ((uint8_t)0x00) 00732 #define CLK_ECKCR_RESET_VALUE ((uint8_t)0x00) 00733 #define CLK_SCSR_RESET_VALUE ((uint8_t)0x01) 00734 #define CLK_SWR_RESET_VALUE ((uint8_t)0x01) 00735 #define CLK_SWCR_RESET_VALUE ((uint8_t)0x00) 00736 #define CLK_CSSR_RESET_VALUE ((uint8_t)0x00) 00737 #define CLK_CBEEPR_RESET_VALUE ((uint8_t)0x00) 00738 #define CLK_HSICALR_RESET_VALUE ((uint8_t)0x00) 00739 #define CLK_HSITRIMR_RESET_VALUE ((uint8_t)0x00) 00740 #define CLK_HSIUNLCKR_RESET_VALUE ((uint8_t)0x00) 00741 #define CLK_REGCSR_RESET_VALUE ((uint8_t)0xB9) 00742 /** 00743 * @} 00744 */ 00745 00746 /** @addtogroup CLK_Registers_Bits_Definition 00747 * @{ 00748 */ 00749 00750 #define CLK_CKDIVR_CKM ((uint8_t)0x07) /*!< System clock prescaler mask */ 00751 00752 #define CLK_CRTCR_RTCDIV ((uint8_t)0xE0) /*!< RTC clock prescaler mask*/ 00753 #define CLK_CRTCR_RTCSEL ((uint8_t)0x1E) /*!< RTC clock output selection mask */ 00754 #define CLK_CRTCR_RTCSWBSY ((uint8_t)0x01) /*!< RTC clock switch busy */ 00755 00756 #define CLK_ICKCR_BEEPAHALT ((uint8_t)0x40) /*!< BEEP clock Active Halt/Halt mode */ 00757 #define CLK_ICKCR_FHWU ((uint8_t)0x20) /*!< Fast Wake-up from Active Halt/Halt mode */ 00758 #define CLK_ICKCR_SAHALT ((uint8_t)0x10) /*!< Slow Active-halt mode */ 00759 #define CLK_ICKCR_LSIRDY ((uint8_t)0x08) /*!< Low speed internal RC oscillator ready */ 00760 #define CLK_ICKCR_LSION ((uint8_t)0x04) /*!< Low speed internal RC oscillator enable */ 00761 #define CLK_ICKCR_HSIRDY ((uint8_t)0x02) /*!< High speed internal RC oscillator ready */ 00762 #define CLK_ICKCR_HSION ((uint8_t)0x01) /*!< High speed internal RC oscillator enable */ 00763 00764 #define CLK_PCKENR1_TIM2 ((uint8_t)0x01) /*!< Timer 2 clock enable */ 00765 #define CLK_PCKENR1_TIM3 ((uint8_t)0x02) /*!< Timer 3 clock enable */ 00766 #define CLK_PCKENR1_TIM4 ((uint8_t)0x04) /*!< Timer 4 clock enable */ 00767 #define CLK_PCKENR1_I2C1 ((uint8_t)0x08) /*!< I2C1 clock enable */ 00768 #define CLK_PCKENR1_SPI1 ((uint8_t)0x10) /*!< SPI1 clock enable */ 00769 #define CLK_PCKENR1_USART1 ((uint8_t)0x20) /*!< USART1 clock enable */ 00770 #define CLK_PCKENR1_BEEP ((uint8_t)0x40) /*!< BEEP clock enable */ 00771 #define CLK_PCKENR1_DAC ((uint8_t)0x80) /*!< DAC clock enable */ 00772 00773 #define CLK_PCKENR2_ADC1 ((uint8_t)0x01) /*!< ADC1 clock enable */ 00774 #define CLK_PCKENR2_TIM1 ((uint8_t)0x02) /*!< TIM1 clock enable */ 00775 #define CLK_PCKENR2_RTC ((uint8_t)0x04) /*!< RTC clock enable */ 00776 #define CLK_PCKENR2_LCD ((uint8_t)0x08) /*!< LCD clock enable */ 00777 #define CLK_PCKENR2_DMA1 ((uint8_t)0x10) /*!< DMA1 clock enable */ 00778 #define CLK_PCKENR2_COMP ((uint8_t)0x20) /*!< Comparator clock enable */ 00779 #define CLK_PCKENR2_BOOTROM ((uint8_t)0x80) /*!< Boot ROM clock enable */ 00780 00781 #define CLK_PCKENR3_AES ((uint8_t)0x01) /*!< AES clock enable */ 00782 #define CLK_PCKENR3_TIM5 ((uint8_t)0x02) /*!< Timer 5 clock enable */ 00783 #define CLK_PCKENR3_SPI2 ((uint8_t)0x04) /*!< SPI2 clock enable */ 00784 #define CLK_PCKENR3_UASRT2 ((uint8_t)0x08) /*!< USART2 clock enable */ 00785 #define CLK_PCKENR3_USART3 ((uint8_t)0x10) /*!< USART3 clock enable */ 00786 00787 #define CLK_CCOR_CCODIV ((uint8_t)0xE0) /*!< Configurable Clock output prescaler */ 00788 #define CLK_CCOR_CCOSEL ((uint8_t)0x1E) /*!< Configurable clock output selection */ 00789 #define CLK_CCOR_CCOSWBSY ((uint8_t)0x01) /*!< Configurable clock output switch busy flag */ 00790 00791 #define CLK_ECKCR_LSEBYP ((uint8_t)0x20) /*!< Low speed external clock bypass */ 00792 #define CLK_ECKCR_HSEBYP ((uint8_t)0x10) /*!< High speed external clock bypass */ 00793 #define CLK_ECKCR_LSERDY ((uint8_t)0x08) /*!< Low speed external crystal oscillator ready */ 00794 #define CLK_ECKCR_LSEON ((uint8_t)0x04) /*!< Low speed external crystal oscillator enable */ 00795 #define CLK_ECKCR_HSERDY ((uint8_t)0x02) /*!< High speed external crystal oscillator ready */ 00796 #define CLK_ECKCR_HSEON ((uint8_t)0x01) /*!< High speed external crystal oscillator enable */ 00797 00798 #define CLK_SCSR_CKM ((uint8_t)0x0F) /*!< System clock status bits */ 00799 00800 #define CLK_SWR_SWI ((uint8_t)0x0F) /*!< System clock selection bits */ 00801 00802 #define CLK_SWCR_SWIF ((uint8_t)0x08) /*!< Clock switch interrupt flag */ 00803 #define CLK_SWCR_SWIEN ((uint8_t)0x04) /*!< Clock switch interrupt enable */ 00804 #define CLK_SWCR_SWEN ((uint8_t)0x02) /*!< Switch start/stop */ 00805 #define CLK_SWCR_SWBSY ((uint8_t)0x01) /*!< Switch busy */ 00806 00807 #define CLK_CSSR_CSSDGON ((uint8_t)0x10) /*!< Clock security sytem deglitcher system */ 00808 #define CLK_CSSR_CSSD ((uint8_t)0x08) /*!< Clock security sytem detection */ 00809 #define CLK_CSSR_CSSDIE ((uint8_t)0x04) /*!< Clock security system detection interrupt enable */ 00810 #define CLK_CSSR_AUX ((uint8_t)0x02) /*!< Auxiliary oscillator connected to master clock */ 00811 #define CLK_CSSR_CSSEN ((uint8_t)0x01) /*!< Clock security system enable */ 00812 00813 #define CLK_CBEEPR_CLKBEEPSEL ((uint8_t)0x06) /*!< Configurable BEEP clock source selection */ 00814 #define CLK_CBEEPR_BEEPSWBSY ((uint8_t)0x01) /*!< BEEP clock busy in switch */ 00815 00816 #define CLK_HSICALR_HSICAL ((uint8_t)0xFF) /*!< Copy of otpion byte trimming HSI oscillator */ 00817 00818 #define CLK_HSITRIMR_HSITRIM ((uint8_t)0xFF) /*!< High speed internal oscillator trimmer */ 00819 00820 #define CLK_HSIUNLCKR_HSIUNLCK ((uint8_t)0xFF) /*!< High speed internal oscillator trimmer unlock */ 00821 00822 #define CLK_REGCSR_EEREADY ((uint8_t)0x80) /*!< Flash program memory and Data EEPROM ready */ 00823 #define CLK_REGCSR_EEBUSY ((uint8_t)0x40) /*!< Flash program memory and Data EEPROM busy */ 00824 #define CLK_REGCSR_LSEPD ((uint8_t)0x20) /*!< LSE power-down */ 00825 #define CLK_REGCSR_HSEPD ((uint8_t)0x10) /*!< HSE power-down */ 00826 #define CLK_REGCSR_LSIPD ((uint8_t)0x08) /*!< LSI power-down */ 00827 #define CLK_REGCSR_HSIPD ((uint8_t)0x04) /*!< HSI power-down */ 00828 #define CLK_REGCSR_REGOFF ((uint8_t)0x02) /*!< Main regulator OFF */ 00829 #define CLK_REGCSR_REGREADY ((uint8_t)0x01) /*!< Main regulator ready */ 00830 00831 /** 00832 * @} 00833 */ 00834 /*----------------------------------------------------------------------------ok*/ 00835 00836 /** 00837 * @brief Comparator interface (COMP) 00838 */ 00839 00840 typedef struct COMP_struct 00841 { 00842 __IO uint8_t CSR1; /*!< Control status register 1 */ 00843 __IO uint8_t CSR2; /*!< Control status register 2 */ 00844 __IO uint8_t CSR3; /*!< Control status register 3 */ 00845 __IO uint8_t CSR4; /*!< Control status register 4 */ 00846 __IO uint8_t CSR5; /*!< Control status register 5 */ 00847 } 00848 COMP_TypeDef; 00849 00850 00851 /** @addtogroup COMP_Registers_Reset_Value 00852 * @{ 00853 */ 00854 #define COMP_CSR1_RESET_VALUE ((uint8_t)0x00) 00855 #define COMP_CSR2_RESET_VALUE ((uint8_t)0x00) 00856 #define COMP_CSR3_RESET_VALUE ((uint8_t)0xC0) 00857 #define COMP_CSR4_RESET_VALUE ((uint8_t)0x00) 00858 #define COMP_CSR5_RESET_VALUE ((uint8_t)0x00) 00859 00860 /** 00861 * @} 00862 */ 00863 00864 /** @addtogroup COMP_Registers_Bits_Definition 00865 * @{ 00866 */ 00867 00868 /* CSR1 */ 00869 #define COMP_CSR1_IE1 ((uint8_t)0x20) /*!< Comparator 1 Interrupt Enable Mask. */ 00870 #define COMP_CSR1_EF1 ((uint8_t)0x10) /*!< Comparator 1 Event Flag Mask. */ 00871 #define COMP_CSR1_CMP1OUT ((uint8_t)0x08) /*!< Comparator 1 Ouptput Mask. */ 00872 #define COMP_CSR1_STE ((uint8_t)0x04) /*!< Schmitt trigger enable Mask. */ 00873 #define COMP_CSR1_CMP1 ((uint8_t)0x03) /*!< Comparator 1 Configuration Mask. */ 00874 00875 /* CSR2 */ 00876 #define COMP_CSR2_IE2 ((uint8_t)0x20) /*!< Comparator 2 Interrupt Enable Mask. */ 00877 #define COMP_CSR2_EF2 ((uint8_t)0x10) /*!< Comparator 2 Event Flag Mask. */ 00878 #define COMP_CSR2_CMP2OUT ((uint8_t)0x08) /*!< Comparator 2 Ouptput Mask. */ 00879 #define COMP_CSR2_SPEED ((uint8_t)0x04) /*!< Comparator 2 speed modeMask. */ 00880 #define COMP_CSR2_CMP2 ((uint8_t)0x03) /*!< Comparator 2 Configuration Mask. */ 00881 00882 /* CSR3 */ 00883 #define COMP_CSR3_OUTSEL ((uint8_t)0xC0) /*!< Comparator 2 output selection Mask. */ 00884 #define COMP_CSR3_INSEL ((uint8_t)0x38) /*!< Inversion input selection Mask. */ 00885 #define COMP_CSR3_VREFEN ((uint8_t)0x04) /*!< Internal reference voltage Enable Mask. */ 00886 #define COMP_CSR3_WNDWE ((uint8_t)0x02) /*!< Window Mode Enable Mask. */ 00887 #define COMP_CSR3_VREFOUTEN ((uint8_t)0x01) /*!< VREF Output Enable Mask. */ 00888 00889 /* CSR4 */ 00890 #define COMP_CSR4_NINVTRIG ((uint8_t)0x38) /*!< COMP2 non-inverting input Mask. */ 00891 #define COMP_CSR4_INVTRIG ((uint8_t)0x07) /*!< COMP2 inverting input Mask. */ 00892 00893 /* CSR5 */ 00894 #define COMP_CSR5_DACTRIG ((uint8_t)0x38) /*!< DAC outputs Mask. */ 00895 #define COMP_CSR5_VREFTRIG ((uint8_t)0x07) /*!< VREF outputs Mask. */ 00896 00897 /** 00898 * @} 00899 */ 00900 00901 /*----------------------------------------------------------------------------ok*/ 00902 00903 /** 00904 * @brief External Interrupt Controller (EXTI) 00905 */ 00906 typedef struct EXTI_struct 00907 { 00908 __IO uint8_t CR1; /*!< The four LSB EXTI pin sensitivity */ 00909 __IO uint8_t CR2; /*!< The four MSB EXTI pin sensitivity */ 00910 __IO uint8_t CR3; /*!< EXTI port B & port D sensitivity */ 00911 __IO uint8_t SR1; /*!< Pins Status flag register 1 */ 00912 __IO uint8_t SR2; /*!< Ports Status flage register 2 */ 00913 __IO uint8_t CONF1; /*!< Port interrupt selector */ 00914 uint8_t RESERVED[4]; /*!< reserved area */ 00915 __IO uint8_t CR4; /*!< EXTI port G & port H sensitivity */ 00916 __IO uint8_t CONF2; /*!< Port interrupt selector */ 00917 } 00918 EXTI_TypeDef; 00919 00920 /** @addtogroup EXTI_Registers_Reset_Value 00921 * @{ 00922 */ 00923 00924 #define EXTI_CR1_RESET_VALUE ((uint8_t)0x00) 00925 #define EXTI_CR2_RESET_VALUE ((uint8_t)0x00) 00926 #define EXTI_CR3_RESET_VALUE ((uint8_t)0x00) 00927 #define EXTI_CONF1_RESET_VALUE ((uint8_t)0x00) 00928 #define EXTI_SR1_RESET_VALUE ((uint8_t)0x00) 00929 #define EXTI_SR2_RESET_VALUE ((uint8_t)0x00) 00930 #define EXTI_CR4_RESET_VALUE ((uint8_t)0x00) 00931 #define EXTI_CONF2_RESET_VALUE ((uint8_t)0x00) 00932 00933 /** 00934 * @} 00935 */ 00936 00937 /** @addtogroup EXTI_Registers_Bits_Definition 00938 * @{ 00939 */ 00940 /* CR1 */ 00941 #define EXTI_CR1_P3IS ((uint8_t)0xC0) /*!< EXTI Pin 3 external interrupt sensitivity bit Mask */ 00942 #define EXTI_CR1_P2IS ((uint8_t)0x30) /*!< EXTI Pin 2 external interrupt sensitivity bit Mask */ 00943 #define EXTI_CR1_P1IS ((uint8_t)0x0C) /*!< EXTI Pin 1 external interrupt sensitivity bit Mask */ 00944 #define EXTI_CR1_P0IS ((uint8_t)0x03) /*!< EXTI Pin 0 external interrupt sensitivity bit Mask */ 00945 00946 /* CR2 */ 00947 #define EXTI_CR2_P7IS ((uint8_t)0xC0) /*!< EXTI Pin 7 external interrupt sensitivity bit Mask */ 00948 #define EXTI_CR2_P6IS ((uint8_t)0x30) /*!< EXTI Pin 6 external interrupt sensitivity bit Mask */ 00949 #define EXTI_CR2_P5IS ((uint8_t)0x0C) /*!< EXTI Pin 5 external interrupt sensitivity bit Mask */ 00950 #define EXTI_CR2_P4IS ((uint8_t)0x03) /*!< EXTI Pin 4 external interrupt sensitivity bit Mask */ 00951 00952 /* CR3 */ 00953 #define EXTI_CR3_PBIS ((uint8_t)0x03) /*!< EXTI PORTB external interrupt sensitivity bits Mask */ 00954 #define EXTI_CR3_PDIS ((uint8_t)0x0C) /*!< EXTI PORTD external interrupt sensitivity bits Mask */ 00955 #define EXTI_CR3_PEIS ((uint8_t)0x30) /*!< EXTI PORTE external interrupt sensitivity bits Mask */ 00956 #define EXTI_CR3_PFIS ((uint8_t)0xC0) /*!< EXTI PORTF external interrupt sensitivity bits Mask */ 00957 00958 /* CONF1 */ 00959 #define EXTI_CONF1_PBLIS ((uint8_t)0x01) /*!< EXTI PORTB low interrupt selector bit Mask */ 00960 #define EXTI_CONF1_PBHIS ((uint8_t)0x02) /*!< EXTI PORTB high interrupt selector bit Mask */ 00961 #define EXTI_CONF1_PDLIS ((uint8_t)0x04) /*!< EXTI PORTD low interrupt selector bit Mask */ 00962 #define EXTI_CONF1_PDHIS ((uint8_t)0x08) /*!< EXTI PORTD high interrupt selector bit Mask */ 00963 #define EXTI_CONF1_PELIS ((uint8_t)0x10) /*!< EXTI PORTE low interrupt selector bit Mask */ 00964 #define EXTI_CONF1_PEHIS ((uint8_t)0x20) /*!< EXTI PORTE high interrupt selector bit Mask */ 00965 #define EXTI_CONF1_PFLIS ((uint8_t)0x40) /*!< EXTI PORTF low interrupt selector bit Mask */ 00966 #define EXTI_CONF1_PFES ((uint8_t)0x80) /*!< EXTI PORTF or PORTE interrupt selector bit Mask */ 00967 00968 /* CR4 */ 00969 #define EXTI_CR4_PGIS ((uint8_t)0x03) /*!< EXTI PORTG external interrupt sensitivity bits Mask */ 00970 #define EXTI_CR4_PHIS ((uint8_t)0x0C) /*!< EXTI PORTH external interrupt sensitivity bits Mask */ 00971 00972 /* CONF2 */ 00973 #define EXTI_CONF2_PFHIS ((uint8_t)0x01) /*!< EXTI PORTF high interrupt selector bit Mask */ 00974 #define EXTI_CONF2_PGLIS ((uint8_t)0x02) /*!< EXTI PORTG low interrupt selector bit Mask */ 00975 #define EXTI_CONF2_PGHIS ((uint8_t)0x04) /*!< EXTI PORTG high interrupt selector bit Mask */ 00976 #define EXTI_CONF2_PHLIS ((uint8_t)0x08) /*!< EXTI PORTH low interrupt selector bit Mask */ 00977 #define EXTI_CONF2_PHHIS ((uint8_t)0x10) /*!< EXTI PORTH high interrupt selector bit Mask */ 00978 #define EXTI_CONF2_PGBS ((uint8_t)0x20) /*!< EXTI PORTB or PORTG interrupt selector bit Mask */ 00979 #define EXTI_CONF2_PHDS ((uint8_t)0x40) /*!< EXTI PORTD or PORTH interrupt selector bit Mask */ 00980 00981 /** 00982 * @} 00983 */ 00984 00985 /*----------------------------------------------------------------------------ok*/ 00986 00987 /** 00988 * @brief FLASH and Data EEPROM 00989 */ 00990 typedef struct FLASH_struct 00991 { 00992 __IO uint8_t CR1; /*!< Flash control register 1 */ 00993 __IO uint8_t CR2; /*!< Flash control register 2 */ 00994 __IO uint8_t PUKR; /*!< Flash program memory unprotection register */ 00995 __IO uint8_t DUKR; /*!< Data EEPROM unprotection register */ 00996 __IO uint8_t IAPSR; /*!< Flash in-application programming status register */ 00997 } 00998 FLASH_TypeDef; 00999 01000 /** @addtogroup FLASH_Registers_Reset_Value 01001 * @{ 01002 */ 01003 #define FLASH_CR1_RESET_VALUE ((uint8_t)0x00) 01004 #define FLASH_CR2_RESET_VALUE ((uint8_t)0x00) 01005 #define FLASH_PUKR_RESET_VALUE ((uint8_t)0xAE) 01006 #define FLASH_DUKR_RESET_VALUE ((uint8_t)0x56) 01007 #define FLASH_IAPSR_RESET_VALUE ((uint8_t)0x40) 01008 01009 01010 /** 01011 * @} 01012 */ 01013 01014 /** @addtogroup FLASH_Registers_Bits_Definition 01015 * @{ 01016 */ 01017 #define FLASH_CR1_EEPM ((uint8_t)0x08) /*!< Flash low power selection during Run and Low power run mode Mask */ 01018 #define FLASH_CR1_WAITM ((uint8_t)0x04) /*!< Flash low power selection during Wait and Low power wait mode Mask */ 01019 #define FLASH_CR1_IE ((uint8_t)0x02) /*!< Flash Interrupt enable Mask */ 01020 #define FLASH_CR1_FIX ((uint8_t)0x01) /*!< Fix programming time Mask */ 01021 01022 #define FLASH_CR2_OPT ((uint8_t)0x80) /*!< Enable write access to option bytes*/ 01023 #define FLASH_CR2_WPRG ((uint8_t)0x40) /*!< Word write once Mask */ 01024 #define FLASH_CR2_ERASE ((uint8_t)0x20) /*!< Erase block Mask */ 01025 #define FLASH_CR2_FPRG ((uint8_t)0x10) /*!< Fast programming mode Mask */ 01026 #define FLASH_CR2_PRG ((uint8_t)0x01) /*!< Program block Mask */ 01027 01028 #define FLASH_IAPSR_HVOFF ((uint8_t)0x40) /*!< End of high voltage flag Mask */ 01029 #define FLASH_IAPSR_DUL ((uint8_t)0x08) /*!< Data EEPROM unlocked flag Mask */ 01030 #define FLASH_IAPSR_EOP ((uint8_t)0x04) /*!< End of operation flag Mask */ 01031 #define FLASH_IAPSR_PUL ((uint8_t)0x02) /*!< Program memory unlocked flag Mask */ 01032 #define FLASH_IAPSR_WR_PG_DIS ((uint8_t)0x01) /*!< Write attempted to protected page Mask */ 01033 01034 #define FLASH_PUKR_PUK ((uint8_t)0xFF) /*!< Flash Program memory unprotection mask */ 01035 01036 #define FLASH_DUKR_DUK ((uint8_t)0xFF) /*!< Data EEPROM unprotection mask */ 01037 01038 01039 /** 01040 * @} 01041 */ 01042 01043 /*----------------------------------------------------------------------------*/ 01044 01045 /** 01046 * @brief Inter-Integrated Circuit (I2C) 01047 */ 01048 typedef struct I2C_struct 01049 { 01050 __IO uint8_t CR1; /*!< I2C control register 1 */ 01051 __IO uint8_t CR2; /*!< I2C control register 2 */ 01052 __IO uint8_t FREQR; /*!< I2C frequency register */ 01053 __IO uint8_t OARL; /*!< I2C own address register 1 LSB */ 01054 __IO uint8_t OARH; /*!< I2C own address register 1 MSB */ 01055 __IO uint8_t OAR2; /*!< I2C own address register 2 */ 01056 __IO uint8_t DR; /*!< I2C data register */ 01057 __IO uint8_t SR1; /*!< I2C status register 1 */ 01058 __IO uint8_t SR2; /*!< I2C status register 2 */ 01059 __IO uint8_t SR3; /*!< I2C status register 3 */ 01060 __IO uint8_t ITR; /*!< I2C interrupt & DMA register */ 01061 __IO uint8_t CCRL; /*!< I2C clock control register low */ 01062 __IO uint8_t CCRH; /*!< I2C clock control register high */ 01063 __IO uint8_t TRISER; /*!< I2C maximum rise time register */ 01064 __IO uint8_t PECR; /*!< I2CPacket Error Checking register */ 01065 } 01066 I2C_TypeDef; 01067 01068 /** @addtogroup I2C_Registers_Reset_Value 01069 * @{ 01070 */ 01071 #define I2C_CR1_RESET_VALUE ((uint8_t)0x00) 01072 #define I2C_CR2_RESET_VALUE ((uint8_t)0x00) 01073 #define I2C_FREQR_RESET_VALUE ((uint8_t)0x00) 01074 #define I2C_OARL_RESET_VALUE ((uint8_t)0x00) 01075 #define I2C_OARH_RESET_VALUE ((uint8_t)0x00) 01076 #define I2C_OAR2_RESET_VALUE ((uint8_t)0x00) 01077 #define I2C_DR_RESET_VALUE ((uint8_t)0x00) 01078 #define I2C_SR1_RESET_VALUE ((uint8_t)0x00) 01079 #define I2C_SR2_RESET_VALUE ((uint8_t)0x00) 01080 #define I2C_SR3_RESET_VALUE ((uint8_t)0x00) 01081 #define I2C_ITR_RESET_VALUE ((uint8_t)0x00) 01082 #define I2C_CCRL_RESET_VALUE ((uint8_t)0x00) 01083 #define I2C_CCRH_RESET_VALUE ((uint8_t)0x00) 01084 #define I2C_TRISER_RESET_VALUE ((uint8_t)0x02) 01085 #define I2C_PECR_RESET_VALUE ((uint8_t)0x00) 01086 01087 /** 01088 * @} 01089 */ 01090 01091 /** @addtogroup I2C_Registers_Bits_Definition 01092 * @{ 01093 */ 01094 01095 #define I2C_CR1_NOSTRETCH ((uint8_t)0x80) /*!< Clock Stretching Disable (Slave mode) */ 01096 #define I2C_CR1_ENGC ((uint8_t)0x40) /*!< General Call Enable */ 01097 #define I2C_CR1_ENPEC ((uint8_t)0x20) /*!< PEC Enable */ 01098 #define I2C_CR1_ARP ((uint8_t)0x10) /*!< ARP Enable */ 01099 #define I2C_CR1_SMBTYPE ((uint8_t)0x08) /*!< SMBus type */ 01100 #define I2C_CR1_SMBUS ((uint8_t)0x02) /*!< SMBus mode */ 01101 #define I2C_CR1_PE ((uint8_t)0x01) /*!< Peripheral Enable */ 01102 01103 #define I2C_CR2_SWRST ((uint8_t)0x80) /*!< Software Reset */ 01104 #define I2C_CR2_ALERT ((uint8_t)0x20) /*!< SMBus Alert*/ 01105 #define I2C_CR2_PEC ((uint8_t)0x10) /*!< Packet Error Checking */ 01106 #define I2C_CR2_POS ((uint8_t)0x08) /*!< Acknowledge */ 01107 #define I2C_CR2_ACK ((uint8_t)0x04) /*!< Acknowledge Enable */ 01108 #define I2C_CR2_STOP ((uint8_t)0x02) /*!< Stop Generation */ 01109 #define I2C_CR2_START ((uint8_t)0x01) /*!< Start Generation */ 01110 01111 #define I2C_FREQR_FREQ ((uint8_t)0x3F) /*!< Peripheral Clock Frequency */ 01112 01113 #define I2C_OARL_ADD ((uint8_t)0xFE) /*!< Interface Address bits [7..1] */ 01114 #define I2C_OARL_ADD0 ((uint8_t)0x01) /*!< Interface Address bit0 */ 01115 01116 #define I2C_OARH_ADDMODE ((uint8_t)0x80) /*!< Addressing Mode (Slave mode) */ 01117 #define I2C_OARH_ADDCONF ((uint8_t)0x40) /*!< Address mode configuration */ 01118 #define I2C_OARH_ADD ((uint8_t)0x06) /*!< Interface Address bits [9..8] */ 01119 01120 #define I2C_OAR2_ADD2 ((uint8_t)0xFE) /*!< Interface Address bits [7..1] */ 01121 #define I2C_OAR2_ENDUAL ((uint8_t)0x01) /*!< Dual addressing mode enable */ 01122 01123 #define I2C_DR_DR ((uint8_t)0xFF) /*!< Data Register */ 01124 01125 #define I2C_SR1_TXE ((uint8_t)0x80) /*!< Data Register Empty (transmitters) */ 01126 #define I2C_SR1_RXNE ((uint8_t)0x40) /*!< Data Register not Empty (receivers) */ 01127 #define I2C_SR1_STOPF ((uint8_t)0x10) /*!< Stop detection (Slave mode) */ 01128 #define I2C_SR1_ADD10 ((uint8_t)0x08) /*!< 10-bit header sent (Master mode) */ 01129 #define I2C_SR1_BTF ((uint8_t)0x04) /*!< Byte Transfer Finished */ 01130 #define I2C_SR1_ADDR ((uint8_t)0x02) /*!< Address sent (master mode)/matched (slave mode) */ 01131 #define I2C_SR1_SB ((uint8_t)0x01) /*!< Start Bit (Master mode) */ 01132 01133 #define I2C_SR2_SMBALERT ((uint8_t)0x80) /*!< SMBus Alert */ 01134 #define I2C_SR2_TIMEOUT ((uint8_t)0x40) /*!< Time out or TLow error */ 01135 #define I2C_SR2_WUFH ((uint8_t)0x20) /*!< Wake-up from Halt */ 01136 #define I2C_SR2_PECERR ((uint8_t)0x10) /*!< PEC error in reception */ 01137 #define I2C_SR2_OVR ((uint8_t)0x08) /*!< Overrun/Underrun */ 01138 #define I2C_SR2_AF ((uint8_t)0x04) /*!< Acknowledge Failure */ 01139 #define I2C_SR2_ARLO ((uint8_t)0x02) /*!< Arbitration Lost (master mode) */ 01140 #define I2C_SR2_BERR ((uint8_t)0x01) /*!< Bus Error */ 01141 01142 #define I2C_SR3_DUALF ((uint8_t)0x80) /*!< Dual flag (Slave mode) */ 01143 #define I2C_SR3_SMBHOST ((uint8_t)0x40) /*!< SMBus Host Header (Slave mode) */ 01144 #define I2C_SR3_SMBDEFAULT ((uint8_t)0x20) /*!< SMBus Default Header (Slave mode) */ 01145 #define I2C_SR3_GENCALL ((uint8_t)0x10) /*!< General Call Header (Slave mode) */ 01146 #define I2C_SR3_TRA ((uint8_t)0x04) /*!< Transmitter/Receiver */ 01147 #define I2C_SR3_BUSY ((uint8_t)0x02) /*!< Bus Busy */ 01148 #define I2C_SR3_MSL ((uint8_t)0x01) /*!< Master/Slave */ 01149 01150 #define I2C_ITR_LAST ((uint8_t)0x10) /*!< DMA Last transfer */ 01151 #define I2C_ITR_DMAEN ((uint8_t)0x08) /*!< DMA request Enable */ 01152 #define I2C_ITR_ITBUFEN ((uint8_t)0x04) /*!< Buffer Interrupt Enable */ 01153 #define I2C_ITR_ITEVTEN ((uint8_t)0x02) /*!< Event Interrupt Enable */ 01154 #define I2C_ITR_ITERREN ((uint8_t)0x01) /*!< Error Interrupt Enable */ 01155 01156 #define I2C_CCRL_CCR ((uint8_t)0xFF) /*!< Clock Control Register (Master mode) */ 01157 01158 #define I2C_CCRH_FS ((uint8_t)0x80) /*!< Master Mode Selection */ 01159 #define I2C_CCRH_DUTY ((uint8_t)0x40) /*!< Fast Mode Duty Cycle */ 01160 #define I2C_CCRH_CCR ((uint8_t)0x0F) /*!< Clock Control Register in Fast/Standard mode (Master mode) bits [11..8] */ 01161 01162 #define I2C_TRISER_TRISE ((uint8_t)0x3F) /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */ 01163 01164 #define I2C_PECR_PEC ((uint8_t)0xFF) /*!< Packet error checking */ 01165 01166 /** 01167 * @} 01168 */ 01169 01170 /*----------------------------------------------------------------------------*/ 01171 01172 /** 01173 * @brief IR digital interface (IRTIM) 01174 */ 01175 typedef struct IRTIM_struct 01176 { 01177 __IO uint8_t CR; /*!< control register */ 01178 } 01179 IRTIM_TypeDef; 01180 /** @addtogroup IRTIM_Registers_Reset_Value 01181 * @{ 01182 */ 01183 #define IRTIM_CR_RESET_VALUE ((uint8_t)0x00) 01184 01185 01186 /** 01187 * @} 01188 */ 01189 01190 /** @addtogroup IRTIM_Registers_Bits_Definition 01191 * @{ 01192 */ 01193 /* CR*/ 01194 #define IRTIM_CR_EN ((uint8_t)0x01) /*!< IRTIM_OUT enable Mask. */ 01195 #define IRTIM_CR_HSEN ((uint8_t)0x02) /*!< High sink open drain buffer enable Mask */ 01196 01197 /** 01198 * @} 01199 */ 01200 01201 /*----------------------------------------------------------------------------*/ 01202 01203 /** 01204 * @brief Interrupt Controller (ITC) 01205 */ 01206 typedef struct ITC_struct 01207 { 01208 __IO uint8_t ISPR1; /*!< Interrupt Software Priority register 1 */ 01209 __IO uint8_t ISPR2; /*!< Interrupt Software Priority register 2 */ 01210 __IO uint8_t ISPR3; /*!< Interrupt Software Priority register 3 */ 01211 __IO uint8_t ISPR4; /*!< Interrupt Software Priority register 4 */ 01212 __IO uint8_t ISPR5; /*!< Interrupt Software Priority register 5 */ 01213 __IO uint8_t ISPR6; /*!< Interrupt Software Priority register 6 */ 01214 __IO uint8_t ISPR7; /*!< Interrupt Software Priority register 7 */ 01215 __IO uint8_t ISPR8; /*!< Interrupt Software Priority register 8 */ 01216 } 01217 ITC_TypeDef; 01218 01219 /** @addtogroup ITC_Registers_Reset_Value 01220 * @{ 01221 */ 01222 #define ITC_SPRX_RESET_VALUE ((uint8_t)0xFF) /*!< Reset value of Software Priority registers 0 to 7 */ 01223 /** 01224 * @} 01225 */ 01226 01227 /*----------------------------------------------------------------------------*/ 01228 01229 /** 01230 * @brief Internal Low Speed Watchdog (IWDG) 01231 */ 01232 typedef struct IWDG_struct 01233 { 01234 __IO uint8_t KR; /*!< Low Speed Watchdog Key Register */ 01235 __IO uint8_t PR; /*!< Low Speed Watchdog Prescaler Register */ 01236 __IO uint8_t RLR; /*!< Low Speed Watchdog Reload Register */ 01237 } 01238 IWDG_TypeDef; 01239 01240 /** @addtogroup IWDG_Registers_Reset_Value 01241 * @{ 01242 */ 01243 #define IWDG_RLR_RESET_VALUE ((uint8_t)0xFF) /*! <Reload Register Default Value */ 01244 #define IWDG_PR_RESET_VALUE ((uint8_t)0x00) /*! <Prescaler Register Default Value */ 01245 /** 01246 * @} 01247 */ 01248 /*----------------------------------------------------------------------------*/ 01249 01250 01251 /** 01252 * @brief Wait For Event (WFE) peripheral registers. 01253 */ 01254 /** @addtogroup WFE_Registers 01255 * @{ 01256 */ 01257 typedef struct WFE_struct 01258 { 01259 __IO uint8_t CR1; /*!< Wait for event control register 1 */ 01260 __IO uint8_t CR2; /*!< Wait for event control register 2 */ 01261 __IO uint8_t CR3; /*!< Wait for event control register 3 */ 01262 __IO uint8_t CR4; /*!< Wait for event control register 4 */ 01263 } 01264 WFE_TypeDef; 01265 /** 01266 * @} 01267 */ 01268 /** @addtogroup WFE_Registers_Reset_Value 01269 * @{ 01270 */ 01271 01272 #define WFE_CRX_RESET_VALUE ((uint8_t)0x00) /*!< Reset value wait for event control register */ 01273 /** 01274 * @} 01275 */ 01276 01277 /** @addtogroup WFE_Registers_Bits_Definition 01278 * @{ 01279 */ 01280 01281 #define WFE_CR1_EXTI_EV3 ((uint8_t)0x80) /*!< External interrupt event 3 Mask */ 01282 #define WFE_CR1_EXTI_EV2 ((uint8_t)0x40) /*!< External interrupt event 2 Mask */ 01283 #define WFE_CR1_EXTI_EV1 ((uint8_t)0x20) /*!< External interrupt event 1 Mask */ 01284 #define WFE_CR1_EXTI_EV0 ((uint8_t)0x10) /*!< External interrupt event 0 Mask */ 01285 #define WFE_CR1_TIM1_EV1 ((uint8_t)0x08) /*!< TIM1 event 1 Mask */ 01286 #define WFE_CR1_TIM1_EV0 ((uint8_t)0x04) /*!< TIM1 event 0 Mask */ 01287 #define WFE_CR1_TIM2_EV1 ((uint8_t)0x02) /*!< TIM2 event 1 Mask */ 01288 #define WFE_CR1_TIM2_EV0 ((uint8_t)0x01) /*!< TIM2 event 0 Mask */ 01289 01290 #define WFE_CR2_ADC1_COMP_EV ((uint8_t)0x80) /*!< ADC / COMP event Mask*/ 01291 #define WFE_CR2_EXTI_EVEF ((uint8_t)0x40) /*!< External interrupt event on Port E or Port F Mask */ 01292 #define WFE_CR2_EXTI_EVDH ((uint8_t)0x20) /*!< External interrupt event on Port D or Port H Mask */ 01293 #define WFE_CR2_EXTI_EVBG ((uint8_t)0x10) /*!< External interrupt event on Port B or Port G Mask */ 01294 #define WFE_CR2_EXTI_EV7 ((uint8_t)0x08) /*!< External interrupt event 7 Mask */ 01295 #define WFE_CR2_EXTI_EV6 ((uint8_t)0x04) /*!< External interrupt event 6 Mask */ 01296 #define WFE_CR2_EXTI_EV5 ((uint8_t)0x02) /*!< External interrupt event 5 Mask */ 01297 #define WFE_CR2_EXTI_EV4 ((uint8_t)0x01) /*!< External interrupt event 4 Mask */ 01298 01299 #define WFE_CR3_DMA1CH23_EV ((uint8_t)0x80) /*!< DMA1 channel 2 and 3 interrupt event Mask */ 01300 #define WFE_CR3_DMA1CH01_EV ((uint8_t)0x40) /*!< DMA1 channel 0 and 1 interrupt event Mask */ 01301 #define WFE_CR3_USART1_EV ((uint8_t)0x20) /*!< USART1 Rx and Tx interrupt event Mask */ 01302 #define WFE_CR3_I2C1_EV ((uint8_t)0x10) /*!< I2C1 Rx and Tx interrupt event Mask */ 01303 #define WFE_CR3_SPI1_EV ((uint8_t)0x08) /*!< SPI1 Rx and Tx interrupt event Mask */ 01304 #define WFE_CR3_TIM4_EV ((uint8_t)0x04) /*!< TIM4 event Mask */ 01305 #define WFE_CR3_TIM3_EV1 ((uint8_t)0x02) /*!< TIM3 event 1 Mask */ 01306 #define WFE_CR3_TIM3_EV0 ((uint8_t)0x01) /*!< TIM3 event 0 Mask */ 01307 01308 #define WFE_CR4_AES_EV ((uint8_t)0x40) /*!< AES event Mask */ 01309 #define WFE_CR4_TIM5_EV1 ((uint8_t)0x20) /*!< TIM5 event 1 Mask */ 01310 #define WFE_CR4_TIM5_EV0 ((uint8_t)0x10) /*!< TIM5 event 0 Mask */ 01311 #define WFE_CR4_USART3_EV ((uint8_t)0x08) /*!< USART3 Rx and Tx interrupt event Mask */ 01312 #define WFE_CR4_USART2_EV ((uint8_t)0x04) /*!< USART2 Rx and Tx interrupt event Mask */ 01313 #define WFE_CR4_SPI2_EV ((uint8_t)0x02) /*!< SPI2 Rx and Tx interrupt event Mask */ 01314 #define WFE_CR4_RTC_CSS_EV ((uint8_t)0x01) /*!< RTC or CSS on LSE interrupt event Mask */ 01315 01316 01317 /** 01318 * @} 01319 */ 01320 01321 /*----------------------------------------------------------------------------*/ 01322 /** 01323 * @brief Option Bytes (OPT) 01324 */ 01325 typedef struct OPT_struct 01326 { 01327 __IO uint8_t ROP; /*!< Read-out protection*/ 01328 uint8_t RESERVED1; 01329 __IO uint8_t UBC; /*!< User Boot code size*/ 01330 uint8_t RESERVED2; 01331 uint8_t RESERVED3; 01332 uint8_t RESERVED4; 01333 uint8_t RESERVED5; 01334 __IO uint8_t PCODESIZE; 01335 __IO uint8_t WDG; /*!< Independent and Window watchdog option */ 01336 __IO uint8_t XTSTARTUP; /*!< HSE and LSE option */ 01337 __IO uint8_t BOR; /*!< Brownout option */ 01338 } 01339 OPT_TypeDef; 01340 01341 /** 01342 * @} 01343 */ 01344 /*----------------------------------------------------------------------------*/ 01345 01346 /** 01347 * @brief Reset Controller (RST) 01348 */ 01349 typedef struct RST_struct 01350 { 01351 __IO uint8_t CR; /*!< Multiplex Reset Pad */ 01352 __IO uint8_t SR; /*!< Reset status register */ 01353 01354 } 01355 RST_TypeDef; 01356 /** 01357 * @} 01358 */ 01359 01360 /** @addtogroup RST_Registers_Reset_Value 01361 * @{ 01362 */ 01363 01364 #define RST_CR_RESET_VALUE ((uint8_t)0x00) /*!< Reset pin configuration register 1 reset value */ 01365 #define RST_SR_RESET_VALUE ((uint8_t)0x01) /*!< Reset status register 2 reset value */ 01366 01367 /** 01368 * @} 01369 */ 01370 01371 /** @addtogroup RST_Registers_Bits_Definition 01372 * @{ 01373 */ 01374 #define RST_SR_BORF ((uint8_t)0x20) /*!< Brownout reset flag mask */ 01375 #define RST_SR_WWDGF ((uint8_t)0x10) /*!< Window Watchdog reset flag mask */ 01376 #define RST_SR_SWIMF ((uint8_t)0x08) /*!< SWIM reset flag mask */ 01377 #define RST_SR_ILLOPF ((uint8_t)0x04) /*!< Illegal opcode reset flag mask */ 01378 #define RST_SR_IWDGF ((uint8_t)0x02) /*!< Independent Watchdog reset flag mask */ 01379 #define RST_SR_PORF ((uint8_t)0x01) /*!< Power On Reset (POR) flag mask */ 01380 01381 /** 01382 * @} 01383 */ 01384 /*----------------------------------------------------------------------------*/ 01385 01386 /** 01387 * @brief Power Control (PWR) 01388 */ 01389 typedef struct PWR_struct 01390 { 01391 __IO uint8_t CSR1; /*!< PWR control status register 1 */ 01392 __IO uint8_t CSR2; /*!< PWR control status register 2 */ 01393 01394 } 01395 PWR_TypeDef; 01396 /** 01397 * @} 01398 */ 01399 01400 /** @addtogroup PWR_Registers_Reset_Value 01401 * @{ 01402 */ 01403 01404 #define PWR_CSR1_RESET_VALUE ((uint8_t)0x00) /*!< Control Status Register 1 reset value */ 01405 #define PWR_CSR2_RESET_VALUE ((uint8_t)0x00) /*!< Control Status Register 2 reset value */ 01406 01407 /** 01408 * @} 01409 */ 01410 01411 /** @addtogroup PWR_Registers_Bits_Definition 01412 * @{ 01413 */ 01414 #define PWR_CSR1_PVDOF ((uint8_t)0x40) /*!< PVD output flag mask */ 01415 #define PWR_CSR1_PVDIF ((uint8_t)0x20) /*!< PVD interrupt flag mask */ 01416 #define PWR_CSR1_PVDIEN ((uint8_t)0x10) /*!< PVD interrupt enable mask */ 01417 #define PWR_CSR1_PLS ((uint8_t)0x0E) /*!< PVD Level thresholds selector mask */ 01418 #define PWR_CSR1_PVDE ((uint8_t)0x01) /*!< Power Voltage Detector (PVD) enable mask */ 01419 01420 01421 #define PWR_CSR2_FWU ((uint8_t)0x04) /*!< Fast wake up configuration mask */ 01422 #define PWR_CSR2_ULP ((uint8_t)0x02) /*!< Ultra Low power configuration mask */ 01423 #define PWR_CR2_VREFINTF ((uint8_t)0x01) /*!< Internal reference voltage status flag mask */ 01424 /** 01425 * @} 01426 */ 01427 /*----------------------------------------------------------------------------*/ 01428 01429 /** 01430 * @brief Routing Interface (RI) 01431 */ 01432 typedef struct RI_struct 01433 { 01434 uint8_t RESERVED; 01435 __IO uint8_t ICR1; /*!< Timer input capture routing register 1 */ 01436 __IO uint8_t ICR2; /*!< Timer input capture routing register 2 */ 01437 __IO uint8_t IOIR1; /*!< I/O input register 1 */ 01438 __IO uint8_t IOIR2; /*!< I/O input register 2 */ 01439 __IO uint8_t IOIR3; /*!< I/O input register 3 */ 01440 __IO uint8_t IOCMR1; /*!< I/O control mode register 1 */ 01441 __IO uint8_t IOCMR2; /*!< I/O control mode register 2 */ 01442 __IO uint8_t IOCMR3; /*!< I/O control mode register 3 */ 01443 __IO uint8_t IOSR1; /*!< I/O switch register 1*/ 01444 __IO uint8_t IOSR2; /*!< I/O switch register 2*/ 01445 __IO uint8_t IOSR3; /*!< I/O switch register 3*/ 01446 __IO uint8_t IOGCR; /*!< I/O group control register */ 01447 __IO uint8_t ASCR1; /*!< Analog Switch Control register 1 */ 01448 __IO uint8_t ASCR2; /*!< Analog Switch Control register 2 */ 01449 __IO uint8_t RCR; /*!< Resistor control register */ 01450 uint8_t RESERVED1[16]; 01451 __IO uint8_t CR; /*!< Control Register */ 01452 __IO uint8_t IOMR1; /*!< IO Mask Register 1 */ 01453 __IO uint8_t IOMR2; /*!< IO Mask Register 2 */ 01454 __IO uint8_t IOMR3; /*!< IO Mask Register 3 */ 01455 __IO uint8_t IOMR4; /*!< IO Mask Register 4*/ 01456 __IO uint8_t IOIR4; /*!< I/O input register 4 */ 01457 __IO uint8_t IOCMR4; /*!< I/O control mode register 4 */ 01458 __IO uint8_t IOSR4; /*!< I/O switch register 4 */ 01459 }RI_TypeDef; 01460 /** 01461 * @} 01462 */ 01463 01464 /** @addtogroup RI_Registers_Reset_Value 01465 * @{ 01466 */ 01467 01468 #define RI_ICR1_RESET_VALUE ((uint8_t)0x00) /*!< Timer input capture routing register 1 reset value */ 01469 #define RI_ICR2_RESET_VALUE ((uint8_t)0x00) /*!< Timer input capture routing register 2 reset value */ 01470 01471 #define RI_IOCMR1_RESET_VALUE ((uint8_t)0x00) /*!< I/O control mode register 1 reset value */ 01472 #define RI_IOCMR2_RESET_VALUE ((uint8_t)0x00) /*!< I/O control mode register 2 reset value */ 01473 #define RI_IOCMR3_RESET_VALUE ((uint8_t)0x00) /*!< I/O control mode register 3 reset value */ 01474 01475 #define RI_IOSR1_RESET_VALUE ((uint8_t)0x00) /*!< I/O switch register 1 reset value */ 01476 #define RI_IOSR2_RESET_VALUE ((uint8_t)0x00) /*!< I/O switch register 2 reset value */ 01477 #define RI_IOSR3_RESET_VALUE ((uint8_t)0x00) /*!< I/O switch register 3 reset value */ 01478 01479 #define RI_IOGCR_RESET_VALUE ((uint8_t)0xFF) /*!< IO group control register reset value */ 01480 01481 #define RI_ASCR1_RESET_VALUE ((uint8_t)0x00) /*!< Analog switch register 1 reset value */ 01482 #define RI_ASCR2_RESET_VALUE ((uint8_t)0x00) /*!< Analog switch register 2 reset value */ 01483 #define RI_RCR_RESET_VALUE ((uint8_t)0x00) /*!< Resistor control register reset value */ 01484 01485 #define RI_IOCMR4_RESET_VALUE ((uint8_t)0x00) /*!< I/O control mode register 4 reset value */ 01486 #define RI_IOSR4_RESET_VALUE ((uint8_t)0x00) /*!< I/O switch register 4 reset value */ 01487 01488 /** 01489 * @} 01490 */ 01491 01492 /** @addtogroup RI_Registers_Bits_Definition 01493 * @{ 01494 */ 01495 #define RI_ICR1_IC2CS ((uint8_t)0x1F) /*!< TIM1 Input Capture 2 I/O selection mask */ 01496 01497 #define RI_ICR2_IC3CS ((uint8_t)0x1F) /*!< TIM1 Input Capture 3 I/O selection mask */ 01498 01499 #define RI_IOIR1_CH1I ((uint8_t)0x01) /*!< Channel 1 I/O pin input value */ 01500 #define RI_IOIR1_CH4I ((uint8_t)0x02) /*!< Channel 4 I/O pin input value */ 01501 #define RI_IOIR1_CH7I ((uint8_t)0x04) /*!< Channel 7 I/O pin input value */ 01502 #define RI_IOIR1_CH10I ((uint8_t)0x08) /*!< Channel 10 I/O pin input value */ 01503 #define RI_IOIR1_CH13I ((uint8_t)0x10) /*!< Channel 13 I/O pin input value */ 01504 #define RI_IOIR1_CH16I ((uint8_t)0x20) /*!< Channel 16 I/O pin input value */ 01505 #define RI_IOIR1_CH19I ((uint8_t)0x40) /*!< Channel 19 I/O pin input value */ 01506 #define RI_IOIR1_CH22I ((uint8_t)0x80) /*!< Channel 22 I/O pin input value */ 01507 01508 #define RI_IOIR2_CH2I ((uint8_t)0x01) /*!< Channel 2 I/O pin input value */ 01509 #define RI_IOIR2_CH5I ((uint8_t)0x02) /*!< Channel 5 I/O pin input value */ 01510 #define RI_IOIR2_CH8I ((uint8_t)0x04) /*!< Channel 8 I/O pin input value */ 01511 #define RI_IOIR2_CH11I ((uint8_t)0x08) /*!< Channel 11 I/O pin input value */ 01512 #define RI_IOIR2_CH14I ((uint8_t)0x10) /*!< Channel 14 I/O pin input value */ 01513 #define RI_IOIR2_CH17I ((uint8_t)0x20) /*!< Channel 17 I/O pin input value */ 01514 #define RI_IOIR2_CH20I ((uint8_t)0x40) /*!< Channel 20 I/O pin input value */ 01515 #define RI_IOIR2_CH23I ((uint8_t)0x80) /*!< Channel 23 I/O pin input value */ 01516 01517 #define RI_IOIR3_CH3I ((uint8_t)0x01) /*!< Channel 3 I/O pin input value */ 01518 #define RI_IOIR3_CH6I ((uint8_t)0x02) /*!< Channel 6 I/O pin input value */ 01519 #define RI_IOIR3_CH9I ((uint8_t)0x04) /*!< Channel 9 I/O pin input value */ 01520 #define RI_IOIR3_CH12I ((uint8_t)0x08) /*!< Channel 12 I/O pin input value */ 01521 #define RI_IOIR3_CH15I ((uint8_t)0x10) /*!< Channel 15 I/O pin input value */ 01522 #define RI_IOIR3_CH18I ((uint8_t)0x20) /*!< Channel 18 I/O pin input value */ 01523 #define RI_IOIR3_CH21I ((uint8_t)0x40) /*!< Channel 21 I/O pin input value */ 01524 #define RI_IOIR3_CH24I ((uint8_t)0x80) /*!< Channel 24 I/O pin input value */ 01525 01526 #define RI_IOCMR1_CH1M ((uint8_t)0x01) /*!< Channel 1 I/O control mode */ 01527 #define RI_IOCMR1_CH4M ((uint8_t)0x02) /*!< Channel 4 I/O control mode */ 01528 #define RI_IOCMR1_CH7M ((uint8_t)0x04) /*!< Channel 7 I/O control mode */ 01529 #define RI_IOCMR1_CH10M ((uint8_t)0x08) /*!< Channel 10 I/O control mode */ 01530 #define RI_IOCMR1_CH13M ((uint8_t)0x10) /*!< Channel 13 I/O control mode */ 01531 #define RI_IOCMR1_CH16M ((uint8_t)0x20) /*!< Channel 16 I/O control mode */ 01532 #define RI_IOCMR1_CH19M ((uint8_t)0x40) /*!< Channel 19 I/O control mode */ 01533 #define RI_IOCMR1_CH22M ((uint8_t)0x80) /*!< Channel 22 I/O control mode */ 01534 01535 #define RI_IOCMR2_CH2M ((uint8_t)0x01) /*!< Channel 2 I/O control mode */ 01536 #define RI_IOCMR2_CH5M ((uint8_t)0x02) /*!< Channel 5 I/O control mode */ 01537 #define RI_IOCMR2_CH8M ((uint8_t)0x04) /*!< Channel 8 I/O control mode */ 01538 #define RI_IOCMR2_CH11M ((uint8_t)0x08) /*!< Channel 11 I/O control mode */ 01539 #define RI_IOCMR2_CH14M ((uint8_t)0x10) /*!< Channel 14 I/O control mode */ 01540 #define RI_IOCMR2_CH17M ((uint8_t)0x20) /*!< Channel 17 I/O control mode */ 01541 #define RI_IOCMR2_CH20M ((uint8_t)0x40) /*!< Channel 20 I/O control mode */ 01542 #define RI_IOCMR2_CH23M ((uint8_t)0x80) /*!< Channel 23 I/O control mode */ 01543 01544 #define RI_IOCMR3_CH3M ((uint8_t)0x01) /*!< Channel 3 I/O control mode */ 01545 #define RI_IOCMR3_CH6M ((uint8_t)0x02) /*!< Channel 6 I/O control mode */ 01546 #define RI_IOCMR3_CH9M ((uint8_t)0x04) /*!< Channel 9 I/O control mode */ 01547 #define RI_IOCMR3_CH12M ((uint8_t)0x08) /*!< Channel 12 I/O control mode */ 01548 #define RI_IOCMR3_CH15M ((uint8_t)0x10) /*!< Channel 15 I/O control mode */ 01549 #define RI_IOCMR3_CH18M ((uint8_t)0x20) /*!< Channel 18 I/O control mode */ 01550 #define RI_IOCMR3_CH21M ((uint8_t)0x40) /*!< Channel 21 I/O control mode */ 01551 #define RI_IOCMR3_CH24M ((uint8_t)0x80) /*!< Channel 24 I/O control mode */ 01552 01553 #define RI_IOSR1_CH1E ((uint8_t)0x01) /*!< Channel 1 I/O switch control */ 01554 #define RI_IOSR1_CH4E ((uint8_t)0x02) /*!< Channel 4 I/O switch control */ 01555 #define RI_IOSR1_CH7E ((uint8_t)0x04) /*!< Channel 7 I/O switch control */ 01556 #define RI_IOSR1_CH10E ((uint8_t)0x08) /*!< Channel 10 I/O switch control */ 01557 #define RI_IOSR1_CH13E ((uint8_t)0x10) /*!< Channel 13 I/O switch control */ 01558 #define RI_IOSR1_CH16E ((uint8_t)0x20) /*!< Channel 16 I/O switch control */ 01559 #define RI_IOSR1_CH19E ((uint8_t)0x40) /*!< Channel 19 I/O switch control */ 01560 #define RI_IOSR1_CH22E ((uint8_t)0x80) /*!< Channel 22 I/O switch control */ 01561 01562 #define RI_IOSR2_CH2E ((uint8_t)0x01) /*!< Channel 2 I/O switch control */ 01563 #define RI_IOSR2_CH5E ((uint8_t)0x02) /*!< Channel 5 I/O switch control */ 01564 #define RI_IOSR2_CH8E ((uint8_t)0x04) /*!< Channel 8 I/O switch control */ 01565 #define RI_IOSR2_CH11E ((uint8_t)0x08) /*!< Channel 11 I/O switch control */ 01566 #define RI_IOSR2_CH14E ((uint8_t)0x10) /*!< Channel 14 I/O switch control */ 01567 #define RI_IOSR2_CH17E ((uint8_t)0x20) /*!< Channel 17 I/O switch control */ 01568 #define RI_IOSR2_CH20E ((uint8_t)0x40) /*!< Channel 20 I/O switch control */ 01569 #define RI_IOSR2_CH23E ((uint8_t)0x80) /*!< Channel 23 I/O switch control */ 01570 01571 #define RI_IOSR3_CH3E ((uint8_t)0x01) /*!< Channel 3 I/O switch control */ 01572 #define RI_IOSR3_CH6E ((uint8_t)0x02) /*!< Channel 6 I/O switch control */ 01573 #define RI_IOSR3_CH9E ((uint8_t)0x04) /*!< Channel 9 I/O switch control */ 01574 #define RI_IOSR3_CH12E ((uint8_t)0x08) /*!< Channel 12 I/O switch control */ 01575 #define RI_IOSR3_CH15E ((uint8_t)0x10) /*!< Channel 15 I/O switch control */ 01576 #define RI_IOSR3_CH18E ((uint8_t)0x20) /*!< Channel 18 I/O switch control */ 01577 #define RI_IOSR3_CH21E ((uint8_t)0x40) /*!< Channel 21 I/O switch control */ 01578 #define RI_IOSR3_CH24E ((uint8_t)0x80) /*!< Channel 24 I/O switch control */ 01579 01580 #define RI_IOGCR_IOM1 ((uint8_t)0x03) /*!< I/O mode 1 */ 01581 #define RI_IOGCR_IOM2 ((uint8_t)0x0C) /*!< I/O mode 2 */ 01582 #define RI_IOGCR_IOM3 ((uint8_t)0x30) /*!< I/O mode 3 */ 01583 #define RI_IOGCR_IOM4 ((uint8_t)0xC0) /*!< I/O mode 4 */ 01584 01585 #define RI_ASCR1_AS0 ((uint8_t)0x01) /*!< Analog switch AS0 control */ 01586 #define RI_ASCR1_AS1 ((uint8_t)0x02) /*!< Analog switch AS1 control */ 01587 #define RI_ASCR1_AS2 ((uint8_t)0x04) /*!< Analog switch AS2 control */ 01588 #define RI_ASCR1_AS3 ((uint8_t)0x08) /*!< Analog switch AS3 control */ 01589 #define RI_ASCR1_AS4 ((uint8_t)0x10) /*!< Analog switch AS4 control */ 01590 #define RI_ASCR1_AS5 ((uint8_t)0x20) /*!< Analog switch AS5 control */ 01591 #define RI_ASCR1_AS6 ((uint8_t)0x40) /*!< Analog switch AS6 control */ 01592 #define RI_ASCR1_AS7 ((uint8_t)0x80) /*!< Analog switch AS7 control */ 01593 01594 #define RI_ASCR2_AS8 ((uint8_t)0x01) /*!< Analog switch AS8 control */ 01595 #define RI_ASCR2_AS9 ((uint8_t)0x02) /*!< Analog switch AS9 control */ 01596 #define RI_ASCR2_AS10 ((uint8_t)0x04) /*!< Analog switch AS10 control */ 01597 #define RI_ASCR2_AS11 ((uint8_t)0x08) /*!< Analog switch AS11 control */ 01598 #define RI_ASCR2_AS14 ((uint8_t)0x40) /*!< Analog switch AS14 control */ 01599 01600 #define RI_RCR_400KPD ((uint8_t)0x08) /*!< 400K pull-down resistor Mask. */ 01601 #define RI_RCR_10KPD ((uint8_t)0x04) /*!< 10K pull-down resistor Mask. */ 01602 #define RI_RCR_400KPU ((uint8_t)0x02) /*!< 400K pull-up resistor Mask. */ 01603 #define RI_RCR_10KPU ((uint8_t)0x01) /*!< 10K pull-up resistor Mask. */ 01604 01605 #define RI_IOSR4_CH29E ((uint8_t)0x01) /*!< Channel 29 I/O switch control */ 01606 #define RI_IOSR4_CH26E ((uint8_t)0x02) /*!< Channel 26 I/O switch control */ 01607 #define RI_IOSR4_CH27E ((uint8_t)0x40) /*!< Channel 27 I/O switch control */ 01608 #define RI_IOSR4_CH28E ((uint8_t)0x80) /*!< Channel 28 I/O switch control */ 01609 01610 /** 01611 * @} 01612 */ 01613 /*----------------------------------------------------------------------------ok*/ 01614 01615 /** 01616 * @brief Serial Peripheral Interface (SPI) 01617 */ 01618 typedef struct SPI_struct 01619 { 01620 __IO uint8_t CR1; /*!< SPI control register 1 */ 01621 __IO uint8_t CR2; /*!< SPI control register 2 */ 01622 __IO uint8_t CR3; /*!< SPI DMA and interrupt control register */ 01623 __IO uint8_t SR; /*!< SPI status register */ 01624 __IO uint8_t DR; /*!< SPI data I/O register */ 01625 __IO uint8_t CRCPR; /*!< SPI CRC polynomial register */ 01626 __IO uint8_t RXCRCR; /*!< SPI Rx CRC register */ 01627 __IO uint8_t TXCRCR; /*!< SPI Tx CRC register */ 01628 } 01629 SPI_TypeDef; 01630 01631 /** @addtogroup SPI_Registers_Reset_Value 01632 * @{ 01633 */ 01634 01635 #define SPI_CR1_RESET_VALUE ((uint8_t)0x00) /*!< Control Register 1 reset value */ 01636 #define SPI_CR2_RESET_VALUE ((uint8_t)0x00) /*!< Control Register 2 reset value */ 01637 #define SPI_CR3_RESET_VALUE ((uint8_t)0x00) /*!< DMA and Interrupt Control Register reset value */ 01638 #define SPI_SR_RESET_VALUE ((uint8_t)0x02) /*!< Status Register reset value */ 01639 #define SPI_DR_RESET_VALUE ((uint8_t)0x00) /*!< Data Register reset value */ 01640 #define SPI_CRCPR_RESET_VALUE ((uint8_t)0x07) /*!< Polynomial Register reset value */ 01641 #define SPI_RXCRCR_RESET_VALUE ((uint8_t)0x00) /*!< RX CRC Register reset value */ 01642 #define SPI_TXCRCR_RESET_VALUE ((uint8_t)0x00) /*!< TX CRC Register reset value */ 01643 01644 /** 01645 * @} 01646 */ 01647 01648 /** @addtogroup SPI_Registers_Bits_Definition 01649 * @{ 01650 */ 01651 01652 #define SPI_CR1_LSBFIRST ((uint8_t)0x80) /*!< Frame format mask */ 01653 #define SPI_CR1_SPE ((uint8_t)0x40) /*!< Enable bits mask */ 01654 #define SPI_CR1_BR ((uint8_t)0x38) /*!< Baud rate control mask */ 01655 #define SPI_CR1_MSTR ((uint8_t)0x04) /*!< Master Selection mask */ 01656 #define SPI_CR1_CPOL ((uint8_t)0x02) /*!< Clock Polarity mask */ 01657 #define SPI_CR1_CPHA ((uint8_t)0x01) /*!< Clock Phase mask */ 01658 01659 #define SPI_CR2_BDM ((uint8_t)0x80) /*!< Bi-directional data mode enable mask */ 01660 #define SPI_CR2_BDOE ((uint8_t)0x40) /*!< Output enable in bi-directional mode mask */ 01661 #define SPI_CR2_CRCEN ((uint8_t)0x20) /*!< Hardware CRC calculation enable mask */ 01662 #define SPI_CR2_CRCNEXT ((uint8_t)0x10) /*!< Transmit CRC next mask */ 01663 #define SPI_CR2_RXONLY ((uint8_t)0x04) /*!< Receive only mask */ 01664 #define SPI_CR2_SSM ((uint8_t)0x02) /*!< Software slave management mask */ 01665 #define SPI_CR2_SSI ((uint8_t)0x01) /*!< Internal slave select mask */ 01666 01667 #define SPI_CR3_TXIE ((uint8_t)0x80) /*!< Tx buffer empty interrupt enable mask */ 01668 #define SPI_CR3_RXIE ((uint8_t)0x40) /*!< Rx buffer empty interrupt enable mask */ 01669 #define SPI_CR3_ERRIE ((uint8_t)0x20) /*!< Error interrupt enable mask */ 01670 #define SPI_CR3_WKIE ((uint8_t)0x10) /*!< Wake-up interrupt enable mask */ 01671 #define SPI_CR3_TXDMAEN ((uint8_t)0x02) /*!< Tx Buffer DMA enable mask */ 01672 #define SPI_CR3_RXDMAEN ((uint8_t)0x01) /*!< Rx Buffer DMA enable mask */ 01673 01674 #define SPI_SR_BSY ((uint8_t)0x80) /*!< Busy flag */ 01675 #define SPI_SR_OVR ((uint8_t)0x40) /*!< Overrun flag */ 01676 #define SPI_SR_MODF ((uint8_t)0x20) /*!< Mode fault */ 01677 #define SPI_SR_CRCERR ((uint8_t)0x10) /*!< CRC error flag */ 01678 #define SPI_SR_WKUP ((uint8_t)0x08) /*!< Wake-Up flag */ 01679 #define SPI_SR_TXE ((uint8_t)0x02) /*!< Transmit buffer empty */ 01680 #define SPI_SR_RXNE ((uint8_t)0x01) /*!< Receive buffer not empty */ 01681 /** 01682 * @} 01683 */ 01684 01685 /*----------------------------------------------------------------------------ok*/ 01686 01687 /** 01688 * @brief Advanced 16 bit timer with complementary PWM outputs (TIM1) 01689 */ 01690 typedef struct TIM1_struct 01691 { 01692 __IO uint8_t CR1; /*!< control register 1 */ 01693 __IO uint8_t CR2; /*!< control register 2 */ 01694 __IO uint8_t SMCR; /*!< Synchro mode control register */ 01695 __IO uint8_t ETR; /*!< external trigger register */ 01696 __IO uint8_t DER; /*!< DMA requests enable register */ 01697 __IO uint8_t IER; /*!< interrupt enable register*/ 01698 __IO uint8_t SR1; /*!< status register 1 */ 01699 __IO uint8_t SR2; /*!< status register 2 */ 01700 __IO uint8_t EGR; /*!< event generation register */ 01701 __IO uint8_t CCMR1; /*!< CC mode register 1 */ 01702 __IO uint8_t CCMR2; /*!< CC mode register 2 */ 01703 __IO uint8_t CCMR3; /*!< CC mode register 3 */ 01704 __IO uint8_t CCMR4; /*!< CC mode register 4 */ 01705 __IO uint8_t CCER1; /*!< CC enable register 1 */ 01706 __IO uint8_t CCER2; /*!< CC enable register 2 */ 01707 __IO uint8_t CNTRH; /*!< counter high */ 01708 __IO uint8_t CNTRL; /*!< counter low */ 01709 __IO uint8_t PSCRH; /*!< prescaler high */ 01710 __IO uint8_t PSCRL; /*!< prescaler low */ 01711 __IO uint8_t ARRH; /*!< auto-reload register high */ 01712 __IO uint8_t ARRL; /*!< auto-reload register low */ 01713 __IO uint8_t RCR; /*!< Repetition Counter register */ 01714 __IO uint8_t CCR1H; /*!< capture/compare register 1 high */ 01715 __IO uint8_t CCR1L; /*!< capture/compare register 1 low */ 01716 __IO uint8_t CCR2H; /*!< capture/compare register 2 high */ 01717 __IO uint8_t CCR2L; /*!< capture/compare register 2 low */ 01718 __IO uint8_t CCR3H; /*!< capture/compare register 3 high */ 01719 __IO uint8_t CCR3L; /*!< capture/compare register 3 low */ 01720 __IO uint8_t CCR4H; /*!< capture/compare register 3 high */ 01721 __IO uint8_t CCR4L; /*!< capture/compare register 3 low */ 01722 __IO uint8_t BKR; /*!< Break Register */ 01723 __IO uint8_t DTR; /*!< dead-time register */ 01724 __IO uint8_t OISR; /*!< Output idle register */ 01725 __IO uint8_t DCR1; /*!< DMA control register 1 */ 01726 __IO uint8_t DCR2; /*!< DMA control register 2 */ 01727 __IO uint8_t DMAR; /*!< DMA Address for brust mode */ 01728 } 01729 TIM1_TypeDef; 01730 01731 /** @addtogroup TIM1_Registers_Reset_Value 01732 * @{ 01733 */ 01734 #define TIM1_CR1_RESET_VALUE ((uint8_t)0x00) 01735 #define TIM1_CR2_RESET_VALUE ((uint8_t)0x00) 01736 #define TIM1_SMCR_RESET_VALUE ((uint8_t)0x00) 01737 #define TIM1_ETR_RESET_VALUE ((uint8_t)0x00) 01738 #define TIM1_DER_RESET_VALUE ((uint8_t)0x00) 01739 #define TIM1_IER_RESET_VALUE ((uint8_t)0x00) 01740 #define TIM1_SR1_RESET_VALUE ((uint8_t)0x00) 01741 #define TIM1_SR2_RESET_VALUE ((uint8_t)0x00) 01742 #define TIM1_EGR_RESET_VALUE ((uint8_t)0x00) 01743 #define TIM1_CCMR1_RESET_VALUE ((uint8_t)0x00) 01744 #define TIM1_CCMR2_RESET_VALUE ((uint8_t)0x00) 01745 #define TIM1_CCMR3_RESET_VALUE ((uint8_t)0x00) 01746 #define TIM1_CCMR4_RESET_VALUE ((uint8_t)0x00) 01747 #define TIM1_CCER1_RESET_VALUE ((uint8_t)0x00) 01748 #define TIM1_CCER2_RESET_VALUE ((uint8_t)0x00) 01749 #define TIM1_CNTRH_RESET_VALUE ((uint8_t)0x00) 01750 #define TIM1_CNTRL_RESET_VALUE ((uint8_t)0x00) 01751 #define TIM1_PSCRH_RESET_VALUE ((uint8_t)0x00) 01752 #define TIM1_PSCRL_RESET_VALUE ((uint8_t)0x00) 01753 #define TIM1_ARRH_RESET_VALUE ((uint8_t)0xFF) 01754 #define TIM1_ARRL_RESET_VALUE ((uint8_t)0xFF) 01755 #define TIM1_RCR_RESET_VALUE ((uint8_t)0x00) 01756 #define TIM1_CCR1H_RESET_VALUE ((uint8_t)0x00) 01757 #define TIM1_CCR1L_RESET_VALUE ((uint8_t)0x00) 01758 #define TIM1_CCR2H_RESET_VALUE ((uint8_t)0x00) 01759 #define TIM1_CCR2L_RESET_VALUE ((uint8_t)0x00) 01760 #define TIM1_CCR3H_RESET_VALUE ((uint8_t)0x00) 01761 #define TIM1_CCR3L_RESET_VALUE ((uint8_t)0x00) 01762 #define TIM1_CCR4H_RESET_VALUE ((uint8_t)0x00) 01763 #define TIM1_CCR4L_RESET_VALUE ((uint8_t)0x00) 01764 #define TIM1_BKR_RESET_VALUE ((uint8_t)0x00) 01765 #define TIM1_DTR_RESET_VALUE ((uint8_t)0x00) 01766 #define TIM1_OISR_RESET_VALUE ((uint8_t)0x00) 01767 #define TIM1_DCR1_RESET_VALUE ((uint8_t)0x00) 01768 #define TIM1_DCR2_RESET_VALUE ((uint8_t)0x00) 01769 #define TIM1_DMAR_RESET_VALUE ((uint8_t)0x00) 01770 01771 /** 01772 * @} 01773 */ 01774 01775 /** @addtogroup TIM1_Registers_Bits_Definition 01776 * @{ 01777 */ 01778 /* CR1*/ 01779 #define TIM1_CR1_ARPE ((uint8_t)0x80) /*!< Auto-Reload Preload Enable mask. */ 01780 #define TIM1_CR1_CMS ((uint8_t)0x60) /*!< Center-aligned Mode Selection mask. */ 01781 #define TIM1_CR1_DIR ((uint8_t)0x10) /*!< Direction mask. */ 01782 #define TIM1_CR1_OPM ((uint8_t)0x08) /*!< One Pulse Mode mask. */ 01783 #define TIM1_CR1_URS ((uint8_t)0x04) /*!< Update Request Source mask. */ 01784 #define TIM1_CR1_UDIS ((uint8_t)0x02) /*!< Update DIsable mask. */ 01785 #define TIM1_CR1_CEN ((uint8_t)0x01) /*!< Counter Enable mask. */ 01786 /* CR2*/ 01787 #define TIM1_CR2_TI1S ((uint8_t)0x80) /*!< TI1 selection */ 01788 #define TIM1_CR2_MMS ((uint8_t)0x70) /*!< MMS Selection mask. */ 01789 #define TIM1_CR2_CCDS ((uint8_t)0x08) /*!< Capture/Compare DMA Selection */ 01790 #define TIM1_CR2_CCUS ((uint8_t)0x04) /*!< Capture/Compare Control Update Selection mask. */ 01791 #define TIM1_CR2_CCPC ((uint8_t)0x01) /*!< Capture/Compare Preloaded Control mask. */ 01792 /* SMCR*/ 01793 #define TIM1_SMCR_MSM ((uint8_t)0x80) /*!< Master/Slave Mode mask. */ 01794 #define TIM1_SMCR_TS ((uint8_t)0x70) /*!< Trigger Selection mask. */ 01795 #define TIM1_SMCR_OCCS ((uint8_t)0x08) /*!< OCREFCLR Selection mask. */ 01796 #define TIM1_SMCR_SMS ((uint8_t)0x07) /*!< Slave Mode Selection mask. */ 01797 /* ETR*/ 01798 #define TIM1_ETR_ETP ((uint8_t)0x80) /*!< External Trigger Polarity mask. */ 01799 #define TIM1_ETR_ECE ((uint8_t)0x40) /*!< External Clock mask. */ 01800 #define TIM1_ETR_ETPS ((uint8_t)0x30) /*!< External Trigger Prescaler mask. */ 01801 #define TIM1_ETR_ETF ((uint8_t)0x0F) /*!< External Trigger Filter mask. */ 01802 /* DER*/ 01803 #define TIM1_DER_COMDE ((uint8_t)0x20) /*!< Commutation DMA request Enable mask.*/ 01804 #define TIM1_DER_CC4DE ((uint8_t)0x10) /*!< Capture/Compare 4 DMA request Enable mask.*/ 01805 #define TIM1_DER_CC3DE ((uint8_t)0x08) /*!< Capture/Compare 3 DMA request Enable mask.*/ 01806 #define TIM1_DER_CC2DE ((uint8_t)0x04) /*!< Capture/Compare 2 DMA request Enable mask.*/ 01807 #define TIM1_DER_CC1DE ((uint8_t)0x02) /*!< Capture/Compare 1 DMA request Enable mask.*/ 01808 #define TIM1_DER_UDE ((uint8_t)0x01) /*!< Update DMA request Enable mask. */ 01809 /* IER*/ 01810 #define TIM1_IER_BIE ((uint8_t)0x80) /*!< Break Interrupt Enable mask. */ 01811 #define TIM1_IER_TIE ((uint8_t)0x40) /*!< Trigger Interrupt Enable mask. */ 01812 #define TIM1_IER_COMIE ((uint8_t)0x20) /*!< Commutation Interrupt Enable mask.*/ 01813 #define TIM1_IER_CC4IE ((uint8_t)0x10) /*!< Capture/Compare 4 Interrupt Enable mask. */ 01814 #define TIM1_IER_CC3IE ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt Enable mask. */ 01815 #define TIM1_IER_CC2IE ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Enable mask. */ 01816 #define TIM1_IER_CC1IE ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Enable mask. */ 01817 #define TIM1_IER_UIE ((uint8_t)0x01) /*!< Update Interrupt Enable mask. */ 01818 /* SR1*/ 01819 #define TIM1_SR1_BIF ((uint8_t)0x80) /*!< Break Interrupt Flag mask. */ 01820 #define TIM1_SR1_TIF ((uint8_t)0x40) /*!< Trigger Interrupt Flag mask. */ 01821 #define TIM1_SR1_COMIF ((uint8_t)0x20) /*!< Commutation Interrupt Flag mask. */ 01822 #define TIM1_SR1_CC4IF ((uint8_t)0x10) /*!< Capture/Compare 4 Interrupt Flag mask. */ 01823 #define TIM1_SR1_CC3IF ((uint8_t)0x08) /*!< Capture/Compare 3 Interrupt Flag mask. */ 01824 #define TIM1_SR1_CC2IF ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Flag mask. */ 01825 #define TIM1_SR1_CC1IF ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Flag mask. */ 01826 #define TIM1_SR1_UIF ((uint8_t)0x01) /*!< Update Interrupt Flag mask. */ 01827 /* SR2*/ 01828 #define TIM1_SR2_CC4OF ((uint8_t)0x10) /*!< Capture/Compare 4 Overcapture Flag mask. */ 01829 #define TIM1_SR2_CC3OF ((uint8_t)0x08) /*!< Capture/Compare 3 Overcapture Flag mask. */ 01830 #define TIM1_SR2_CC2OF ((uint8_t)0x04) /*!< Capture/Compare 2 Overcapture Flag mask. */ 01831 #define TIM1_SR2_CC1OF ((uint8_t)0x02) /*!< Capture/Compare 1 Overcapture Flag mask. */ 01832 /*EGR*/ 01833 #define TIM1_EGR_BG ((uint8_t)0x80) /*!< Break Generation mask. */ 01834 #define TIM1_EGR_TG ((uint8_t)0x40) /*!< Trigger Generation mask. */ 01835 #define TIM1_EGR_COMG ((uint8_t)0x20) /*!< Capture/Compare Control Update Generation mask. */ 01836 #define TIM1_EGR_CC4G ((uint8_t)0x10) /*!< Capture/Compare 4 Generation mask. */ 01837 #define TIM1_EGR_CC3G ((uint8_t)0x08) /*!< Capture/Compare 3 Generation mask. */ 01838 #define TIM1_EGR_CC2G ((uint8_t)0x04) /*!< Capture/Compare 2 Generation mask. */ 01839 #define TIM1_EGR_CC1G ((uint8_t)0x02) /*!< Capture/Compare 1 Generation mask. */ 01840 #define TIM1_EGR_UG ((uint8_t)0x01) /*!< Update Generation mask. */ 01841 /*CCMR*/ 01842 #define TIM1_CCMR_ICxPSC ((uint8_t)0x0C) /*!< Input Capture x Prescaler mask. */ 01843 #define TIM1_CCMR_ICxF ((uint8_t)0xF0) /*!< Input Capture x Filter mask. */ 01844 #define TIM1_CCMR_OCM ((uint8_t)0x70) /*!< Output Compare x Mode mask. */ 01845 #define TIM1_CCMR_OCxPE ((uint8_t)0x08) /*!< Output Compare x Preload Enable mask. */ 01846 #define TIM1_CCMR_OCxFE ((uint8_t)0x04) /*!< Output Compare x Fast Enable mask. */ 01847 #define TIM1_CCMR_CCxS ((uint8_t)0x03) /*!< Capture/Compare x Selection mask. */ 01848 #define TIM1_CCMR_OCxCE ((uint8_t)0x80) /*!< Output Compare x Clear Enable mask. */ 01849 01850 #define CCMR_TIxDirect_Set ((uint8_t)0x01) 01851 /*CCER1*/ 01852 #define TIM1_CCER1_CC2NP ((uint8_t)0x80) /*!< Capture/Compare 2 Complementary output Polarity mask. */ 01853 #define TIM1_CCER1_CC2NE ((uint8_t)0x40) /*!< Capture/Compare 2 Complementary output enable mask. */ 01854 #define TIM1_CCER1_CC2P ((uint8_t)0x20) /*!< Capture/Compare 2 output Polarity mask. */ 01855 #define TIM1_CCER1_CC2E ((uint8_t)0x10) /*!< Capture/Compare 2 output enable mask. */ 01856 #define TIM1_CCER1_CC1NP ((uint8_t)0x08) /*!< Capture/Compare 1 Complementary output Polarity mask. */ 01857 #define TIM1_CCER1_CC1NE ((uint8_t)0x04) /*!< Capture/Compare 1 Complementary output enable mask. */ 01858 #define TIM1_CCER1_CC1P ((uint8_t)0x02) /*!< Capture/Compare 1 output Polarity mask. */ 01859 #define TIM1_CCER1_CC1E ((uint8_t)0x01) /*!< Capture/Compare 1 output enable mask. */ 01860 /*CCER2*/ 01861 #define TIM1_CCER2_CC4P ((uint8_t)0x20) /*!< Capture/Compare 4 Polarity mask. */ 01862 #define TIM1_CCER2_CC4E ((uint8_t)0x10) /*!< Capture/Compare 4 Enable mask. */ 01863 #define TIM1_CCER2_CC3NP ((uint8_t)0x08) /*!< Capture/Compare 3 Complementary output Polarity mask. */ 01864 #define TIM1_CCER2_CC3NE ((uint8_t)0x04) /*!< Capture/Compare 3 Complementary output enable mask. */ 01865 #define TIM1_CCER2_CC3P ((uint8_t)0x02) /*!< Capture/Compare 3 output Polarity mask. */ 01866 #define TIM1_CCER2_CC3E ((uint8_t)0x01) /*!< Capture/Compare 3 output enable mask. */ 01867 /*CNTR*/ 01868 #define TIM1_CNTRH_CNT ((uint8_t)0xFF) /*!< Counter Value (MSB) mask. */ 01869 #define TIM1_CNTRL_CNT ((uint8_t)0xFF) /*!< Counter Value (LSB) mask. */ 01870 /*PSCR*/ 01871 #define TIM1_PSCH_PSC ((uint8_t)0xFF) /*!< Prescaler Value (MSB) mask. */ 01872 #define TIM1_PSCL_PSC ((uint8_t)0xFF) /*!< Prescaler Value (LSB) mask. */ 01873 /*ARR*/ 01874 #define TIM1_ARRH_ARR ((uint8_t)0xFF) /*!< Autoreload Value (MSB) mask. */ 01875 #define TIM1_ARRL_ARR ((uint8_t)0xFF) /*!< Autoreload Value (LSB) mask. */ 01876 /*RCR*/ 01877 #define TIM1_RCR_REP ((uint8_t)0xFF) /*!< Repetition Counter Value mask. */ 01878 /*CCR1*/ 01879 #define TIM1_CCR1H_CCR1 ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (MSB) mask. */ 01880 #define TIM1_CCR1L_CCR1 ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (LSB) mask. */ 01881 /*CCR2*/ 01882 #define TIM1_CCR2H_CCR2 ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (MSB) mask. */ 01883 #define TIM1_CCR2L_CCR2 ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (LSB) mask. */ 01884 /*CCR3*/ 01885 #define TIM1_CCR3H_CCR3 ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (MSB) mask. */ 01886 #define TIM1_CCR3L_CCR3 ((uint8_t)0xFF) /*!< Capture/Compare 3 Value (LSB) mask. */ 01887 /*CCR4*/ 01888 #define TIM1_CCR4H_CCR4 ((uint8_t)0xFF) /*!< Capture/Compare 4 Value (MSB) mask. */ 01889 #define TIM1_CCR4L_CCR4 ((uint8_t)0xFF) /*!< Capture/Compare 4 Value (LSB) mask. */ 01890 /*BKR*/ 01891 #define TIM1_BKR_MOE ((uint8_t)0x80) /*!< Main Output Enable mask. */ 01892 #define TIM1_BKR_AOE ((uint8_t)0x40) /*!< Automatic Output Enable mask. */ 01893 #define TIM1_BKR_BKP ((uint8_t)0x20) /*!< Break Polarity mask. */ 01894 #define TIM1_BKR_BKE ((uint8_t)0x10) /*!< Break Enable mask. */ 01895 #define TIM1_BKR_OSSR ((uint8_t)0x08) /*!< Off-State Selection for Run mode mask. */ 01896 #define TIM1_BKR_OSSI ((uint8_t)0x04) /*!< Off-State Selection for Idle mode mask. */ 01897 #define TIM1_BKR_LOCK ((uint8_t)0x03) /*!< Lock Configuration mask. */ 01898 /*DTR*/ 01899 #define TIM1_DTR_DTG ((uint8_t)0xFF) /*!< Dead-Time Generator set-up mask. */ 01900 /*OISR*/ 01901 #define TIM1_OISR_OIS3N ((uint8_t)0x20) /*!< Output Idle state 3 (OC3N output) mask. */ 01902 #define TIM1_OISR_OIS3 ((uint8_t)0x10) /*!< Output Idle state 3 (OC3 output) mask. */ 01903 #define TIM1_OISR_OIS2N ((uint8_t)0x08) /*!< Output Idle state 2 (OC2N output) mask. */ 01904 #define TIM1_OISR_OIS2 ((uint8_t)0x04) /*!< Output Idle state 2 (OC2 output) mask. */ 01905 #define TIM1_OISR_OIS1N ((uint8_t)0x02) /*!< Output Idle state 1 (OC1N output) mask. */ 01906 #define TIM1_OISR_OIS1 ((uint8_t)0x01) /*!< Output Idle state 1 (OC1 output) mask. */ 01907 01908 /*DCR1*/ 01909 #define TIM1_DCR1_DBA ((uint8_t)0x1F) /*!< DMA Base Address mask. */ 01910 01911 /*DCR2*/ 01912 #define TIM1_DCR2_DBL ((uint8_t)0x1F) /*!< DMA Burst Length mask. */ 01913 01914 /*DMAR*/ 01915 #define TIM1_DMAR_VR ((uint8_t)0xFF) /*!< Virtual register mask. */ 01916 01917 01918 /** 01919 * @} 01920 */ 01921 /*----------------------------------------------------------------------------*/ 01922 01923 /** 01924 * @brief 16 bit timer :TIM2, TIM3 & TIM5 01925 */ 01926 typedef struct TIM_struct 01927 { 01928 __IO uint8_t CR1; /*!< control register 1 */ 01929 __IO uint8_t CR2; /*!< control register 2 */ 01930 __IO uint8_t SMCR; /*!< Synchro mode control register */ 01931 __IO uint8_t ETR; /*!< external trigger register */ 01932 __IO uint8_t DER; /*!< DMA requests enable register */ 01933 __IO uint8_t IER; /*!< interrupt enable register*/ 01934 __IO uint8_t SR1; /*!< status register 1 */ 01935 __IO uint8_t SR2; /*!< status register 2 */ 01936 __IO uint8_t EGR; /*!< event generation register */ 01937 __IO uint8_t CCMR1; /*!< CC mode register 1 */ 01938 __IO uint8_t CCMR2; /*!< CC mode register 2 */ 01939 __IO uint8_t CCER1; /*!< CC enable register 1 */ 01940 __IO uint8_t CNTRH; /*!< counterregister high */ 01941 __IO uint8_t CNTRL; /*!< counterregister low */ 01942 __IO uint8_t PSCR; /*!< prescaler register */ 01943 __IO uint8_t ARRH; /*!< auto-reload register high */ 01944 __IO uint8_t ARRL; /*!< auto-reload register low */ 01945 __IO uint8_t CCR1H; /*!< capture/compare register 1 high */ 01946 __IO uint8_t CCR1L; /*!< capture/compare register 1 low */ 01947 __IO uint8_t CCR2H; /*!< capture/compare register 2 high */ 01948 __IO uint8_t CCR2L; /*!< capture/compare register 2 low */ 01949 __IO uint8_t BKR; /*!< Break Register */ 01950 __IO uint8_t OISR; /*!< Output idle register */ 01951 } 01952 TIM_TypeDef; 01953 01954 /** @addtogroup TIM2_TIM3_Registers_Reset_Value 01955 * @{ 01956 */ 01957 #define TIM_CR1_RESET_VALUE ((uint8_t)0x00) 01958 #define TIM_CR2_RESET_VALUE ((uint8_t)0x00) 01959 #define TIM_SMCR_RESET_VALUE ((uint8_t)0x00) 01960 #define TIM_ETR_RESET_VALUE ((uint8_t)0x00) 01961 #define TIM_DER_RESET_VALUE ((uint8_t)0x00) 01962 #define TIM_IER_RESET_VALUE ((uint8_t)0x00) 01963 #define TIM_SR1_RESET_VALUE ((uint8_t)0x00) 01964 #define TIM_SR2_RESET_VALUE ((uint8_t)0x00) 01965 #define TIM_EGR_RESET_VALUE ((uint8_t)0x00) 01966 #define TIM_CCMR1_RESET_VALUE ((uint8_t)0x00) 01967 #define TIM_CCMR2_RESET_VALUE ((uint8_t)0x00) 01968 01969 #define TIM_CCER1_RESET_VALUE ((uint8_t)0x00) 01970 01971 #define TIM_CNTRH_RESET_VALUE ((uint8_t)0x00) 01972 #define TIM_CNTRL_RESET_VALUE ((uint8_t)0x00) 01973 01974 #define TIM_PSCR_RESET_VALUE ((uint8_t)0x00) 01975 #define TIM_ARRH_RESET_VALUE ((uint8_t)0xFF) 01976 #define TIM_ARRL_RESET_VALUE ((uint8_t)0xFF) 01977 01978 #define TIM_CCR1H_RESET_VALUE ((uint8_t)0x00) 01979 #define TIM_CCR1L_RESET_VALUE ((uint8_t)0x00) 01980 #define TIM_CCR2H_RESET_VALUE ((uint8_t)0x00) 01981 #define TIM_CCR2L_RESET_VALUE ((uint8_t)0x00) 01982 01983 #define TIM_BKR_RESET_VALUE ((uint8_t)0x00) 01984 #define TIM_OISR_RESET_VALUE ((uint8_t)0x00) 01985 01986 /** 01987 * @} 01988 */ 01989 01990 /** @addtogroup TIM2_TIM3_TIM5_Registers_Bits_Definition 01991 * @{ 01992 */ 01993 /* CR1*/ 01994 #define TIM_CR1_ARPE ((uint8_t)0x80) /*!< Auto-Reload Preload Enable Mask. */ 01995 #define TIM_CR1_CMS ((uint8_t)0x60) /*!< Center-aligned Mode Selection Mask. */ 01996 #define TIM_CR1_DIR ((uint8_t)0x10) /*!< Direction Mask. */ 01997 #define TIM_CR1_OPM ((uint8_t)0x08) /*!< One Pulse Mode Mask. */ 01998 #define TIM_CR1_URS ((uint8_t)0x04) /*!< Update Request Source Mask. */ 01999 #define TIM_CR1_UDIS ((uint8_t)0x02) /*!< Update DIsable Mask. */ 02000 #define TIM_CR1_CEN ((uint8_t)0x01) /*!< Counter Enable Mask. */ 02001 02002 /* CR2*/ 02003 #define TIM_CR2_TI1S ((uint8_t)0x80) /*!< TI1 selection */ 02004 #define TIM_CR2_MMS ((uint8_t)0x70) /*!< MMS Selection Mask. */ 02005 #define TIM_CR2_CCDS ((uint8_t)0x08) /*!< Capture/Compare DMA Selection */ 02006 02007 02008 /* SMCR*/ 02009 #define TIM_SMCR_MSM ((uint8_t)0x80) /*!< Master/Slave Mode Mask. */ 02010 #define TIM_SMCR_TS ((uint8_t)0x70) /*!< Trigger Selection Mask. */ 02011 #define TIM_SMCR_SMS ((uint8_t)0x07) /*!< Slave Mode Selection Mask. */ 02012 02013 02014 /* ETR*/ 02015 #define TIM_ETR_ETP ((uint8_t)0x80) /*!< External Trigger Polarity Mask. */ 02016 #define TIM_ETR_ECE ((uint8_t)0x40)/*!< External Clock Mask. */ 02017 #define TIM_ETR_ETPS ((uint8_t)0x30) /*!< External Trigger Prescaler Mask. */ 02018 #define TIM_ETR_ETF ((uint8_t)0x0F) /*!< External Trigger Filter Mask. */ 02019 02020 /* DER*/ 02021 #define TIM_DER_CC2DE ((uint8_t)0x04) /*!< Capture/Compare 2 DMA request Enable mask.*/ 02022 #define TIM_DER_CC1DE ((uint8_t)0x02) /*!< Capture/Compare 1 DMA request Enable mask.*/ 02023 #define TIM_DER_UDE ((uint8_t)0x01) /*!< Update DMA request Enable mask. */ 02024 02025 /* IER*/ 02026 #define TIM_IER_BIE ((uint8_t)0x80) /*!< Break Interrupt Enable Mask. */ 02027 #define TIM_IER_TIE ((uint8_t)0x40) /*!< Trigger Interrupt Enable Mask. */ 02028 #define TIM_IER_CC2IE ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Enable Mask. */ 02029 #define TIM_IER_CC1IE ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Enable Mask. */ 02030 #define TIM_IER_UIE ((uint8_t)0x01) /*!< Update Interrupt Enable Mask. */ 02031 02032 /* SR1*/ 02033 #define TIM_SR1_BIF ((uint8_t)0x80) /*!< Break Interrupt Flag Mask. */ 02034 #define TIM_SR1_TIF ((uint8_t)0x40) /*!< Trigger Interrupt Flag Mask. */ 02035 #define TIM_SR1_CC2IF ((uint8_t)0x04) /*!< Capture/Compare 2 Interrupt Flag Mask. */ 02036 #define TIM_SR1_CC1IF ((uint8_t)0x02) /*!< Capture/Compare 1 Interrupt Flag Mask. */ 02037 #define TIM_SR1_UIF ((uint8_t)0x01) /*!< Update Interrupt Flag Mask. */ 02038 02039 /* SR2*/ 02040 #define TIM_SR2_CC2OF ((uint8_t)0x04) /*!< Capture/Compare 2 Overcapture Flag Mask. */ 02041 #define TIM_SR2_CC1OF ((uint8_t)0x02) /*!< Capture/Compare 1 Overcapture Flag Mask. */ 02042 02043 /*EGR*/ 02044 #define TIM_EGR_BG ((uint8_t)0x80) /*!< Break Generation Mask. */ 02045 #define TIM_EGR_TG ((uint8_t)0x40) /*!< Trigger Generation Mask. */ 02046 #define TIM_EGR_CC2G ((uint8_t)0x04) /*!< Capture/Compare 2 Generation Mask. */ 02047 #define TIM_EGR_CC1G ((uint8_t)0x02) /*!< Capture/Compare 1 Generation Mask. */ 02048 #define TIM_EGR_UG ((uint8_t)0x01) /*!< Update Generation Mask. */ 02049 02050 /*CCMR*/ 02051 #define TIM_CCMR_ICxF ((uint8_t)0xF0) /*!< Input Capture x Filter Mask. */ 02052 #define TIM_CCMR_ICxPSC ((uint8_t)0x0C) /*!< Input Capture x Prescaler Mask. */ 02053 #define TIM_CCMR_CCxS ((uint8_t)0x03) /*!< Capture/Compare x Selection Mask. */ 02054 #define TIM_CCMR_OCM ((uint8_t)0x70) /*!< Output Compare x Mode Mask. */ 02055 #define TIM_CCMR_OCxPE ((uint8_t)0x08) /*!< Output Compare x Preload Enable Mask. */ 02056 #define TIM_CCMR_OCxFE ((uint8_t)0x04) /*!< Output Compare x Fast Enable Mask. */ 02057 02058 #define TIM_CCMR_TIxDirect_Set ((uint8_t)0x01) 02059 02060 /*CCER1*/ 02061 #define TIM_CCER1_CC2P ((uint8_t)0x20) /*!< Capture/Compare 2 output Polarity Mask. */ 02062 #define TIM_CCER1_CC2E ((uint8_t)0x10) /*!< Capture/Compare 2 output enable Mask. */ 02063 #define TIM_CCER1_CC1P ((uint8_t)0x02) /*!< Capture/Compare 1 output Polarity Mask. */ 02064 #define TIM_CCER1_CC1E ((uint8_t)0x01) /*!< Capture/Compare 1 output enable Mask. */ 02065 02066 /*CNTR*/ 02067 #define TIM_CNTRH_CNT ((uint8_t)0xFF) /*!< Counter Value (MSB) Mask. */ 02068 #define TIM_CNTRL_CNT ((uint8_t)0xFF) /*!< Counter Value (LSB) Mask. */ 02069 02070 /*PSCR*/ 02071 #define TIM_PSCR_PSC ((uint8_t)0x07) /*!< Prescaler Value Mask. */ 02072 02073 /*ARR*/ 02074 #define TIM_ARRH_ARR ((uint8_t)0xFF) /*!< Autoreload Value (MSB) Mask. */ 02075 #define TIM_ARRL_ARR ((uint8_t)0xFF) /*!< Autoreload Value (LSB) Mask. */ 02076 02077 02078 /*CCR1*/ 02079 #define TIM_CCR1H_CCR1 ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (MSB) Mask. */ 02080 #define TIM_CCR1L_CCR1 ((uint8_t)0xFF) /*!< Capture/Compare 1 Value (LSB) Mask. */ 02081 02082 /*CCR2*/ 02083 #define TIM_CCR2H_CCR2 ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (MSB) Mask. */ 02084 #define TIM_CCR2L_CCR2 ((uint8_t)0xFF) /*!< Capture/Compare 2 Value (LSB) Mask. */ 02085 02086 02087 /*BKR*/ 02088 #define TIM_BKR_MOE ((uint8_t)0x80) /*!< Main Output Enable Mask. */ 02089 #define TIM_BKR_AOE ((uint8_t)0x40) /*!< Automatic Output Enable Mask. */ 02090 #define TIM_BKR_BKP ((uint8_t)0x20) /*!< Break Polarity Mask. */ 02091 #define TIM_BKR_BKE ((uint8_t)0x10) /*!< Break Enable Mask. */ 02092 #define TIM_BKR_OSSI ((uint8_t)0x04) /*!< Off-State Selection for Idle mode Mask. */ 02093 #define TIM_BKR_LOCK ((uint8_t)0x03) /*!<Lock Configuration Mask. */ 02094 02095 /*OISR*/ 02096 #define TIM_OISR_OIS2 ((uint8_t)0x04) /*!< Output Idle state 2 (OC2 output) Mask. */ 02097 #define TIM_OISR_OIS1 ((uint8_t)0x01) /*!< Output Idle state 1 (OC1 output) Mask. */ 02098 /** 02099 * @} 02100 */ 02101 02102 02103 /*----------------------------------------------------------------------------*/ 02104 02105 /** 02106 * @brief 8-bit system or Low End Small Timer (TIM4) 02107 */ 02108 typedef struct TIM4_struct 02109 { 02110 __IO uint8_t CR1; /*!< control register 1 */ 02111 __IO uint8_t CR2; /*!< control register 2 */ 02112 __IO uint8_t SMCR; /*!< Synchro mode control register */ 02113 __IO uint8_t DER; /*!< DMA requests enable register */ 02114 __IO uint8_t IER; /*!< interrupt enable register */ 02115 __IO uint8_t SR1; /*!< status register 1 */ 02116 __IO uint8_t EGR; /*!< event generation register */ 02117 __IO uint8_t CNTR; /*!< counter register */ 02118 __IO uint8_t PSCR; /*!< prescaler register */ 02119 __IO uint8_t ARR; /*!< auto-reload register */ 02120 } 02121 TIM4_TypeDef; 02122 /** @addtogroup TIM4_Registers_Reset_Value 02123 * @{ 02124 */ 02125 #define TIM4_CR1_RESET_VALUE ((uint8_t)0x00) 02126 #define TIM4_CR2_RESET_VALUE ((uint8_t)0x00) 02127 #define TIM4_SMCR_RESET_VALUE ((uint8_t)0x00) 02128 #define TIM4_DER_RESET_VALUE ((uint8_t)0x00) 02129 #define TIM4_IER_RESET_VALUE ((uint8_t)0x00) 02130 #define TIM4_SR1_RESET_VALUE ((uint8_t)0x00) 02131 #define TIM4_EGR_RESET_VALUE ((uint8_t)0x00) 02132 #define TIM4_CNTR_RESET_VALUE ((uint8_t)0x00) 02133 #define TIM4_PSCR_RESET_VALUE ((uint8_t)0x00) 02134 #define TIM4_ARR_RESET_VALUE ((uint8_t)0xFF) 02135 02136 /** 02137 * @} 02138 */ 02139 02140 /** @addtogroup TIM4_Registers_Bits_Definition 02141 * @{ 02142 */ 02143 /* CR1*/ 02144 #define TIM4_CR1_ARPE ((uint8_t)0x80) /*!< Auto-Reload Preload Enable Mask. */ 02145 #define TIM4_CR1_OPM ((uint8_t)0x08) /*!< One Pulse Mode Mask. */ 02146 #define TIM4_CR1_URS ((uint8_t)0x04) /*!< Update Request Source Mask. */ 02147 #define TIM4_CR1_UDIS ((uint8_t)0x02) /*!< Update DIsable Mask. */ 02148 #define TIM4_CR1_CEN ((uint8_t)0x01) /*!< Counter Enable Mask. */ 02149 02150 /* CR2*/ 02151 #define TIM4_CR2_MMS ((uint8_t)0x70) /*!< MMS Selection Mask. */ 02152 02153 /* SMCR*/ 02154 #define TIM4_SMCR_MSM ((uint8_t)0x80) /*!< Master/Slave Mode Mask. */ 02155 #define TIM4_SMCR_TS ((uint8_t)0x70) /*!< Trigger Selection Mask. */ 02156 #define TIM4_SMCR_SMS ((uint8_t)0x07) /*!< Slave Mode Selection Mask. */ 02157 02158 /* DER*/ 02159 #define TIM4_DER_UDE ((uint8_t)0x01) /*!< Update DMA request Enable mask. */ 02160 02161 /* IER*/ 02162 #define TIM4_IER_TIE ((uint8_t)0x40) /*!< Trigger Interrupt Enable Mask. */ 02163 #define TIM4_IER_UIE ((uint8_t)0x01) /*!< Update Interrupt Enable Mask. */ 02164 02165 /* SR1*/ 02166 #define TIM4_SR1_UIF ((uint8_t)0x01) /*!< Update Interrupt Flag Mask. */ 02167 #define TIM4_SR1_TIF ((uint8_t)0x40) /*!< Trigger Interrupt Flag Mask. */ 02168 02169 /* EGR*/ 02170 #define TIM4_EGR_UG ((uint8_t)0x01) /*!< Update Generation Mask. */ 02171 #define TIM4_EGR_TG ((uint8_t)0x40) /*!< Trigger Generation Mask. */ 02172 02173 /* CNTR*/ 02174 #define TIM4_CNTR_CNT ((uint8_t)0xFF) /*!<Counter Value (LSB) Mask. */ 02175 02176 /* PSCR*/ 02177 #define TIM4_PSCR_PSC ((uint8_t)0x0F) /*!<Prescaler Value Mask. */ 02178 02179 /* ARR*/ 02180 #define TIM4_ARR_ARR ((uint8_t)0xFF) /*!<Autoreload Value Mask. */ 02181 /** 02182 * @} 02183 */ 02184 02185 /*----------------------------------------------------------------------------*/ 02186 02187 /** 02188 * @brief USART 02189 */ 02190 typedef struct USART_struct 02191 { 02192 __IO uint8_t SR; /*!< USART status register */ 02193 __IO uint8_t DR; /*!< USART data register */ 02194 __IO uint8_t BRR1; /*!< USART baud rate register */ 02195 __IO uint8_t BRR2; /*!< USART DIV mantissa[11:8] SCIDIV fraction */ 02196 __IO uint8_t CR1; /*!< USART control register 1 */ 02197 __IO uint8_t CR2; /*!< USART control register 2 */ 02198 __IO uint8_t CR3; /*!< USART control register 3 */ 02199 __IO uint8_t CR4; /*!< USART control register 4 */ 02200 __IO uint8_t CR5; /*!< USART control register 5 */ 02201 __IO uint8_t GTR; /*!< USART guard time register */ 02202 __IO uint8_t PSCR; /*!< USART prescaler register */ 02203 } 02204 USART_TypeDef; 02205 02206 02207 /** @addtogroup USART_Registers_Reset_Value 02208 * @{ 02209 */ 02210 #define USART_SR_RESET_VALUE ((uint8_t)0xC0) 02211 #define USART_BRR1_RESET_VALUE ((uint8_t)0x00) 02212 #define USART_BRR2_RESET_VALUE ((uint8_t)0x00) 02213 #define USART_CR1_RESET_VALUE ((uint8_t)0x00) 02214 #define USART_CR2_RESET_VALUE ((uint8_t)0x00) 02215 #define USART_CR3_RESET_VALUE ((uint8_t)0x00) 02216 #define USART_CR4_RESET_VALUE ((uint8_t)0x00) 02217 02218 /** 02219 * @} 02220 */ 02221 02222 /** @addtogroup USART_Registers_Bits_Definition 02223 * @{ 02224 */ 02225 #define USART_SR_TXE ((uint8_t)0x80) /*!< Transmit Data Register Empty mask */ 02226 #define USART_SR_TC ((uint8_t)0x40) /*!< Transmission Complete mask */ 02227 #define USART_SR_RXNE ((uint8_t)0x20) /*!< Read Data Register Not Empty mask */ 02228 #define USART_SR_IDLE ((uint8_t)0x10) /*!< IDLE line detected mask */ 02229 #define USART_SR_OR ((uint8_t)0x08) /*!< OverRun error mask */ 02230 #define USART_SR_NF ((uint8_t)0x04) /*!< Noise Flag mask */ 02231 #define USART_SR_FE ((uint8_t)0x02) /*!< Framing Error mask */ 02232 #define USART_SR_PE ((uint8_t)0x01) /*!< Parity Error mask */ 02233 02234 #define USART_BRR1_DIVM ((uint8_t)0xFF) /*!< LSB mantissa of USARTDIV [7:0] mask */ 02235 02236 #define USART_BRR2_DIVM ((uint8_t)0xF0) /*!< MSB mantissa of USARTDIV [11:8] mask */ 02237 #define USART_BRR2_DIVF ((uint8_t)0x0F) /*!< Fraction bits of USARTDIV [3:0] mask */ 02238 02239 #define USART_CR1_R8 ((uint8_t)0x80) /*!< Receive Data bit 8 */ 02240 #define USART_CR1_T8 ((uint8_t)0x40) /*!< Transmit data bit 8 */ 02241 #define USART_CR1_USARTD ((uint8_t)0x20) /*!< USART Disable (for low power consumption) */ 02242 #define USART_CR1_M ((uint8_t)0x10) /*!< Word length mask */ 02243 #define USART_CR1_WAKE ((uint8_t)0x08) /*!< Wake-up method mask */ 02244 #define USART_CR1_PCEN ((uint8_t)0x04) /*!< Parity Control Enable mask */ 02245 #define USART_CR1_PS ((uint8_t)0x02) /*!< USART Parity Selection */ 02246 #define USART_CR1_PIEN ((uint8_t)0x01) /*!< USART Parity Interrupt Enable mask */ 02247 02248 #define USART_CR2_TIEN ((uint8_t)0x80) /*!< Transmitter Interrupt Enable mask */ 02249 #define USART_CR2_TCIEN ((uint8_t)0x40) /*!< TransmissionComplete Interrupt Enable mask */ 02250 #define USART_CR2_RIEN ((uint8_t)0x20) /*!< Receiver Interrupt Enable mask */ 02251 #define USART_CR2_ILIEN ((uint8_t)0x10) /*!< IDLE Line Interrupt Enable mask */ 02252 #define USART_CR2_TEN ((uint8_t)0x08) /*!< Transmitter Enable mask */ 02253 #define USART_CR2_REN ((uint8_t)0x04) /*!< Receiver Enable mask */ 02254 #define USART_CR2_RWU ((uint8_t)0x02) /*!< Receiver Wake-Up mask */ 02255 #define USART_CR2_SBK ((uint8_t)0x01) /*!< Send Break mask */ 02256 02257 #define USART_CR3_STOP ((uint8_t)0x30) /*!< STOP bits [1:0] mask */ 02258 #define USART_CR3_CLKEN ((uint8_t)0x08) /*!< Clock Enable mask */ 02259 #define USART_CR3_CPOL ((uint8_t)0x04) /*!< Clock Polarity mask */ 02260 #define USART_CR3_CPHA ((uint8_t)0x02) /*!< Clock Phase mask */ 02261 #define USART_CR3_LBCL ((uint8_t)0x01) /*!< Last Bit Clock pulse mask */ 02262 02263 #define USART_CR4_ADD ((uint8_t)0x0F) /*!< Address of the USART node mask */ 02264 02265 #define USART_CR5_DMAT ((uint8_t)0x80) /*!< DMA Enable transmitter mask */ 02266 #define USART_CR5_DMAR ((uint8_t)0x40) /*!< DMA Enable receiver mask */ 02267 #define USART_CR5_SCEN ((uint8_t)0x20) /*!< Smart Card Enable mask */ 02268 #define USART_CR5_NACK ((uint8_t)0x10) /*!< Smart Card Nack Enable mask */ 02269 #define USART_CR5_HDSEL ((uint8_t)0x08) /*!< Half-Duplex Selection mask */ 02270 #define USART_CR5_IRLP ((uint8_t)0x04) /*!< Irda Low Power Selection mask */ 02271 #define USART_CR5_IREN ((uint8_t)0x02) /*!< Irda Enable mask */ 02272 #define USART_CR5_EIE ((uint8_t)0x01) /*!< Error Interrupt mask */ 02273 /** 02274 * @} 02275 */ 02276 /*----------------------------------------------------------------------------*/ 02277 02278 /** 02279 * @brief Analog to Digital Converter (ADC) peripheral 02280 */ 02281 typedef struct ADC_struct 02282 { 02283 __IO uint8_t CR1; /*!< Control register 1 */ 02284 __IO uint8_t CR2; /*!< Control register 2 */ 02285 __IO uint8_t CR3; /*!< Control register 3 */ 02286 __IO uint8_t SR; /*!< Status register */ 02287 __IO uint8_t DRH; /*!< Data register MSB */ 02288 __IO uint8_t DRL; /*!< Data register LSB */ 02289 __IO uint8_t HTRH; /*!< High voltage reference register MSB */ 02290 __IO uint8_t HTRL; /*!< High voltage reference register LSB */ 02291 __IO uint8_t LTRH; /*!< Low voltage reference register MSB */ 02292 __IO uint8_t LTRL; /*!< Low voltage reference register LSB */ 02293 __IO uint8_t SQR[4]; /*!< Channel select scan registers */ 02294 __IO uint8_t TRIGR[4]; /*!< Trigger disable registers */ 02295 } 02296 ADC_TypeDef; 02297 02298 /** @addtogroup ADC_Registers_Reset_Value 02299 * @{ 02300 */ 02301 #define ADC_CR1_RESET_VALUE ((uint8_t) 0x00) 02302 #define ADC_CR2_RESET_VALUE ((uint8_t) 0x00) 02303 #define ADC_CR3_RESET_VALUE ((uint8_t) 0x1F) 02304 #define ADC_SR_RESET_VALUE ((uint8_t) 0x00) 02305 #define ADC_DRH_RESET_VALUE ((uint8_t) 0x00) 02306 #define ADC_DRL_RESET_VALUE ((uint8_t) 0x00) 02307 #define ADC_HTRH_RESET_VALUE ((uint8_t) 0x0F) 02308 #define ADC_HTRL_RESET_VALUE ((uint8_t) 0xFF) 02309 #define ADC_LTRH_RESET_VALUE ((uint8_t) 0x00) 02310 #define ADC_LTRL_RESET_VALUE ((uint8_t) 0x00) 02311 #define ADC_SQR1_RESET_VALUE ((uint8_t) 0x00) 02312 #define ADC_SQR2_RESET_VALUE ((uint8_t) 0x00) 02313 #define ADC_SQR3_RESET_VALUE ((uint8_t) 0x00) 02314 #define ADC_SQR4_RESET_VALUE ((uint8_t) 0x00) 02315 #define ADC_TRIGR1_RESET_VALUE ((uint8_t) 0x00) 02316 #define ADC_TRIGR2_RESET_VALUE ((uint8_t) 0x00) 02317 #define ADC_TRIGR3_RESET_VALUE ((uint8_t) 0x00) 02318 #define ADC_TRIGR4_RESET_VALUE ((uint8_t) 0x00) 02319 02320 02321 /** 02322 * @} 02323 */ 02324 02325 /** @addtogroup ADC_Registers_Bits_Definition 02326 * @{ 02327 */ 02328 #define ADC_CR1_ADON ((uint8_t)0x01) 02329 #define ADC_CR1_START ((uint8_t)0x02) 02330 #define ADC_CR1_CONT ((uint8_t)0x04) 02331 #define ADC_CR1_EOCIE ((uint8_t)0x08) 02332 #define ADC_CR1_AWDIE ((uint8_t)0x10) 02333 #define ADC_CR1_RES ((uint8_t)0x60) 02334 #define ADC_CR1_OVERIE ((uint8_t)0x80) 02335 02336 02337 #define ADC_CR2_SMPT1 ((uint8_t)0x07) 02338 #define ADC_CR2_EXTSEL ((uint8_t)0x18) 02339 #define ADC_CR2_TRIGEDGE ((uint8_t)0x60) 02340 #define ADC_CR2_PRESC ((uint8_t)0x80) 02341 02342 #define ADC_CR3_CHSEL ((uint8_t)0x1F) 02343 #define ADC_CR3_SMPT2 ((uint8_t)0xE0) 02344 02345 #define ADC_SR_EOC ((uint8_t)0x01) 02346 #define ADC_SR_AWD ((uint8_t)0x02) 02347 #define ADC_SR_OVER ((uint8_t)0x04) 02348 02349 #define ADC_DRH_CONVDATA ((uint8_t)0x0F) 02350 #define ADC_DRL_CONVDATA ((uint8_t)0xFF) 02351 02352 #define ADC_HTRH_HT ((uint8_t)0x0F) 02353 #define ADC_HTRL_HT ((uint8_t)0xFF) 02354 02355 #define ADC_LTRH_LT ((uint8_t)0x0F) 02356 #define ADC_LTRL_LT ((uint8_t)0xFF) 02357 02358 #define ADC_SQR1_CHSELS ((uint8_t)0x3F) 02359 #define ADC_SQR1_DMAOFF ((uint8_t)0x80) 02360 #define ADC_SQR2_CHSELS ((uint8_t)0xFF) 02361 #define ADC_SQR3_CHSELS ((uint8_t)0xFF) 02362 #define ADC_SQR4_CHSELS ((uint8_t)0xFF) 02363 02364 #define ADC_TRIGR1_TRIG ((uint8_t)0x0F) 02365 #define ADC_TRIGR1_VREFINTON ((uint8_t)0x10) 02366 #define ADC_TRIGR1_TSON ((uint8_t)0x20) 02367 02368 #define ADC_TRIGR2_TRIG ((uint8_t)0xFF) 02369 #define ADC_TRIGR3_TRIG ((uint8_t)0xFF) 02370 #define ADC_TRIGR4_TRIG ((uint8_t)0xFF) 02371 02372 /** 02373 * @} 02374 */ 02375 /*----------------------------------------------------------------------------*/ 02376 /*----------------------------------------------------------------------------*/ 02377 02378 /** 02379 * @brief Digital to Analog Converter (DAC) peripheral 02380 */ 02381 typedef struct DAC_struct 02382 { 02383 __IO uint8_t CH1CR1; /*!< DAC control register 1 */ 02384 __IO uint8_t CH1CR2; /*!< DAC control register 2 */ 02385 __IO uint8_t CH2CR1; /*!< DAC channel 2 control register 1 */ 02386 __IO uint8_t CH2CR2; /*!< DAC channel 2 control register 2 */ 02387 __IO uint8_t SWTRIGR; /*!< DAC software trigger register */ 02388 __IO uint8_t SR; /*!< DAC status register */ 02389 02390 /*Channel 1 registers*/ 02391 __IO uint8_t RESERVED0[2]; 02392 __IO uint8_t CH1RDHRH; /*!< DAC Channel 1 right aligned data holding register MSB */ 02393 __IO uint8_t CH1RDHRL; /*!< DAC Channel 1 right aligned data holding register LSB */ 02394 __IO uint8_t RESERVED1[2]; 02395 __IO uint8_t CH1LDHRH; /*!< DAC Channel 1 left aligned data holding register MSB */ 02396 __IO uint8_t CH1LDHRL; /*!< DAC Channel 1 left aligned data holding register LSB */ 02397 __IO uint8_t RESERVED2[2]; 02398 __IO uint8_t CH1DHR8; /*!< DAC Channel 1 8-bit data holding register */ 02399 02400 /*Channel 2 registers*/ 02401 __IO uint8_t RESERVED3[3]; 02402 __IO uint8_t CH2RDHRH; /*!< DAC Channel 2 right aligned data holding register MSB */ 02403 __IO uint8_t CH2RDHRL; /*!< DAC Channel 2 right aligned data holding register LSB */ 02404 __IO uint8_t RESERVED4[2]; 02405 __IO uint8_t CH2LDHRH; /*!< DAC Channel 2 left aligned data holding register MSB */ 02406 __IO uint8_t CH2LDHRL; /*!< DAC Channel 2 left aligned data holding register LSB */ 02407 __IO uint8_t RESERVED5[2]; 02408 __IO uint8_t CH2DHR8; /*!< DAC Channel 2 8-bit data holding register */ 02409 02410 02411 /* Dual mode registers */ 02412 __IO uint8_t RESERVED6[3]; 02413 __IO uint8_t DCH1RDHRH; /*!< DAC Dual mode Channel 1 right aligned data holding register MSB */ 02414 __IO uint8_t DCH1RDHRL; /*!< DAC Dual mode Channel 1 right aligned data holding register LSB */ 02415 __IO uint8_t DCH2RDHRH; /*!< DAC Dual mode Channel 2 right aligned data holding register MSB */ 02416 __IO uint8_t DCH2RDHRL; /*!< DAC Dual mode Channel 2 right aligned data holding register LSB */ 02417 __IO uint8_t DCH1LDHRH; /*!< DAC Dual mode Channel 1 left aligned data holding register MSB */ 02418 __IO uint8_t DCH1LDHRL; /*!< DAC Dual mode Channel 1 left aligned data holding register LSB */ 02419 __IO uint8_t DCH2LDHRH; /*!< DAC Dual mode Channel 2 left aligned data holding register MSB */ 02420 __IO uint8_t DCH2LDHRL; /*!< DAC Dual mode Channel 2 left aligned data holding register LSB */ 02421 __IO uint8_t DCH1DHR8; /*!< DAC Dual mode Channel 1 8-bit data holding register */ 02422 __IO uint8_t DCH2DHR8; /*!< DAC Dual mode Channel 2 8-bit data holding register */ 02423 02424 /* DOR registers*/ 02425 __IO uint8_t RESERVED7[2]; 02426 __IO uint8_t CH1DORH; /*!< DAC Channel 1 data output register MSB */ 02427 __IO uint8_t CH1DORL; /*!< DAC Channel 1 data output register LSB */ 02428 __IO uint8_t RESERVED8[2]; 02429 __IO uint8_t CH2DORH; /*!< DAC Channel 2 data output register MSB */ 02430 __IO uint8_t CH2DORL; /*!< DAC Channel 2 data output register LSB */ 02431 } 02432 DAC_TypeDef; 02433 02434 /** @addtogroup DAC_Registers_Reset_Value 02435 * @{ 02436 */ 02437 #define DAC_CR1_RESET_VALUE ((uint8_t)0x00) 02438 #define DAC_CR2_RESET_VALUE ((uint8_t)0x00) 02439 #define DAC_SWTRIGR_RESET_VALUE ((uint8_t)0x00) 02440 #define DAC_SR_RESET_VALUE ((uint8_t)0x00) 02441 #define DAC_RDHRH_RESET_VALUE ((uint8_t)0x00) 02442 #define DAC_RDHRL_RESET_VALUE ((uint8_t)0x00) 02443 #define DAC_LDHRH_RESET_VALUE ((uint8_t)0x00) 02444 #define DAC_LDHRL_RESET_VALUE ((uint8_t)0x00) 02445 #define DAC_DHR8_RESET_VALUE ((uint8_t)0x00) 02446 #define DAC_DORH_RESET_VALUE ((uint8_t)0x00) 02447 #define DAC_DORL_RESET_VALUE ((uint8_t)0x00) 02448 /** 02449 * @} 02450 */ 02451 02452 /** @addtogroup DAC_Registers_Bits_Definition 02453 * @{ 02454 */ 02455 02456 /* CR1*/ 02457 #define DAC_CR1_TSEL ((uint8_t)0x38) /*!< DAC channel trigger selection. */ 02458 #define DAC_CR1_TEN ((uint8_t)0x04) /*!< DAC channel trigger enable. */ 02459 #define DAC_CR1_BOFF ((uint8_t)0x02) /*!< DAC channel output buffer disable. */ 02460 #define DAC_CR1_EN ((uint8_t)0x01) /*!< DAC channel enable. */ 02461 #define DAC_CR1_WAVEN ((uint8_t)0xC0) /*!< DAC channel wave generation enable. */ 02462 02463 /* CR2*/ 02464 #define DAC_CR2_DMAUDRIE ((uint8_t)0x20) /*!< DAC channel DMA underrun interrupt enable. */ 02465 #define DAC_CR2_DMAEN ((uint8_t)0x10) /*!< DAC DMA enable. */ 02466 #define DAC_CR2_MAMPx ((uint8_t)0x0F) /*!< DAC Dchannel wave generation config. */ 02467 02468 /* SWTRIGR*/ 02469 #define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!< DAC channel 1 software trigger. */ 02470 #define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /*!< DAC channel 2 software trigger. */ 02471 02472 /* SR*/ 02473 #define DAC_SR_DMAUDR1 ((uint8_t)0x01) /*!< DAC channel 1 DMA underrun flag. */ 02474 #define DAC_SR_DMAUDR2 ((uint8_t)0x02) /*!< DAC channel 2 DMA underrun flag. */ 02475 02476 /* RDHRH*/ 02477 #define DAC_RDHRH_RDHRH ((uint8_t)0x0F) /*!< DAC right aligned data holding register most significant bits. */ 02478 02479 /* RDHRL*/ 02480 #define DAC_RDHRL_RDHRL ((uint8_t)0xFF) /*!< DAC right aligned data holding register least significant bits. */ 02481 02482 /* LDHRL*/ 02483 #define DAC_LDHRH_LDHRH ((uint8_t)0xFF) /*!< DAC left aligned data holding register most significant bits. */ 02484 02485 /* LDHRL*/ 02486 #define DAC_LDHRL_LDHRL ((uint8_t)0xF0) /*!< DAC left aligned data holding register least significant bits. */ 02487 02488 /* DHR8*/ 02489 #define DAC_DHR8_8DHR ((uint8_t)0xFF) /*!< DAC 8bit data holding bits */ 02490 02491 /* DORH*/ 02492 #define DAC_DORH_DORH ((uint8_t)0x0F) /*!< DAC data output register most significant bit */ 02493 02494 /* DORL*/ 02495 #define DAC_DORL_DORL ((uint8_t)0xFF) /*!< DAC data output register least significant bit */ 02496 02497 /** 02498 * @} 02499 */ 02500 02501 /*----------------------------------------------------------------------------*/ 02502 02503 /** 02504 * @brief Direct-Memory Access (DMA) 02505 */ 02506 typedef struct DMA_struct 02507 { 02508 __IO uint8_t GCSR; /*!< Global configuration and status register */ 02509 __IO uint8_t GIR1; /*!< Global interrupt register 1 */ 02510 } 02511 DMA_TypeDef; 02512 /** 02513 * @} 02514 */ 02515 typedef struct DMA_Channel_struct 02516 { 02517 __IO uint8_t CCR; /*!< CHx Control register */ 02518 __IO uint8_t CSPR; /*!< CHx Status & Priority register */ 02519 __IO uint8_t CNBTR; /*!< CHx Number of Bytes to Tranfer register */ 02520 __IO uint8_t CPARH; /*!< Peripheral Address High register */ 02521 __IO uint8_t CPARL; /*!< Peripheral Address Low register */ 02522 __IO uint8_t CM0EAR; /*!< Memory 0 Extended Address register (for channel3)*/ 02523 __IO uint8_t CM0ARH; /*!< Memory 0 Address High register */ 02524 __IO uint8_t CM0ARL; /*!< Memory 0 Address Low register */ 02525 } 02526 DMA_Channel_TypeDef; 02527 /** 02528 * @} 02529 */ 02530 02531 /** @addtogroup DMA_Registers_Reset_Value 02532 * @{ 02533 */ 02534 #define DMA_GCSR_RESET_VALUE ((uint8_t)0xFC) 02535 #define DMA_GIR1_RESET_VALUE ((uint8_t)0x00) 02536 /** 02537 * @} 02538 */ 02539 02540 /** @addtogroup DMA_Channels_Registers_Reset_Value 02541 * @{ 02542 */ 02543 #define DMA_CCR_RESET_VALUE ((uint8_t)0x00) 02544 #define DMA_CSPR_RESET_VALUE ((uint8_t)0x00) 02545 #define DMA_CNBTR_RESET_VALUE ((uint8_t)0x00) 02546 #define DMA_CPARH_RESET_VALUE ((uint8_t)0x52) 02547 #define DMA_C3PARH_RESET_VALUE ((uint8_t)0x40) 02548 #define DMA_CPARL_RESET_VALUE ((uint8_t)0x00) 02549 #define DMA_C3M0EAR_RESET_VALUE ((uint8_t)0x00) 02550 #define DMA_CM0ARH_RESET_VALUE ((uint8_t)0x00) 02551 #define DMA_CM0ARL_RESET_VALUE ((uint8_t)0x00) 02552 /** @addtogroup DMA_Registers_Bits_Definition 02553 * @{ 02554 */ 02555 02556 /* Bit definition for DMA_GCSR register */ 02557 02558 #define DMA_GCSR_GE ((uint8_t)0x01) /*!<Global Enable */ 02559 #define DMA_GCSR_GB ((uint8_t)0x02) /*!<Global Busy */ 02560 #define DMA_GCSR_TO ((uint8_t)0xFC) /*!<Time Out */ 02561 02562 /* Bit definition for DMA_GIR1 register */ 02563 #define DMA_GIR1_IFC0 ((uint8_t)0x01) /*!< Interrupt Flag Channel 0 */ 02564 #define DMA_GIR1_IFC1 ((uint8_t)0x02) /*!< Interrupt Flag Channel 1 */ 02565 #define DMA_GIR1_IFC2 ((uint8_t)0x04) /*!< Interrupt Flag Channel 2 */ 02566 #define DMA_GIR1_IFC3 ((uint8_t)0x08) /*!< Interrupt Flag Channel 3 */ 02567 02568 02569 /* Bit definition for DMA_CCR registers */ 02570 #define DMA_CCR_CE ((uint8_t)0x01) /*!<Channel enable*/ 02571 #define DMA_CCR_TCIE ((uint8_t)0x02) /*!<Transfer complete interrupt enable */ 02572 #define DMA_CCR_HTIE ((uint8_t)0x04) /*!<Half Transfer interrupt enable */ 02573 #define DMA_CCR_DTD ((uint8_t)0x08) /*!<Data transfer direction */ 02574 #define DMA_CCR_ARM ((uint8_t)0x10) /*!<Autorelaod mode Circular buffer mode */ 02575 #define DMA_CCR_IDM ((uint8_t)0x20) /*!<Inc/Dec mode */ 02576 #define DMA_CCR_MEM ((uint8_t)0x40) /*!<Memory Transfer Enable */ 02577 02578 02579 /* Bit definition for DMA_CSPR registers */ 02580 #define DMA_CSPR_TCIF ((uint8_t)0x02) /*!<Transaction Complete Interrupt Flag*/ 02581 #define DMA_CSPR_HTIF ((uint8_t)0x04) /*!<Half Transaction Interrupt Flag*/ 02582 #define DMA_CSPR_16BM ((uint8_t)0x08) /*!<16 bit mode*/ 02583 #define DMA_CSPR_PL ((uint8_t)0x30) /*!<Channel priority level*/ 02584 #define DMA_CSPR_PEND ((uint8_t)0x40) /*!<Channel pending*/ 02585 #define DMA_CSPR_BUSY ((uint8_t)0x80) /*!<Channel Busy */ 02586 02587 02588 /* Bit definition for DMA_CNBTR register */ 02589 #define DMA_CNBTR_NDT ((uint8_t)0xFF) /*!<Number of data to Transfer */ 02590 02591 02592 /* Bit definition for DMA_CPARH register */ 02593 #define DMA_CPARH_PA ((uint8_t)0xFF) /*!<Peripheral MSB Address Pointer */ 02594 /* Bit definition for DMA_CPARL register */ 02595 #define DMA_CPARL_PA ((uint8_t)0xFF) /*!<Peripheral LSB Address Pointer */ 02596 02597 02598 /* Bit definition for DMA_CMAR registers */ 02599 #define DMA_CM0EAR_MA ((uint8_t)0x01) /* Memory Extended Address Pointer only for channel 3 in Memory to memory transfer*/ 02600 #define DMA_CM0ARH_MA ((uint8_t)0xFF) /*!<Memory MSB Address Pointer*/ 02601 #define DMA_CM0ARL_MA ((uint8_t)0xFF) /*!<Memory LSB Address Pointer */ 02602 02603 02604 /** 02605 * @} 02606 */ 02607 /*----------------------------------------------------------------------------*/ 02608 02609 /** 02610 * @brief Window Watchdog (WWDG) 02611 */ 02612 typedef struct WWDG_struct 02613 { 02614 __IO uint8_t CR; /*!< Control Register */ 02615 __IO uint8_t WR; /*!< Window Register */ 02616 } 02617 WWDG_TypeDef; 02618 02619 /** @addtogroup WWDG_Registers_Reset_Value 02620 * @{ 02621 */ 02622 02623 #define WWDG_CR_RESET_VALUE ((uint8_t)0x7F) 02624 #define WWDG_WR_RESET_VALUE ((uint8_t)0x7F) 02625 02626 /** 02627 * @} 02628 */ 02629 02630 /** @addtogroup WWDG_Registers_Bits_Definition 02631 * @{ 02632 */ 02633 02634 #define WWDG_CR_WDGA ((uint8_t)0x80) /*!< WDGA bit mask */ 02635 #define WWDG_CR_T6 ((uint8_t)0x40) /*!< T6 bit mask */ 02636 #define WWDG_CR_T ((uint8_t)0x7F) /*!< T bits mask */ 02637 02638 #define WWDG_WR_MSB ((uint8_t)0x80) /*!< MSB bit mask */ 02639 #define WWDG_WR_W ((uint8_t)0x7F) /*!< W bits mask */ 02640 02641 02642 /** 02643 * @} 02644 */ 02645 02646 /*----------------------------------------------------------------------------*/ 02647 /** 02648 * @brief LCD Controller (LCD) 02649 */ 02650 typedef struct LCD_struct 02651 { 02652 __IO uint8_t CR1; /*!< LCD control register 1 */ 02653 __IO uint8_t CR2; /*!< LCD control register 2 */ 02654 __IO uint8_t CR3; /*!< LCD control register 3 */ 02655 __IO uint8_t FRQ; /*!< LCD frequency register */ 02656 __IO uint8_t PM[6]; /*!< LCD portmask registers*/ 02657 uint8_t RESERVED1[2]; /*!< Reserved */ 02658 __IO uint8_t RAM[22]; /*!< LCD RAM registers*/ 02659 uint8_t RESERVED2[13]; /*!< Reserved */ 02660 __IO uint8_t CR4; /*!< LCD control register 4 */ 02661 } 02662 LCD_TypeDef; 02663 /** @addtogroup LCD_Registers_Reset_Value 02664 * @{ 02665 */ 02666 #define LCD_CR1_RESET_VALUE ((uint8_t)0x00) /*!< Control Register 1 reset value */ 02667 #define LCD_CR2_RESET_VALUE ((uint8_t)0x00) /*!< Control Register 2 reset value */ 02668 #define LCD_CR3_RESET_VALUE ((uint8_t)0x00) /*!< Control Register 3 reset value */ 02669 #define LCD_FRQ_RESET_VALUE ((uint8_t)0x00) /*!< Register Frequency reset value */ 02670 #define LCD_PM_RESET_VALUE ((uint8_t)0x00) /*!< Port mask Register reset value */ 02671 #define LCD_RAM_RESET_VALUE ((uint8_t)0x00) /*!< RAM Register reset value */ 02672 #define LCD_CR4_RESET_VALUE ((uint8_t)0x00) /*!< Control Register 4 reset value */ 02673 02674 02675 /** 02676 * @} 02677 */ 02678 02679 /** @addtogroup LCD_Registers_Bits_Definition 02680 * @{ 02681 */ 02682 #define LCD_CR1_BLINK ((uint8_t)0xC0) /*!< Blink bits mask */ 02683 #define LCD_CR1_BLINKF ((uint8_t)0x38) /*!< Blink frequency bits mask */ 02684 #define LCD_CR1_DUTY ((uint8_t)0x06) /*!< Duty bits mask */ 02685 #define LCD_CR1_B2 ((uint8_t)0x01) /*!< Bias selector bit mask */ 02686 02687 02688 #define LCD_CR2_PON ((uint8_t)0xE0) /*!< Pulse on duration bits mask */ 02689 #define LCD_CR2_HD ((uint8_t)0x10) /*!< High drive enable bit mask */ 02690 #define LCD_CR2_CC ((uint8_t)0x0E) /*!< Contrast control bits mask */ 02691 #define LCD_CR2_VSEL ((uint8_t)0x01) /*!< Voltage source bit mask */ 02692 02693 #define LCD_CR3_LCDEN ((uint8_t)0x40) /*!< Enable bit mask */ 02694 #define LCD_CR3_SOFIE ((uint8_t)0x20) /*!< Start of frame interrupt enable mask */ 02695 #define LCD_CR3_SOF ((uint8_t)0x10) /*!< Start of frame bit mask */ 02696 #define LCD_CR3_SOFC ((uint8_t)0x08) /*!< Clear start of frame bit mask */ 02697 #define LCD_CR3_DEAD ((uint8_t)0x07) /*!< DEAD time bits mask */ 02698 02699 #define LCD_FRQ_DIV ((uint8_t)0x0F) /*!< Divider bits mask */ 02700 #define LCD_FRQ_PS ((uint8_t)0xF0) /*!< 16 bits prescaler bits mask */ 02701 02702 #define LCD_CR4_MAPCOM ((uint8_t)0x08) /*!< Select the mapping scheme for the COM[7:4] */ 02703 #define LCD_CR4_PAGECOM ((uint8_t)0x04) /*!< Select the LCD RAM page sector */ 02704 #define LCD_CR4_DUTY8 ((uint8_t)0x02) /*!< Enable the 1/8 duty */ 02705 #define LCD_CR4_B4 ((uint8_t)0x01) /*!< Enable the 1/4 bias */ 02706 02707 02708 /** 02709 * @} 02710 */ 02711 02712 /*----------------------------------------------------------------------------*/ 02713 /* This peripheral is avilable in STM8L16x devices only*/ 02714 /** 02715 * @brief AES tiny (AES) 02716 */ 02717 typedef struct AES_struct 02718 { 02719 __IO uint8_t CR; /*!< AES control register */ 02720 __IO uint8_t SR; /*!< AES status register */ 02721 __IO uint8_t DINR; /*!< AES Data input register */ 02722 __IO uint8_t DOUTR; /*!< AES Data output register */ 02723 } 02724 AES_TypeDef; 02725 02726 /** @addtogroup AES_Registers_Reset_Value 02727 * @{ 02728 */ 02729 #define AES_CR_RESET_VALUE ((uint8_t)0x00) /*!< Control Register reset value */ 02730 #define AES_SR_RESET_VALUE ((uint8_t)0x00) /*!< Status Register reset value */ 02731 #define AES_DINR_RESET_VALUE ((uint8_t)0x00) /*!< Data input register reset value */ 02732 #define AES_DOUTR_RESET_VALUE ((uint8_t)0x00) /*!< Data output register reset value */ 02733 /** 02734 * @} 02735 */ 02736 02737 /** @addtogroup AES_Registers_Bits_Definition 02738 * @{ 02739 */ 02740 #define AES_CR_DMAEN ((uint8_t)0x80) /*!< DMA Enable bit mask */ 02741 #define AES_CR_ERRIE ((uint8_t)0x40) /*!< Error Interrupt Enable bit mask */ 02742 #define AES_CR_CCIE ((uint8_t)0x20) /*!< Computation Complete Interrupt Enable bit mask */ 02743 #define AES_CR_ERRC ((uint8_t)0x10) /*!< Error Clear bit mask */ 02744 #define AES_CR_CCFC ((uint8_t)0x08) /*!< Computation Complete Flag Clear bit mask */ 02745 #define AES_CR_MODE ((uint8_t)0x06) /*!< AES Modes of Operation bits mask */ 02746 #define AES_CR_EN ((uint8_t)0x01) /*!< AES Enable bit mask */ 02747 02748 #define AES_SR_WRERR ((uint8_t)0x04) /*!< Write Error Flag bit mask */ 02749 #define AES_SR_RDERR ((uint8_t)0x02) /*!< Read Error Flag bit mask */ 02750 #define AES_SR_CCF ((uint8_t)0x01) /*!< Computation Complete Flag bit mask */ 02751 02752 #define AES_DINR ((uint8_t)0xFF) /*!< Data Input bits mask */ 02753 #define AES_DOUTR ((uint8_t)0xFF) /*!< Data Output bits mask */ 02754 02755 /** 02756 * @} 02757 */ 02758 /******************************************************************************/ 02759 /* Peripherals Base Address */ 02760 /******************************************************************************/ 02761 #define OPT_BASE (uint16_t)0x4800 02762 #define GPIOA_BASE (uint16_t)0x5000 02763 #define GPIOB_BASE (uint16_t)0x5005 02764 #define GPIOC_BASE (uint16_t)0x500A 02765 #define GPIOD_BASE (uint16_t)0x500F 02766 #define GPIOE_BASE (uint16_t)0x5014 02767 #define GPIOF_BASE (uint16_t)0x5019 02768 #define GPIOG_BASE (uint16_t)0x501E 02769 #define GPIOH_BASE (uint16_t)0x5023 02770 #define GPIOI_BASE (uint16_t)0x5028 02771 #define FLASH_BASE (uint16_t)0x5050 02772 #define DMA1_BASE (uint16_t)0x5070 02773 #define DMA1_Channel0_BASE (uint16_t)0x5075 02774 #define DMA1_Channel1_BASE (uint16_t)0x507F 02775 #define DMA1_Channel2_BASE (uint16_t)0x5089 02776 #define DMA1_Channel3_BASE (uint16_t)0x5093 02777 #define SYSCFG_BASE (uint16_t)0x509D 02778 #define EXTI_BASE (uint16_t)0x50A0 02779 #define WFE_BASE (uint16_t)0x50A6 02780 #define RST_BASE (uint16_t)0x50B0 02781 #define PWR_BASE (uint16_t)0x50B2 02782 #define CLK_BASE (uint16_t)0x50C0 02783 #define WWDG_BASE (uint16_t)0x50D3 02784 #define IWDG_BASE (uint16_t)0x50E0 02785 #define BEEP_BASE (uint16_t)0x50F0 02786 #define RTC_BASE (uint16_t)0x5140 02787 #define CSSLSE_BASE (uint16_t)0x5190 02788 #define SPI1_BASE (uint16_t)0x5200 02789 #define SPI2_BASE (uint16_t)0x53C0 02790 #define I2C1_BASE (uint16_t)0x5210 02791 #define USART1_BASE (uint16_t)0x5230 02792 #define USART2_BASE (uint16_t)0x53E0 02793 #define USART3_BASE (uint16_t)0x53F0 02794 #define TIM2_BASE (uint16_t)0x5250 02795 #define TIM3_BASE (uint16_t)0x5280 02796 #define TIM1_BASE (uint16_t)0x52B0 02797 #define TIM4_BASE (uint16_t)0x52E0 02798 #define IRTIM_BASE (uint16_t)0x52FF 02799 #define TIM5_BASE (uint16_t)0x5300 02800 #define ADC1_BASE (uint16_t)0x5340 02801 #define DAC_BASE (uint16_t)0x5380 02802 #define AES_BASE (uint16_t)0x53D0 02803 #define LCD_BASE (uint16_t)0x5400 02804 #define RI_BASE (uint16_t)0x5430 02805 #define COMP_BASE (uint16_t)0x5440 02806 #define CFG_BASE (uint16_t)0x7F60 02807 #define ITC_BASE (uint16_t)0x7F70 02808 #define DM_BASE (uint16_t)0x7F90 02809 02810 /******************************************************************************/ 02811 /* Peripherals declarations */ 02812 /******************************************************************************/ 02813 02814 02815 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) 02816 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) 02817 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) 02818 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) 02819 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) 02820 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) 02821 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) 02822 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) 02823 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) 02824 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) 02825 #define RTC ((RTC_TypeDef *) RTC_BASE) 02826 #define FLASH ((FLASH_TypeDef *) FLASH_BASE) 02827 #define EXTI ((EXTI_TypeDef *) EXTI_BASE) 02828 #define RST ((RST_TypeDef *) RST_BASE) 02829 #define PWR ((PWR_TypeDef *) PWR_BASE) 02830 #define CLK ((CLK_TypeDef *) CLK_BASE) 02831 #define CSSLSE ((CSSLSE_TypeDef *) CSSLSE_BASE) 02832 #define WWDG ((WWDG_TypeDef *) WWDG_BASE) 02833 #define IWDG ((IWDG_TypeDef *) IWDG_BASE) 02834 #define WFE ((WFE_TypeDef *) WFE_BASE) 02835 #define BEEP ((BEEP_TypeDef *) BEEP_BASE) 02836 #define SPI1 ((SPI_TypeDef *) SPI1_BASE) 02837 #define SPI2 ((SPI_TypeDef *) SPI2_BASE) 02838 #define I2C1 ((I2C_TypeDef *) I2C1_BASE) 02839 #define USART1 ((USART_TypeDef *) USART1_BASE) 02840 #define USART2 ((USART_TypeDef *) USART2_BASE) 02841 #define USART3 ((USART_TypeDef *) USART3_BASE) 02842 #define LCD ((LCD_TypeDef *) LCD_BASE) 02843 #define TIM1 ((TIM1_TypeDef *) TIM1_BASE) 02844 #define TIM2 ((TIM_TypeDef *) TIM2_BASE) 02845 #define TIM3 ((TIM_TypeDef *) TIM3_BASE) 02846 #define TIM4 ((TIM4_TypeDef *) TIM4_BASE) 02847 #define TIM5 ((TIM_TypeDef *) TIM5_BASE) 02848 #define IRTIM ((IRTIM_TypeDef *) IRTIM_BASE) 02849 #define ITC ((ITC_TypeDef *) ITC_BASE) 02850 #define DAC ((DAC_TypeDef *) DAC_BASE) 02851 #define DMA1 ((DMA_TypeDef *) DMA1_BASE) 02852 #define DMA1_Channel0 ((DMA_Channel_TypeDef *) DMA1_Channel0_BASE) 02853 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) 02854 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) 02855 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) 02856 #define DM ((DM_TypeDef *) DM_BASE) 02857 #define RI ((RI_TypeDef *) RI_BASE) 02858 #define COMP ((COMP_TypeDef *) COMP_BASE) 02859 #define AES ((AES_TypeDef *) AES_BASE) 02860 #define ADC1 ((ADC_TypeDef *) ADC1_BASE) 02861 #define CFG ((CFG_TypeDef *) CFG_BASE) 02862 #define OPT ((OPT_TypeDef *) OPT_BASE) 02863 02864 #ifdef USE_STDPERIPH_DRIVER 02865 #include "stm8l15x_conf.h" 02866 #endif 02867 02868 /* Exported macro --------------------------------------------------------------*/ 02869 02870 /*============================== Interrupts ====================================*/ 02871 #ifdef _RAISONANCE_ 02872 #include <intrist7.h> 02873 #define enableInterrupts() _rim_() /*!<enable interrupts */ 02874 #define disableInterrupts() _sim_() /*!<disable interrupts */ 02875 #define rim() _rim_() /*!<enable interrupts */ 02876 #define sim() _sim_() /*!<disable interrupts */ 02877 #define nop() _nop_() /*!<No Operation */ 02878 #define trap() _trap_() /*!<Trap (soft IT) */ 02879 #define wfi() _wfi_() /*!<Wait For Interrupt */ 02880 #define wfe() _wfe_() /*!<Wait For Interrupt */ 02881 #define halt() _halt_() /*!<Halt */ 02882 #elif defined(_COSMIC_) 02883 #define enableInterrupts() {_asm("rim\n");} /*!<enable interrupts */ 02884 #define disableInterrupts() {_asm("sim\n");} /*!<disable interrupts */ 02885 #define rim() {_asm("rim\n");} /*!<enable interrupts */ 02886 #define sim() {_asm("sim\n");} /*!<disable interrupts */ 02887 #define nop() {_asm("nop\n");} /*!<No Operation */ 02888 #define trap() {_asm("trap\n");} /*!<Trap (soft IT) */ 02889 #define wfi() {_asm("wfi\n");} /*!<Wait For Interrupt */ 02890 #define wfe() {_asm("wfe\n");} /*!<Wait for event */ 02891 #define halt() {_asm("halt\n");} /*!<Halt */ 02892 #else /*_IAR*/ 02893 #include <intrinsics.h> 02894 #define enableInterrupts() __enable_interrupt() /* enable interrupts */ 02895 #define disableInterrupts() __disable_interrupt() /* disable interrupts */ 02896 #define rim() __enable_interrupt() /* enable interrupts */ 02897 #define sim() __disable_interrupt() /* disable interrupts */ 02898 #define nop() __no_operation() /* No Operation */ 02899 #define trap() __trap() /* Trap (soft IT) */ 02900 #define wfi() __wait_for_interrupt() /* Wait For Interrupt */ 02901 #define wfe() __wait_for_event(); /* Wait for event */ 02902 #define halt() __halt() /* Halt */ 02903 #endif /* _RAISONANCE_ */ 02904 02905 /*============================== Interrupt vector Handling ========================*/ 02906 02907 #ifdef _COSMIC_ 02908 #define INTERRUPT_HANDLER(a,b) @far @interrupt void a(void) 02909 #define INTERRUPT_HANDLER_TRAP(a) void @far @interrupt a(void) 02910 #endif /* _COSMIC_ */ 02911 02912 #ifdef _RAISONANCE_ 02913 #define INTERRUPT_HANDLER(a,b) void a(void) interrupt b 02914 #define INTERRUPT_HANDLER_TRAP(a) void a(void) trap 02915 #endif /* _RAISONANCE_ */ 02916 02917 #ifdef _IAR_ 02918 #define STRINGVECTOR(x) #x 02919 #define VECTOR_ID(x) STRINGVECTOR( vector = (x) ) 02920 #define INTERRUPT_HANDLER( a, b ) \ 02921 _Pragma( VECTOR_ID( (b)+2 ) ) \ 02922 __interrupt void (a)( void ) 02923 #define INTERRUPT_HANDLER_TRAP(a) \ 02924 _Pragma( VECTOR_ID( 1 ) ) \ 02925 __interrupt void (a) (void) 02926 #endif /* _IAR_ */ 02927 02928 /*============================== Interrupt Handler declaration ========================*/ 02929 #ifdef _COSMIC_ 02930 #define INTERRUPT @far @interrupt 02931 #elif defined(_IAR_) 02932 #define INTERRUPT __interrupt 02933 #endif /* _COSMIC_ */ 02934 02935 /*============================== Handling bits ====================================*/ 02936 /*----------------------------------------------------------------------------- 02937 Method : I 02938 Description : Handle the bit from the character variables. 02939 Comments : The different parameters of commands are 02940 - VAR : Name of the character variable where the bit is located. 02941 - Place : Bit position in the variable (7 6 5 4 3 2 1 0) 02942 - Value : Can be 0 (reset bit) or not 0 (set bit) 02943 The "MskBit" command allows to select some bits in a source 02944 variables and copy it in a destination var (return the value). 02945 The "ValBit" command returns the value of a bit in a char 02946 variable: the bit is reseted if it returns 0 else the bit is set. 02947 This method generates not an optimised code yet. 02948 -----------------------------------------------------------------------------*/ 02949 #define SetBit(VAR,Place) ( (VAR) |= (uint8_t)((uint8_t)1<<(uint8_t)(Place)) ) 02950 #define ClrBit(VAR,Place) ( (VAR) &= (uint8_t)((uint8_t)((uint8_t)1<<(uint8_t)(Place))^(uint8_t)255) ) 02951 02952 #define ChgBit(VAR,Place) ( (VAR) ^= (uint8_t)((uint8_t)1<<(uint8_t)(Place)) ) 02953 #define AffBit(VAR,Place,Value) ((Value) ? \ 02954 ((VAR) |= ((uint8_t)1<<(Place))) : \ 02955 ((VAR) &= (((uint8_t)1<<(Place))^(uint8_t)255))) 02956 #define MskBit(Dest,Msk,Src) ( (Dest) = ((Msk) & (Src)) | ((~(Msk)) & (Dest)) ) 02957 02958 #define ValBit(VAR,Place) ((uint8_t)(VAR) & (uint8_t)((uint8_t)1<<(uint8_t)(Place))) 02959 02960 #define BYTE_0(n) ((uint8_t)((n) & (uint8_t)0xFF)) /*!< Returns the low byte of the 32-bit value */ 02961 #define BYTE_1(n) ((uint8_t)(BYTE_0((n) >> (uint8_t)8))) /*!< Returns the second byte of the 32-bit value */ 02962 #define BYTE_2(n) ((uint8_t)(BYTE_0((n) >> (uint8_t)16))) /*!< Returns the third byte of the 32-bit value */ 02963 #define BYTE_3(n) ((uint8_t)(BYTE_0((n) >> (uint8_t)24))) /*!< Returns the high byte of the 32-bit value */ 02964 02965 /*============================== Assert Macros ====================================*/ 02966 #define IS_STATE_VALUE(STATE) \ 02967 (((STATE) == SET) || \ 02968 ((STATE) == RESET)) 02969 02970 /*----------------------------------------------------------------------------- 02971 Method : II 02972 Description : Handle directly the bit. 02973 Comments : The idea is to handle directly with the bit name. For that, it is 02974 necessary to have RAM area descriptions (example: HW register...) 02975 and the following command line for each area. 02976 This method generates the most optimized code. 02977 -----------------------------------------------------------------------------*/ 02978 02979 #define AREA 0x00 /* The area of bits begins at address 0x10. */ 02980 02981 #define BitClr(BIT) ( *((unsigned char *) (AREA+(BIT)/8)) &= (~(1<<(7-(BIT)%8))) ) 02982 #define BitSet(BIT) ( *((unsigned char *) (AREA+(BIT)/8)) |= (1<<(7-(BIT)%8)) ) 02983 #define BitVal(BIT) ( *((unsigned char *) (AREA+(BIT)/8)) & (1<<(7-(BIT)%8)) ) 02984 02985 02986 #endif /* __STM8L15x_H */ 02987 02988 /** 02989 * @} 02990 */ 02991 02992 /** 02993 * @} 02994 */ 02995 02996 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/