Timing Configurations

NI RF Signal Generator

Timing Configurations

The timebases of both RF signal generator hardware modules (the AWG module and the upconverter module) must be frequency-locked to a common 10 MHz reference clock. The following clock sources are available:

10 MHz NI 5610 upconverter module Onboard Reference Clock
10 MHz External Reference Clock (connected to NI 5610 front panel REF IN connector)
PXI 10 MHz backplane clock

The NI 5610 onboard frequency reference (a very accurate and stable OCXO) can drive the 10 MHz PXI backplane clock only if the upconverter module is installed in Slot 2 of a PXI chassis. The NI 5610 cannot drive the 10 MHz PXI backplane clock in a PXI Express chassis. When the NI 5610 is installed in PXI Slot 2 of a PXI chassis, you can configure it to drive the 10 MHz PXI backplane clock with the NI 5610 onboard frequency reference or with an external frequency source connected to the REF IN front panel connector on the NI 5610 module.

Available timing configurations are shown in the following table.

Timing Configuration	NI 5610 PXI Slot Location	Compatible Chassis	Module Front Panel Connections	Configuration Instructions
AWG module locked to upconverter module onboard OCXO, 10 MHz PXI backplane clock independent (default configuration)	Any PXI slot	PXI/PXIe	Connect the TO AWG CLK IN front panel connector on the upconverter module to the CLK IN front panel connector on the AWG module.	Set the Reference Clock Source property to OnBoardClock or the NIRFSG_ATTR_REF_CLOCK_SOURCE attribute to NIRFSG_VAL_ONBOARD_CLOCK_STR. Set the PXI Chassis Clk 10 Source property to None or the NIRFSG_ATTR_PXI_CHASSIS_CLK10_SOURCE attribute to NIRFSG_VAL_NONE_STR.
AWG module locked to upconverter module onboard OCXO, 10 MHz PXI backplane clock locked to upconverter module onboard OCXO	PXI Slot 2 only	PXI	Connect the TO AWG CLK IN front panel connector on the upconverter module to the CLK IN front panel connector on the AWG module.	Set the Reference Clock Source property to OnBoardClock or the NIRFSG_ATTR_REF_CLOCK_SOURCE attribute to NIRFSG_VAL_ONBOARD_CLOCK_STR. Set the PXI Chassis Clk 10 Source property to OnBoardClock or the NIRFSG_ATTR_PXI_CHASSIS_CLK10_SOURCE attribute to NIRFSG_VAL_ONBOARD_CLOCK_STR.
Upconverter module and AWG module locked to external reference, 10 MHz PXI backplane clock independent	Any PXI slot	PXI/PXIe	Connect the TO AWG CLK IN front panel connector on the upconverter module to the CLK IN front panel connector on the AWG module; connect the external reference signal to the upconverter module REF IN front panel connector	Set the Reference Clock Source property to RefIn or the NIRFSG_ATTR_REF_CLOCK_SOURCE attribute to NIRFSG_VAL_REF_IN_STR. Set the PXI Chassis Clk 10 Source property to None or the NIRFSG_ATTR_PXI_CHASSIS_CLK10_SOURCE attribute to NIRFSG_VAL_NONE_STR.
Upconverter module and AWG module locked to external reference, 10 MHz PXI backplane clock locked to external reference	PXI Slot 2 only	PXI	Connect the TO AWG CLK IN front panel connector on the upconverter to the CLK IN front panel connector on the AWG module; connect the external reference signal to the upconverter module REF IN connector front panel.	Set the Reference Clock Source property to RefIn or the NIRFSG_ATTR_REF_CLOCK_SOURCE attribute to NIRFSG_VAL_REF_IN_STR. Set the PXI Chassis Clk 10 Source property to RefIn or the NIRFSG_ATTR_PXI_CHASSIS_CLK10_SOURCE attribute to NIRFSG_VAL_REF_IN_STR.
RF signal generator locked to 10 MHz PXI backplane clock*	Any PXI slot	PXI/PXIe	No front panel connections are required	Set the Reference Clock Source property to PXI_CLK10 or the NIRFSG_ATTR_REF_CLOCK_SOURCE attribute to NIRFSG_VAL_PXI_CLK10_STR. Set the PXI Chassis Clk 10 Source property to None or the NIRFSG_ATTR_PXI_CHASSIS_CLK10_SOURCE attribute to NIRFSG_VAL_NONE_STR.
AWG module sampled externally using the external sample clock	Any PXI slot	PXI/PXIe	Connect the TO AWG CLK IN front panel connector on the upconverter module to the external clock source on the NI 5650/5651/5652 module; connect the external reference clock source to the CLK IN front panel connector on the AWG module.	Set the Arb Sample Clock Source property to ClkIn or the NIRFSG_ATTR_ARB_SAMPLE_CLOCK_SOURCE attribute to NIRFSG_VAL_CLK_IN_STR.
*The onboard reference of the NI 5610 upconverter module offers frequency stability and phase noise that are far superior to the frequency reference built into most PXI chassis. Do not lock to the 10 MHz PXI backplane clock unless the backplane clock is driven by a high-accuracy reference (built-in or installed in PXI Slot 2).

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