By Nir Adar, Rotem Grosman -

VAX11

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The Basic structure of VAX-11 Computer

 

 

This section will describe the different parts of the computer.

 

The memory system

 

The memory contains programs and data. In the original VAX11, the cache memory is used to speed-up the access time to the memory.

From the user’s point of view, VAX-11 memory is consecutive.

The addresses of the VAX-11 are 32 bit addresses; therefore each program can use up to 4096MB of memory space.

 

Central Processing Unit (CPU)

 

The VAX-11 ALU supports the basic math operations (+, -, *, /) for integers only.

It also supports logic operations: shift, rotate, and, or and not.

 

The control unit reads commands from the memory and executing it.

PC, the Program Counter, contains the address of the next command to be executed.

The value of the PC is advanced during the decoding of the opcode and the operands.

 

 

Processor Status Word (PSW)

 

The Processor Status Word (the lower word of the Processor Status Longword) is a special processor register that a program uses to check its status and to control synchronous error conditions. The Processor Status Word contains two sets of bit fields:

  1. The condition codes.
  2. The trap enabled flag.

 

The condition codes indicate the outcome of a particular logical or arithmetic operation.

There are two kinds of traps that concern the user process: trace traps and arithmetic traps. The trace trap is used by debugging programs or performance evaluators. Arithmetic traps include:

  • Integer, floating point, or decimal string overflow, in which the result was too large to be stored in the given format.
  • Integer, floating point, or decimal string divide by zero, in which the divisor supplied was zero.

 

Processor Status Longword (PSL)

 

There are a number of processor state variables associated with each process, which VAX-11 groups together into the 32-bit Processor Status Longword. Bit 15-0 of the PSL are referred to separately as Processor Status Word (PSW). The PSW contains unprivileged information, and those bits of the PSW which have defined meaning are freely controllable by any program. Bits 31-15 of the PSL contain privileged status, and while any program can perform the REI instruction (which loads PSL), REI will refuse to load any PSL which increase the privileged of a process, or create an undefined state in the processor.

 

31

30

29                            21

20            16

15                            8

7

6

5

4

3

2

1

0

CM

TP

Others

IPL

Unused

DV

FU

IV

T

N

Z

V

C

 

The PSL

 

Bits 3:0 of the PSL are termed the condition codes; in general they reflect the result status of the most recent instruction which affects them. The condition codes are tested by the conditional branch instructions.

 

  • N Bit (Negative): Bit 3 is the Negative condition code. In general it is set by instructions in which result stored is negative, and cleared by instructions in which the result is zero or positive.
  •  Z Bit (Zero): Bit 2 is the Zero condition code. In general it is set by instructions in which result stored is zero, and cleared by instructions in which the result is not zero.
  • V Bit (Overflow): Bit 1 is the Overflow condition code; In general it is set after arithmetic operations in which the magnitude of the algebraically correct result is too large to be represented in the available space, and cleared after operations whose result fits.
  • C Bit (Carry): Bit 0 is the Carry condition code; In general it is set after arithmetic operations in which a carry out of, or borrow into, the most significant bit occurred. C is cleared after arithmetic operations which had no carry or borrow, and either cleared or unaffected by other instructions.

 

Bits 7:4 of the PSL are trap-enable flags, which cause traps to occur under special circumstances.

 

  • T Bit (Trace): Bit 4 is the trace bit; when set, it causes a trace trap to occur after execution of the next instruction.
  • IV Bit (Integer Overflow): Bit 5 is the Integer overflow trap enable; when set, it causes an integer overflow trap after an instruction which produced an integer result that could not be correctly represented in the space provided. When bit 5 is clear, no integer overflow trap occurs.
  • FU bit (Floating Underflow): Bit 6 is the Floating Underflow bit. Our simulator doesn't support this bit.
  • DV Bit (Decimal Overflow): Bit 7 is the Decimal Overflow trap enable. When set, it causes a decimal overflow trap after the execution of any instruction which produces a decimal result whose absolute value is too large to be represented in the destination space provided.

 

  • IPL Bits: Bits 16-20 represent the processor's Interrupt Priority level. An interrupt, in order to be acknowledged by the processor, must be at a priority higher than the current IPL.
  • TP Bit: Bit 30 is the Trace Pending bit, which is used by the processor to ensure that one, and only one, trace trap occurs for each instruction performed with the Trace bit (bit 4) set.

 

Registers

 

A Register is special hardware within the processor that can be used for temporary data storage and addressing. Instruction operands are often stored in the processor's general registers or accessed through them.

The VAX-11 computer has 16 32-bit Registers, named r0...r15.

r0…r11 are general purpose registers, while r12…r15 are special control registers.

 

Register

Alternative Name

Description

r12

AP

Argument Pointer - contains the address of the base of a software data structure called the argument list, which is maintained for procedure calls.

r13

FP

Frame Pointer - contains the address of the base of a software data structure stored on the stack called the stack frame, which is maintained for procedure calls.

r14

SP

Stack Pointer - contains the address of the base (also called the top) of a stack maintained for subroutine and procedure calls.

r15

PC

Program Counter - contains the address of the next byte to be processed in the instruction stream.

 

Input/Output Devices

 

The simulator supports serial input / output devices.

Input:               The keyboard (KBD) or input file.

Output:            The monitor (CRT) or output file.

 

VAX-11 Information Unit

 

VAX-11 Information units are: Byte(1), Word(2), Long(4), Quad(8).

Data stored in the memory in Little-Endian – The first byte is always the LSB.

The CPU always considers the numbers as signed.

 

Instruction Format

 

The first byte denotes:

  • The operation type.
  • The number of operands and their size.

 

The following bytes of the instruction contain the operands, each of which may use a different addressing mode.

 

The VAX-11 instruction length is variable.

 

Addressing Modes

 

 

Addressing Mode

Assembly Code

Machine Implementation

1

Register

rNUMBER

50+Number

 

2

Register Deferred

(rNUMBER)

60+Number

 

3

Autoincrement

(rNUMBER)+

80+Number

 

4

Autodecrement

-(rNUMBER)

70+Number

 

5

Autoincrement Deferred

*(rNUMBER)+

90+Number

 

6a

6b

6c

Displacement

OFFSET(rNUMBER)

or

OFFSET[rNUMBER]

A0+Number

C0+Number

E0+Number

Byte Offset

Word Offset

Long Offset

7a

7b

7c

Displacement Deferred

*OFFSET(rNUMBER)

B0+Number

D0+Number

F0+Number

Byte Offset

Word Offset

Long Offset

8a

8b

8c

8d

8e

8f

Index

(rBASE)[rINDEX]

(rBASE)+[rINDEX]

-(rBASE)[rINDEX]

*(rBASE)+[rINDEX]

OFFSET(rBASE)[rINDEX]

*OFFSET(rBASE)[rINDEX]

40+Index

Depending on  the BASE addressing mode.

9

Literal

$VALUE  (<64)

00+VALUE

 

10

Immediate

$VALUE

8F

Long Number

11

Absolute

*$ADDRESS

9F

Long Address

12

Relative

ADDRESS

EF

Long Address

13

Relative Deferred

*ADDRESS

FF

Long Address

 

We can see that addressing modes 1-9 are the only real addressing modes. Addressing modes 10-13 uses the previous addressing modes to achieve some special effects using PC register.

 

To show the meaning of the different addressing modes more clearly, we put here the nine basic addressing modes, and their "equivalents" on C language:

 

 

Addressing Mode

Assembly Code

C Code

1

Register

rNUMBER

r

2

Register Deferred

(rNUMBER)

*r

3

Autoincrement

(rNUMBER)+

*(r++)

4

Autodecrement

-(rNUMBER)

*(--r)

5

Autoincrement Deferred

*(rNUMBER)+

**(r++)

6

Displacement

OFFSET(rNUMBER)

*((char*)r+OFFSET)

7

Displacement Deferred

*OFFSET(rNUMBER)

**((char*)r+OFFSET)

8

Index

(rBASE)[rINDEX]

(rBASE)+[rINDEX]

-(rBASE)[rINDEX]

*(rBASE)+[rINDEX]

OFFSET(rBASE)[rINDEX]

*OFFSET(rBASE)[rINDEX]

*(rBASE+rINDEX)

*((rBASE++)+rINDEX)

*((--rBASE)+rINDEX)

**(rBASE+rINDEX)

*((OFFSET+(char*)rBASE)+rINDEX)

*(*(OFFSET+(char*)rBASE)+rINDEX)

9

Literal

$VALUE  (<64)

VALUE

 

 

Function Calls

 

VAX-11 supplies several mechanisms for calling to functions.

 

Calling using JSB

 

Syntax: JSB <function_name>

 

Actions:

  1. Push PC
  2. Update PC to new value.

 

Remarks:

  • Returning from the function using RSB.

 

Calling using CALLS

 

Syntax: CALLS <parameters_number>, <function_name>

 

 

 

F

E

D

C

B

A

9

8

7

6

5

4

3

2

1

0

PSW

Flags: N, Z, V, C, T, More...

Misc.

SPA

S

0

Register Mask for r0-r11

 

S is 1 for calls.

 

Actions:

0.    Caller Pushes parameters.

1.    Push parameters number (N). Max: 255

2.    The 2 lsb bits of SP goes to SPA. Also tempßsp

3.    Using SPA, we decide to fill 0-3 bytes, to align the stack.

4.    Pushing r0-r11 according to the mask.

5.    Pushing pc, fp, ap (Returning Address).

6.    Resetting PSW Flags.

7.    Push PSW+Misc.

8.    Push 0 to mark the frame's end.

9.    FPßSP, APßtemp

10. PCßFunction Address + 2

0

ßsp(r14), fp(r13)

Misc.

PSW

 

ap(r12)

 

fp(r13)

 

pc(r15)

 

r0

 

r1

 

...

 

r11

 

Fill (0-3 bytes, according to SPA)

 

ßap(r12)

0

0

0

N

 

arg1

Parameters

List

arg2

 

...

 

argN

 

…

 

 

 

 

Calling using CALLG

 

Syntax: CALLG <global_section>, <function name>

 

·        Uses global section to pass parameters.

·        The global section should be similar to the one in the CALLS

0

0

0

N

arg1

arg2

...

argN

Stack structure after CALLG:

 

 

F

E

D

C

B

A

9

8

7

6

5

4

3

2

1

0

PSW

Flags: N, Z, V, C, T, More...

Misc.

SPA

S

0

Register Mask for r0-r11

 

S is 0 for callg.

 

Actions:

0.    Preparing parameters list on the global memory.

1.    Including parameters number (N). Max: 255

2.    The 2 lsb bits of SP goes to SPA.

3.    Using SPA, we decide to fill 0-3 bytes, to align the stack.

4.    Pushing r0-r11 according to the mask.

5.    Pushing pc, fp, ap (Returning Address).

6.    Resetting PSW Flags.

7.    Push PSW+Misc.

8.    Push 0 to mark the frame's end.

9.    FPßSP, APßglobal section address.

10. PCßFunction Address + 2

0

 

Misc.

PSW

 

ap(r12)

 

fp(r13)

 

pc(r15)

 

r0

 

r1

 

...

 

r11

 

Fill (0-3 bytes, according to SPA)

 

 

 

 

 

  • callg doesn’t fit for recursive functions.
  • Can be used for RPC (Remote Procedure Call) - Function that is called by another process.

 

 

Returning from function using RET

 

1.    spßfp+4

2.    tempßMisc. + PSW

3.    Restoring the pc, fp, ap registers.

4.    Restoring r0-r11 according to the mask.

5.    Restoring SP using SPA from temp.

6.    Restoring PSW from temp.

7.    Skipping the fill using SPA.

8.    If S = 1, then read N and jump over the parameters. (Assuming each parameter is exact one longword).

 

 

Local Variables

 

We can allocate space for N local variables using: "subl2 $N, sp".

We can use the variables using negative offset from fp:

  • -4(fp) for the first word.
  • -8(fp) for the second word.
  • etc...

 

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