ADWC

Purpose

perform extended-precision addition

Format

opcode add.rl, sum.ml

Operation

sum ß sum + add + C;

Condition codes

N ß sum LSS 0;

Z ß sum EQL 0;

V ß {integer overlow};

C ß {carry from most significant bit};

Exceptions

Integer overflow

Opcodes

D8       ADWC                                    Add with Carry

Description

The contents of the condition code C bit and the addend operand are added to the sum operand and the sum operand is replaced by the result.

Notes

1.         On overflow, the sum operand is replaced by the low order bits of the results.

2.         The two additions in the operation are performed simultaneously.