BB BRANCH ON BIT
|
Purpose |
test selected bit |
|
Format |
opcode pos.rl, base.vb, displ.bb |
|
Operation |
teststate = if {BBS} then 1 else 0; if FIELD (pos, 1, base) EQL teststate then PC ß PC + SEXT (displ); |
|
Condition codes |
N ß N; Z ß Z; V ß V; C ß C; |
|
Exceptions |
reserved operand |
|
Opcodes |
E0 BBS Branch on Bit Set El BBC Branch on Bit Clear |
|
Description |
The single bit field specified by the position and base operands is tested. If it is in the test state indicated by the instruction, the sign-extended branch displacement is added to PC and PC is replaced by the result. |
|
Notes |
1. A reserved operand fault occurs if pos GTRU 31 and the bit is contained in a register. 2. On a reserved operand fault, the condition codes are unpredictable. 3. The modification of the bit is not an interlocked operation. See BBSSII and BBCCI for interlocking instructions. |
Example 1
.text
main: .word 0
movb $0x80, r1
bbs $7, r1, prn_true
calls $0, prn_false
jmp end_prog
eq2: calls $0, prn_false
end_prog:
pushl $0
calls $1, .exit
prn_false: .word 0
pushal lbl_false
pushal format
calls $2, .printf
ret
prn_true:
pushal lbl_true
pushal format
calls $2, .printf
jmp end_prog
.data
lbl_true: .asciz "True"
lbl_false: .asciz "False"
format: .asciz "%s\n"
BB BRANCH ON BIT (AND MODIFY WITHOUT INTERLOCKED)
|
Purpose |
test and modify selected bit |
|
Format |
opcode pos.rl, base.vb, displ.bb |
|
Operation |
teststate = if {BBSS or BBSC} then 1 else 0; newstate = if {BBSS or BBCS} then 1 else 0; temp ß FIELD (pos, 1, base); FIELD (pos, 1, base) ß newstate; if tmp EQL teststate then PC ß PC + SEXT (displ); |
|
Condition codes |
N ß N: Z ß Z; V ß V; C ß C; |
|
Exceptions |
reserved operand |
|
Opcodes |
E2 BBSS Branch on Bit Set and Set E3 BBCS Branch on Bit Clear and Set E4 BBSC Branch on Bit Set and Clear E5 BBCC Branch on Bit Clear and Clear |
|
Description |
The single bit field specified by the position and base operands is tested. If it is in the test state indicated by the instruction, the sign-extended branch displacement is added to PC and PC is replaced by the result. Regardless of whether the branch is taken or not, the tested bit is put in the new state as indicated by the instruction. |
|
Notes |
1. A reserved operand fault occurs if 0 BTRU 31 and the bit is contained in a register. 2. On a reserved operand fault, the field is unaffected and the condition codes are unpredictable. 3. The modification of the bit is not an interlocked operation. See BBSSI and BBCCI for interlocking instructions. |
BB BRANCH ON BIT INTERLOCKED
|
Purpose |
test and modify selected bit under memory interlock |
|
Format |
opcode pos.rl, base.vb, displ.bb |
|
Operation |
teststate = if {BBSSI} the 1 else 0; newstafe = teststate; {set interlock}; temp ß FIELD (pos, 1, base); FIELD (pos, 1, base) ß newstate; {release interlock}; if tmp EQL teststate then PC ß PC + SEXT (displ); |
|
Condition codes |
N ß N; Z ß Z; V ß V; C ß C; |
|
Exceptions |
reserved operand |
|
Opcodes |
E6 BBSSI Branch on Bit Set and Set Interlocked E7 BBCCI Branch on Bit Clear and Clear Interlocked |
|
Description |
The single bit field specified by the position and base operands is tested. If it is in the test state indicated by the instruction, the sign-extended branch displacement is added to the PC and PC is replaced by the result. Regardless of whether the branch is effected or not, the tested bit is put in the new state as indicated by the instruction. If the bit is contained in memory, the reading of the state of the bit and the setting of it to the new state is an interlocked operation. The operation is interlocked against similar operations by other processors or devices in the system. |
|
Notes |
1. A reserved operand fault occurs if pos GTRU 31 and the bit is contained in registers. 2. On a reserved operand fault, the field is unaffected and the condition codes are unpredictable. 3. Except for memory interlocking BBSSI is equivalent to BBSS and BBCCI is equivalent to BBCC. |