BISPSW

Purpose

set or clear trap enables

Format

opcode mask.rw

Operation

PSW ß PSW OR mask;                                             BISPSW

PSW ß PSW AND {NOT mask};                             BICPSW

Condition codes

N ß N OR mask <3>;                                                BISPSW

Z ß Z OR mask <2>;

V ß V OR mask <1>;

C ß C OR mask <0>;

N ß N AND {NOT mask} <3>;                                BICPSW

Z ß Z AND {NOT mask} <2>;

V ß VAND {NOT mask} <1>;

C ß C AND {NOT mask} <0>;

Exceptions

Reserved Operand

Opcodes

B8        BISPSW          Bit set PSW

B9        BICPSW         Bit clear PSW

Description

On BISPSW, the processor status longword is ORed with the 16-bit mask operand and the PSW is replaced by the result. On BICPSW, the processor status longword is ANDed with the l’s complement of the 16-bit mask operand and the PSW is replaced by the result.

Notes

A reserved operand fault occurs if mask <15:8> is not zero. On a reserved operand fault, the PSW is not affected.