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STM8L15x Standard Peripherals Drivers
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stm8l15x_dma.c
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00001 /** 00002 ****************************************************************************** 00003 * @file stm8l15x_dma.c 00004 * @author MCD Application Team 00005 * @version V1.5.0 00006 * @date 13-May-2011 00007 * @brief This file provides all the DMA firmware functions. 00008 * @brief This file provides firmware functions to manage the following 00009 * functionalities of the Direct Memory Access controller (DMA): 00010 * - Initialization and Configuration 00011 * - Data Counter 00012 * - Interrupts and flags management 00013 * 00014 * @verbatim 00015 * 00016 * =================================================================== 00017 * How to use this driver 00018 * =================================================================== 00019 * 1. Enable The DMA controller clock using CLK_PeripheralClockConfig() 00020 * function: CLK_PeripheralClockConfig(CLK_Peripheral_DMA1, ENABLE). 00021 * 00022 * 2. Enable and configure the peripheral to be connected to the DMA 00023 * channel (except for internal SRAM / FLASH memories: no 00024 * initialization is necessary). 00025 * 00026 * 3. For a given Channel, program the Source and Destination 00027 * addresses, the transfer Direction, the Buffer Size, the 00028 * Peripheral and Memory Incrementation mode and Data Size, 00029 * the Circular or Normal mode, the channel transfer Priority 00030 * and the Memory-to-Memory transfer mode (for channel 3 only, 00031 * if needed) using the DMA_Init() function. 00032 * 00033 * 4. Enable the the corresponding interrupt(s) using the function 00034 * DMA_ITConfig() if you need to use DMA interrupts. 00035 * 00036 * 5. Enable the DMA channel using the DMA_Cmd() function. 00037 * 00038 * 6. Activate the needed channel Request using PPP_DMACmd() function 00039 * for any PPP peripheral except internal SRAM and FLASH (ie. TIM4, 00040 * USART ...). The function allowing this operation is provided in 00041 * each PPP peripheral driver (ie. TIM4_DMACmd for TIM4 peripheral). 00042 * 00043 * 7. Optionally, you can configure the number of data to be 00044 * transferred when the channel is disabled (ie. after each 00045 * Transfer Complete event or when a Transfer Error occurs) using 00046 * the function DMA_SetCurrDataCounter(). 00047 * And you can get the number of remaining data to be transferred 00048 * using the function DMA_GetCurrDataCounter() at run time (when 00049 * the DMA channel is enabled and running). 00050 * 00051 * 8. To control DMA events you can use one of the following 00052 * two methods: 00053 * a- Check on DMA channel flags using the function 00054 * DMA_GetFlagStatus(). 00055 * b- Use DMA interrupts through the function DMA_ITConfig() 00056 * at initialization phase and DMA_GetITStatus() function 00057 * into interrupt routines in communication phase. 00058 * After checking on a flag you should clear it using 00059 * DMA_ClearFlag() function. And after checking on an interrupt 00060 * event you should clear it using DMA_ClearITPendingBit() 00061 * function. 00062 * 00063 * @endverbatim 00064 * 00065 ****************************************************************************** 00066 * @attention 00067 * 00068 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 00069 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 00070 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 00071 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 00072 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 00073 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 00074 * 00075 * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> 00076 ****************************************************************************** 00077 */ 00078 00079 /* Includes ------------------------------------------------------------------*/ 00080 #include "stm8l15x_dma.h" 00081 00082 /** @addtogroup STM8L15x_StdPeriph_Driver 00083 * @{ 00084 */ 00085 00086 /** @defgroup DMA 00087 * @brief DMA driver modules 00088 * @{ 00089 */ 00090 /* Private typedef -----------------------------------------------------------*/ 00091 /* Private define ------------------------------------------------------------*/ 00092 /* Private macro -------------------------------------------------------------*/ 00093 /* Private variables ---------------------------------------------------------*/ 00094 /* Private function prototypes -----------------------------------------------*/ 00095 /* Private functions ---------------------------------------------------------*/ 00096 00097 /** @defgroup DMA_Private_Functions 00098 * @{ 00099 */ 00100 00101 /** @defgroup DMA_Group1 Initialization and Configuration functions 00102 * @brief Initialization and Configuration functions 00103 * 00104 @verbatim 00105 =============================================================================== 00106 Initialization and Configuration functions 00107 =============================================================================== 00108 00109 This subsection provides functions allowing to initialize the DMA channel 00110 source and destination addresses, incrementation and data sizes, transfer 00111 direction, buffer size, circular/normal mode selection, memory-to-memory mode 00112 selection and channel priority value. 00113 00114 - The DMA_Init() function follows the DMA configuration procedures. 00115 - All DMA channels can be enabled and disabled in the same time using 00116 DMA_GlobalCmd() function. 00117 - The DMA has 4 channels, User can enable or disable channels using 00118 DMA_Cmd() function. 00119 - The timeout duration (number of wait cycles starting from the latest 00120 request) is configured using DMA_SetTimeOut() function. The DMA then waits 00121 until this timeout has elapsed before requesting from the core a high 00122 priority access to the bus. 00123 00124 @endverbatim 00125 * @{ 00126 */ 00127 00128 /** 00129 * @brief Deinitializes the DMA Global Status register to its default reset 00130 * values. 00131 * @param None 00132 * @retval None 00133 */ 00134 void DMA_GlobalDeInit(void) 00135 { 00136 /* Disable the DMA */ 00137 DMA1->GCSR &= (uint8_t)~(DMA_GCSR_GE); 00138 00139 /* Reset DMA Channelx control register */ 00140 DMA1->GCSR = (uint8_t)DMA_GCSR_RESET_VALUE; 00141 } 00142 00143 /** 00144 * @brief Deinitializes the DMA Channelx registers to their default reset 00145 * values. 00146 * @param DMA_Channelx: selects the DMA Channelx where x can be 0 to 3 00147 * @retval None 00148 */ 00149 void DMA_DeInit(DMA_Channel_TypeDef* DMA_Channelx) 00150 { 00151 /* Check the parameters */ 00152 assert_param(IS_DMA_CHANNEL(DMA_Channelx)); 00153 00154 /* Disable the selected DMA Channelx */ 00155 DMA_Channelx->CCR &= (uint8_t)~(DMA_CCR_CE); 00156 00157 /* Reset DMA Channelx control register */ 00158 DMA_Channelx->CCR = DMA_CCR_RESET_VALUE; 00159 00160 /* Reset DMA Channelx remaining bytes register */ 00161 DMA_Channelx->CNBTR = DMA_CNBTR_RESET_VALUE; 00162 00163 /* Reset DMA Channelx peripheral address register */ 00164 if (DMA_Channelx == DMA1_Channel3) 00165 { 00166 DMA_Channelx->CPARH = DMA_C3PARH_RESET_VALUE; 00167 DMA_Channelx->CM0EAR = DMA_C3M0EAR_RESET_VALUE; 00168 } 00169 else 00170 { 00171 DMA_Channelx->CPARH = DMA_CPARH_RESET_VALUE; 00172 } 00173 DMA_Channelx->CPARL = DMA_CPARL_RESET_VALUE; 00174 00175 /* Reset DMA Channelx memory address register */ 00176 DMA_Channelx->CM0ARH = DMA_CM0ARH_RESET_VALUE; 00177 DMA_Channelx->CM0ARL = DMA_CM0ARL_RESET_VALUE; 00178 00179 /* Reset interrupt pending bits for DMA Channel */ 00180 DMA_Channelx->CSPR = DMA_CSPR_RESET_VALUE; 00181 } 00182 00183 00184 /** 00185 * @brief Initializes the DMA Channelx according to the specified parameters. 00186 * @param DMA_Channelx: selects the DMA Channelx where x can be 0 to 3 00187 * @param DMA_Memory0BaseAddr: Specifies Memory 0 Base Address 00188 * @param DMA_PeripheralMemory1BaseAddr: Specifies DMA channelx Peripheral 00189 * Base Address (if data is from/to peripheral) or DMA channelx 00190 * Memory1 Base Address (if data is from Memory0 to Memory1). 00191 * @param DMA_BufferSize: Specifies the size of the DMA channelx Buffer. 00192 * This parameter must be a value greater than 0. 00193 * @param DMA_DIR: Specifies the DMA Channelx transfer direction. 00194 * This parameter can be one of the following values: 00195 * @arg DMA_DIR_PeripheralToMemory: Data transfer direction is Peripheral To Memory 00196 * @arg DMA_DIR_MemoryToPeripheral: Data transfer direction is Memory To Peripheral 00197 * @arg DMA_DIR_Memory0ToMemory1: Data transfer direction is Memory0 To Memory 1 00198 * @param DMA_Mode: Specifies the DMA channelx mode. 00199 * This parameter can be one of the following values: 00200 * @arg DMA_Mode_Normal: DMA normal buffer mode 00201 * @arg DMA_Mode_Circular: DMA circular buffer mode 00202 * @param DMA_MemoryIncMode: Specifies the DMA channelx memory Incremental/Decremental mode 00203 * This parameter can be one of the following values: 00204 * @arg DMA_MemoryIncMode_Dec: DMA memory incremented mode is decremental 00205 * @arg DMA_MemoryIncMode_Inc: DMA memory incremented mode is incremental 00206 * @param DMA_Priority: Specifies the DMA channelx priority. 00207 * This parameter can be one of the following values: 00208 * @arg DMA_Priority_Low: Software Priority is Low 00209 * @arg DMA_Priority_Medium: Software Priority is Medium 00210 * @arg DMA_Priority_High: Software Priority is High 00211 * @arg DMA_Priority_VeryHigh: Software Priority is Very High 00212 * @param DMA_MemoryDataSize: Specifies the DMA channelx transfer Data size 00213 * This parameter can be one of the following values: 00214 * @arg DMA_MemoryDataSize_Byte: Memory Data Size is 1 Byte 00215 * @arg DMA_MemoryDataSize_HalfWord: Memory Data Size is 2 Bytes 00216 * @retval None 00217 */ 00218 void DMA_Init(DMA_Channel_TypeDef* DMA_Channelx, 00219 uint32_t DMA_Memory0BaseAddr, 00220 uint16_t DMA_PeripheralMemory1BaseAddr, 00221 uint8_t DMA_BufferSize, 00222 DMA_DIR_TypeDef DMA_DIR, 00223 DMA_Mode_TypeDef DMA_Mode, 00224 DMA_MemoryIncMode_TypeDef DMA_MemoryIncMode, 00225 DMA_Priority_TypeDef DMA_Priority, 00226 DMA_MemoryDataSize_TypeDef DMA_MemoryDataSize ) 00227 { 00228 /* Check the parameters */ 00229 assert_param(IS_DMA_CHANNEL(DMA_Channelx)); 00230 assert_param(IS_DMA_DIR(DMA_DIR)); 00231 assert_param(IS_DMA_BUFFER_SIZE(DMA_BufferSize)); 00232 assert_param(IS_DMA_MODE(DMA_Mode)); 00233 assert_param(IS_DMA_MEMORY_INC_MODE(DMA_MemoryIncMode)); 00234 assert_param(IS_DMA_PRIORITY(DMA_Priority)); 00235 00236 /*--------------------------- DMA Channelx CCR Configuration ---------------*/ 00237 /* Disable the selected DMA Channelx */ 00238 DMA_Channelx->CCR &= (uint8_t)~(DMA_CCR_CE); 00239 00240 /* Reset DMA Channelx control register */ 00241 DMA_Channelx->CCR = DMA_CCR_RESET_VALUE; 00242 00243 /* Set DMA direction & Mode & Incremental Memory mode */ 00244 DMA_Channelx->CCR |= (uint8_t)((uint8_t)((uint8_t)DMA_DIR | \ 00245 (uint8_t)DMA_Mode) | \ 00246 (uint8_t)DMA_MemoryIncMode); 00247 00248 /*Clear old priority and memory data size option */ 00249 DMA_Channelx->CSPR &= (uint8_t)(~(uint8_t)(DMA_CSPR_PL | DMA_CSPR_16BM)); 00250 00251 /* Set old priority and memory data size option */ 00252 DMA_Channelx->CSPR |= (uint8_t)((uint8_t)DMA_Priority | \ 00253 (uint8_t)DMA_MemoryDataSize); 00254 00255 /*--------------------------- DMA Channelx CNDTR Configuration -------------*/ 00256 /* Write to DMA Channelx CNDTR */ 00257 DMA_Channelx->CNBTR = (uint8_t)DMA_BufferSize; 00258 00259 /*--------------------------- DMA Channelx CPAR Configuration --------------*/ 00260 /* Write to DMA Channelx (0, 1 or 2) Peripheral address or Write to 00261 DMA Channel 3 Memory 1 address */ 00262 DMA_Channelx->CPARH = (uint8_t)(DMA_PeripheralMemory1BaseAddr >> (uint8_t)8); 00263 DMA_Channelx->CPARL = (uint8_t)(DMA_PeripheralMemory1BaseAddr); 00264 00265 /*--------------------------- DMA Channelx CMAR Configuration --------------*/ 00266 /* Write to DMA Channelx Memory address */ 00267 if (DMA_Channelx == DMA1_Channel3) 00268 { 00269 DMA_Channelx->CM0EAR = (uint8_t)(DMA_Memory0BaseAddr >> (uint8_t)16); 00270 } 00271 DMA_Channelx->CM0ARH = (uint8_t)(DMA_Memory0BaseAddr >> (uint8_t)8); 00272 DMA_Channelx->CM0ARL = (uint8_t)(DMA_Memory0BaseAddr); 00273 00274 } 00275 00276 /** 00277 * @brief Enables or disables All the DMA. 00278 * @param NewState: new state of the DMA. This parameter can be: ENABLE 00279 * or DISABLE. 00280 * @retval None 00281 */ 00282 void DMA_GlobalCmd(FunctionalState NewState) 00283 { 00284 /* Check the parameters */ 00285 assert_param(IS_FUNCTIONAL_STATE(NewState)); 00286 00287 if (NewState != DISABLE) 00288 { 00289 /* Enable the DMA */ 00290 DMA1->GCSR |= (uint8_t)DMA_GCSR_GE; 00291 } 00292 else 00293 { 00294 /* Disable the DMA */ 00295 DMA1->GCSR &= (uint8_t)(~DMA_GCSR_GE); 00296 } 00297 } 00298 00299 /** 00300 * @brief Enables or disables the specified DMA Channelx. 00301 * @note DMA_GlobalCmd function must be called first to enable or disable 00302 * the global DMA. 00303 * @param DMA_Channelx: selects the DMA Channelx where x can be 0 to 3 00304 * @param NewState: new state of the DMA Channelx. 00305 * This parameter can be: ENABLE or DISABLE. 00306 * @retval None 00307 */ 00308 void DMA_Cmd(DMA_Channel_TypeDef* DMA_Channelx, FunctionalState NewState) 00309 { 00310 /* Check the parameters */ 00311 assert_param(IS_DMA_CHANNEL(DMA_Channelx)); 00312 assert_param(IS_FUNCTIONAL_STATE(NewState)); 00313 00314 if (NewState != DISABLE) 00315 { 00316 /* Enable the selected DMA Channelx */ 00317 DMA_Channelx->CCR |= DMA_CCR_CE; 00318 } 00319 else 00320 { 00321 /* Disable the selected DMA Channelx */ 00322 DMA_Channelx->CCR &= (uint8_t)(~DMA_CCR_CE); 00323 } 00324 } 00325 00326 /** 00327 * @brief Sets the Time out Value. 00328 * @param DMA_TimeOut: an integer from 0 to 63 00329 * @note If timeout duration >0 (number of wait cycles starting from the 00330 * latest request), the DMA waits until this timeout has elapsed before 00331 * requesting from the core a high priority access to the bus. 00332 * @note If timeout duration =0, there is no timeout and once a request is served, 00333 * the DMA immediately asks to the CPU a high priority access to the bus. 00334 * @retval None 00335 */ 00336 void DMA_SetTimeOut(uint8_t DMA_TimeOut) 00337 { 00338 /* Check the parameters */ 00339 assert_param(IS_DMA_TIMEOUT(DMA_TimeOut)); 00340 00341 /* set the time out, GB and GE must be = 0 */ 00342 DMA1->GCSR = 0; 00343 DMA1->GCSR = (uint8_t)(DMA_TimeOut << (uint8_t)2); 00344 00345 } 00346 00347 /** 00348 * @} 00349 */ 00350 00351 /** @defgroup DMA_Group2 Data Counter functions 00352 * @brief Data Counter functions 00353 * 00354 @verbatim 00355 =============================================================================== 00356 Data Counter functions 00357 =============================================================================== 00358 00359 This subsection provides functions allowing to configure and read the buffer 00360 size (number of data to be transferred). 00361 00362 The DMA data counter can be written only when the DMA channel is disabled 00363 (ie. after transfer complete event). 00364 00365 The DMA_SetCurrDataCounter() function can be used to write the Channel data 00366 counter value. 00367 00368 00369 Note: It is advised to use this function rather than DMA_Init() (DMA_BufferSize 00370 parameter) in situations where only the Data buffer needs to be reloaded. 00371 00372 The DMA data counter can be read to indicate the number of remaining transfers 00373 for the relative DMA channel. This counter is decremented at the end of each 00374 data transfer and when the transfer is complete: 00375 - If Normal mode is selected: the counter is set to 0. 00376 - If Circular mode is selected: the counter is reloaded with the initial value 00377 (configured before enabling the DMA channel) 00378 00379 The DMA_GetCurrDataCounter() function can be used to read the Channel current 00380 data counter value. 00381 00382 @endverbatim 00383 * @{ 00384 */ 00385 00386 /** 00387 * @brief Set the number of data units to transfer for DMA Channelx. 00388 * @param DMA_Channelx: selects the DMA Channelx where x can be 0 to 3 00389 * @param DataNumber: The number of data units to transfer, it can be any value 00390 * from 0 to 255 00391 * @note It is advised to use this function rather than DMA_Init() in situations 00392 * where only the Data buffer needs to be reloaded. 00393 * @retval None 00394 */ 00395 void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMA_Channelx, uint8_t DataNumber) 00396 { 00397 /* Check the parameters */ 00398 assert_param(IS_DMA_CHANNEL(DMA_Channelx)); 00399 00400 /*Set the number of data units for DMA Channelx */ 00401 DMA_Channelx->CNBTR = DataNumber; 00402 } 00403 00404 /** 00405 * @brief Returns the number of remaining data units in the current DMA Channelx transfer. 00406 * @param DMA_Channelx: selects the DMA Channelx where x can be 0 to 3 00407 * @retval The number of remaining data units in the current DMA Channelx 00408 */ 00409 uint8_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMA_Channelx) 00410 { 00411 /* Check the parameters */ 00412 assert_param(IS_DMA_CHANNEL(DMA_Channelx)); 00413 00414 /* Return the number of remaining data units for DMA Channelx */ 00415 return ((uint8_t)(DMA_Channelx->CNBTR)); 00416 } 00417 00418 /** 00419 * @} 00420 */ 00421 00422 /** @defgroup DMA_Group3 Interrupts and flags management functions 00423 * @brief Interrupts and flags management functions 00424 * 00425 @verbatim 00426 =============================================================================== 00427 Interrupts and flags management functions 00428 =============================================================================== 00429 00430 This subsection provides functions allowing to configure the DMA Interrupts 00431 sources and check or clear the flags or pending bits status. 00432 The user should identify which mode will be used in his application to manage 00433 the DMA controller events: Polling mode or Interrupt mode. 00434 00435 Polling Mode 00436 ============= 00437 Each DMA channel can be managed through 2 event Flags: 00438 (x: DMA channel number ) 00439 1. DMA1_FLAG_TCx: to indicate that a Transfer Complete event occurred 00440 2. DMA1_FLAG_HTx: to indicate that a Half-Transfer Complete event 00441 occurred 00442 00443 In this Mode it is advised to use DMA_GetFlagStatus() and DMA_ClearFlag() 00444 functions. 00445 00446 00447 Interrupt Mode 00448 =============== 00449 Each DMA channel can be managed through 2 Interrupts: 00450 00451 Interrupt Source 00452 ---------------- 00453 1. DMA_IT_TC: specifies the interrupt source for the Transfer Complete 00454 event. 00455 2. DMA_IT_HT: specifies the interrupt source for the Half-transfer 00456 Complete event. 00457 00458 In this Mode it is advised to use DMA_ITConfig(), DMA_GetITStatus() and 00459 DMA_ClearITPendingBit() functions. 00460 00461 @endverbatim 00462 * @{ 00463 */ 00464 00465 /** 00466 * @brief Enables or disables the specified DMA Channelx interrupts. 00467 * @param DMA_Channelx: selects the DMA Channelx where x can be 0 to 3 00468 * @param DMA_ITx: specifies the DMA interrupts sources to be enabled or disabled. 00469 * This parameter can be one of the following values: 00470 * @arg DMA_ITx_TC: Transaction Complete Interrupt 00471 * @arg DMA_ITx_HT: Half Transaction Interrupt 00472 * @param NewState: new state of the specified DMA interrupts. 00473 * This parameter can be: ENABLE or DISABLE. 00474 * @retval None 00475 */ 00476 void DMA_ITConfig(DMA_Channel_TypeDef* DMA_Channelx, 00477 DMA_ITx_TypeDef DMA_ITx, 00478 FunctionalState NewState) 00479 { 00480 /* Check the parameters */ 00481 assert_param(IS_DMA_CHANNEL(DMA_Channelx)); 00482 assert_param(IS_DMA_CONFIG_ITX(DMA_ITx)); 00483 assert_param(IS_FUNCTIONAL_STATE(NewState)); 00484 00485 if (NewState != DISABLE) 00486 { 00487 /* Enable the selected DMA interrupts */ 00488 DMA_Channelx->CCR |= (uint8_t)(DMA_ITx); 00489 } 00490 else 00491 { 00492 /* Disable the selected DMA interrupts */ 00493 DMA_Channelx->CCR &= (uint8_t)~(DMA_ITx); 00494 } 00495 } 00496 00497 /** 00498 * @brief Checks whether the specified DMA Channelx flag is set or not. 00499 * @param DMA_FLAG: specifies the flag to check. 00500 * This parameter can be one of the following values: 00501 * @arg DMA1_FLAG_GB: Global Busy Flag 00502 * @arg DMA1_FLAG_IFC0: Global Interrupt Flag Channel 0 00503 * @arg DMA1_FLAG_IFC1: Global Interrupt Flag Channel 1 00504 * @arg DMA1_FLAG_IFC2: Global Interrupt Flag Channel 2 00505 * @arg DMA1_FLAG_IFC3: Global Interrupt Flag Channel 3 00506 * @arg DMA1_FLAG_TC0: Transaction Complete Interrupt Flag Channel 0 00507 * @arg DMA1_FLAG_TC1: Transaction Complete Interrupt Flag Channel 1 00508 * @arg DMA1_FLAG_TC2: Transaction Complete Interrupt Flag Channel 2 00509 * @arg DMA1_FLAG_TC2: Transaction Complete Interrupt Flag Channel 3 00510 * @arg DMA1_FLAG_HT0: Half Transaction Interrupt Flag Channel 0 00511 * @arg DMA1_FLAG_HT1: Half Transaction Interrupt Flag Channel 1 00512 * @arg DMA1_FLAG_HT2: Half Transaction Interrupt Flag Channel 2 00513 * @arg DMA1_FLAG_HT3: Half Transaction Interrupt Flag Channel 3 00514 * @arg DMA1_FLAG_PEND0: DMA Request pending on Channel 0 00515 * @arg DMA1_FLAG_PEND1: DMA Request pending on Channel 1 00516 * @arg DMA1_FLAG_PEND2: DMA Request pending on Channel 2 00517 * @arg DMA1_FLAG_PEND3: DMA Request pending on Channel 3 00518 * @arg DMA1_FLAG_BUSY0: No DMA transfer on going in Channel 0 00519 * @arg DMA1_FLAG_BUSY1: No DMA transfer on going in Channel 1 00520 * @arg DMA1_FLAG_BUSY2: No DMA transfer on going in Channel 2 00521 * @arg DMA1_FLAG_BUSY3: No DMA transfer on going in Channel 3 00522 * @retval The status of DMA_FLAG (SET or RESET). 00523 */ 00524 FlagStatus DMA_GetFlagStatus(DMA_FLAG_TypeDef DMA_FLAG) 00525 { 00526 FlagStatus flagstatus = RESET; 00527 DMA_Channel_TypeDef* DMA_Channelx = DMA1_Channel0; 00528 uint8_t tmpgir1 = 0; 00529 uint8_t tmpgcsr = 0; 00530 00531 /* Check the parameters */ 00532 assert_param(IS_DMA_GET_FLAG(DMA_FLAG)); 00533 00534 /* Get flags registers values*/ 00535 tmpgcsr = DMA1->GCSR; 00536 tmpgir1 = DMA1->GIR1; 00537 00538 if (((uint16_t)DMA_FLAG & (uint16_t)0x0F00) != (uint16_t)RESET) 00539 { 00540 /* find the used DMA channel */ 00541 if (((uint16_t)DMA_FLAG & 0x0100) != (uint16_t)RESET) 00542 { 00543 DMA_Channelx = DMA1_Channel0; 00544 } 00545 else if (((uint16_t)DMA_FLAG & 0x0200) != (uint16_t)RESET) 00546 { 00547 DMA_Channelx = DMA1_Channel1; 00548 } 00549 else if (((uint16_t)DMA_FLAG & 0x0400) != (uint16_t)RESET) 00550 { 00551 DMA_Channelx = DMA1_Channel2; 00552 } 00553 else 00554 { 00555 DMA_Channelx = DMA1_Channel3; 00556 } 00557 00558 /* Get the specified DMA Channelx flag status. */ 00559 flagstatus = (FlagStatus)((uint8_t)(DMA_Channelx->CSPR) & (uint8_t)DMA_FLAG); 00560 } 00561 else if (((uint16_t)DMA_FLAG & 0x1000) != (uint16_t)RESET) 00562 { 00563 /* Get the specified DMA Channelx flag status. */ 00564 flagstatus = (FlagStatus)(tmpgir1 & (uint8_t)DMA_FLAG); 00565 } 00566 else /*if ((DMA_FLAG & DMA_FLAG_GB) != (uint16_t)RESET)*/ 00567 { 00568 /* Get the specified DMA Channelx flag status. */ 00569 flagstatus = (FlagStatus)(tmpgcsr & DMA_GCSR_GB); 00570 } 00571 00572 /* Return the specified DMA Channelx flag status. */ 00573 return (flagstatus); 00574 } 00575 00576 /** 00577 * @brief Clears the DMA Channels selected flags. 00578 * @param DMA_FLAG: specifies the flag to clear. 00579 * This parameter can be one or a combination (for the same channel)of 00580 * the following values: 00581 * @arg DMA1_FLAG_TC0: Transaction Complete Interrupt Flag Channel 0 00582 * @arg DMA1_FLAG_TC1: Transaction Complete Interrupt Flag Channel 1 00583 * @arg DMA1_FLAG_TC2: Transaction Complete Interrupt Flag Channel 2 00584 * @arg DMA1_FLAG_TC2: Transaction Complete Interrupt Flag Channel 3 00585 * @arg DMA1_FLAG_HT0: Half Transaction Interrupt Flag Channel 0 00586 * @arg DMA1_FLAG_HT1: Half Transaction Interrupt Flag Channel 1 00587 * @arg DMA1_FLAG_HT2: Half Transaction Interrupt Flag Channel 2 00588 * @arg DMA1_FLAG_HT3: Half Transaction Interrupt Flag Channel 3 00589 * @retval None 00590 */ 00591 void DMA_ClearFlag(DMA_FLAG_TypeDef DMA_FLAG) 00592 { 00593 DMA_Channel_TypeDef* DMA_Channelx = DMA1_Channel0; 00594 00595 /* Check the parameters */ 00596 assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG)); 00597 00598 /* Identify the used DMA channel */ 00599 if (((uint16_t)DMA_FLAG & (uint16_t)0x0100) != (uint16_t)RESET) 00600 { 00601 DMA_Channelx = DMA1_Channel0; 00602 } 00603 else 00604 { 00605 if (((uint16_t)DMA_FLAG & (uint16_t)0x0200) != (uint16_t)RESET) 00606 { 00607 DMA_Channelx = DMA1_Channel1; 00608 } 00609 else 00610 { 00611 if (((uint16_t)DMA_FLAG & (uint16_t)0x0400) != (uint16_t)RESET) 00612 { 00613 DMA_Channelx = DMA1_Channel2; 00614 } 00615 else 00616 { 00617 DMA_Channelx = DMA1_Channel3; 00618 } 00619 } 00620 } 00621 00622 /*Clears the DMA flags.*/ 00623 DMA_Channelx->CSPR &= (uint8_t)~(uint8_t)((uint8_t)DMA_FLAG & (uint8_t)0x06); 00624 } 00625 00626 /** 00627 * @brief Checks whether the specified DMA Channelx interrupt has occurred or not. 00628 * @param DMA_IT: specifies the DMA interrupt source to check. 00629 * This parameter can be one or a combination of the following values: 00630 * @arg DMA1_IT_TC0: Transaction Complete Interrupt Channel 0 00631 * @arg DMA1_IT_TC1: Transaction Complete Interrupt Channel 1 00632 * @arg DMA1_IT_TC2: Transaction Complete Interrupt Channel 2 00633 * @arg DMA1_IT_TC3: Transaction Complete Interrupt Channel 3 00634 * @arg DMA1_IT_HT0: Half Transaction Interrupt Channel 0 00635 * @arg DMA1_IT_HT1: Half Transaction Interrupt Channel 1 00636 * @arg DMA1_IT_HT2: Half Transaction Interrupt Channel 2 00637 * @arg DMA1_IT_HT3: Half Transaction Interrupt Channel 3 00638 * @retval ITStatus: The status of DMA_IT (SET or RESET). 00639 */ 00640 ITStatus DMA_GetITStatus(DMA_IT_TypeDef DMA_IT) 00641 { 00642 ITStatus itstatus = RESET; 00643 uint8_t tmpreg = 0; 00644 uint8_t tmp2 = 0; 00645 DMA_Channel_TypeDef* DMA_Channelx = DMA1_Channel0; 00646 00647 /* Check the parameters */ 00648 assert_param(IS_DMA_GET_IT(DMA_IT)); 00649 00650 /* Identify the used DMA channel */ 00651 if ((DMA_IT & 0x10) != (uint8_t)RESET) 00652 { 00653 DMA_Channelx = DMA1_Channel0; 00654 } 00655 else 00656 { 00657 if ((DMA_IT & 0x20) != (uint8_t)RESET) 00658 { 00659 DMA_Channelx = DMA1_Channel1; 00660 } 00661 else 00662 { 00663 if ((DMA_IT & 0x40) != (uint8_t)RESET) 00664 { 00665 DMA_Channelx = DMA1_Channel2; 00666 } 00667 else 00668 { 00669 DMA_Channelx = DMA1_Channel3; 00670 } 00671 } 00672 } 00673 /* Get the specified DMA Channelx interrupt status. */ 00674 tmpreg = DMA_Channelx->CSPR ; 00675 tmpreg &= DMA_Channelx->CCR ; 00676 tmp2 = (uint8_t)(DMA_IT & (uint8_t)(DMA_CCR_TCIE | DMA_CCR_HTIE)); 00677 itstatus = (ITStatus)((uint8_t)tmpreg & (uint8_t)tmp2); 00678 00679 /* Return the specified DMA Channelx interrupt status. */ 00680 return (itstatus); 00681 } 00682 00683 /** 00684 * @brief Clears the DMA Channelx�s interrupt pending bits. 00685 * @param DMA_IT: specifies the DMA interrupt pending bit to clear. 00686 * This parameter can be one or a combination(for the same channel)of 00687 * the following values: 00688 * @arg DMA1_IT_TC0: Transaction Complete Interrupt Channel 0 00689 * @arg DMA1_IT_TC1: Transaction Complete Interrupt Channel 1 00690 * @arg DMA1_IT_TC2: Transaction Complete Interrupt Channel 2 00691 * @arg DMA1_IT_TC3: Transaction Complete Interrupt Channel 3 00692 * @arg DMA1_IT_HT0: Half Transaction Interrupt Channel 0 00693 * @arg DMA1_IT_HT1: Half Transaction Interrupt Channel 1 00694 * @arg DMA1_IT_HT2: Half Transaction Interrupt Channel 2 00695 * @arg DMA1_IT_HT3: Half Transaction Interrupt Channel 3 00696 * @retval None 00697 */ 00698 void DMA_ClearITPendingBit(DMA_IT_TypeDef DMA_IT) 00699 { 00700 DMA_Channel_TypeDef* DMA_Channelx = DMA1_Channel0; 00701 00702 /* Check the parameters */ 00703 assert_param(IS_DMA_CLEAR_IT(DMA_IT)); 00704 /* Identify the used DMA channel */ 00705 if ((DMA_IT & 0x10) != (uint8_t)RESET) 00706 { 00707 DMA_Channelx = DMA1_Channel0; 00708 } 00709 else 00710 { 00711 if ((DMA_IT & 0x20) != (uint8_t)RESET) 00712 { 00713 DMA_Channelx = DMA1_Channel1; 00714 } 00715 else 00716 { 00717 if ((DMA_IT & 0x40) != (uint8_t)RESET) 00718 { 00719 DMA_Channelx = DMA1_Channel2; 00720 } 00721 else 00722 { 00723 DMA_Channelx = DMA1_Channel3; 00724 } 00725 } 00726 } 00727 /*Clears the DMA Channelx�s interrupt pending bits*/ 00728 DMA_Channelx->CSPR &= (uint8_t)~(uint8_t)(DMA_IT & (uint8_t)0x06); 00729 } 00730 00731 /** 00732 * @} 00733 */ 00734 00735 /** 00736 * @} 00737 */ 00738 00739 /** 00740 * @} 00741 */ 00742 00743 /** 00744 * @} 00745 */ 00746 00747 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/