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STM8L15x Standard Peripherals Drivers
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stm8l15x_dma.h
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00001 /** 00002 ****************************************************************************** 00003 * @file stm8l15x_dma.h 00004 * @author MCD Application Team 00005 * @version V1.5.0 00006 * @date 13-May-2011 00007 * @brief This file contains all the functions prototypes for the DMA 00008 * firmware library. 00009 ****************************************************************************** 00010 * @attention 00011 * 00012 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 00013 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 00014 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 00015 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 00016 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 00017 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 00018 * 00019 * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> 00020 ****************************************************************************** 00021 */ 00022 /* Define to prevent recursive inclusion -------------------------------------*/ 00023 #ifndef __STM8L15x_DMA_H 00024 #define __STM8L15x_DMA_H 00025 00026 /* Includes ------------------------------------------------------------------*/ 00027 #include "stm8l15x.h" 00028 00029 /** @addtogroup STM8L15x_StdPeriph_Driver 00030 * @{ 00031 */ 00032 00033 /** @addtogroup DMA 00034 * @{ 00035 */ 00036 00037 /* Exported types ------------------------------------------------------------*/ 00038 00039 /** @addtogroup DMA_Exported_Types 00040 * @{ 00041 */ 00042 00043 /** @defgroup DMA_Data_Transfer_Direction 00044 * @{ 00045 */ 00046 typedef enum 00047 { 00048 DMA_DIR_PeripheralToMemory = ((uint8_t)0x00), /*!< Data transfer direction is Peripheral To Memory */ 00049 DMA_DIR_MemoryToPeripheral = ((uint8_t)0x08), /*!< Data transfer direction is Memory To Peripheral */ 00050 DMA_DIR_Memory0ToMemory1 = ((uint8_t)0x40) /*!< Data transfer direction is Memory0 To Memory 1 */ 00051 }DMA_DIR_TypeDef; 00052 00053 #define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_MemoryToPeripheral) || \ 00054 ((DIR) == DMA_DIR_PeripheralToMemory) || \ 00055 ((DIR) == DMA_DIR_Memory0ToMemory1 )) 00056 /** 00057 * @} 00058 */ 00059 00060 /** @defgroup DMA_Mode 00061 * @{ 00062 */ 00063 typedef enum 00064 { 00065 DMA_Mode_Normal = ((uint8_t)0x00), /*!< DMA normal buffer mode*/ 00066 DMA_Mode_Circular = ((uint8_t)0x10) /*!< DMA circular buffer mode */ 00067 }DMA_Mode_TypeDef; 00068 00069 #define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || \ 00070 ((MODE) == DMA_Mode_Normal)) 00071 /** 00072 * @} 00073 */ 00074 00075 /** @defgroup DMA_Incremented_Mode 00076 * @{ 00077 */ 00078 typedef enum 00079 { 00080 DMA_MemoryIncMode_Dec = ((uint8_t)0x00), /*!< DMA memory incremented mode is decremental */ 00081 DMA_MemoryIncMode_Inc = ((uint8_t)0x20) /*!< DMA memory incremented mode is incremental */ 00082 }DMA_MemoryIncMode_TypeDef; 00083 00084 #define IS_DMA_MEMORY_INC_MODE(MODE) (((MODE) == DMA_MemoryIncMode_Inc) || \ 00085 ((MODE) == DMA_MemoryIncMode_Dec)) 00086 /** 00087 * @} 00088 */ 00089 00090 /** @defgroup DMA_Priority 00091 * @{ 00092 */ 00093 typedef enum 00094 { 00095 DMA_Priority_Low = ((uint8_t)0x00), /*!< Software Priority is Low */ 00096 DMA_Priority_Medium = ((uint8_t)0x10), /*!< Software Priority is Medium */ 00097 DMA_Priority_High = ((uint8_t)0x20), /*!< Software Priority is High */ 00098 DMA_Priority_VeryHigh = ((uint8_t)0x30) /*!< Software Priority is Very High*/ 00099 }DMA_Priority_TypeDef; 00100 00101 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \ 00102 ((PRIORITY) == DMA_Priority_High) || \ 00103 ((PRIORITY) == DMA_Priority_Medium) || \ 00104 ((PRIORITY) == DMA_Priority_Low)) 00105 /** 00106 * @} 00107 */ 00108 00109 /** @defgroup DMA_Memory_Data_Size 00110 * @{ 00111 */ 00112 typedef enum 00113 { 00114 DMA_MemoryDataSize_Byte = ((uint8_t)0x00),/*!< Memory Data Size is 1 Byte */ 00115 DMA_MemoryDataSize_HalfWord = ((uint8_t)0x08) /*!< Memory Data Size is 2 Bytes */ 00116 }DMA_MemoryDataSize_TypeDef; 00117 00118 #define IS_DMA_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \ 00119 ((SIZE) == DMA_MemoryDataSize_HalfWord)) 00120 /** 00121 * @} 00122 */ 00123 00124 /** @defgroup DMA_Flags 00125 * @{ 00126 */ 00127 typedef enum 00128 { 00129 DMA1_FLAG_GB = ((uint16_t)0x0002), /*!< Global Busy Flag */ 00130 00131 DMA1_FLAG_IFC0 = ((uint16_t)0x1001), /*!< Global Interrupt Flag Channel 0 */ 00132 DMA1_FLAG_IFC1 = ((uint16_t)0x1002), /*!< Global Interrupt Flag Channel 1 */ 00133 DMA1_FLAG_IFC2 = ((uint16_t)0x1004), /*!< Global Interrupt Flag Channel 2 */ 00134 DMA1_FLAG_IFC3 = ((uint16_t)0x1008), /*!< Global Interrupt Flag Channel 3 */ 00135 00136 DMA1_FLAG_TC0 = ((uint16_t)0x0102), /*!< Transaction Complete Interrupt Flag Channel 0 */ 00137 DMA1_FLAG_TC1 = ((uint16_t)0x0202), /*!< Transaction Complete Interrupt Flag Channel 1 */ 00138 DMA1_FLAG_TC2 = ((uint16_t)0x0402), /*!< Transaction Complete Interrupt Flag Channel 2 */ 00139 DMA1_FLAG_TC3 = ((uint16_t)0x0802), /*!< Transaction Complete Interrupt Flag Channel 3 */ 00140 00141 DMA1_FLAG_HT0 = ((uint16_t)0x0104), /*!< Half Transaction Interrupt Flag Channel 0 */ 00142 DMA1_FLAG_HT1 = ((uint16_t)0x0204), /*!< Half Transaction Interrupt Flag Channel 1 */ 00143 DMA1_FLAG_HT2 = ((uint16_t)0x0404), /*!< Half Transaction Interrupt Flag Channel 2 */ 00144 DMA1_FLAG_HT3 = ((uint16_t)0x0804), /*!< Half Transaction Interrupt Flag Channel 3 */ 00145 00146 DMA1_FLAG_PEND0 = ((uint16_t)0x0140), /*!< DMA Request pending on Channel 0 */ 00147 DMA1_FLAG_PEND1 = ((uint16_t)0x0240), /*!< DMA Request pending on Channel 1 */ 00148 DMA1_FLAG_PEND2 = ((uint16_t)0x0440), /*!< DMA Request pending on Channel 2 */ 00149 DMA1_FLAG_PEND3 = ((uint16_t)0x0840), /*!< DMA Request pending on Channel 3 */ 00150 00151 DMA1_FLAG_BUSY0 = ((uint16_t)0x0180), /*!< No DMA transfer on going in Channel 0 */ 00152 DMA1_FLAG_BUSY1 = ((uint16_t)0x0280), /*!< No DMA transfer on going in Channel 1 */ 00153 DMA1_FLAG_BUSY2 = ((uint16_t)0x0480), /*!< No DMA transfer on going in Channel 2 */ 00154 DMA1_FLAG_BUSY3 = ((uint16_t)0x0880) /*!< No DMA transfer on going in Channel 3 */ 00155 }DMA_FLAG_TypeDef; 00156 00157 #define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GB) || \ 00158 ((FLAG) == DMA1_FLAG_IFC0) || \ 00159 ((FLAG) == DMA1_FLAG_IFC1) || \ 00160 ((FLAG) == DMA1_FLAG_IFC2) || \ 00161 ((FLAG) == DMA1_FLAG_IFC3) || \ 00162 ((FLAG) == DMA1_FLAG_TC0) || \ 00163 ((FLAG) == DMA1_FLAG_TC1) || \ 00164 ((FLAG) == DMA1_FLAG_TC2) || \ 00165 ((FLAG) == DMA1_FLAG_TC3) || \ 00166 ((FLAG) == DMA1_FLAG_HT0) || \ 00167 ((FLAG) == DMA1_FLAG_HT1) || \ 00168 ((FLAG) == DMA1_FLAG_HT2) || \ 00169 ((FLAG) == DMA1_FLAG_HT3) || \ 00170 ((FLAG) == DMA1_FLAG_PEND0) || \ 00171 ((FLAG) == DMA1_FLAG_PEND1) || \ 00172 ((FLAG) == DMA1_FLAG_PEND2) || \ 00173 ((FLAG) == DMA1_FLAG_PEND3) || \ 00174 ((FLAG) == DMA1_FLAG_BUSY0) || \ 00175 ((FLAG) == DMA1_FLAG_BUSY1) || \ 00176 ((FLAG) == DMA1_FLAG_BUSY2) || \ 00177 ((FLAG) == DMA1_FLAG_BUSY3)) 00178 00179 #define IS_DMA_CLEAR_FLAG(FLAG) (((FLAG) == DMA1_FLAG_TC0) || \ 00180 ((FLAG) == DMA1_FLAG_TC1) || \ 00181 ((FLAG) == DMA1_FLAG_TC2) || \ 00182 ((FLAG) == DMA1_FLAG_TC3) || \ 00183 ((FLAG) == DMA1_FLAG_HT0) || \ 00184 ((FLAG) == DMA1_FLAG_HT1) || \ 00185 ((FLAG) == DMA1_FLAG_HT2) || \ 00186 ((FLAG) == DMA1_FLAG_HT3) || \ 00187 ((FLAG) == (DMA1_FLAG_TC0 |DMA1_FLAG_HT0)) || \ 00188 ((FLAG) == (DMA1_FLAG_TC1 |DMA1_FLAG_HT1)) || \ 00189 ((FLAG) == (DMA1_FLAG_TC2 |DMA1_FLAG_HT2)) || \ 00190 ((FLAG) == (DMA1_FLAG_TC3 |DMA1_FLAG_HT3))) 00191 /** 00192 * @} 00193 */ 00194 00195 /** @defgroup DMA_One_Channel_Interrupts 00196 * @{ 00197 */ 00198 typedef enum 00199 { 00200 DMA_ITx_TC = ((uint8_t)0x02),/*!< Transaction Complete Interrupt */ 00201 DMA_ITx_HT = ((uint8_t)0x04) /*!< Half Transaction Interrupt*/ 00202 }DMA_ITx_TypeDef; 00203 00204 #define IS_DMA_CONFIG_ITX(IT) ((((IT) & 0xF9) == 0x00) && ((IT) != 0x00)) 00205 /** 00206 * @} 00207 */ 00208 00209 /** @defgroup DMA_Interrupts 00210 * @{ 00211 */ 00212 typedef enum 00213 { 00214 /* Transaction Complete Interrupts*/ 00215 DMA1_IT_TC0 = ((uint8_t)0x12), /*!< Transaction Complete Interrupt Channel 0 */ 00216 DMA1_IT_TC1 = ((uint8_t)0x22), /*!< Transaction Complete Interrupt Channel 1 */ 00217 DMA1_IT_TC2 = ((uint8_t)0x42), /*!< Transaction Complete Interrupt Channel 2 */ 00218 DMA1_IT_TC3 = ((uint8_t)0x82), /*!< Transaction Complete Interrupt Channel 3 */ 00219 /* Half Transaction Interrupts */ 00220 DMA1_IT_HT0 = ((uint8_t)0x14), /*!< Half Transaction Interrupt Channel 0 */ 00221 DMA1_IT_HT1 = ((uint8_t)0x24), /*!< Half Transaction Interrupt Channel 1 */ 00222 DMA1_IT_HT2 = ((uint8_t)0x44), /*!< Half Transaction Interrupt Channel 2 */ 00223 DMA1_IT_HT3 = ((uint8_t)0x84) /*!< Half Transaction Interrupt Channel 3 */ 00224 }DMA_IT_TypeDef; 00225 00226 #define IS_DMA_CLEAR_IT(IT) (((IT) == DMA1_IT_TC0) || \ 00227 ((IT) == DMA1_IT_TC1) || \ 00228 ((IT) == DMA1_IT_TC2) || \ 00229 ((IT) == DMA1_IT_TC3) || \ 00230 ((IT) == DMA1_IT_HT0) || \ 00231 ((IT) == DMA1_IT_HT1) || \ 00232 ((IT) == DMA1_IT_HT2) || \ 00233 ((IT) == DMA1_IT_HT3) || \ 00234 ((IT) == (DMA1_IT_TC0|DMA1_IT_HT0)) || \ 00235 ((IT) == (DMA1_IT_TC1|DMA1_IT_HT1)) || \ 00236 ((IT) == (DMA1_IT_TC2|DMA1_IT_HT2)) || \ 00237 ((IT) == (DMA1_IT_TC3|DMA1_IT_HT3))) 00238 00239 #define IS_DMA_GET_IT(IT)(((IT) == DMA1_IT_TC0) || \ 00240 ((IT) == DMA1_IT_TC1) || \ 00241 ((IT) == DMA1_IT_TC2) || \ 00242 ((IT) == DMA1_IT_TC3) || \ 00243 ((IT) == DMA1_IT_HT0) || \ 00244 ((IT) == DMA1_IT_HT1) || \ 00245 ((IT) == DMA1_IT_HT2) || \ 00246 ((IT) == DMA1_IT_HT3)) 00247 /** 00248 * @} 00249 */ 00250 00251 /** 00252 * @} 00253 */ 00254 /* Exported constants --------------------------------------------------------*/ 00255 /* Exported macro ------------------------------------------------------------*/ 00256 /** @addtogroup DMA_Exported_Macros 00257 * @{ 00258 */ 00259 00260 /** @defgroup DMA_Channels 00261 * @{ 00262 */ 00263 #define IS_DMA_CHANNEL(PERIPH) (((*(uint16_t*)&(PERIPH)) == DMA1_Channel0_BASE) || \ 00264 ((*(uint16_t*)&(PERIPH)) == DMA1_Channel1_BASE) || \ 00265 ((*(uint16_t*)&(PERIPH)) == DMA1_Channel2_BASE) || \ 00266 ((*(uint16_t*)&(PERIPH)) == DMA1_Channel3_BASE)) 00267 /** 00268 * @} 00269 */ 00270 00271 00272 /** @defgroup DMA_Buffer_Size 00273 * @{ 00274 */ 00275 #define IS_DMA_BUFFER_SIZE(SIZE) ((SIZE) > (uint8_t)0x0) 00276 00277 /** 00278 * @} 00279 */ 00280 00281 /** @defgroup DMA_Timeout 00282 * @{ 00283 */ 00284 #define IS_DMA_TIMEOUT(TIME) ((TIME) < (uint8_t)0x40) 00285 00286 /** 00287 * @} 00288 */ 00289 00290 /** 00291 * @} 00292 */ 00293 00294 /* Exported functions ------------------------------------------------------- */ 00295 00296 /* Functions used to set the DMA configuration to the default reset state ****/ 00297 void DMA_GlobalDeInit(void); 00298 void DMA_DeInit(DMA_Channel_TypeDef* DMA_Channelx); 00299 00300 /* Initialization and Configuration functions *********************************/ 00301 void DMA_Init(DMA_Channel_TypeDef* DMA_Channelx, 00302 uint32_t DMA_Memory0BaseAddr, 00303 uint16_t DMA_PeripheralMemory1BaseAddr, 00304 uint8_t DMA_BufferSize, 00305 DMA_DIR_TypeDef DMA_DIR, 00306 DMA_Mode_TypeDef DMA_Mode, 00307 DMA_MemoryIncMode_TypeDef DMA_MemoryIncMode, 00308 DMA_Priority_TypeDef DMA_Priority, 00309 DMA_MemoryDataSize_TypeDef DMA_MemoryDataSize ); 00310 void DMA_GlobalCmd(FunctionalState NewState); 00311 void DMA_Cmd(DMA_Channel_TypeDef* DMA_Channelx, FunctionalState NewState); 00312 void DMA_SetTimeOut(uint8_t DMA_TimeOut); 00313 00314 /* Data Counter functions *****************************************************/ 00315 void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMA_Channelx, uint8_t DataNumber); 00316 uint8_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMA_Channelx); 00317 00318 /* Interrupts and flags management functions **********************************/ 00319 void DMA_ITConfig(DMA_Channel_TypeDef* DMA_Channelx, DMA_ITx_TypeDef DMA_ITx, FunctionalState NewState); 00320 FlagStatus DMA_GetFlagStatus(DMA_FLAG_TypeDef DMA_FLAG); 00321 void DMA_ClearFlag(DMA_FLAG_TypeDef DMA_FLAG); 00322 ITStatus DMA_GetITStatus(DMA_IT_TypeDef DMA_IT); 00323 void DMA_ClearITPendingBit(DMA_IT_TypeDef DMA_IT); 00324 00325 #endif /*__STM8L15x_DMA_H */ 00326 00327 /** 00328 * @} 00329 */ 00330 00331 /** 00332 * @} 00333 */ 00334 00335 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/