Hardware-Timed Simultaneously Updated I/O
Requirement
The I/O must be hardware-timed. All output values need to simultaneously update at the arrival of the sample clock edge.
Solution
Use the Wait For Next Sample Clock function/VI to verify that a new sample clock edge has not yet occurred.
Advantages
- The current iteration's output samples are guaranteed to be aligned with the next iteration's input samples.
- NI-DAQmx returns an error if the Wait For Next Sample Clock function/VI does not start before the next sample clock edge occurs.
- I/O jitter is confined to the jitter of the hardware clock, which is on the order of a few nanoseconds.
Restrictions
Read, process, and write operations are confined to the time available between the moment the device starts acquiring data and the moment the next sample clock edge arrives.
Sample Application
An example of this kind of application is an analog control loop that reads samples from a specific number of analog input channels, processes the data using a control algorithm (such as PID), and writes new control values to the analog output channels.
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