Fsp T Configuration. More...

#include <FsptUpd.h>

Public Attributes
UINT8	PcdSerialIoUartDebugEnable
	Offset 0x0040 - PcdSerialIoUartDebugEnable Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP. More...

UINT8	PcdSerialIoUartNumber
	Offset 0x0041 - PcdSerialIoUartNumber - FSPT Select SerialIo Uart Controller for debug. More...

UINT8	PcdSerialIoUart0PinMuxing
	Offset 0x0042 - PcdSerialIoUart0PinMuxing - FSPT Select SerialIo Uart0 pin muxing. More...

UINT8	UnusedUpdSpace0
	Offset 0x0043.

UINT32	PcdSerialIoUartInputClock
	Offset 0x0044.

UINT64	PcdPciExpressBaseAddress
	Offset 0x0048 - Pci Express Base Address Base address to be programmed for Pci Express.

UINT32	PcdPciExpressRegionLength
	Offset 0x0050 - Pci Express Region Length Region Length to be programmed for Pci Express.

UINT8	ReservedFsptUpd1 [44]
	Offset 0x0054.

Detailed Description

Fsp T Configuration.

Definition at line 68 of file FsptUpd.h.

Member Data Documentation

UINT8 FSP_T_CONFIG::PcdSerialIoUart0PinMuxing

Offset 0x0042 - PcdSerialIoUart0PinMuxing - FSPT Select SerialIo Uart0 pin muxing.

Setting valid only if PcdSerialIoUartNumber is set to UART0. 0:default pins, 1:pins muxed with CNV_BRI/RGI

Definition at line 88 of file FsptUpd.h.

UINT8 FSP_T_CONFIG::PcdSerialIoUartDebugEnable

Offset 0x0040 - PcdSerialIoUartDebugEnable Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP.

0:Disable, 1:Enable and Initialize, 2:Enable without Initializing

Definition at line 74 of file FsptUpd.h.

UINT8 FSP_T_CONFIG::PcdSerialIoUartNumber

Offset 0x0041 - PcdSerialIoUartNumber - FSPT Select SerialIo Uart Controller for debug.

Note: If UART0 is selected as CNVi BT Core interface, it cannot be used for debug purpose. 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2

Definition at line 81 of file FsptUpd.h.

The documentation for this struct was generated from the following file: