CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide: FsptUpd.h Source File

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CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide
FsptUpd.h
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1 /** @file
2 
3 Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
4 
5 Redistribution and use in source and binary forms, with or without modification,
6 are permitted provided that the following conditions are met:
7 
8 * Redistributions of source code must retain the above copyright notice, this
9  list of conditions and the following disclaimer.
10 * Redistributions in binary form must reproduce the above copyright notice, this
11  list of conditions and the following disclaimer in the documentation and/or
12  other materials provided with the distribution.
13 * Neither the name of Intel Corporation nor the names of its contributors may
14  be used to endorse or promote products derived from this software without
15  specific prior written permission.
16 
17  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
18  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
21  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27  THE POSSIBILITY OF SUCH DAMAGE.
28 
29  This file is automatically generated. Please do NOT modify !!!
30 
31 **/
32 
33 #ifndef __FSPTUPD_H__
34 #define __FSPTUPD_H__
35 
36 #include <FspUpd.h>
37 
38 #pragma pack(1)
39 
40 
41 /** Fsp T Core UPD
42 **/
43 typedef struct {
44 
45 /** Offset 0x0020
46 **/
48 
49 /** Offset 0x0024
50 **/
52 
53 /** Offset 0x0028
54 **/
56 
57 /** Offset 0x002C
58 **/
60 
61 /** Offset 0x0030
62 **/
63  UINT8 Reserved[16];
65 
66 /** Fsp T Configuration
67 **/
68 typedef struct {
69 
70 /** Offset 0x0040 - PcdSerialIoUartDebugEnable
71  Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP.
72  0:Disable, 1:Enable and Initialize, 2:Enable without Initializing
73 **/
75 
76 /** Offset 0x0041 - PcdSerialIoUartNumber - FSPT
77  Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT
78  Core interface, it cannot be used for debug purpose.
79  0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
80 **/
82 
83 /** Offset 0x0042 - PcdSerialIoUart0PinMuxing - FSPT
84  Select SerialIo Uart0 pin muxing. Setting valid only if PcdSerialIoUartNumber is
85  set to UART0.
86  0:default pins, 1:pins muxed with CNV_BRI/RGI
87 **/
89 
90 /** Offset 0x0043
91 **/
93 
94 /** Offset 0x0044
95 **/
97 
98 /** Offset 0x0048 - Pci Express Base Address
99  Base address to be programmed for Pci Express
100 **/
102 
103 /** Offset 0x0050 - Pci Express Region Length
104  Region Length to be programmed for Pci Express
105 **/
107 
108 /** Offset 0x0054
109 **/
110  UINT8 ReservedFsptUpd1[44];
111 } FSP_T_CONFIG;
112 
113 /** Fsp T UPD Configuration
114 **/
115 typedef struct {
116 
117 /** Offset 0x0000
118 **/
119  FSP_UPD_HEADER FspUpdHeader;
120 
121 /** Offset 0x0020
122 **/
124 
125 /** Offset 0x0040
126 **/
128 
129 /** Offset 0x0080
130 **/
132 } FSPT_UPD;
133 
134 #pragma pack()
135 
136 #endif
UINT8 UnusedUpdSpace0
Offset 0x0043.
Definition: FsptUpd.h:92
UINT32 CodeRegionBase
Offset 0x0028.
Definition: FsptUpd.h:55
FSPT_CORE_UPD FsptCoreUpd
Offset 0x0020.
Definition: FsptUpd.h:123
FSP_T_CONFIG FsptConfig
Offset 0x0040.
Definition: FsptUpd.h:127
UINT32 PcdPciExpressRegionLength
Offset 0x0050 - Pci Express Region Length Region Length to be programmed for Pci Express.
Definition: FsptUpd.h:106
UINT8 PcdSerialIoUartDebugEnable
Offset 0x0040 - PcdSerialIoUartDebugEnable Enable SerialIo Uart debug library with/without initializi...
Definition: FsptUpd.h:74
UINT8 PcdSerialIoUart0PinMuxing
Offset 0x0042 - PcdSerialIoUart0PinMuxing - FSPT Select SerialIo Uart0 pin muxing.
Definition: FsptUpd.h:88
UINT32 CodeRegionSize
Offset 0x002C.
Definition: FsptUpd.h:59
Copyright (c) 2018, Intel Corporation.
UINT64 PcdPciExpressBaseAddress
Offset 0x0048 - Pci Express Base Address Base address to be programmed for Pci Express.
Definition: FsptUpd.h:101
UINT8 PcdSerialIoUartNumber
Offset 0x0041 - PcdSerialIoUartNumber - FSPT Select SerialIo Uart Controller for debug.
Definition: FsptUpd.h:81
UINT16 UpdTerminator
Offset 0x0080.
Definition: FsptUpd.h:131
Fsp T UPD Configuration.
Definition: FsptUpd.h:115
UINT32 PcdSerialIoUartInputClock
Offset 0x0044.
Definition: FsptUpd.h:96
FSP_UPD_HEADER FspUpdHeader
Offset 0x0000.
Definition: FsptUpd.h:119
UINT32 MicrocodeRegionSize
Offset 0x0024.
Definition: FsptUpd.h:51
Fsp T Configuration.
Definition: FsptUpd.h:68
UINT32 MicrocodeRegionBase
Offset 0x0020.
Definition: FsptUpd.h:47
Fsp T Core UPD.
Definition: FsptUpd.h:43
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