|
|
UINT32 | LogoPtr |
| | Offset 0x0020 - Logo Pointer Points to PEI Display Logo Image.
|
| |
|
UINT32 | LogoSize |
| | Offset 0x0024 - Logo Size Size of PEI Display Logo Image.
|
| |
|
UINT32 | GraphicsConfigPtr |
| | Offset 0x0028 - Graphics Configuration Ptr Points to VBT.
|
| |
|
UINT8 | Device4Enable |
| | Offset 0x002C - Enable Device 4 Enable/disable Device 4 $EN_DIS.
|
| |
| UINT8 | PchHdaDspEnable |
| | Offset 0x002D - Enable HD Audio DSP Enable/disable HD Audio DSP feature. More...
|
| |
|
UINT8 | UnusedUpdSpace0 [3] |
| | Offset 0x002E.
|
| |
| UINT8 | ScsEmmcEnabled |
| | Offset 0x0031 - Enable eMMC Controller Enable/disable eMMC Controller. More...
|
| |
| UINT8 | ScsEmmcHs400Enabled |
| | Offset 0x0032 - Enable eMMC HS400 Mode Enable eMMC HS400 Mode. More...
|
| |
| UINT8 | ScsSdCardEnabled |
| | Offset 0x0033 - Enable SdCard Controller Enable/disable SD Card Controller. More...
|
| |
| UINT8 | ShowSpiController |
| | Offset 0x0034 - Show SPI controller Enable/disable to show SPI controller. More...
|
| |
|
UINT8 | UnusedUpdSpace1 [3] |
| | Offset 0x0035.
|
| |
|
UINT32 | MicrocodeRegionBase |
| | Offset 0x0038 - MicrocodeRegionBase Memory Base of Microcode Updates.
|
| |
|
UINT32 | MicrocodeRegionSize |
| | Offset 0x003C - MicrocodeRegionSize Size of Microcode Updates.
|
| |
| UINT8 | TurboMode |
| | Offset 0x0040 - Turbo Mode Enable/Disable Turbo mode. More...
|
| |
| UINT8 | SataSalpSupport |
| | Offset 0x0041 - Enable SATA SALP Support Enable/disable SATA Aggressive Link Power Management. More...
|
| |
| UINT8 | SataPortsEnable [8] |
| | Offset 0x0042 - Enable SATA ports Enable/disable SATA ports. More...
|
| |
| UINT8 | SataPortsDevSlp [8] |
| | Offset 0x004A - Enable SATA DEVSLP Feature Enable/disable SATA DEVSLP per port. More...
|
| |
| UINT8 | PortUsb20Enable [16] |
| | Offset 0x0052 - Enable USB2 ports Enable/disable per USB2 ports. More...
|
| |
| UINT8 | PortUsb30Enable [10] |
| | Offset 0x0062 - Enable USB3 ports Enable/disable per USB3 ports. More...
|
| |
| UINT8 | XdciEnable |
| | Offset 0x006C - Enable xDCI controller Enable/disable to xDCI controller. More...
|
| |
|
UINT8 | UnusedUpdSpace2 [2] |
| | Offset 0x006D.
|
| |
| UINT8 | SerialIoDevMode [12] |
| | Offset 0x006F - Enable SerialIo Device Mode 0:Disabled, 1:PCI Mode, 2:Acpi mode, 3:Hidden mode (Legacy UART mode) - Enable/disable SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5,SPI0,SPI1,SPI2,UART0,UART1,UART2 device mode respectively. More...
|
| |
| UINT32 | DevIntConfigPtr |
| | Offset 0x007B - Address of PCH_DEVICE_INTERRUPT_CONFIG table. More...
|
| |
| UINT8 | NumOfDevIntConfig |
| | Offset 0x007F - Number of DevIntConfig Entry Number of Device Interrupt Configuration Entry. More...
|
| |
| UINT8 | PxRcConfig [8] |
| | Offset 0x0080 - PIRQx to IRQx Map Config PIRQx to IRQx mapping. More...
|
| |
| UINT8 | GpioIrqRoute |
| | Offset 0x0088 - Select GPIO IRQ Route GPIO IRQ Select. More...
|
| |
| UINT8 | SciIrqSelect |
| | Offset 0x0089 - Select SciIrqSelect SCI IRQ Select. More...
|
| |
| UINT8 | TcoIrqSelect |
| | Offset 0x008A - Select TcoIrqSelect TCO IRQ Select. More...
|
| |
|
UINT8 | TcoIrqEnable |
| | Offset 0x008B - Enable/Disable Tco IRQ Enable/disable TCO IRQ $EN_DIS.
|
| |
|
UINT8 | PchHdaVerbTableEntryNum |
| | Offset 0x008C - PCH HDA Verb Table Entry Number Number of Entries in Verb Table.
|
| |
|
UINT32 | PchHdaVerbTablePtr |
| | Offset 0x008D - PCH HDA Verb Table Pointer Pointer to Array of pointers to Verb Table.
|
| |
|
UINT8 | PchHdaCodecSxWakeCapability |
| | Offset 0x0091 - PCH HDA Codec Sx Wake Capability Capability to detect wake initiated by a codec in Sx.
|
| |
| UINT8 | SataEnable |
| | Offset 0x0092 - Enable SATA Enable/disable SATA controller. More...
|
| |
| UINT8 | SataMode |
| | Offset 0x0093 - SATA Mode Select SATA controller working mode. More...
|
| |
| UINT8 | Usb2AfePetxiset [16] |
| | Offset 0x0094 - USB Per Port HS Preemphasis Bias USB Per Port HS Preemphasis Bias. More...
|
| |
| UINT8 | Usb2AfeTxiset [16] |
| | Offset 0x00A4 - USB Per Port HS Transmitter Bias USB Per Port HS Transmitter Bias. More...
|
| |
| UINT8 | Usb2AfePredeemp [16] |
| | Offset 0x00B4 - USB Per Port HS Transmitter Emphasis USB Per Port HS Transmitter Emphasis. More...
|
| |
| UINT8 | Usb2AfePehalfbit [16] |
| | Offset 0x00C4 - USB Per Port Half Bit Pre-emphasis USB Per Port Half Bit Pre-emphasis. More...
|
| |
| UINT8 | Usb3HsioTxDeEmphEnable [10] |
| | Offset 0x00D4 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. More...
|
| |
| UINT8 | Usb3HsioTxDeEmph [10] |
| | Offset 0x00DE - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16], Default = 29h (approximately -3.5dB De-Emphasis). More...
|
| |
| UINT8 | Usb3HsioTxDownscaleAmpEnable [10] |
| | Offset 0x00E8 - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value in arrary can be between 0-1. More...
|
| |
| UINT8 | Usb3HsioTxDownscaleAmp [10] |
| | Offset 0x00F2 - USB 3.0 TX Output Downscale Amplitude Adjustment USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], Default = 00h. More...
|
| |
| UINT8 | PchLanEnable |
| | Offset 0x00FC - Enable LAN Enable/disable LAN controller. More...
|
| |
| UINT8 | PchHdaAudioLinkHda |
| | Offset 0x00FD - Enable HD Audio Link Enable/disable HD Audio Link. More...
|
| |
| UINT8 | PchHdaAudioLinkDmic0 |
| | Offset 0x00FE - Enable HD Audio DMIC0 Link Enable/disable HD Audio DMIC0 link. More...
|
| |
| UINT8 | PchHdaAudioLinkDmic1 |
| | Offset 0x00FF - Enable HD Audio DMIC1 Link Enable/disable HD Audio DMIC1 link. More...
|
| |
| UINT8 | PchHdaAudioLinkSsp0 |
| | Offset 0x0100 - Enable HD Audio SSP0 Link Enable/disable HD Audio SSP0/I2S link. More...
|
| |
| UINT8 | PchHdaAudioLinkSsp1 |
| | Offset 0x0101 - Enable HD Audio SSP1 Link Enable/disable HD Audio SSP1/I2S link. More...
|
| |
| UINT8 | PchHdaAudioLinkSsp2 |
| | Offset 0x0102 - Enable HD Audio SSP2 Link Enable/disable HD Audio SSP2/I2S link. More...
|
| |
| UINT8 | PchHdaAudioLinkSndw1 |
| | Offset 0x0103 - Enable HD Audio SoundWire#1 Link Enable/disable HD Audio SNDW1 link. More...
|
| |
| UINT8 | PchHdaAudioLinkSndw2 |
| | Offset 0x0104 - Enable HD Audio SoundWire#2 Link Enable/disable HD Audio SNDW2 link. More...
|
| |
| UINT8 | PchHdaAudioLinkSndw3 |
| | Offset 0x0105 - Enable HD Audio SoundWire#3 Link Enable/disable HD Audio SNDW3 link. More...
|
| |
| UINT8 | PchHdaAudioLinkSndw4 |
| | Offset 0x0106 - Enable HD Audio SoundWire#4 Link Enable/disable HD Audio SNDW4 link. More...
|
| |
| UINT8 | PchHdaSndwBufferRcomp |
| | Offset 0x0107 - Soundwire Clock Buffer GPIO RCOMP Setting 0: non-ACT - 50 Ohm driver impedance, 1: ACT - 8 Ohm driver impedance. More...
|
| |
| UINT32 | PcieRpPtmMask |
| | Offset 0x0108 - PTM for PCIE RP Mask Enable/disable Precision Time Measurement for PCIE Root Ports. More...
|
| |
| UINT32 | PcieRpDpcMask |
| | Offset 0x010C - DPC for PCIE RP Mask Enable/disable Downstream Port Containment for PCIE Root Ports. More...
|
| |
| UINT32 | PcieRpDpcExtensionsMask |
| | Offset 0x0110 - DPC Extensions PCIE RP Mask Enable/disable DPC Extensions for PCIE Root Ports. More...
|
| |
| UINT8 | UsbPdoProgramming |
| | Offset 0x0114 - USB PDO Programming Enable/disable PDO programming for USB in PEI phase. More...
|
| |
| UINT32 | PmcPowerButtonDebounce |
| | Offset 0x0115 - Power button debounce configuration Debounce time for PWRBTN in microseconds. More...
|
| |
|
UINT8 | PchEspiBmeMasterSlaveEnabled |
| | Offset 0x0119 - PCH eSPI Master and Slave BME enabled PCH eSPI Master and Slave BME enabled $EN_DIS.
|
| |
|
UINT8 | SataRstLegacyOrom |
| | Offset 0x011A - PCH SATA use RST Legacy OROM Use PCH SATA RST Legacy OROM when CSM is Enabled $EN_DIS.
|
| |
|
UINT32 | TraceHubMemBase |
| | Offset 0x011B - Trace Hub Memory Base If Trace Hub is enabled and trace to memory is desired, BootLoader needs to allocate trace hub memory as reserved and uncacheable, set the base to ensure Trace Hub memory is configured properly.
|
| |
| UINT8 | PmcDbgMsgEn |
| | Offset 0x011F - PMC Debug Message Enable When Enabled, PMC HW will send debug messages to trace hub; When Disabled, PMC HW will never send debug meesages to trace hub. More...
|
| |
|
UINT32 | ChipsetInitBinPtr |
| | Offset 0x0120 - Pointer of ChipsetInit Binary ChipsetInit Binary Pointer.
|
| |
|
UINT32 | ChipsetInitBinLen |
| | Offset 0x0124 - Length of ChipsetInit Binary ChipsetInit Binary Length.
|
| |
|
UINT8 | PchPostMemRsvd [29] |
| | Offset 0x0128 - PchPostMemRsvd Reserved for PCH Post-Mem $EN_DIS.
|
| |
| UINT8 | ScsUfsEnabled |
| | Offset 0x0145 - Enable Ufs Controller Enable/disable Ufs 2.0 Controller. More...
|
| |
| UINT8 | PchCnviMode |
| | Offset 0x0146 - CNVi Configuration This option allows for automatic detection of Connectivity Solution. More...
|
| |
|
UINT8 | SdCardPowerEnableActiveHigh |
| | Offset 0x0147 - SdCard power enable polarity Choose SD_PWREN# polarity 0: Active low, 1: Active high.
|
| |
|
UINT8 | PchUsb2PhySusPgEnable |
| | Offset 0x0148 - PCH USB2 PHY Power Gating enable 1: Will enable USB2 PHY SUS Well Power Gating, 0: Will not enable PG of USB2 PHY Sus Well PG $EN_DIS.
|
| |
|
UINT8 | PchUsbOverCurrentEnable |
| | Offset 0x0149 - PCH USB OverCurrent mapping enable 1: Will program USB OC pin mapping in xHCI controller memory, 0: Will clear OC pin mapping allow for NOA usage of OC pins $EN_DIS.
|
| |
|
UINT8 | UnusedUpdSpace3 |
| | Offset 0x014A.
|
| |
|
UINT8 | PchCnviMfUart1Type |
| | Offset 0x014B - CNVi MfUart1 Type This option configures Uart type which connects to MfUart1 0:ISH Uart0, 1:SerialIO Uart2, 2:Uart over external pads.
|
| |
|
UINT8 | PchEspiLgmrEnable |
| | Offset 0x014C - Espi Lgmr Memory Range decode This option enables or disables espi lgmr $EN_DIS.
|
| |
| UINT8 | Heci3Enabled |
| | Offset 0x014D - HECI3 state The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed. More...
|
| |
|
UINT8 | UnusedUpdSpace4 |
| | Offset 0x014E.
|
| |
| UINT8 | PchHotEnable |
| | Offset 0x014F - PCHHOT# pin Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. More...
|
| |
| UINT8 | SataLedEnable |
| | Offset 0x0150 - SATA LED SATA LED indicating SATA controller activity. More...
|
| |
| UINT8 | PchPmVrAlert |
| | Offset 0x0151 - VRAlert# Pin When VRAlert# feature pin is enabled and its state is '0', the PMC requests throttling to a T3 Tstate to the PCH throttling unit. More...
|
| |
| UINT8 | PchPmSlpS0VmRuntimeControl |
| | Offset 0x0152 - SLP_S0 VM Dynamic Control SLP_S0 Voltage Margining Runtime Control Policy. More...
|
| |
| UINT8 | PchPmSlpS0Vm070VSupport |
| | Offset 0x0153 - SLP_S0 VM 0.70V Support SLP_S0 Voltage Margining 0.70V Support Policy. More...
|
| |
| UINT8 | PchPmSlpS0Vm075VSupport |
| | Offset 0x0154 - SLP_S0 VM 0.75V Support SLP_S0 Voltage Margining 0.75V Support Policy. More...
|
| |
| UINT8 | AmtEnabled |
| | Offset 0x0155 - AMT Switch Enable/Disable. More...
|
| |
| UINT8 | WatchDog |
| | Offset 0x0156 - WatchDog Timer Switch Enable/Disable. More...
|
| |
| UINT8 | AsfEnabled |
| | Offset 0x0157 - ASF Switch Enable/Disable. More...
|
| |
| UINT8 | ManageabilityMode |
| | Offset 0x0158 - Manageability Mode set by Mebx Enable/Disable. More...
|
| |
| UINT8 | FwProgress |
| | Offset 0x0159 - PET Progress Enable/Disable. More...
|
| |
| UINT8 | AmtSolEnabled |
| | Offset 0x015A - SOL Switch Enable/Disable. More...
|
| |
| UINT16 | WatchDogTimerOs |
| | Offset 0x015B - OS Timer 16 bits Value, Set OS watchdog timer. More...
|
| |
| UINT16 | WatchDogTimerBios |
| | Offset 0x015D - BIOS Timer 16 bits Value, Set BIOS watchdog timer. More...
|
| |
| UINT8 | RemoteAssistance |
| | Offset 0x015F - Remote Assistance Trigger Availablilty Enable/Disable. More...
|
| |
| UINT8 | AmtKvmEnabled |
| | Offset 0x0160 - KVM Switch Enable/Disable. More...
|
| |
| UINT8 | ForcMebxSyncUp |
| | Offset 0x0161 - MEBX execution Enable/Disable. More...
|
| |
|
UINT8 | UnusedUpdSpace5 [1] |
| | Offset 0x0162.
|
| |
|
UINT8 | PcieRpSlotImplemented [24] |
| | Offset 0x0163 - PCH PCIe root port connection type 0: built-in device, 1:slot.
|
| |
|
UINT8 | PcieClkSrcUsage [16] |
| | Offset 0x017B - Usage type for ClkSrc 0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use (free running), 0xFF: not used.
|
| |
|
UINT8 | PcieClkSrcClkReq [16] |
| | Offset 0x018B - ClkReq-to-ClkSrc mapping Number of ClkReq signal assigned to ClkSrc.
|
| |
|
UINT8 | PcieRpAcsEnabled [24] |
| | Offset 0x019B - PCIE RP Access Control Services Extended Capability Enable/Disable PCIE RP Access Control Services Extended Capability.
|
| |
|
UINT8 | PcieRpEnableCpm [24] |
| | Offset 0x01B3 - PCIE RP Clock Power Management Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal can still be controlled by L1 PM substates mechanism.
|
| |
|
UINT16 | PcieRpDetectTimeoutMs [24] |
| | Offset 0x01CB - PCIE RP Detect Timeout Ms The number of milliseconds within 0~65535 in reference code will wait for link to exit Detect state for enabled ports before assuming there is no device and potentially disabling the port.
|
| |
| UINT8 | PmcModPhySusPgEnable |
| | Offset 0x01FB - ModPHY SUS Power Domain Dynamic Gating Enable/Disable ModPHY SUS Power Domain Dynamic Gating. More...
|
| |
| UINT8 | SlpS0WithGbeSupport |
| | Offset 0x01FC - SlpS0WithGbeSupport Enable/Disable SLP_S0 with GBE Support. More...
|
| |
|
UINT8 | UnusedUpdSpace6 [3] |
| | Offset 0x01FD.
|
| |
|
UINT8 | CridEnable |
| | Offset 0x0200 - Enable/Disable SA CRID Enable: SA CRID, Disable (Default): SA CRID $EN_DIS.
|
| |
|
UINT8 | DmiAspm |
| | Offset 0x0201 - DMI ASPM 0=Disable, 1:L0s, 2:L1, 3(Default)=L0sL1 0:Disable, 1:L0s, 2:L1, 3:L0sL1.
|
| |
|
UINT8 | PegDeEmphasis [4] |
| | Offset 0x0202 - PCIe DeEmphasis control per root port 0: -6dB, 1(Default): -3.5dB 0:-6dB, 1:-3.5dB.
|
| |
|
UINT8 | PegSlotPowerLimitValue [4] |
| | Offset 0x0206 - PCIe Slot Power Limit value per root port Slot power limit value per root port.
|
| |
|
UINT8 | PegSlotPowerLimitScale [4] |
| | Offset 0x020A - PCIe Slot Power Limit scale per root port Slot power limit scale per root port 0:1.0x, 1:0.1x, 2:0.01x, 3:0x001x.
|
| |
|
UINT16 | PegPhysicalSlotNumber [4] |
| | Offset 0x020E - PCIe Physical Slot Number per root port Physical Slot Number per root port.
|
| |
|
UINT8 | PavpEnable |
| | Offset 0x0216 - Enable/Disable PavpEnable Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable $EN_DIS.
|
| |
|
UINT8 | CdClock |
| | Offset 0x0217 - CdClock Frequency selection 0=337.5 Mhz, 1=450 Mhz, 2=540 Mhz, 3(Default)=675 Mhz 0: 337.5 Mhz, 1: 450 Mhz, 2: 540 Mhz, 3: 675 Mhz.
|
| |
|
UINT8 | PeiGraphicsPeimInit |
| | Offset 0x0218 - Enable/Disable PeiGraphicsPeimInit Enable: Enable PeiGraphicsPeimInit, Disable(Default): Disable PeiGraphicsPeimInit $EN_DIS.
|
| |
|
UINT8 | UnusedUpdSpace7 |
| | Offset 0x0219.
|
| |
|
UINT8 | GnaEnable |
| | Offset 0x021A - Enable or disable GNA device 0=Disable, 1(Default)=Enable $EN_DIS.
|
| |
|
UINT8 | X2ApicOptOut |
| | Offset 0x021B - State of X2APIC_OPT_OUT bit in the DMAR table 0=Disable/Clear, 1=Enable/Set $EN_DIS.
|
| |
|
UINT32 | VtdBaseAddress [3] |
| | Offset 0x021C - Base addresses for VT-d function MMIO access Base addresses for VT-d MMIO access per VT-d engine.
|
| |
|
UINT8 | DdiPortEdp |
| | Offset 0x0228 - Enable or disable eDP device 0=Disable, 1(Default)=Enable $EN_DIS.
|
| |
|
UINT8 | DdiPortBHpd |
| | Offset 0x0229 - Enable or disable HPD of DDI port B 0=Disable, 1(Default)=Enable $EN_DIS.
|
| |
|
UINT8 | DdiPortCHpd |
| | Offset 0x022A - Enable or disable HPD of DDI port C 0=Disable, 1(Default)=Enable $EN_DIS.
|
| |
|
UINT8 | DdiPortDHpd |
| | Offset 0x022B - Enable or disable HPD of DDI port D 0=Disable, 1(Default)=Enable $EN_DIS.
|
| |
|
UINT8 | DdiPortFHpd |
| | Offset 0x022C - Enable or disable HPD of DDI port F 0=Disable, 1(Default)=Enable $EN_DIS.
|
| |
|
UINT8 | DdiPortBDdc |
| | Offset 0x022D - Enable or disable DDC of DDI port B 0=Disable, 1(Default)=Enable $EN_DIS.
|
| |
|
UINT8 | DdiPortCDdc |
| | Offset 0x022E - Enable or disable DDC of DDI port C 0=Disable, 1(Default)=Enable $EN_DIS.
|
| |
|
UINT8 | DdiPortDDdc |
| | Offset 0x022F - Enable or disable DDC of DDI port D 0=Disable, 1(Default)=Enable $EN_DIS.
|
| |
|
UINT8 | DdiPortFDdc |
| | Offset 0x0230 - Enable or disable DDC of DDI port F 0(Default)=Disable, 1=Enable $EN_DIS.
|
| |
|
UINT8 | SkipS3CdClockInit |
| | Offset 0x0231 - Enable/Disable SkipS3CdClockInit Enable: Skip Full CD clock initializaton, Disable(Default): Initialize the full CD clock in S3 resume due to GOP absent $EN_DIS.
|
| |
| UINT16 | DeltaT12PowerCycleDelay |
| | Offset 0x0232 - Delta T12 Power Cycle Delay required in ms Select the value for delay required. More...
|
| |
|
UINT32 | BltBufferAddress |
| | Offset 0x0234 - Blt Buffer Address Address of Blt buffer.
|
| |
|
UINT32 | BltBufferSize |
| | Offset 0x0238 - Blt Buffer Size Size of Blt Buffer, is equal to PixelWidth * PixelHeight * 4 bytes (the size of EFI_GRAPHICS_OUTPUT_BLT_PIXEL)
|
| |
|
UINT8 | SaPostMemProductionRsvd [35] |
| | Offset 0x023C - SaPostMemProductionRsvd Reserved for SA Post-Mem Production $EN_DIS.
|
| |
|
UINT8 | PcieRootPortGen2PllL1CgDisable [24] |
| | Offset 0x025F - PCIE RP Disable Gen2PLL Shutdown and L1 Clock Gating Enable PCIE RP Disable Gen2PLL Shutdown and L1 Clock Gating Enable Workaround needed for Alpine ridge.
|
| |
|
UINT8 | AesEnable |
| | Offset 0x0277 - Advanced Encryption Standard (AES) feature Enable or Disable Advanced Encryption Standard (AES) feature; 0: Disable; 1: Enable $EN_DIS.
|
| |
| UINT8 | Psi3Enable [5] |
| | Offset 0x0278 - Power State 3 enable/disable PCODE MMIO Mailbox: Power State 3 enable/disable; 0: Disable; 1: Enable. More...
|
| |
|
UINT8 | Psi4Enable [5] |
| | Offset 0x027D - Power State 4 enable/disable PCODE MMIO Mailbox: Power State 4 enable/disable; 0: Disable; 1: Enable.For all VR Indexes.
|
| |
| UINT8 | ImonSlope [5] |
| | Offset 0x0282 - Imon slope correction PCODE MMIO Mailbox: Imon slope correction. More...
|
| |
| UINT8 | ImonOffset [5] |
| | Offset 0x0287 - Imon offset correction PCODE MMIO Mailbox: Imon offset correction. More...
|
| |
|
UINT8 | VrConfigEnable [5] |
| | Offset 0x028C - Enable/Disable BIOS configuration of VR Enable/Disable BIOS configuration of VR; 0: Disable; 1: Enable.For all VR Indexes.
|
| |
|
UINT8 | TdcEnable [5] |
| | Offset 0x0291 - Thermal Design Current enable/disable PCODE MMIO Mailbox: Thermal Design Current enable/disable; 0: Disable; 1: Enable.For all VR Indexes.
|
| |
| UINT8 | TdcTimeWindow [5] |
| | Offset 0x0296 - HECI3 state PCODE MMIO Mailbox: Thermal Design Current time window. More...
|
| |
|
UINT8 | TdcLock [5] |
| | Offset 0x029B - Thermal Design Current Lock PCODE MMIO Mailbox: Thermal Design Current Lock; 0: Disable; 1: Enable.For all VR Indexes.
|
| |
| UINT8 | PsysSlope |
| | Offset 0x02A0 - Platform Psys slope correction PCODE MMIO Mailbox: Platform Psys slope correction. More...
|
| |
| UINT8 | PsysOffset |
| | Offset 0x02A1 - Platform Psys offset correction PCODE MMIO Mailbox: Platform Psys offset correction. More...
|
| |
| UINT8 | AcousticNoiseMitigation |
| | Offset 0x02A2 - Acoustic Noise Mitigation feature Enable or Disable Acoustic Noise Mitigation feature. More...
|
| |
| UINT8 | FastPkgCRampDisableIa |
| | Offset 0x02A3 - Disable Fast Slew Rate for Deep Package C States for VR IA domain Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation feature enabled. More...
|
| |
| UINT8 | SlowSlewRateForIa |
| | Offset 0x02A4 - Slew Rate configuration for Deep Package C States for VR IA domain Slew Rate configuration for Deep Package C States for VR IA domain based on Acoustic Noise Mitigation feature enabled. More...
|
| |
| UINT8 | SlowSlewRateForGt |
| | Offset 0x02A5 - Slew Rate configuration for Deep Package C States for VR GT domain Slew Rate configuration for Deep Package C States for VR GT domain based on Acoustic Noise Mitigation feature enabled. More...
|
| |
| UINT8 | SlowSlewRateForSa |
| | Offset 0x02A6 - Slew Rate configuration for Deep Package C States for VR SA domain Slew Rate configuration for Deep Package C States for VR SA domain based on Acoustic Noise Mitigation feature enabled. More...
|
| |
| UINT16 | TdcPowerLimit [5] |
| | Offset 0x02A7 - Thermal Design Current current limit PCODE MMIO Mailbox: Thermal Design Current current limit. More...
|
| |
| UINT16 | AcLoadline [5] |
| | Offset 0x02B1 - AcLoadline PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. More...
|
| |
|
UINT8 | UnusedUpdSpace8 [10] |
| | Offset 0x02BB.
|
| |
| UINT16 | DcLoadline [5] |
| | Offset 0x02C5 - DcLoadline PCODE MMIO Mailbox: DcLoadline in 1/100 mOhms (ie. More...
|
| |
| UINT16 | Psi1Threshold [5] |
| | Offset 0x02CF - Power State 1 Threshold current PCODE MMIO Mailbox: Power State 1 current cuttof in 1/4 Amp increments. More...
|
| |
| UINT16 | Psi2Threshold [5] |
| | Offset 0x02D9 - Power State 2 Threshold current PCODE MMIO Mailbox: Power State 2 current cuttof in 1/4 Amp increments. More...
|
| |
| UINT16 | Psi3Threshold [5] |
| | Offset 0x02E3 - Power State 3 Threshold current PCODE MMIO Mailbox: Power State 3 current cuttof in 1/4 Amp increments. More...
|
| |
| UINT16 | IccMax [5] |
| | Offset 0x02ED - Icc Max limit PCODE MMIO Mailbox: VR Icc Max limit. More...
|
| |
| UINT16 | VrVoltageLimit [5] |
| | Offset 0x02F7 - VR Voltage Limit PCODE MMIO Mailbox: VR Voltage Limit. More...
|
| |
| UINT8 | FastPkgCRampDisableGt |
| | Offset 0x0301 - Disable Fast Slew Rate for Deep Package C States for VR GT domain Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation feature enabled. More...
|
| |
| UINT8 | FastPkgCRampDisableSa |
| | Offset 0x0302 - Disable Fast Slew Rate for Deep Package C States for VR SA domain Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation feature enabled. More...
|
| |
| UINT8 | SendVrMbxCmd |
| | Offset 0x0303 - Enable VR specific mailbox command VR specific mailbox commands. More...
|
| |
|
UINT8 | Reserved2 |
| | Offset 0x0304 - Reserved Reserved.
|
| |
| UINT8 | TxtEnable |
| | Offset 0x0305 - Enable or Disable TXT Enable or Disable TXT; 0: Disable; 1: Enable. More...
|
| |
|
UINT8 | UnusedUpdSpace9 [6] |
| | Offset 0x0306.
|
| |
| UINT8 | SkipMpInit |
| | Offset 0x030C - Deprecated DO NOT USE Skip Multi-Processor Initialization. More...
|
| |
| UINT8 | McivrRfiFrequencyPrefix |
| | Offset 0x030D - McIVR RFI Frequency Prefix PCODE MMIO Mailbox: McIVR RFI Frequency Adjustment Prefix. More...
|
| |
| UINT8 | McivrRfiFrequencyAdjust |
| | Offset 0x030E - McIVR RFI Frequency Adjustment PCODE MMIO Mailbox: Adjust the RFI frequency relative to the nominal frequency in increments of 100KHz. More...
|
| |
| UINT16 | FivrRfiFrequency |
| | Offset 0x030F - FIVR RFI Frequency PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz. More...
|
| |
| UINT8 | McivrSpreadSpectrum |
| | Offset 0x0311 - McIVR RFI Spread Spectrum PCODE MMIO Mailbox: McIVR RFI Spread Spectrum. More...
|
| |
| UINT8 | FivrSpreadSpectrum |
| | Offset 0x0312 - FIVR RFI Spread Spectrum PCODE MMIO Mailbox: FIVR RFI Spread Spectrum, in 0.1% increments. More...
|
| |
| UINT8 | FastPkgCRampDisableFivr |
| | Offset 0x0313 - Disable Fast Slew Rate for Deep Package C States for VR FIVR domain Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation feature enabled. More...
|
| |
| UINT8 | SlowSlewRateForFivr |
| | Offset 0x0314 - Slew Rate configuration for Deep Package C States for VR FIVR domain Slew Rate configuration for Deep Package C States for VR FIVR domain based on Acoustic Noise Mitigation feature enabled. More...
|
| |
|
UINT32 | CpuBistData |
| | Offset 0x0315 - CpuBistData Pointer CPU BIST Data.
|
| |
| UINT8 | IslVrCmd |
| | Offset 0x0319 - Activates VR mailbox command for Intersil VR C-state issues. More...
|
| |
| UINT16 | ImonSlope1 [5] |
| | Offset 0x031A - Imon slope1 correction PCODE MMIO Mailbox: Imon slope correction. More...
|
| |
| UINT32 | VrPowerDeliveryDesign |
| | Offset 0x0324 - CPU VR Power Delivery Design Used to communicate the power delivery design capability of the board. More...
|
| |
| UINT8 | PreWake |
| | Offset 0x0328 - Pre Wake Randomization time PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum pre-wake randomization time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled. More...
|
| |
|
UINT8 | RampUp |
| | Offset 0x0329 - Ramp Up Randomization time PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum Ramp Up randomization time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled.Range 0-255 0.
|
| |
|
UINT8 | RampDown |
| | Offset 0x032A - Ramp Down Randomization time PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum Ramp Down randomization time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled.Range 0-255 0.
|
| |
|
UINT32 | CpuMpPpi |
| | Offset 0x032B - CpuMpPpi Pointer for CpuMpPpi.
|
| |
| UINT32 | CpuMpHob |
| | Offset 0x032F - CpuMpHob Pointer for CpuMpHob. More...
|
| |
| UINT8 | DebugInterfaceEnable |
| | Offset 0x0333 - Enable or Disable processor debug features Enable or Disable processor debug features; 0: Disable; 1: Enable. More...
|
| |
|
UINT8 | ReservedCpuPostMemProduction [18] |
| | Offset 0x0334 - ReservedCpuPostMemProduction Reserved for CPU Post-Mem Production $EN_DIS.
|
| |
| UINT8 | PchDmiAspm |
| | Offset 0x0346 - Enable DMI ASPM Deprecated. More...
|
| |
| UINT8 | PchPwrOptEnable |
| | Offset 0x0347 - Enable Power Optimizer Enable DMI Power Optimizer on PCH side. More...
|
| |
|
UINT8 | PchWriteProtectionEnable [5] |
| | Offset 0x0348 - PCH Flash Protection Ranges Write Enble Write or erase is blocked by hardware.
|
| |
|
UINT8 | PchReadProtectionEnable [5] |
| | Offset 0x034D - PCH Flash Protection Ranges Read Enble Read is blocked by hardware.
|
| |
|
UINT16 | PchProtectedRangeLimit [5] |
| | Offset 0x0352 - PCH Protect Range Limit Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for limit comparison.
|
| |
|
UINT16 | PchProtectedRangeBase [5] |
| | Offset 0x035C - PCH Protect Range Base Left shifted address by 12 bits with address bits 11:0 are assumed to be 0.
|
| |
| UINT8 | PchHdaPme |
| | Offset 0x0366 - Enable Pme Enable Azalia wake-on-ring. More...
|
| |
|
UINT8 | UnusedUpdSpace10 |
| | Offset 0x0367.
|
| |
| UINT8 | PchHdaVcType |
| | Offset 0x0368 - VC Type Virtual Channel Type Select: 0: VC0, 1: VC1. More...
|
| |
| UINT8 | PchHdaLinkFrequency |
| | Offset 0x0369 - HD Audio Link Frequency HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, 1: 12MHz, 2: 24MHz. More...
|
| |
| UINT8 | PchHdaIDispLinkFrequency |
| | Offset 0x036A - iDisp-Link Frequency iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz. More...
|
| |
| UINT8 | PchHdaIDispLinkTmode |
| | Offset 0x036B - iDisp-Link T-mode iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 1: 1T. More...
|
| |
| UINT8 | PchHdaDspUaaCompliance |
| | Offset 0x036C - Universal Audio Architecture compliance for DSP enabled system 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox driver or SST driver supported). More...
|
| |
| UINT8 | PchHdaIDispCodecDisconnect |
| | Offset 0x036D - iDisplay Audio Codec disconnection 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable. More...
|
| |
| UINT8 | PchUsbHsioFilterSel [10] |
| | Offset 0x036E - USB LFPS Filter selection For each byte bits 2:0 are for p, bits 4:6 are for n. More...
|
| |
|
UINT8 | UnusedUpdSpace11 [5] |
| | Offset 0x0378.
|
| |
| UINT8 | PchIoApicEntry24_119 |
| | Offset 0x037D - Enable PCH Io Apic Entry 24-119 0: Disable; 1: Enable. More...
|
| |
| UINT8 | PchIoApicId |
| | Offset 0x037E - PCH Io Apic ID This member determines IOAPIC ID. More...
|
| |
|
UINT8 | UnusedUpdSpace12 |
| | Offset 0x037F.
|
| |
| UINT8 | PchIshSpiGpioAssign |
| | Offset 0x0380 - Enable PCH ISH SPI GPIO pins assigned 0: Disable; 1: Enable. More...
|
| |
| UINT8 | PchIshUart0GpioAssign |
| | Offset 0x0381 - Enable PCH ISH UART0 GPIO pins assigned 0: Disable; 1: Enable. More...
|
| |
| UINT8 | PchIshUart1GpioAssign |
| | Offset 0x0382 - Enable PCH ISH UART1 GPIO pins assigned 0: Disable; 1: Enable. More...
|
| |
| UINT8 | PchIshI2c0GpioAssign |
| | Offset 0x0383 - Enable PCH ISH I2C0 GPIO pins assigned 0: Disable; 1: Enable. More...
|
| |
| UINT8 | PchIshI2c1GpioAssign |
| | Offset 0x0384 - Enable PCH ISH I2C1 GPIO pins assigned 0: Disable; 1: Enable. More...
|
| |
| UINT8 | PchIshI2c2GpioAssign |
| | Offset 0x0385 - Enable PCH ISH I2C2 GPIO pins assigned 0: Disable; 1: Enable. More...
|
| |
| UINT8 | PchIshGp0GpioAssign |
| | Offset 0x0386 - Enable PCH ISH GP_0 GPIO pin assigned 0: Disable; 1: Enable. More...
|
| |
| UINT8 | PchIshGp1GpioAssign |
| | Offset 0x0387 - Enable PCH ISH GP_1 GPIO pin assigned 0: Disable; 1: Enable. More...
|
| |
| UINT8 | PchIshGp2GpioAssign |
| | Offset 0x0388 - Enable PCH ISH GP_2 GPIO pin assigned 0: Disable; 1: Enable. More...
|
| |
| UINT8 | PchIshGp3GpioAssign |
| | Offset 0x0389 - Enable PCH ISH GP_3 GPIO pin assigned 0: Disable; 1: Enable. More...
|
| |
| UINT8 | PchIshGp4GpioAssign |
| | Offset 0x038A - Enable PCH ISH GP_4 GPIO pin assigned 0: Disable; 1: Enable. More...
|
| |
| UINT8 | PchIshGp5GpioAssign |
| | Offset 0x038B - Enable PCH ISH GP_5 GPIO pin assigned 0: Disable; 1: Enable. More...
|
| |
| UINT8 | PchIshGp6GpioAssign |
| | Offset 0x038C - Enable PCH ISH GP_6 GPIO pin assigned 0: Disable; 1: Enable. More...
|
| |
| UINT8 | PchIshGp7GpioAssign |
| | Offset 0x038D - Enable PCH ISH GP_7 GPIO pin assigned 0: Disable; 1: Enable. More...
|
| |
| UINT8 | PchIshPdtUnlock |
| | Offset 0x038E - PCH ISH PDT Unlock Msg 0: False; 1: True. More...
|
| |
| UINT8 | PchLanLtrEnable |
| | Offset 0x038F - Enable PCH Lan LTR capabilty of PCH internal LAN 0: Disable; 1: Enable. More...
|
| |
|
UINT8 | UnusedUpdSpace13 [3] |
| | Offset 0x0390.
|
| |
| UINT8 | PchLockDownBiosLock |
| | Offset 0x0393 - Enable LOCKDOWN BIOS LOCK Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region protection. More...
|
| |
| UINT8 | PchCrid |
| | Offset 0x0394 - PCH Compatibility Revision ID This member describes whether or not the CRID feature of PCH should be enabled. More...
|
| |
| UINT8 | PchLockDownRtcMemoryLock |
| | Offset 0x0395 - RTC CMOS MEMORY LOCK Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper and and lower 128-byte bank of RTC RAM. More...
|
| |
|
UINT8 | PcieRpHotPlug [24] |
| | Offset 0x0396 - Enable PCIE RP HotPlug Indicate whether the root port is hot plug available.
|
| |
|
UINT8 | PcieRpPmSci [24] |
| | Offset 0x03AE - Enable PCIE RP Pm Sci Indicate whether the root port power manager SCI is enabled.
|
| |
|
UINT8 | PcieRpExtSync [24] |
| | Offset 0x03C6 - Enable PCIE RP Ext Sync Indicate whether the extended synch is enabled.
|
| |
|
UINT8 | PcieRpTransmitterHalfSwing [24] |
| | Offset 0x03DE - Enable PCIE RP Transmitter Half Swing Indicate whether the Transmitter Half Swing is enabled.
|
| |
|
UINT8 | PcieRpClkReqDetect [24] |
| | Offset 0x03F6 - Enable PCIE RP Clk Req Detect Probe CLKREQ# signal before enabling CLKREQ# based power management.
|
| |
|
UINT8 | PcieRpAdvancedErrorReporting [24] |
| | Offset 0x040E - PCIE RP Advanced Error Report Indicate whether the Advanced Error Reporting is enabled.
|
| |
|
UINT8 | PcieRpUnsupportedRequestReport [24] |
| | Offset 0x0426 - PCIE RP Unsupported Request Report Indicate whether the Unsupported Request Report is enabled.
|
| |
|
UINT8 | PcieRpFatalErrorReport [24] |
| | Offset 0x043E - PCIE RP Fatal Error Report Indicate whether the Fatal Error Report is enabled.
|
| |
|
UINT8 | PcieRpNoFatalErrorReport [24] |
| | Offset 0x0456 - PCIE RP No Fatal Error Report Indicate whether the No Fatal Error Report is enabled.
|
| |
|
UINT8 | PcieRpCorrectableErrorReport [24] |
| | Offset 0x046E - PCIE RP Correctable Error Report Indicate whether the Correctable Error Report is enabled.
|
| |
|
UINT8 | PcieRpSystemErrorOnFatalError [24] |
| | Offset 0x0486 - PCIE RP System Error On Fatal Error Indicate whether the System Error on Fatal Error is enabled.
|
| |
|
UINT8 | PcieRpSystemErrorOnNonFatalError [24] |
| | Offset 0x049E - PCIE RP System Error On Non Fatal Error Indicate whether the System Error on Non Fatal Error is enabled.
|
| |
|
UINT8 | PcieRpSystemErrorOnCorrectableError [24] |
| | Offset 0x04B6 - PCIE RP System Error On Correctable Error Indicate whether the System Error on Correctable Error is enabled.
|
| |
|
UINT8 | PcieRpMaxPayload [24] |
| | Offset 0x04CE - PCIE RP Max Payload Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD.
|
| |
|
UINT8 | PchUsbHsioRxTuningParameters [10] |
| | Offset 0x04E6 - PCH USB3 RX HSIO Tuning parameters Bits 7:3 are for Signed Magnatude number added to the CTLE code, Bits 2:0 are for controlling the input offset.
|
| |
| UINT8 | PchUsbHsioRxTuningEnable [10] |
| | Offset 0x04F0 - PCH USB3 HSIO Rx Tuning Enable Mask for enabling tuning of HSIO Rx signals of USB3 ports. More...
|
| |
|
UINT8 | UnusedUpdSpace14 [4] |
| | Offset 0x04FA.
|
| |
| UINT8 | PcieRpPcieSpeed [24] |
| | Offset 0x04FE - PCIE RP Pcie Speed Determines each PCIE Port speed capability. More...
|
| |
| UINT8 | PcieRpGen3EqPh3Method [24] |
| | Offset 0x0516 - PCIE RP Gen3 Equalization Phase Method PCIe Gen3 Eq Ph3 Method (see PCH_PCIE_EQ_METHOD). More...
|
| |
| UINT8 | PcieRpPhysicalSlotNumber [24] |
| | Offset 0x052E - PCIE RP Physical Slot Number Indicates the slot number for the root port. More...
|
| |
| UINT8 | PcieRpCompletionTimeout [24] |
| | Offset 0x0546 - PCIE RP Completion Timeout The root port completion timeout(see: PCH_PCIE_COMPLETION_TIMEOUT). More...
|
| |
|
UINT8 | UnusedUpdSpace15 [106] |
| | Offset 0x055E.
|
| |
| UINT8 | PcieRpAspm [24] |
| | Offset 0x05C8 - PCIE RP Aspm The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). More...
|
| |
| UINT8 | PcieRpL1Substates [24] |
| | Offset 0x05E0 - PCIE RP L1 Substates The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL). More...
|
| |
|
UINT8 | PcieRpLtrEnable [24] |
| | Offset 0x05F8 - PCIE RP Ltr Enable Latency Tolerance Reporting Mechanism.
|
| |
|
UINT8 | PcieRpLtrConfigLock [24] |
| | Offset 0x0610 - PCIE RP Ltr Config Lock 0: Disable; 1: Enable.
|
| |
| UINT8 | PcieEqPh3LaneParamCm [24] |
| | Offset 0x0628 - PCIE Eq Ph3 Lane Param Cm PCH_PCIE_EQ_LANE_PARAM. More...
|
| |
| UINT8 | PcieEqPh3LaneParamCp [24] |
| | Offset 0x0640 - PCIE Eq Ph3 Lane Param Cp PCH_PCIE_EQ_LANE_PARAM. More...
|
| |
| UINT8 | PcieSwEqCoeffListCm [5] |
| | Offset 0x0658 - PCIE Sw Eq CoeffList Cm PCH_PCIE_EQ_PARAM. More...
|
| |
| UINT8 | PcieSwEqCoeffListCp [5] |
| | Offset 0x065D - PCIE Sw Eq CoeffList Cp PCH_PCIE_EQ_PARAM. More...
|
| |
| UINT8 | PcieDisableRootPortClockGating |
| | Offset 0x0662 - PCIE Disable RootPort Clock Gating Describes whether the PCI Express Clock Gating for each root port is enabled by platform modules. More...
|
| |
| UINT8 | PcieEnablePeerMemoryWrite |
| | Offset 0x0663 - PCIE Enable Peer Memory Write This member describes whether Peer Memory Writes are enabled on the platform. More...
|
| |
|
UINT8 | UnusedUpdSpace16 |
| | Offset 0x0664.
|
| |
| UINT8 | PcieComplianceTestMode |
| | Offset 0x0665 - PCIE Compliance Test Mode Compliance Test Mode shall be enabled when using Compliance Load Board. More...
|
| |
| UINT8 | PcieRpFunctionSwap |
| | Offset 0x0666 - PCIE Rp Function Swap Allows BIOS to use root port function number swapping when root port of function 0 is disabled. More...
|
| |
| UINT8 | TetonGlacierSupport |
| | Offset 0x0667 - Teton Glacier Support Enables support for the Teton Glacier card. More...
|
| |
| UINT8 | TetonGlacierCR |
| | Offset 0x0668 - Teton Glacier Cycle Router Specify to which cycle router Teton Glacier is connected, it is valid only when Teton Glacier support is enabled. More...
|
| |
| UINT8 | PchPmPmeB0S5Dis |
| | Offset 0x0669 - PCH Pm PME_B0_S5_DIS When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1. More...
|
| |
|
UINT8 | SerialIoSpiCsPolarity [3] |
| | Offset 0x066A - SPI ChipSelect signal polarity Selects SPI ChipSelect signal polarity.
|
| |
| UINT8 | PcieRpImrEnabled |
| | Offset 0x066D - PCIE IMR Enables Isolated Memory Region for PCIe. More...
|
| |
|
UINT8 | PcieRpImrSelection |
| | Offset 0x066E - PCIE IMR port number Selects PCIE root port number for IMR feature.
|
| |
|
UINT8 | UnusedUpdSpace17 |
| | Offset 0x066F.
|
| |
| UINT8 | PchPmWolEnableOverride |
| | Offset 0x0670 - PCH Pm Wol Enable Override Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register. More...
|
| |
| UINT8 | PchPmPcieWakeFromDeepSx |
| | Offset 0x0671 - PCH Pm Pcie Wake From DeepSx Determine if enable PCIe to wake from deep Sx. More...
|
| |
| UINT8 | PchPmWoWlanEnable |
| | Offset 0x0672 - PCH Pm WoW lan Enable Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register. More...
|
| |
| UINT8 | PchPmWoWlanDeepSxEnable |
| | Offset 0x0673 - PCH Pm WoW lan DeepSx Enable Determine if WLAN wake from DeepSx, corresponds to the DSX_WLAN_PP_EN bit in the PWRM_CFG3 register. More...
|
| |
| UINT8 | PchPmLanWakeFromDeepSx |
| | Offset 0x0674 - PCH Pm Lan Wake From DeepSx Determine if enable LAN to wake from deep Sx. More...
|
| |
| UINT8 | PchPmDeepSxPol |
| | Offset 0x0675 - PCH Pm Deep Sx Pol Deep Sx Policy. More...
|
| |
| UINT8 | PchPmSlpS3MinAssert |
| | Offset 0x0676 - PCH Pm Slp S3 Min Assert SLP_S3 Minimum Assertion Width Policy. More...
|
| |
| UINT8 | PchPmSlpS4MinAssert |
| | Offset 0x0677 - PCH Pm Slp S4 Min Assert SLP_S4 Minimum Assertion Width Policy. More...
|
| |
| UINT8 | PchPmSlpSusMinAssert |
| | Offset 0x0678 - PCH Pm Slp Sus Min Assert SLP_SUS Minimum Assertion Width Policy. More...
|
| |
| UINT8 | PchPmSlpAMinAssert |
| | Offset 0x0679 - PCH Pm Slp A Min Assert SLP_A Minimum Assertion Width Policy. More...
|
| |
| UINT8 | SlpS0Override |
| | Offset 0x067A - SLP_S0# Override Select 'Auto', it will be auto-configured according to probe type. More...
|
| |
| UINT8 | SlpS0DisQForDebug |
| | Offset 0x067B - S0ix Override Settings Select 'Auto', it will be auto-configured according to probe type. More...
|
| |
| UINT8 | PchEnableDbcObs |
| | Offset 0x067C - USB Overcurrent Override for DbC This option overrides USB Over Current enablement state that USB OC will be disabled after enabling this option. More...
|
| |
|
UINT8 | UnusedUpdSpace18 [3] |
| | Offset 0x067D.
|
| |
| UINT8 | PchPmLpcClockRun |
| | Offset 0x0680 - PCH Pm Lpc Clock Run This member describes whether or not the LPC ClockRun feature of PCH should be enabled. More...
|
| |
| UINT8 | PchPmSlpStrchSusUp |
| | Offset 0x0681 - PCH Pm Slp Strch Sus Up Enable SLP_X Stretching After SUS Well Power Up. More...
|
| |
| UINT8 | PchPmSlpLanLowDc |
| | Offset 0x0682 - PCH Pm Slp Lan Low Dc Enable/Disable SLP_LAN# Low on DC Power. More...
|
| |
| UINT8 | PchPmPwrBtnOverridePeriod |
| | Offset 0x0683 - PCH Pm Pwr Btn Override Period PCH power button override period. More...
|
| |
| UINT8 | PchPmDisableDsxAcPresentPulldown |
| | Offset 0x0684 - PCH Pm Disable Dsx Ac Present Pulldown When Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit. More...
|
| |
|
UINT8 | UnusedUpdSpace19 |
| | Offset 0x0685.
|
| |
| UINT8 | PchPmDisableNativePowerButton |
| | Offset 0x0686 - PCH Pm Disable Native Power Button Power button native mode disable. More...
|
| |
| UINT8 | PchPmSlpS0Enable |
| | Offset 0x0687 - PCH Pm Slp S0 Enable Indicates whether SLP_S0# is to be asserted when PCH reaches idle state. More...
|
| |
| UINT8 | PchPmMeWakeSts |
| | Offset 0x0688 - PCH Pm ME_WAKE_STS Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register. More...
|
| |
| UINT8 | PchPmWolOvrWkSts |
| | Offset 0x0689 - PCH Pm WOL_OVR_WK_STS Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register. More...
|
| |
| UINT8 | PchPmPwrCycDur |
| | Offset 0x068A - PCH Pm Reset Power Cycle Duration Could be customized in the unit of second. More...
|
| |
| UINT8 | PchPmPciePllSsc |
| | Offset 0x068B - PCH Pm Pcie Pll Ssc Specifies the Pcie Pll Spread Spectrum Percentage. More...
|
| |
|
UINT8 | UnusedUpdSpace20 |
| | Offset 0x068C.
|
| |
| UINT8 | SataPwrOptEnable |
| | Offset 0x068D - PCH Sata Pwr Opt Enable SATA Power Optimizer on PCH side. More...
|
| |
| UINT8 | EsataSpeedLimit |
| | Offset 0x068E - PCH Sata eSATA Speed Limit When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed. More...
|
| |
|
UINT8 | SataSpeedLimit |
| | Offset 0x068F - PCH Sata Speed Limit Indicates the maximum speed the SATA controller can support 0h: PchSataSpeedDefault.
|
| |
|
UINT8 | SataPortsHotPlug [8] |
| | Offset 0x0690 - Enable SATA Port HotPlug Enable SATA Port HotPlug.
|
| |
|
UINT8 | SataPortsInterlockSw [8] |
| | Offset 0x0698 - Enable SATA Port Interlock Sw Enable SATA Port Interlock Sw.
|
| |
|
UINT8 | SataPortsExternal [8] |
| | Offset 0x06A0 - Enable SATA Port External Enable SATA Port External.
|
| |
|
UINT8 | SataPortsSpinUp [8] |
| | Offset 0x06A8 - Enable SATA Port SpinUp Enable the COMRESET initialization Sequence to the device.
|
| |
|
UINT8 | SataPortsSolidStateDrive [8] |
| | Offset 0x06B0 - Enable SATA Port Solid State Drive 0: HDD; 1: SSD.
|
| |
|
UINT8 | SataPortsEnableDitoConfig [8] |
| | Offset 0x06B8 - Enable SATA Port Enable Dito Config Enable DEVSLP Idle Timeout settings (DmVal, DitoVal).
|
| |
| UINT8 | SataPortsDmVal [8] |
| | Offset 0x06C0 - Enable SATA Port DmVal DITO multiplier. More...
|
| |
|
UINT16 | SataPortsDitoVal [8] |
| | Offset 0x06C8 - Enable SATA Port DmVal DEVSLP Idle Timeout (DITO), Default is 625.
|
| |
|
UINT8 | SataPortsZpOdd [8] |
| | Offset 0x06D8 - Enable SATA Port ZpOdd Support zero power ODD.
|
| |
| UINT8 | SataRstRaidDeviceId |
| | Offset 0x06E0 - PCH Sata Rst Raid Device Id Enable RAID Alternate ID. More...
|
| |
| UINT8 | SataRstRaid0 |
| | Offset 0x06E1 - PCH Sata Rst Raid0 RAID0. More...
|
| |
| UINT8 | SataRstRaid1 |
| | Offset 0x06E2 - PCH Sata Rst Raid1 RAID1. More...
|
| |
| UINT8 | SataRstRaid10 |
| | Offset 0x06E3 - PCH Sata Rst Raid10 RAID10. More...
|
| |
| UINT8 | SataRstRaid5 |
| | Offset 0x06E4 - PCH Sata Rst Raid5 RAID5. More...
|
| |
| UINT8 | SataRstIrrt |
| | Offset 0x06E5 - PCH Sata Rst Irrt Intel Rapid Recovery Technology. More...
|
| |
| UINT8 | SataRstOromUiBanner |
| | Offset 0x06E6 - PCH Sata Rst Orom Ui Banner OROM UI and BANNER. More...
|
| |
|
UINT8 | SataRstOromUiDelay |
| | Offset 0x06E7 - PCH Sata Rst Orom Ui Delay 00b: 2 secs; 01b: 4 secs; 10b: 6 secs; 11: 8 secs (see: PCH_SATA_OROM_DELAY).
|
| |
| UINT8 | SataRstHddUnlock |
| | Offset 0x06E8 - PCH Sata Rst Hdd Unlock Indicates that the HDD password unlock in the OS is enabled. More...
|
| |
| UINT8 | SataRstLedLocate |
| | Offset 0x06E9 - PCH Sata Rst Led Locate Indicates that the LED/SGPIO hardware is attached and ping to locate feature is enabled on the OS. More...
|
| |
| UINT8 | SataRstIrrtOnly |
| | Offset 0x06EA - PCH Sata Rst Irrt Only Allow only IRRT drives to span internal and external ports. More...
|
| |
| UINT8 | SataRstSmartStorage |
| | Offset 0x06EB - PCH Sata Rst Smart Storage RST Smart Storage caching Bit. More...
|
| |
|
UINT8 | SataRstPcieEnable [3] |
| | Offset 0x06EC - PCH Sata Rst Pcie Storage Remap enable Enable Intel RST for PCIe Storage remapping.
|
| |
|
UINT8 | SataRstPcieStoragePort [3] |
| | Offset 0x06EF - PCH Sata Rst Pcie Storage Port Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect).
|
| |
| UINT8 | SataRstPcieDeviceResetDelay [3] |
| | Offset 0x06F2 - PCH Sata Rst Pcie Device Reset Delay PCIe Storage Device Reset Delay in milliseconds. More...
|
| |
| UINT8 | PchScsEmmcHs400TuningRequired |
| | Offset 0x06F5 - Enable eMMC HS400 Training Deprecated. More...
|
| |
| UINT8 | PchScsEmmcHs400DllDataValid |
| | Offset 0x06F6 - Set HS400 Tuning Data Valid Set if HS400 Tuning Data Valid. More...
|
| |
|
UINT8 | PchScsEmmcHs400RxStrobeDll1 |
| | Offset 0x06F7 - Rx Strobe Delay Control Rx Strobe Delay Control - Rx Strobe Delay DLL 1 (HS400 Mode).
|
| |
|
UINT8 | PchScsEmmcHs400TxDataDll |
| | Offset 0x06F8 - Tx Data Delay Control Tx Data Delay Control 1 - Tx Data Delay (HS400 Mode).
|
| |
| UINT8 | PchScsEmmcHs400DriverStrength |
| | Offset 0x06F9 - I/O Driver Strength Deprecated. More...
|
| |
| UINT8 | PchSerialIoI2cPadsTermination [6] |
| | Offset 0x06FA - PCH SerialIo I2C Pads Termination 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5 pads termination respectively. More...
|
| |
|
UINT8 | UnusedUpdSpace21 |
| | Offset 0x0700.
|
| |
| UINT8 | SerialIoUart0PinMuxing |
| | Offset 0x0701 - PcdSerialIoUart0PinMuxing Select SerialIo Uart0 pin muxing. More...
|
| |
|
UINT8 | UnusedUpdSpace22 [1] |
| | Offset 0x0702.
|
| |
|
UINT8 | SerialIoUartHwFlowCtrl [3] |
| | Offset 0x0703 - Enables UART hardware flow control, CTS and RTS lines Enables UART hardware flow control, CTS and RTS linesh.
|
| |
| UINT8 | SerialIoDebugUartNumber |
| | Offset 0x0706 - UART Number For Debug Purpose UART number for debug purpose. More...
|
| |
| UINT8 | SerialIoEnableDebugUartAfterPost |
| | Offset 0x0707 - Enable Debug UART Controller Enable debug UART controller after post. More...
|
| |
| UINT8 | PchSirqEnable |
| | Offset 0x0708 - Enable Serial IRQ Determines if enable Serial IRQ. More...
|
| |
| UINT8 | PchSirqMode |
| | Offset 0x0709 - Serial IRQ Mode Select Serial IRQ Mode Select, 0: quiet mode, 1: continuous mode. More...
|
| |
| UINT8 | PchStartFramePulse |
| | Offset 0x070A - Start Frame Pulse Width Start Frame Pulse Width, 0: PchSfpw4Clk, 1: PchSfpw6Clk, 2: PchSfpw8Clk. More...
|
| |
|
UINT8 | ReservedForFuture1 |
| | Offset 0x070B - Reserved Reserved $EN_DIS.
|
| |
| UINT8 | PchTsmicLock |
| | Offset 0x070C - Thermal Device SMI Enable This locks down SMI Enable on Alert Thermal Sensor Trip. More...
|
| |
|
UINT16 | PchT0Level |
| | Offset 0x070D - Thermal Throttling Custimized T0Level Value Custimized T0Level value.
|
| |
|
UINT16 | PchT1Level |
| | Offset 0x070F - Thermal Throttling Custimized T1Level Value Custimized T1Level value.
|
| |
|
UINT16 | PchT2Level |
| | Offset 0x0711 - Thermal Throttling Custimized T2Level Value Custimized T2Level value.
|
| |
| UINT8 | PchTTEnable |
| | Offset 0x0713 - Enable The Thermal Throttle Enable the thermal throttle function. More...
|
| |
| UINT8 | PchTTState13Enable |
| | Offset 0x0714 - PMSync State 13 When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force at least T2 state. More...
|
| |
| UINT8 | PchTTLock |
| | Offset 0x0715 - Thermal Throttle Lock Thermal Throttle Lock. More...
|
| |
| UINT8 | TTSuggestedSetting |
| | Offset 0x0716 - Thermal Throttling Suggested Setting Thermal Throttling Suggested Setting. More...
|
| |
|
UINT8 | TTCrossThrottling |
| | Offset 0x0717 - Enable PCH Cross Throttling Enable/Disable PCH Cross Throttling $EN_DIS.
|
| |
| UINT8 | PchDmiTsawEn |
| | Offset 0x0718 - DMI Thermal Sensor Autonomous Width Enable DMI Thermal Sensor Autonomous Width Enable. More...
|
| |
| UINT8 | DmiSuggestedSetting |
| | Offset 0x0719 - DMI Thermal Sensor Suggested Setting DMT thermal sensor suggested representative values. More...
|
| |
| UINT8 | DmiTS0TW |
| | Offset 0x071A - Thermal Sensor 0 Target Width DMT thermal sensor suggested representative values. More...
|
| |
| UINT8 | DmiTS1TW |
| | Offset 0x071B - Thermal Sensor 1 Target Width Thermal Sensor 1 Target Width. More...
|
| |
| UINT8 | DmiTS2TW |
| | Offset 0x071C - Thermal Sensor 2 Target Width Thermal Sensor 2 Target Width. More...
|
| |
| UINT8 | DmiTS3TW |
| | Offset 0x071D - Thermal Sensor 3 Target Width Thermal Sensor 3 Target Width. More...
|
| |
|
UINT8 | SataP0T1M |
| | Offset 0x071E - Port 0 T1 Multipler Port 0 T1 Multipler.
|
| |
|
UINT8 | SataP0T2M |
| | Offset 0x071F - Port 0 T2 Multipler Port 0 T2 Multipler.
|
| |
|
UINT8 | SataP0T3M |
| | Offset 0x0720 - Port 0 T3 Multipler Port 0 T3 Multipler.
|
| |
|
UINT8 | SataP0TDisp |
| | Offset 0x0721 - Port 0 Tdispatch Port 0 Tdispatch.
|
| |
|
UINT8 | SataP1T1M |
| | Offset 0x0722 - Port 1 T1 Multipler Port 1 T1 Multipler.
|
| |
|
UINT8 | SataP1T2M |
| | Offset 0x0723 - Port 1 T2 Multipler Port 1 T2 Multipler.
|
| |
|
UINT8 | SataP1T3M |
| | Offset 0x0724 - Port 1 T3 Multipler Port 1 T3 Multipler.
|
| |
|
UINT8 | SataP1TDisp |
| | Offset 0x0725 - Port 1 Tdispatch Port 1 Tdispatch.
|
| |
|
UINT8 | SataP0Tinact |
| | Offset 0x0726 - Port 0 Tinactive Port 0 Tinactive.
|
| |
| UINT8 | SataP0TDispFinit |
| | Offset 0x0727 - Port 0 Alternate Fast Init Tdispatch Port 0 Alternate Fast Init Tdispatch. More...
|
| |
|
UINT8 | SataP1Tinact |
| | Offset 0x0728 - Port 1 Tinactive Port 1 Tinactive.
|
| |
| UINT8 | SataP1TDispFinit |
| | Offset 0x0729 - Port 1 Alternate Fast Init Tdispatch Port 1 Alternate Fast Init Tdispatch. More...
|
| |
| UINT8 | SataThermalSuggestedSetting |
| | Offset 0x072A - Sata Thermal Throttling Suggested Setting Sata Thermal Throttling Suggested Setting. More...
|
| |
| UINT8 | PchMemoryThrottlingEnable |
| | Offset 0x072B - Enable Memory Thermal Throttling Enable Memory Thermal Throttling. More...
|
| |
|
UINT8 | PchMemoryPmsyncEnable [2] |
| | Offset 0x072C - Memory Thermal Throttling Enable Memory Thermal Throttling.
|
| |
|
UINT8 | PchMemoryC0TransmitEnable [2] |
| | Offset 0x072E - Enable Memory Thermal Throttling Enable Memory Thermal Throttling.
|
| |
|
UINT8 | PchMemoryPinSelection [2] |
| | Offset 0x0730 - Enable Memory Thermal Throttling Enable Memory Thermal Throttling.
|
| |
|
UINT16 | PchTemperatureHotLevel |
| | Offset 0x0732 - Thermal Device Temperature Decides the temperature.
|
| |
| UINT8 | PchEnableComplianceMode |
| | Offset 0x0734 - Enable xHCI Compliance Mode Compliance Mode can be enabled for testing through this option but this is disabled by default. More...
|
| |
|
UINT8 | Usb2OverCurrentPin [16] |
| | Offset 0x0735 - USB2 Port Over Current Pin Describe the specific over current pin number of USB 2.0 Port N.
|
| |
|
UINT8 | Usb3OverCurrentPin [10] |
| | Offset 0x0745 - USB3 Port Over Current Pin Describe the specific over current pin number of USB 3.0 Port N.
|
| |
| UINT8 | Enable8254ClockGating |
| | Offset 0x074F - Enable 8254 Static Clock Gating Set 8254CGE=1 is required for SLP_S0 support. More...
|
| |
|
UINT8 | SataRstOptaneMemory |
| | Offset 0x0750 - PCH Sata Rst Optane Memory Optane Memory $EN_DIS.
|
| |
|
UINT8 | SataRstCpuAttachedStorage |
| | Offset 0x0751 - PCH Sata Rst CPU Attached Storage CPU Attached Storage $EN_DIS.
|
| |
| UINT8 | Enable8254ClockGatingOnS3 |
| | Offset 0x0752 - Enable 8254 Static Clock Gating On S3 This is only applicable when Enable8254ClockGating is disabled. More...
|
| |
|
UINT8 | UnusedUpdSpace23 |
| | Offset 0x0753.
|
| |
| UINT32 | PchPcieDeviceOverrideTablePtr |
| | Offset 0x0754 - Pch PCIE device override table pointer The PCIe device table is being used to override PCIe device ASPM settings. More...
|
| |
| UINT8 | EnableTcoTimer |
| | Offset 0x0758 - Enable TCO timer. More...
|
| |
|
UINT64 | BgpdtHash [4] |
| | Offset 0x0759 - BgpdtHash[4] BgpdtHash values.
|
| |
|
UINT32 | BiosGuardAttr |
| | Offset 0x0779 - BiosGuardAttr BiosGuardAttr default values.
|
| |
|
UINT64 | BiosGuardModulePtr |
| | Offset 0x077D - BiosGuardModulePtr BiosGuardModulePtr default values.
|
| |
| UINT64 | SendEcCmd |
| | Offset 0x0785 - SendEcCmd SendEcCmd function pointer. More...
|
| |
| UINT8 | EcCmdProvisionEav |
| | Offset 0x078D - EcCmdProvisionEav Ephemeral Authorization Value default values. More...
|
| |
| UINT8 | EcCmdLock |
| | Offset 0x078E - EcCmdLock EcCmdLock default values. More...
|
| |
|
UINT64 | SgxEpoch0 |
| | Offset 0x078F - SgxEpoch0 SgxEpoch0 default values.
|
| |
|
UINT64 | SgxEpoch1 |
| | Offset 0x0797 - SgxEpoch1 SgxEpoch1 default values.
|
| |
|
UINT8 | SgxSinitNvsData |
| | Offset 0x079F - SgxSinitNvsData SgxSinitNvsData default values.
|
| |
| UINT8 | SiCsmFlag |
| | Offset 0x07A0 - Si Config CSM Flag. More...
|
| |
|
UINT32 | SiSsidTablePtr |
| | Offset 0x07A1.
|
| |
|
UINT16 | SiNumberOfSsidTableEntry |
| | Offset 0x07A5.
|
| |
| UINT8 | SataRstInterrupt |
| | Offset 0x07A7 - SATA RST Interrupt Mode Allowes to choose which interrupts will be implemented by SATA controller in RAID mode. More...
|
| |
| UINT8 | MeUnconfigOnRtcClear |
| | Offset 0x07A8 - ME Unconfig on RTC clear 0: Disable ME Unconfig On Rtc Clear. More...
|
| |
| UINT8 | PsOnEnable |
| | Offset 0x07A9 - Enable PS_ON. More...
|
| |
| UINT8 | PmcCpuC10GatePinEnable |
| | Offset 0x07AA - Pmc Cpu C10 Gate Pin Enable Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO and VccSTG rails instead of SLP_S0# pin. More...
|
| |
| UINT8 | PchDmiAspmCtrl |
| | Offset 0x07AB - Pch Dmi Aspm Ctrl ASPM configuration on the PCH side of the DMI/OPI Link. More...
|
| |
|
UINT8 | ReservedFspsUpd [1] |
| | Offset 0x07AC.
|
| |
1.8.10